CA2081338A1 - Process and circuit for operating an inverter with n parallel servo components - Google Patents

Abstract

Abstract The invention relates to a process for operating an inverter arrangement with n parallel servo components (2, 4, 6) in each case consisting of m converter valves (Tln, ..., Tnn), these n servo components (2, 4, 6) being supplied from a common direct-voltage source (Uz) at the input end and being combined with one another at the output end by means of a txansformer (10) followed by a filter capacitor circuit (12), and to a circuit arrangement for carrying out the process. According to the invention, each of the m drive signals (UAT1,...,UATm) generated is jointly supplied to n parallel converter valves (Tl1, Tl2, ..., Tlu and ... and Tm1, Tm2, ..., Tmn, respectively) of the n servo components (2, 4, 6) and an enable signal (UFS1 and ..., and UFSm respectively) is generated in each case precisely when each of the n parallel converter valves (Tl1, Tl2, ..., Tln and ... and Tml/ Tm2,... Tmn, respectively) generates an off signal (Uoff11, Uoff12, ... Uoff1n and ... and UOffm1, UOffm2, ..., Uoffnm, respectively) and each enable signal (UFS1 and ... and UFSm, respectively) enables a drive signal (UAT1 and ... and UATm, respectively) for n parallel converter valves (Tl1, Tl2, ..., Tln and ... and Tm1, Tm2,..., Tmu, respectively), switching in complementary fashion. This provides an inverter arrangement having only one regulating and control device (8) for n servo components (2, 4, 6), the load current being distributed symmetrically to the n servo components (2, 4, 6).

Figure 1

Description

21~13~8 Proces~ and circuit arrangement for operating an inverter arrangement with n parallel servo components The invention relate~ to a proce~ for operating an inverter arrangement with n parallel servo components in each case consisting o~ m converter ~alves, these n servo component3 being supplied from a common direct-voltage source at the input end and being combined with one another at the output end by means of a tran~former followed by a ~ilter capacitor circuit, each servo component being provided with at least m/2-1 measuring device~ for detecting actual valu~ of the phase output currents, and the outputs of the inverter arrangement being provided with mea~uring device for detecting actual value~ of the phase output voltage and for ~etecting actual value~ of the capacitor pha~e currents, and to a circuit arrangement for carrying out the proces~.
DE 36 02 496 C2 discloses an inverter arrangement with n parallel inve~ter~ whose output current~, added to form a sum current, are regulated in such a manner that their phases essentially corre~pond to one another and their amount~ are in each case l~n~tLmes the amount of the sum current. Each inverter contain~ a power section and a regulating and control device. A fully controlled single-phase brid~e circuit i3 provided as power section.
The reyulating and control device contains a ma~netiza-tion current regulator, a voltage regulator, a comparator, a triangular wave generator and a plurality of add~r~. In addition, ~his inverter arrangement comprise~ mea~uri.ng device~ for detecting the output currents o all n inverter~, a ~umming device or forming a ~um current signal corre~ponding to the sum of the output current~ d~tected, a dividing devicP for generating a current reference ~ignal which corresponds to the sum current divided by n, and actual current value forming devices for forming actual current ~alue signal~.
Furthenmore, ~ ~ current value forming ~evice for ', ~ "',, ~,: ,' ~:

generating a ~ current value in accordance with the ~mount of the component of that current reference signal whose phase i~ equal to a r~ference phase is provided, (n-l~ actual current value forming devices form ~n-1) S actual current value signal~, each of which correspo~ds to the amount of that component of the output current of an in each case different one of (n-l~ of the inverters whose phase i9 equal to the reference phase, and the device to which the difference between the ~u~lh~
curr~nt value ~lgnal and a respective actual current value signal of the output currents is applied consis~s of (n-l) curr~nt regulators such that the output currents of (n-l) o~ th~ inverters are regulated.
disadvan~ageous factor in thi~ inverter i3 that n lS complete inverter~ (power section and regulating and control device) are operated in parallel and higher~level load current compensating regulation i8 al90 required.
The invention i~ then based on the object of simplifying the inverter arrangement initially mentioned in such a manner that no higher-level load current regulation is needed and the expenditure for the regulating a.nd control device becomes independent of the numher of inverters or part-inverters operated in parallel.
According to the invention, this object is achieved by the characterizing features of claim 1. The proce~3 according to the invention i8 based on the n parallel ~ervo components, consisting in each case of m converter valve~, being considered aR one servo component. For thi~ rea~on, m drive signals are ~enerated for each pha~e by mean~ of the actual and ~ values of the phase output volta~e of the inverter arrangement and of the actual and ~ values of the capacitor current of the filter capacitor circuit with the aid of a voltage regulation with aecondary current regulation and a sampling voltage, that i~ to say, one control ~ignal for each of the m converter valve~ of one servo component. Since, however, n aervo componenta are , : ,, . . ~ , .

2~3~

operated in parallel, one drive signal i9 in each case supplied to n converter valves operated in parallel.
For each phase and for each servo component, two converter valves are alway~ pxovided which switch in complementary fashion. The switching state of the mxn converter valves of the n servo components is detected individually. The switching ~tate~ of the n parallel converter valves of the n ~ervo components form an enable signal at the precise moment when all n parallel conver-ter valves are in the off state. That i6 to say, thedrive signal for the n parallel converter valves switch-ing in complementary fa~hion i enabled only with the off-state ~ignal of the converter valve with the greatest ~torage time of the n parallel converter valves. ~y generating in each ca~e m enable signals, the n parallel converter valves of the n servo components are in each case considered as one converter valve by the regulating and control device. The result i~ that the load current i~ symmetrically distributed to the n servo components without requiring current compensating regulation.
Si~c2 the ~e~vo components are constructed with nonlinear converter valve~ and it cannot be a~sumed that in each case n parallel converter valves have correspond-ing characteristic data, the output voltages of the servo components are different and can al~o contain different voltage/time areas (DC component). The consequence of thi~ i5 ~aturation phenomena in magnetically passive component~.
In an advantageous process, the actual value~ of the phase output current~ datected are in each case added with respect to phase to form a phase ~um current and are then integrated to form a correction value. Each phase correation value i~ ~ubtract~d from a corresponding generated pha~e ad~u~tment voltage, from which drive slgnals are then generated by means of a sampling voltage. Due to this DC component regulation of the phase 5~m current, the tran~former can no longer go intv ~aturation~

, . .: .: : , : .

::, : :::: ::: :, ,. ': : : .:
:: ::: : : . , : : .
: - :: :

3 ~ ~ !

A circuit arrangement for carrying out the process and the advantageous developments of this circuit ~rrangement can be found in claims 3 to 6. By using the l~gic circuit which jointly supplie~ each of the m drive signals to in each ca~e n parallel converter valves of the n servo component~ and in each case generates one enabl~ signal or the n parallel converter valves switch-ing in complementary fashion, only one clrcuit arrange-ment, al~o called regulatin~ and control device, is needed for n servo components. That is to say, the n parallel servo co~ponents appear as one servo component to the regulating and control device. The regulating and control device for n servo components can be expanded at any time to n+x servo components by simply extending the - 15 logic circuit and the current ~um forming circuit. When expanding from n ~ervo components to n+x servo compo-nents, the number of primary and secondary windings of the transformer must also be extended rom n to n+x primary and secondary windings.
In further explanation of th~ invention, refer-ence i~ made to the drawing t in which an exemplary ~mbodiment of an inYerter arrangement with three parallel ~ervo component is diagrammatically illustrAted, and in which:
Figure 1 show~ an inverter arrangement with three parallel servo components, F~gure 2 shows a ~lock diagram of a control voltage device of the regulating and control device according to Figure 1, Figure 3 3how~ an m-th ~ection of a logic circuit of the regulating and control device according to Figure 1, Figure 4 show~ the phas~ output current I~ and I~W2 of two parallel 3ervo component~ of the inverter arrangement of Figure 1 in a diagram versus time t, Figure S shows a drive signal UA~1 in a diagram versus time t, :
, , .

$ ~ 3 ~ ~ ~
Figures 6 and 7 show the base currents of two of the n parallel converter valves in each case in a diagram versu~ time t, Figure 8 ~howY an enable 3ignal UFS1 in a diagr~l versus time t, Figure 9 shows a drive 3ignal UAT2~ which is complementary to the drive signal of Figure 5, in a diagram versus time t, and Figures 10 and 11 show the base current~ of two of the n parallel converter valve~ which are driven by the complementary drive signal, in each case in a diagxam versus time t.
The inverter arranyement shown in Fi~ure contains three servo components 2, 4 and 6 and a common regulating and control arrangement 8. The inverter arrangement described i~ basically suitable for an arbitrary number n of parallel servo components and the case of n=3 and m=6 i~ selected only by way of example for the arrangement 3hown in Figure 1 and described in the text which follows. The ~ervo component~ 2, 4 and 6 have the same configuration with respect to one another.
The ervo cQmponent 2 and 4 and 6, respectively, consists of six converter valves Tl1 to T61 and Tl2 to T62 and Tl3 to T63/ respectively, which are configured as three-phase bridge circuit. Commercially available transistor modules with integrated regenerating diode~, also called freewheeling diode~, are used a~ valve~ Tll to T61 and Tl2 to T6~ and Tl3 to T63, re~pectively. It should be empha~ized at thi~ point that for the reasons mentioned initially the proce~s de~ribed here and the inverter arrangement de~cribed are suitahle, in particular, for the fast~witching but power-limited power transi~tox~.
Regardle~ of this, the proce~s and arrangement can al~o be used in thP case o ~ervo component~, the bridge clrcuit3 of which do not have power transistors but thyri~tor3, GTOY or other switching elements as valves.
The servo components 2, 4 and 6 are fed at the input end rom a common direct-voltag~ source U~. A

. ... .

~8~3~
-- fi "- !
battery or a mains powered rectifier, not shown in this figure, can be provided a~ direct-voltage source Vz. At the output end, the servo components 2, 4 and 6 are combined with one another by means of a transformer 10 followed by a ~ilter capacitor circuit 12. The transformer 10 has on one core three primary windin~s 14, 16 and 18, which in each cas~ con~ist of three delta-connected windings 20, and three secondary windings 22, 24, and 26 which in each case also con~ist of three windings 2a. These winding~ 28 of the secondary windings 22, 24 and 26 are electrically connected in 3exies with respect to phase. Owing to the us~ of thi~ transformer 10, the servo component~ 2, 4 and 6 are decoupled from one another. The de¢oupling i~ equal to the ~tray induc-tance~ between the primaxy winding~ 14, 16 and 18. 5ince the stray inductances between the primary and secondary winding~ 14, 16~ 18 and 22, 24 and 26 are equal and larg2 enough, no output filter inductances are needed. Together with the stray inductance~ of the primary and secondary winding~ 14, 16, 18 and 22, 24, 26, the filter capacitor cixcuit 12, which consi~t~ of three delta-connected filter capacitors 30, 32 and 34, smooths the output voltages UR~ U5 and Ul. The actual values of at Ieast two pha~e output voltages UR and Us are detected by means of measuring devices 36, and the actual values of at lea~t two capacitor phase current~ I~ and IFS are detected by means of mea~uring dev;.ce~ 38.
Each servo component 2 and 4 and 6, re~pectively, exhibit~ at the output end at least two mea~uring devices 40 and 42 and 44, re~pectively, by means of which the actual value~ of two pha~e output current~ IRWI and Is~1, and IRW2 ~nd ISW2l and I~3 and IsW3, r~spectively, are datected. Each ~ervo component 2 and 4 and 6, re~pectively, i8 al~o a~ociated with a drive device 46 a~d 48 and 50, respectively, each drive device 46 and 48 a~d 50 for each converter valve T11 to T61 and T12 to T62 and T13 to T63 exhibiting a drive circuit~

:

~ ~: `:,: : . ,: :

- 2 ~ 3 ~
, The regulating and cont~ol devica 8, that is to say the circuit arrangement of the process accordirlg to the invention, contains two control voltage device~ 52 and 54, three modulation stages 56, 58 and 60, a 5ampling voltag~ generator 62, a drive signal device 64 and a logic circuit 66. Figure 2 shows a block diagram of a control voltage device 52 and Figure 3 ~how3 the con-figuration of the logic circuit 66, only one channel of thi~ logic circuit 66 being illustrated in greater detail~ for reasons of clarity. The modulation ~tage 56 and 58 and 60~ respect~vely, con~ist~ of a comparator 68 and 70 and 72, resp~ctively, and a comparator 74 and 76 ~nd 78, reRpectively. At the positiv~ input of the comparator 68 and 70 and 72, re~pectively, the phase control voltage U~ and Usst andl re~pectively, the corrected phase control voltage Ul~t, respectiv~ly, i~
pre6ent. At the first negative inp~t of the comparator 68 and 70 and 72; respec~ively, a sampling voltage U~ i~
present which is ge~erated by the sampling voltage generator 62. A txiangular-wave voltage, th~ requency of which i~ a multiple of the Xundamental frequency of the inverter output voltage URt U5 and U~ i~ provided a8 sampling voltage u~. At the ~econd negative input of the comparator 6B and 70, re~pectively, a correct~on value Ula~ and UI~ re~pectively, i~ present. It i~ known that the modulation stage 56 and 58 and 60, respectively, generate~ a pul~e-width-modulated phasa control voltage U~ and U~ and U~, respectively. These pulse-width-modulated phase control voltage U~, U~ and U~ are ~upplied ~o th~ drive signal device 64, which generate~
from these BiX drive signalB U~T1 to UAT~ in familiar manner. Each o~ these drive ~ignals UA~1 to U~6 1~ in each case supplied to one channel of the logic circuit 66, the outputs of which are connected to the driv~ device~ 46, 3S 48 and 50. The status inpUts of each channel of the logic circuit 66 are combined with the drive d~vices 46, 48 and 50 and the enable output of each channel i~ connected to a control input of the drive signal device 64.

.

3 3 ~

Using this inverter arrangement, the output power can be increased 400 kVA, whereaY a power of only 150 kVA
is reached when transistor modules are directly connected in parallel, due to the mechanical construction~ In com-S parison with a known inverter arrangement, which consists of three parallel invertPrs, the expenditure for this inverter arrangement is les~, since only three servo components (power section) are operated in parallel for the inverter arran~ement according to the invention. Only one regulating and control device 8, which essentially corre~ponds to a regulating an~ control device of a part-inverter, is needed for operating this inverter arrangement. The regulating and control device 8 is extended by a logic circuit 66 and a correction section.
Figure 2 show~ in greater detail a block diagram of the control voltage device 52 according to Figure 1.
Thi~ control voltage device 52 contain~ a voltage regulator 80 and a .~econdary current regulator 82t The voltage regulator 80 is ~upplied with a phase output voltage difference QUR which i9 determined by means of a comparison of the actual value of the phase output setpolnt voltage Ua with the ~omi~ value of the phase output voltage UR* . A P-type requlator which amplifies the voltage difference ~UR i~ provided as voltage regulator 80. The currant regulator 80, which is also a P-type regulator, i3 supplied with a capacitor pha~e current difference ~I~. Thi~ current dif~erence ~I~R is determined by mean~ of a comparison of the actual value setpolnt of the capacitor pha~e current I~ with the ~effl~value of the capacitor phase current IFR~r the a~plified voltage difference value ~UR al~o being ~ubtracted from the emLn~ value of the capacitor phase current I~. ~he output of the current regulator 82 is logically combined with a negative input of a comparator 84, at the positive input o~ which the -nv~in~ value of the phase output voltage UR* is present. At the output of the comparator 8~, a phase control voltage U~t i9 obtained which is ~upplied to the modulation ~tage 56. Due to the fact that 2 ~ 3 ~
_ g - , set~oint the ~bd~r~value of the phase output voltage UR~ is also I
directed supplied to the comparator 84, dynamic processes (nominal-value discontinuitie~) are also detected.
This control voltage device 52 also contains a correction section consisting of a sum current forming circuit 86 followed by a PI-type regulator 88. If only static processes are taken into con~ideration, a I-type regulator can also be used instead of the PI-type regula-tor 88. The sum current forming circuit 86 is supplied with the actual values of the phase output currents IR~I ~
IR~2 and IR~3 of the two parallel servo components 2, 4 and 6. At the output of the sum current forming circuit a6, an actual phase sum current value IRHS i5 present which is integrated by means of the PI-type regulator 88. At the output of the PI-type regulator 88, a correction value UIRWS i~ present which is supplied to the comparator 68 of the modulation stage 56. This correction ~ection is integrated in the control voltage device 52, for in-stance.
Since the servo components 2, 4 and 6 are con-~tructed with non-linear switching elements and it is also too expensive to seiect the parallel s~itching element~ in such a manner that the characteristic data corre~pond to one another, DC component~ occur in the ~5 output voltage of the in~erter arrangement due to storage time difference~. Th~ consequence would be a saturation phenomenon in the transformer 10. U~ing the correction section ~sum current forming circuit 86 followed by PI-type regulator 88), any DC component which may be present is determined in each pha~e of the inverter arrangement by adding the phase output current~ IRW1 to IR~3 and r respectively, I~, to I~u3~ phase by phase and by integrating this actual sum phase value IR~ Since this DC component is ~ubtracted from the pha~e control voltage UR~t as correction value Ul~s, the DC component is corrected to a value of zero.
The different switching time~ of the parallel converter valves T1l to Tl3 and, ..., and T61 to T63, ": . ,: ~: : .

3 ~
-- 10 -- i respectively, al~o produce different alternating-current cQmponents which are minimized by mean~ of the tranR~ormer circuit 10. In thi~ arrangement, the primary-s~condary ~tray inductances must be equal. The current is impressed by the series-connected winding~ 28 of the secondary windings 22, 24 and 26.
Figure 3 shows in greater detail a first channel of the ~ix-channel logic circuit 66. At a first terminal 90 of the control input of the first channel shown, a drive signal UAT1 i~ present, a positive voltage P15 (+ 15 V) being present at the second terminal 92 of thi~
control input. Thi.s drive signal U~ to be supplied simultaneously to the converter valves T1l, T12 and Tl3 of the three parallel servo components 2, 4 and 6. For this reason, three optocoupler~ 94 are electrically connected in ~eri~s at the transmitting end. At the receiviRg end, each optocoupler 94 in each case connects the base of a converter valve, the converter valves 'rll, Tl2 and 'rl3 in the example shown, to a corresponding drive ~ircuit which i9 not shown for reason3 of clarity but is in each ca~e component of the drive device 46 and 48 and 50, respectively. Of the three servo components 2, 4 and 6~ in each casa only a fir~t bridge arm 96r 98 and 100, in each case con~isting of two electrically series-connected converter valves Tl~ and T2l, and Tl2 and T22,and Tl3 and T23, re~pectively, i8 shown. Three further optocouplers 102 are present in the first channel shown, which in each case determine the switching state of the converter valve T1l and Tl2 and Tl3, respectively, at the transmitting end by evaluation of the base-emitter voltage~ present a~ ~he status input~ 104, 106 and 108.
At the receiving end, each optocoupler 102 controls one of three electrically series-connectPd switches 110. When the converter valve Tll and Tl2 and Tl3, re~pectively, goes ko the off state, the switch 110 i~ switched to conduct by means of ~n off ~ignal Uof~1l and UO~f12 and Uoffl3, respectively, a~ the receiving end. At a first terminal 112 o the enable output of this ~erie~ clrcuit of ..

,: ~ .~ :: - :
~ . - :

3 3 ~

switches 110, an ena~le 3ignal U~sl is present precisely when all switche~ 110 are closed, a negative voltage N21 (- 21 V~ being pre~ent at its second terminal 114. Thi~
enable signal UFS1 generated is supplied to a control input of the drive ~ignal device 64.
The operation of the logic circuit 66 of the regulating and control device 8 according to Figure 1 i9 now explained in greater detail with reference to Figure~

4 to 11. At time t~, the drive signal ~TI changes from a low level ~on stats) to the high l~vel (off state) in accordance with the variation with time of Figure 5~ This drive signal U~T1 jointly drives th~ three converter valves T11, Tl2 and Tl3 of the three parallel servo components 2, 4 and 6, a~ shown in Fiqure 3. For the lS explanatlon of the operation, only the phase currents IR~
and I~2 of two servo components 2 and 4 are shown as excerpt~ (approximately one commutation period) in Figure 4, for rea60ns of clarity. The pha~e output current I~W
and XRW21 re~pectively, i~ composed of two part-currents IRW1D and I~D~ and IRW21 and I~22, respectively. As a consequence of the drive signal UAT1, the ba~e currents ~ and I~T~ are reversed after a ~hort delay time. Since the two eonverter valve~ Tl1 and Tl~ of the parallel servo component~ 2 and 4 do not have identical characteristic data, the storage times of the two converter valve~ T1 and T12 are different~ From time t~ to th~ respective off state of each convertex valve Tl~ and T12t the part current I~1D and I~2~, respectively, o~ the phase output current IRW1 and I~2, re~pectively, flow~ via a freewheel-ing diode, not hown in graater detail, con~ected electr-ically in parallel with the converter valve Tll and T1~, re~pect.ively. The converter valve Tl1 is in the off state at time t2 and the converter valv~ T12 i~ in the off state at time t3. Since the converter valve T21, which switche~
in complementary fashion ~o the converter valve Tl~
not yet driven at tLme t2~ no further pha~e output current I~l can flowu At tLme t2, an off 9ignal UOr~ll i9 generated by mean of the optocoupler 102, which is used for . ''' ~ , ' ' " ' . . ',. ' ~ .

2~ ~ 33~ 1 driving the switch 110 ~Figure 3). At time t3, an output signal UOffl2, which indicates the o~f state of the converter valve Tl2 and by means of which a further switch 110 i~ driven, is generated by means of a further optocoupler 102. The third converter valve T13, which is driven jointly with the converter valves Tll and T12, ha~
changed to the off state, characterized by the generation of an off signal UOftl~, within the time difference t3-t2 in accordance with its storage time. That i3 to say, at time t3 the three electrically series-connected switches 110 of the first channel of the logic circuit 66 are switched to conduct, as a result of which an enable signal Uys"
which is shown in a diagram versus time t in Fi~ure 8, is pre~ent at the enable output 112 - 114. This enable signal Up5l enables the drive signal U~T2 for the converter valves T2" T2, and T23, which switch in complementary fashion to the converter valves Tl~, T12 and Tl3. That is to 3ay the drive signal uA~r2 goes from the high level (off state) to ths low level ( on state ) in accordance with Figure 9. With a ~light time delay, the base current I~T21 and I~T~, re~pectively, flows at time t; and t5, respectively, as a result of which the converter valve T2l and T22, respectively, carries the part-current IRWal and I~w~, respectively, of the phase output current IR~I and 25 IRW2/ respectively.
The time interval t3-t, corresponds to approxim-ately 20 to 25 ~sec. Due to the different characteristic data of the converter valves Tl~ and T12, the current di~tribution to the individual parallel servo components 2 and 4 i8 not symmetric, ~ince the phaqe output current IR~1 (part current IR~ID) ha~ already reached the value zero at time t~, whereas the phase output current IR~2 ( part CUrrent IR~2D) reaches the value zero only at time t3.
Using the proces~ for operating an inverter arrangement with a plurality of parallel servo components 2, 4 and 6, the parallel converter valves Tll, T1~ and T13 to T61, T62, T63 for the regulating and control device 8 in each ca~e appear as one converter valve. Thi~ also provide~ a :,- ~: ... . .
.

, . . . . . . .
~ !
:, ~$3.33~ ;

~:, symmetric current distribution over a plurality of servo component~ without using curren~ compensating regulator.

. ::: . ,: : , , .. ~.. , . , . ; , -- : : : - . .: . -.,: . ~ ~ . ,: : :.
- :: .: : :- . ,;. - ~ , , , :
, , , , ~ :. , : :, , ~ . , . : .. : . : :
: ~: ... .:.... : :

Claims (7)

Patent Claims

1. A process for operating an inverter arrangement with n parallel servo components (2, 4, 6) in each case consisting of m converter valves (T1n, ..., Tmn), these n servo components (2, 4, 6) being supplied from a common direct-voltage source (UI) at the input end and being combined with one another at the output end by means of a transformer (10) followed by a filter capacitor circuit (12), each servo component (2, 4, 6) being provided with at least m/2-1 measuring devices (40, 42, 44) for detecting actual values of the phase output currents (IRWI, ISWI, ..., IRWn, ISWn), and the outputs of the inverter arrangement being provided with measuring devices (36, 38) for detecting actual values of the phase output voltage (UR, US) and for detecting actual values of the capacitor phase currents (IFR, IFS), wherein a) at least m/2-1 phase control voltages (URST, ISSt) are generated by means of a comparison of actual and setpoint values of the phase output voltages (UR, US) and of a secondary comparison of actual and setpoint values of the capacitor phase currents, b) m drive signals (UAT1, ..., UATm) are generated by means of a sampling voltage (US) from m/2 phase control voltages (URSt, Usst, UTst) generated, one drive signal (UAT1 and ...
and UATm, respectively) each being jointly supplied to n parallel converter valves (T1, Tl2, ..., Tln and ... and Tm1, Tm2, ..., Tmn, respectively,) of the n servo components (2, 4, 6), c) in each case one enable signal (UFS1 and ... and UFSm, respectively) is generated precisely when each of the n parallel converter valves (T11, Tl2, ..., Tln and ... and Tm1, Tm2, Tmn, respectively) of the n servo components (2, 4, 6) generate an off signal (Uoffl1, UOffl2, ..., UOffln and ... and Uoff11, Uoff12, ..., UOffmn, respectively,), and d) each enable signal (UFS1 and ... and UFSm respectively) generated enables a drive signal (UAT1 and ... and UATm, respectivaly) for n parallel converter valves (T1l, T12, ...., Tln and ... and Tml, Tm2, ..., Tmn, respectively), switching in complementary fashion, of the n servo components (2, 4, 6).

2. The process as claimed in claim 1, where.in a) the actual values of the phase output currents (IRWI, IRW2, ..., IRWn and ISW1, ISW2, ..., ISWn, reqpectively) are in each case added with respect to phase to form an actual phase sum value (IRWS and ITSWS,respectively), b) each actual phase sum value (IRWS and ISWS, respectively) is integrated to form a correction value (UIRWS and UISWS, respectively), and c) each correction value (UIRWS and UISWS, respect1vely) is subtracted from a corresponding phase control voltage (URSt and USSt) respectively).

3. A circuit arrangement for carrying out the process as claimed in claim 1, wherein at least m/2-1 control voltage devices (52, 52), m/2 modulation stages (56, 58, 60) and one drive signal device (64) followed by a logic circuit (66) are provided, each control voltage device (52, 54) being supplied with an actual value and setpoint value of a phase output voltage (UR, UH* and US, US*, respectively) of the inverter arrangement and an actual value and a setpoint value of a capacitor phase current (IFR, IFR* and IFS, IFS*, respectively) of the filter capacitor circuit (12), each of the m outputs of the logic circuit (66) in each case connects each of the n parallel converter valves (Tll, T12, ..., Tln and ...
and Tml, Tm2, ..., Tmn, respectively) to one drive circuit (46, 48, 50), the switching states of these n parallel converter valves (T11, Tl2, ..., Tln and ..., and Tml, Tm2, ..., Tmn, respectively) are in each case present at one of the n status inputs (104, 106, 108) of the logic circuit (66), and in each case one of the m enable outputs (102) of the logic circuit (66) is connected to one control input of the drive signal device (64).

4. The circuit arrangement as claimed in claim 3, wherein the control voltage device (52, 54) contains a sum current forming circuit (86) followed by an I-type regulator, the output of the I-type regulator being connected to a second negatlve input of a comparator (68, 70) of the modulation stage (56, 58), and the actual values of the phase output currents ( IRWI, IRH2, ..., IRWn and ISW1, ISW2, ..., ISWn, respectively) of the n servo components (2, 4, 6) being present at the inputs of the sum current forming circuit (86).

5. The circuit arrangement as claimed in claim 3, wherein the logic circuit (66) contains mxnx2 opto-couplers (94, 102), in each case n optocouplers (94) being electrically connected in series at the transmitt-ing end and in each case being supplied with one of the m drive signals (UAT1 ..., UAT2), these n optocouplers (94) in each case electrically conductively connect one of the n parallel converter valves (T11 T12, ..., Tln and ...
and Tm1, Tm2, TMn, respectively) to the corresponding drive device (46, 48, 50) at the receiving end, and in each case n optocouplers (102) are connacted in each case to the base and the emitter of one of the n parallel converter valves (T11, Tl2, ..., Tln and ... and Tm1 Tm2, ..., Tmn, respectively) at the transmitting end, these n optocouplers (102) actuating in each case one of n electrically series-connected switches (110) at the receiving end, and it being possible to pick up one of the m enable signals (UFS1, ... UFSm) at the output (112) of this series circuit.

6. The circuit arrangement as claimed in claim 4, wherein a PI-type regulator (88) follows the sum current forming circuit 186).

7. An inverter arrangement with n parallel servo components (2, 4, 6) in each case consisting of m conver-ter valves (T1n, ..., Tmn) and with a circuit arrangement as claimed in claim 3, these n servo components (2, 4, 6) being supplied from a direct-voltage source (Uz) at the input end and being combined with one another at the output end by means of a transformer (10) followed by a filter capacitor circuit (12), each servo component (2, 4, 6) being provided with at least m/2-1 measuring devices (40, 42, 44) for detectinq actual values of the phase output currents ( IRWI, IRW2, ..., IRWn, ISW1, ISW2, ..., ISWn), and the outputs of the inverter arrangement being provided with measuring devices (36, 38) for detecting actual values of the phase output voltage (UR, US) and for detecting actual values of the capacitor phase currents (IFR, IFS), wherein the transformer (10) exhibits n primary and secondary windings (14, 16, 18 and 22, 24, 26), each nth primary winding (14, 16, 18) and each nth secondary winding (22, 24, 26) in each case consisting of m/2 windings (20, 283, the m/2 windings (20) of each nth primary winding (14, 16, 18) being connected to form an m/2-polygon, and the m/2 th winding (28) of the n secondary windings (22, 24, 26) in each case being electrically connected in series.