CA2063229A1 - Binary phase shift keying modulation system and/or frequency multiplier - Google Patents
Binary phase shift keying modulation system and/or frequency multiplierInfo
- Publication number
- CA2063229A1 CA2063229A1 CA 2063229 CA2063229A CA2063229A1 CA 2063229 A1 CA2063229 A1 CA 2063229A1 CA 2063229 CA2063229 CA 2063229 CA 2063229 A CA2063229 A CA 2063229A CA 2063229 A1 CA2063229 A1 CA 2063229A1
- Authority
- CA
- Canada
- Prior art keywords
- present
- phase shift
- shift keying
- binary phase
- frequency multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Amplitude Modulation (AREA)
Abstract
A low cost spread spectrum modulator for BPSK, or Binary Phase Shift Keying capable of outputting the high modulation rate and suppressed carrier output needed in spread spectrum systems. The present invention provides high quality BPSK
modulation without the double balance mixers as required in the prior art, thereby dispensing with the necessity of complex transistor/potonciometer or diode/transformer arrangements. The present invention provides BPSK modulation utilizing only one transformer, which can be adjusted for carrier suppression and two transistors, FET's, or digital logic gates or the like, allowing the present system to be driven from low power CMOS logic levels, yet producing eight db of gain. The present invention may also be utilized as a frequency multiplier, with the utilization of the appropriately high frequency transistor, FET, digital logic gate, or the like.
modulation without the double balance mixers as required in the prior art, thereby dispensing with the necessity of complex transistor/potonciometer or diode/transformer arrangements. The present invention provides BPSK modulation utilizing only one transformer, which can be adjusted for carrier suppression and two transistors, FET's, or digital logic gates or the like, allowing the present system to be driven from low power CMOS logic levels, yet producing eight db of gain. The present invention may also be utilized as a frequency multiplier, with the utilization of the appropriately high frequency transistor, FET, digital logic gate, or the like.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA 2063229 CA2063229C (en) | 1992-03-17 | 1992-03-17 | Binary phase shift keying modulation system and/or frequency multiplier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA 2063229 CA2063229C (en) | 1992-03-17 | 1992-03-17 | Binary phase shift keying modulation system and/or frequency multiplier |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2063229A1 true CA2063229A1 (en) | 1993-09-18 |
CA2063229C CA2063229C (en) | 1999-09-07 |
Family
ID=4149443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA 2063229 Expired - Fee Related CA2063229C (en) | 1992-03-17 | 1992-03-17 | Binary phase shift keying modulation system and/or frequency multiplier |
Country Status (1)
Country | Link |
---|---|
CA (1) | CA2063229C (en) |
-
1992
- 1992-03-17 CA CA 2063229 patent/CA2063229C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CA2063229C (en) | 1999-09-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |