CA2041740A1 - Apparatus incorporating ic card reader for use in a computer device - Google Patents

Abstract

Title: Apparatus Incorporating IC Card Reader for use in a Computer Device Inventors: Terence Wister, Stephen J. Feldman, Roddie R. H. Leung ABSTRACT OF THE DISCLOSURE

An apparatus has a disk drive unit, and IC card acceptor unit for reading and writing to an IC card and an access control unit. It is for use in a computing device including a disk drive controller. The access control unit is connected between the disk drive controller and both the disk drive unit and the IC card acceptor unit.
This access control unit is adapted to selectively connect the disk drive controller to one of the disk drive unit and the IC card acceptor unit, for read/write operation and is such that it simulates the disk drive unit when providing communication to the IC card acceptor unit. The computing device would be provided with appropriate interrupt handlers and a communication port driver, so that the apparatus can simply be connected to the port where a conventional disk drive unit is usually connected.

Description

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RBP File No. 0432-170 Title: Computer Device Incorporating IC Card Reader FIEL.D OF l'HE I~VENTION
This invention relates to IC card technology and computer devices. More particularly, it is concerned with the integration of an IC card reader/writer mechanism or unit with portable computer products or devices.

BACl~GROUND OF I~ VENTION
Over recent years, personal computers have become progressively smaller and more compact, whilst at the same time becoming more powerful. At the present time, there are available a number of portable or laptop computers, which can be readily transported or carried around by a user.
For a computing device that is in a fixed location, controlling access to the device is relatively simple. For a portable or laptop computer, controlling access is much more difficult. There is also the possibility that the device may simply be lost, e.g. by the user simply accidentally leaving it in some public place, where it is removPd by someone else.
It has thus been recognized that it is desirable to provide some unit or mechanism which restricts access to a computing device to an authorized user or users. One known technique relies upon the use of IC (integrated circuits) cards. An IC card is a plastic card physically comparable to a conventional plastic credit card, but incorporating a small processing unit and memory, and including electrical contacts for power supply, data transfer, etc.
Such cards require a card acceptor mechanism, capable of reading and writing to the card. A variety of such card acceptor mechanisms are known, and indeed the assignee of the present invention currently produces a number of standard card acceptor mechanisms. One type of 2~7~

card acceptor mechanism is a stand-alone unit, which has a number of disadvantages. It requires a separate power supply and is bulky. It is highly inconvenient for a personal computer user to have to carry a separate card acceptor unit, and as a separate unit, it does not provide that great a degree of security.
Another known card acceptor mechanism of the assignee of the present invention is intended for integration into a portable personal computer. Such an acceptor mechanism has dimensions comparable to a half height diskette drive, and is intended to replace the B-drive in a two drive PC. Internal cabling is provided to connect this card acceptor mechanism to the rest of the computer. The arrangement is such that this results in the loss of the B-drive, and also the loss of the serial port, which is used for the connection to the acceptor mechanism.
A few years ago, it was satisfactory to lose a diskette drive, since it was common for personal computers to have dual diskette drives. Now, it is becoming increasingly common for personal computers, and certainly portable computers, to have a single hard disk and a single floppy diskette.
It is therefore desirable to provide some way of integrating a card acceptor mechanism into a personal computer, without losing any of the disk drives.

ST,~IIMARY OF TEIE PRESENT INVENTION
In accordance with the present invention, there is provided, in a- computing device, an apparatus comprising: a disk drive unit; a card acceptor unit, capable of reading and writing to an IC card; a disk drive controller; and an access control unit connected between the disk drive controller, and both of the disk drive unit and the card acceptor unit, the access control unit being adapted to selectively connect the disk drive controller to one of the disk drive unit and the card acceptor unit L r for read/write operation, the access control unit simulating the disk drive unit when providing communication to the card acceptor unit.
Further, in this specification including the claims, reference to disk drive unit Pncompasses any suitable storage medium, and similarly disk drive controller encompasses any suitable control device for controlling such a storage medium.
In this specification including the claims, the term IC Card encompasses both known Integrated Circuit Cards and any other element that has data processing and/or storage facilities, so that communication can be effected between that element and the computing device.
Preferably, the apparatus of the present invention is combined in a package which fits into the standard bay for a floppy diskette drive. At the present time, many personal computers provide a full 2/3 half height 3.5 inch high density floppy diskette drive. In the present invention, this is replaced by a 1/3 half height 3.5 inch high density floppy diskette drive, thereby leaving room for the card acceptor and a printed circuit board carrying the access control unit.
The invention provides a mechanism, to access an IC card, which does not force the loss of a FDD or a serial communications port. The existing floppy diskette controller (FDC) is connected by the access control unit utilizing communications and electrical requirement from the computing device, to either the floppy disk drive or the card acceptor unit. The card acceptor mechanism, is accessed by a memory resident communication port driver of the computing device, via the FDC. The FDC reads and writes information to/from a disk drive in Modified Frequency Modulation (MFM) formatted data. To facilitate the working of the FDC, the access control unit mimics the FDD. When the access control unit receives data from the FDC, it decodes the MFN data into binary format and transmits the request to the IC card via the serial I/O of the access control unit. Vice-Versa, when the card returns data to the access control unit, it encodes the data to NFM form which is then sent via the FDC. The communication port driver ensures that all data transmitted through the FDC is in the appropriate format, i.e. simulating communication with a disk drive unit The data from the disk drive is in an MFM
format, whereas from the IC card acceptor mechanism the data is serial, preferably in accordance with the T-14 protocol. The T-14 protocol is a standard protocol, in Japan at least, for IC cards. It is preferred for the present invention to be provided in accordance with this protocol.

BRIEF DESCRIPTION OF THE DRAWING FIGURES
For a better understanding of the present invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, which show a preferred embodiment of the present invention and in which:
Figure 1 is a perspective view of an apparatus including a card acceptor mechanism and disk drive in accordance with the present invention;
Figure 2 and 3 are front views of an apparatus in accordance with the present invention~ for replacing a conventional floppy disk drive;
Figure 4a is a schematic block diagram of the circuit of the apparatus of Figure 1, and Figure 4b shows details of the pins for a Programmable Gate Array in Figure 4a;
Figures 5a and 5b are block diagrams of an MFM
encoder and an MFM decoder respectively;
Figures 6a and 6b are diagrams showing variations of voltage with time for an application send request and an application read status/data;
Figure 7 is a schematic block diagram of a 2Q~7~

firmware overview;
Figure 8 is a schematic block diagram of the firmware main loop;
Figures 9a and 9b are a schematic block diagram of a T-14 protocol checker;
Figure 10 is a schematic block diagram of a command dispatcher;
Figures 11 - 16 are schematic flow charts of individual commands;
Figure 17 is schematic flow chart of a terminate and stay resident routine;
Figure 18 is a schematic diagram of device handler main line code;
Figures 19, 20 and 21a, are schematic flow diagrams for interrupt handlers for Interrupts 9h, 13h and 14h;
Figures 22a and b are schematic flow charts for a floppy disk simulator;
Figures 23 a, b and c are schematic flow charts for a serial interrupt service routine; and Figure 24 is a graphical schematic of timing for IC card access.

DESCRIPTION OF THE PREFERRED EMBODINE~T
Referring first to Figure l, the reference 1 denotes the combined unit or apparatus, comprising an IC
card acceptor mechanism and a floppy disk drive unit. The combined unit 1 has a front plastic bezzle 3, providing access to a 3.5" high density floppy diskette drive (FDD), indicated at 5. At the top of the bezzle 3, there is a slot 7 for receiving an IC card.
Extending back from the plastic bezzle 3 are two left and right hand side brackets 9, which support a printed circuit board 11, the FDD 5 and a card acceptor mechanism 15. The printed circuit board 11 has the components of an access control or interface unit mounted on it.

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An IC card acceptor mechanism, for reading and writing to an IC card is indicated at 15. Thus, it can be seen that the PCB 11 is a generally L-shape and is configured to fit around the IC card acceptor mechanism 15. An LED 53 is provided, whose function is detailed below.
The apparatus 1 is configured to be mechanically and electrically equivalent to a full 2/3 half height 3.5 inch high density floppy diskette drive. Hexe, the original disk drive is replaced by a 1/3 half height 3.5 inch high density floppy diskette drive, preferably Matsushita ZA0~56PO1. This drive would be located under the PCB 11.
Turning to Figure 2, there is shown a configuration for adapting the present invention to a personal computer incorporating a 1/2 height high density FDD. The front view of the bezzle 3 shows the opening for the IC card acceptor at 16, and an LED, indicating IC card activity, is shown at 53. Again, the reference 5 indicates the FDD.
Figure 3 shows a configuration for adapting the present invention to a personal computer alrsady incorporating a 1/3 half height high density FDD. Here, in view of the reduced size of the FDD, there is simply insufficient space to incorporate both the FDD, the card acceptor mechanism and PCB 11 within the computer as a whole. Here, the PCB 11 and the card acceptor 15 are mounted together behind a front bezzle 21 with a slot 22 for the IC card. A connector 25 is provided for providing a connection to a separate FDD. The connector 25 is provided with a cover door 26. This has the advantage of integratinq the IC Card Acceptor into the computer device, although it does require the FDD to be provided separately.
Referring now to Figure 4a, this shows a block diagram of the overall circuit, with like components being given the same reference numerals as in Figures 1, 2 and 2~4~ 7~0 3. Here, the printed circuit board 11 is indicated schematically by dotted lines.
The components mounted on the PCB 11 form an access control or interface unit, generally indicated by the reference 31. The control unit 31 has a micro-controller 33. This is an INTEL 80C31 CHMOS single chip 8-bit micro controller running at 16 megahertz. It includes two built-in timers, one for baud rate generation the other for program timing. The built-in serial port is set at 9600 baud, even parity, one start bit and one stop bit and is used to communicate to the IC card. This serial port is connected to a line, which is connected to an XILINX unit indicated generally at 37. The XILINX 37 is an XILINX Programmable Gate Array, Serial No. X3020-50 PC 68C from XILINX Inc.
The micro controller 33 has two external interrupts, which are again connected to the XILINX 37.
Parallel port one of the micro controller 33 is connected via a bus to the XILINX 37 to control the XILINX for up-loading and other purposes.
Memory capacity is provided by 8K static RAM, expandable to 32K, indicated at 45, and by 32K of OTP ROM, indicated at 47. The RAM 45 and ROM 47 are connected by an address bus 49 and data bus 51 to the micro controller 25 33 and the XILINX 37, in known manner. A latch 43 is also connected to the address and data buses 49, 51 to control data flow between the microcontroller 31 and XILINX 37.
The LED indicator 53 is connected to the micro controller 33, as shown.
The XILINX 37, when programmed, has a CPU
interface unit 55, including a register 56.
The interface unit 55 is connected by an SRAM
decode unit 57 to the SRAM 45.
An IC card control unit 59 connects the interface unit 55 to the IC card acceptor mechanism, indicated schematically at 15.
A floppy disk drive 61 and a floppy disk 2 ~

controller 63 are provided with an external connection 65.The floppy disk controller 63 would be the conventional controller forming part of the computing device. The remainder of the computing device is indicated schematically at 67. Thus, the floppy disk controller 63 provides the connection through to the access control unit 31.
The floppy disk drive controller 63 is connected to a floppy disk control unit 69, an MFM encoder 71 and an MFM decoder 73. The connection between the FDC 63 and the MFM decoder 71 is through a data separator 75, which serves to separate clock signals from data signals, in known manner.
As shown the floppy disk control unit 69 is additionally connected directly to the floppy disk drive 61.
The CPU interface 55 decodes the address and data lines from the CPU 33 and provides controls (read, write, clocks and interrupts) for the rest of the functional blocks within the XILINX 37.
The SRAM decode unit 57 provides chip select to the static RAM 45, and allows the SRAM 45 to be accessed from the CPU or microcontroller 3 via code memory and external data memory. This feature allows the access control unit 11 to upload program externally for execution. The address location is EOOOH to FFFFH.
The IC card control unit 59 provides controls through an I/O port. It connects the asynchronous port of the micro controller 33 to the IC card acceptor unit 15.
It also controls a variety of IC card functions, such as power, reset and clock.
The floppy disk control unit 69 monitors commands from the floppy disk controller 63. Any normal floppy disk access will be passed directly through the unit 69 to the floppy disk drive 61. Any card access commands will be intercepted. The connection between the disk control unit 69 and the FDD 61 will then be disabled, 9 ~ 7 ~ ~
and the access control unit 11 will then emulate the FDD
61 and acknowledge such a command to the FDC 63.
The MFM encoder 71 and MFN decoder 73 are shown in greater detail in figures Sa and 5b.
Considering first the MFN encoder 71, its basic function is to encode parallel data from the microcontroller 33, and generate serial MFM encoded data for the FDC 63. Here, timing is extremely critical, since the FDC 63 is, in effect, expecting to receive a continuous serial stream of data. Consequently, the MFM
encoder 71 has to ensure that the information that is converted into serial data is provided as a continuous stream, without any interruptions.
The encoder 71 has an 8 bit parallel port 80 providing communication between the microcontroller 33 and a parallel to serial shift register 82.
The shift register 82 is connected to a pulse generator 84, which in turn has an output that is connected to the FDC 63.
The microcontroller 33 is also connected directly to the pulse generator 84 and through a pulse suppression unit 86 to the pulse generator 84. A read data flag unit 88 is connected between the pulse generator 84 and the microcontroller 33.
The circuit continuously loads data from the 8 bit parallel port 80 into the shift register 82. Pulse generator 84 takes the serial data from the register 82 and converts it to MFM format. The pulse suppression unit 86 controls the MFM data violation in the MFM header.
The read data flag 88 checks to see when the hardware is finished with the last byte, to ensure that a fresh byte is loaded into the register 82, thereby ensuring a continuous flow of data.
Turning to the MFM decoder 73, this has, correspondingly, an 8 bit parallel port 90 connected to the microcontroller 33. An MFM data/clock synchronizer 92 has inputs for both data and a clock connected to the data ; l separator 75. The synchronizer 92 converts MFM data to NRZ (non-return to 0) serial data format. This serial data is then passed to a serial to parallel shift register 94, where the NRZ serial data is converted to parallel data.
A header detector and synchronizer 96 detects headers conventional to MFN data. It synchronizes the serial input data and lock onto each data frame. It then takes each frame and compares it to the pre-defined MFM
header data. Once the header is verified, the data flag is enabled. This enables the microcontroller 33 to receive data as input through the parallel port 90.
~ he XILINX 37 is connected to the IC card acceptor 15 by a serial data connection which essentially acts as an extension of the serial connection between XILINX 37 and microcontroller 33.
The first and second interrupt lines from the microcontroller are, in effect, continued through by lines to the floppy disk drive 61 and the IC card acceptor 15.
20The XILINX 37 has three major functions. The first function is to control the IC card interface, which controls the power, reset and communication to the IC
card. The second function is to provide interface to the floppy disk drive controller 69. The third function is to encode and decode MFM data from the floppy disk controller and provide interface to the rest of the personal computer. The XILINX provides I/O to emulate the floppy disk drive 61.
The pin configuration of the XILINX 37 is shown in Figure 4b, and the pin descriptions are given below:

PIN DESCRIPTIONS
VCC
Supply Voltage.
GND
Circuit Ground.

High order address inputs.

p~

Lower order address lines and data lines.
AT.R
Address Latch Enable input from CPU for latching the low byte of the address during access to the internal registers.
PSEN
Program Store Enable input from CPU 33 to strobe for external program memory.
XTALl input to the inverting oscillator amplifier.

Output from the inverting oscillator amplifier.
~R
Write input from CPUI active low.
RD
Read input from CPU, active low.
CLR
System clock input.
INTO
Interrupt output for IC CARD out, high = card out, low =
card in.
INTl Interrupt output to CPU 33 for motor on pulse while controller 31 is disabled. Read data flag while controller 31 is enabled and FDC read. Write data flag while controller 31 is enabled and FDC write.
~GATE
Floppy Disk Controller Write Gate output to CPU 33, to indicate Floppy Disk Controller is in data output process.
COMCLX
Clock output for Async port ( 614 KHZ ).
~DATA
Xilinx programming data input.
XLCR
Xilinx programming clock input.
XRESET
Xilinx reset input.
XDONE
Xilinx programming status output, High when program done.

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R~MRD
External SRAM read output, active low.
RAMWR
External SRAM write output, active low.
RAMCS
External SRAM chip select output, active low.
q~EST
~est input to enable production test configuration.
CP~RST
CPU reset output to reset the CPU, active high.
SCRSTIN
IC CARD reset input to indicate IC CARD in reset state, active low.
SCRST
IC CARD reset output to reset IC CARD, active low.
SCCLR
IC CARD clock output for IC CARD clock.
SCO
IC CARD data output.
SCI
IC CARD data input.
CVCC
IC CARD power control output, active high.
S~IN
IC CARD IN input, indicating IC CARD is in, active low.
DRVSEL
Drive Select input, from Floppy Disk Controller 63.
MTRON
Motor On input, from Floppy Disk Controller 63.
RDY
Ready output, to Floppy Disk Controller 63.
RDD
Read Data output, to Floppy Disk Controller 63.
WRD
Write Data input, from Floppy Disk Controller 63.
SEPCLK
Separated Clock input from External Data Separator 75.

REFCLK
Reference Clock output ( 8MHZ ), to the External Data Separator 75.
The PSEN input is for receiving the program stored in the ROM 47.
The INT0 interrupt is provided for indication of whether an IC card is in or out. It is high for a card removed, and low when the card is inserted.
The interrupt INTl indicates that a motor on pulse is present while the access control unit 31 is disabled. When the access control unit 31 is enabled, it will read a data flag and perform a read from the FDC 63;
similarly, for a write data flag, a write will be accepted from the FDC 6 3.
The WGATE output is connected to the CPU 33, to provide indication that the FDC 63 is in a data output process.
The CPURST signal provides a reset output, to reset microcontroller 33.
The SCRSTN input provides an indication that the IC card is in a reset state. It is active on low.
Similarly, the SCRST output is for resetting the IC card, and again is active on low.
The outputs SCCLK and SCO are for clock and data outputs to the IC card. The input SCI is for data from the IC card. CVCC provides power to the IC card, and is active on high. SCIN provides an indication of whether an IC card is present or not, and is active on low.
The DRVSEL input is for the FDC63, and is used to select drive for the FDD 61. The MTRON input is a standard signal from the FDC 63 which is for the FDD 61, to turn the motor on.
The RDY output is standard output for providing communication from the FDD 61 to the FDC 63 that the FDD
is ready.
The output RDD and input WRD are for reading to and writing data from the FDC 63 respectively. These are o used when the unit 31 is simulating the floppy disk drive 61.
The XILINX has the following ports with each bit having the function indicated.
Control port Address 0000, Write Bit Name Description O RDY indicate drive ready 1 5CRST Smart Card Reset 0 = reset 1 = normal operations 2 CVCC Smart Card VCC enable O = no power to card 1 = power to card 15 3 FDDISABL Floppy disable O = enable floppy disk drive 1 = disable floppy disk drive 4 TRACKO Track O line O = active 1 = not active INDEX Floppy index pulse O = active 1 = not active 6 SUPAl Suppress A1 from address header 0 = not active 1 = active 7 SUPC2 Suppress C2 from track reader O = not active 1 = active Note that the FDC63 communicates in conventional MFM formatj with the unit 31 generating all the Index header and sector information for data transfers. As the index and data header are MFM clock violations, special steps are needed to generate this condition. SUPAI and SUCPCZ bits are used for this. In the Index header generation, SUCPCZ bit is set before data "C2" is sent and reset afterwards. In the address header generation, SUPAI
bit is set and reset similarly.

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Status port Address 0000, Read Bit Name Description 0 SCRSTIN Smart Card reset input 0 = card in reset state 1 = card ok 1 SCRST_STS Smart Card reset status 0 = reset 1 = normal operations 10 2 CVCC_STS Smart Card VCC status, 0 = no power to card 1 = power to card 3 SCIN Smart Card in 0 = card out 1 = card in 4 TRACKO Track 0 line 0 = active 1 = not active INDEX Floppy Index Pulse 0 = not active 1 = active 6 SUPA 1 Suppress Al from address header 0 = active 1 = not active 25 7 SUPCS Suppress CS from track reader 0 = active 1 = not active MFM DATA PORT
Address 0001, read/write Used for input and output to Disk controller 63.
INTERNAL I/O PORTS
PORT# NAME DESCRIPTION
Pl.0 XDATA Xilinx data Pl.l XCLK Xilinx clock 35 P1.2 XRESET Xilinx reset Pl.3 XDONE Xilinx done ~4~7~

Pl.4 N/C
Pl.5 TEST Test input 0 = test mode 1 = normal 5 P1.6 GLED green LED
0 = off 1 = on P3.2 INTO Control unit 31 select interrupt 0 = selected 1 = not selected P3.3 INT1 Read buffer empty/ write buffer full P4.4 WGATE Write gate from FDC
0 = write enable 1 = not enable As detailed below, an interface for the floppy disk drive controller 63 is built into the XILINX 37.
This provides for data transfer between the disk drive controller 69 and the IC card acceptor 15, whilst emulating the floppy disk drive functions 61, i.e. so that the floppy disk drive controller 63 communicates in exactly the same manner as it would in direct communication with a conventional disk drive. When an appropriate command is sensed by the XILINX 37, then the floppy disk drive 61 is disabled, and, in essence, the control unit 31 translates the data between the different formats for the disk drive controller 63 and the IC card acceptor 15.
The interface and the XILINX 37 has a one byte buffer for data transfers and one dedicated interrupt handler at the interface.
The LED indicator 53 notifies the user of the operational status, during operation. To indicate that a card should be inserted, the LED 53 flashes slowly (for one second), and is illuminated continuously once a card has been accepted.
The IC card acceptor 15, in known manner, provides mechanical contacts for the smart card. It also 7 ~ ~

provides power on/off timing requirements. When the card is first inserted into the card acceptor 15, the electrical contacts are made. The card acceptor informs the operator by shorting out the last contact. The CPU of the card will then start a power on sequence, detailed below. On card extraction, the last contact will break first, and the power off sequence will start immediately, to ensure safe power shut down of card. A similar sequence occurs when power goes off to the controller 31 and hence to the card acceptor 15.
An interrupt 08h. is a 'Icall Timer Interrupt".
This occurs every 55 milliseconds, which the TSR a communications port driver detailed below, uses to pause between write sector and read sector. This gives the controller 31 time to perform a request. Once the delay time has expired, the interrupt 08 handler checks to see if DOS is busy. If DOS is not busy, it performs a read sector; if DOS is busy, it sets a flag NEED READ for the INT 28 handler, which will perform the read the next time it is executed.
The interrupt 28h is call "DOS free" interrupt.
This interrupt is performed by DOS when it is waiting for console I/O. This allows memory resident programs the ability to access devices without destroying DOS, because it is non re-entrant. If the NEED READ flag was set in the INT 0~ handler, the sector is read via INT 13h.
An existing application will run perfectly on an external IC card reader. Even existing software can access the control or interface unit 31, by adding one line to the "auto exec. batll file, and loading the TSR, which would be provided with the controller 31 as a retrofit kit. Existing applications will have to be linked with a new library. The line in the auto exec bat file "SET SMART = A" sets a DOS environment variable which is accessed within application programs. The variable SNAR~ has been selected to conform with the trademark under which the assignee intends to market the device, 7 ~ ~

this trademark being SMARTDRIVE. It will be appreciated that any suitable variable can be used.
The library will search the environment at start up time, i.e. initialization of RS232 port, for the variable SNART. If this variable is not set, then there will be a default, so that the application will access the reader connected to COM 1. If it is set, the application will access whichever device is indicated by the following table:
Set SMART = 1 - communications port 1 Set SMART = 2 - communications port 2 Set SMART = A-Access Control Unit on A Drive Set SMART = B-Access Control Unit on B Drive The application can change the device anytime during run time by changing the global variable A CHANNEL.
The application has full responsibility for keeping track of this variable, if it wishes to manipulate multiple IC
readers.

DESCRIPTION OF FI~MWARE A~D SOFTWARE
Figure 7 shows at 101 the main loop, from which there are two principal interrupts. The first interrupt is to a motor-on ISR (Interrupt Service Routine), indicated at 103, with the interrupt return indicated by IRET. Similarly, for serial input and output to the IC
card, there is a serial ISR 105, with again the interrupt return being shown by IRET. For the control or interface unit 31, the motor on ISR 103 provides for communication to the computer 67, whilst the Serial I/O ISR 105 provides for communication to`the IC card through IC card acceptor 15.
The main loop facilitates transition from one state to another and contains a code which processes the protocol verification, command dispatcher, CRC
calculation, commands for control unit 31, and performs buffer manipulation.

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The IC card or serial I/O ISR is activated by hardware whenever a byte is put into the SIO (serial I/O) byte buffer either by the IC card itself, or by the SIO
ISR. This routine first checks whether this interrupt was generated by a send buffer empty or a receive buffer full operation. For the send, the next byte is placed into the SIO buffer, if there is one, and following the last byte, the routine returns from the interrupt. For receive, bytes are taken successively from the buffer until the length byte is satisfied in T-14 block. The basic T-14 checks are performed as in the motor on ISR. The state is set to VERIFY PROTOCOL, and then return from interrupt.
The motor on ISR interrupt (motor on pulse interrupt) is activated by an interrupt when the motor on line is active without drive select line, for more than 16 microseconds. This interrupt routine has the highest priority and disables all other interrupts.
A timer for motor on ISR (FDD simulation) ensures that the firmware is not caught in an infinite loop. If the timer goes off, the power on sequence will be performed.
Thus the control unit 31 operates as a sequential state machine with the following interrupts:
(1) External interrupt from TSR Motor On pulse for the FDD simulator;
(2) Internal System Timer 0 interrupt for 1.2 millisecond character wait timer, and a dead man timer for motor on ISR;
(3) Internal serial communication TX/RX interrupt SIO ISR.
Turning to figure 8, the firmware main loop 101 is started, when power is initially supplied to the PC or other computing device. The PC will go through its own INIT sequence.
The microcontroller 33 starts its own INIT
sequence, as shown in the main loop which initially includes a set up of stack and initialization of timers, 2 ~

as shown at 107. This is followed by a Power On Confidence (POC) check and XILINX programming, as indicated at 109.
Thus the controller 33 does a read and write to all the internal registers to check for the integrity of the CPU.
The controller 33 performs a POC on the RAM 45 and does a check sum calculation on the data in the ROM
47, to ensure that it is intact. If any of these tests fails, an error message will be generated via the LED 53.
The next stage of power up, reads an external port pin to determine if a functional production test mode is required. If a jumper is present at the port input pin, the microcontroller 33 will execute the functional test program via the serial communication lines.
After the power up sequence is completed, the XILINX 37 is programmed. This consists of reading bit patterns from the ROM 47 and shifting them out to the XILINX via two output pins of the parallel port and bus 51. When this is completed, a test is conducted to ensure that the XILINX is configured correctly. Again, an error message will be generated as a blinking signal at the LED
53, if this test fails.
Upon Power On Reset, the micro controller 33 additionally does a read and write to all locations in the RAM 45, to verify the static RAM. The IC card acceptor interface is checked by sending serial data out and comparing to data received in through the port.
Additionally, more checks are made that power supply to the smart card can be switched on and off, and that reset and clock lines are working.
A floppy interface check is carried out that checks the internal floppy interface logic within the XILINX 37, and checks for MFN data transfers, internal I/O
register and interrupt, etc.
The controller 33 finishes the POC test at this stage. It reports in two different modes, namely normal 2~7~

mode and monitor mode. In the normal mode, the controller 33 waits for the PC to poll for the POC results, whilst in the monitor mode the POC status can be monitored via serial port. In both modes, the LED 53 will also indicate the status of the system.
For XILINX programming, this is achieved through built-in I/O port #1, bits 0, 1 and 2. The XILINX
configurations are stored in the ROM 47. During power up, the controller 33 will toggle XRESET line first to start programming. Program data will then be shifted serially and synchronously through XCLK and XDATA lines.
As indicated at 111, if there is any POC test failure, then the firmware main loop starts the LED 53 flashing as indicated at 113.
Otherwise, if the test was satisfactory, the firmware main loop moves to a state loop indicated at 115.
This state loop sequentially checks for different states.
As indicated 116, it first checks for an idle state, and if this state is present, it essentially remains in a loop monitoring the state.
The next check is whether the state equals "VERIFY", as indicated at 117. If this is the case, then indicated at 118, the buffer is verified for the T-14 protocol.
The next check is for the state being equal to "COMMAND", as indicated at 119, and in this case a command dispatcher is activated, as indicated at 120.
Again if a negative answer is received, then the next check is for the state being equal to "IC CARD", as indicated at 121. If this state is present, then the appropriate IC card command is sent to the IC Card as indicated at 122.
If none of these states are present, then the buffer is set to "en", indicating that this is an invalid request and no continuation is possible. This is indicated at 123. The main loop continues in this state, Loop 115, monitoring the state.

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Turning to Figure 9, this shows a schematic for the sequence for checking for the T-14 protocol.
The T-14 protocol states that, if 1.2 milliseconds elapses between transmission of characters during a block transfer, a time-out condition will occur.
If this timer goes off in receive mode, a ~'te~' (transmission error) is sent to the IC card. In a send mode the ISR must send "cn" (Continuation not permitted) to the IC card. Note that interrupts must have been disabled by motor on ISR.
The T-14 protocol driver conforms to all the rules pertaining to the T-14 protocol. This protocol checker is divided into two parts, namely:
(1) The protocol drivers that prepare the data for transmission of T-14 (card driver sets up BCC and CRC for block); and (2) The T-14 Protocol verifier that checks to ensure received data conforms to T-14 specifications (both for the floppy disk drive controller and the IC card acceptor 15).
The T-14 protocol checker is generally indicated by the reference 125. The first check is whether the buffer length is greater than the maximum permitted, as indicated at 126. If this is the case, then the buffer is set to "en~ as indicated at 127, to indicate that continuation is not possible. Otherwise, the checker proceeds to the next check, indicated at 128, where the BCC (Block Control Character) is checked. As indicated at 129, if this is not okay, then the buffer is set up with ~te" to indicate a transmission error.
Otherwise, the next check indicated at 130 is for the protocol control byte to be equal to response. If this is the case, as indicated at 131, the buffer is again set up with "en" to indicate that continuation is not possible.
If this is not the case, then at 132 a check is made for the NAD for the IC card. This is a check for the 2~7~

address for the card on the unit 31. The address has different values for the interface unit 31, and Card acceptor 15, and further the address will indicate whether the communication is to or from the relevant unit.
If the answer is in the affirmative, i.e. the NAD is the card address, then at 133, a check is made for whether the card is present or inserted. At 134, if the card is not inserted, then a bad status is inserted, whilst at 135 the state is switched to IC CARD, where the card is inserted.
Where the NAD is for the board or interface unit 31, then a check is made at 136 for a supervisory block.
If this is not present, then the state is set to COMMAND
at 137; when the supervisory block is present, then the checker moves to the next decision block 138. At 138, a check is made for the length byte being equal to zero.
If the length byte does equal zero, then the buffer is set up with "en~, indicating that it is unable to continue.
As indicated at A, if the length byte does not equal zero, then the checker moves to the next decision block, as shown in Figure 9b.
It is here noted that following the actions in any of blocks 127, 129, 131, 134, 135, 137 and 139, the protocol checker ends, as indicated at 140.
With reference to Figure 9b, as indicated at 141, 142 and 143, successive checks are made for: whether the protocol control byte, PCB, is equal to ~en~; whether the fixed block is ''**ll, i.e. impermissible code; or whether the PCB is equal to ~nb~ indicating that the next chained block is acceptable. In all these cases if the answer is in the affirmative, then a return buffer is set to "en" as indicated at 144.
A succession of further checks are then made for whether the protocol control byte is equal to: cn; ci; or te, as indicated at 145, 146, 147. In the first two cases, if the PCB is equal to cn or ci, then this is returned. In the latter case, the PCB being equal to te, ~4~7~

then the last buffer is returned, these actions are indicated at 148, 149 and 150.
Finally, if none of these conditions are present, then "en~ is returned, as indicated at 151, and the protocol checker then ends at 140.
Turning to the command dispatcher, this is shown in detail in Figure 10. The command dispatcher generally indicated by the reference 153. It comprises a series of sequential decision blocks 154 - 159 for checking for various commands, and corresponding actions indicated at 160 - 166.
The control unit 31 supports 7 commands, as detailed in the following table:
1. Control unit 31 diagnostic 15 2. Reader initialization 3. Reset card 4. Clear command 5. Read/Write status 6. Card-in 20 7. Card-out Other possible commands are either sent directly to the IC card by the unit 31, or commands that the library will filter and not reach the controller 31.
Similarly, the access control unit 31 effectively passes various commands from and IC card directly to the computing device 67.
The control unit diagnostic mode will cause the control unit to do an internal diagnostic of all its relevant parts, and report the status of those parts; this is not shown on Figure 10. Reader initialization resets the firmware to initial set up.
The reset card command causes the control unit 31 to check if the IC card is in the IC card acceptor 15.
If so, the control unit 31 will proceed to activate the RESET IC CARD LINE. This will cause the IC card to generate an answer-to-reset (ATR) sequence. The information is received by the control unit 31 and 2~4~7~

verified and returned to the application. This ATR
sequence enables the IC card for further data transfers.
The clear command, simply clears the last command sent to the controller 31. The read/write status returns the current status o~ the system.
On receiving the card in command, the controller 31 will check if the card is currently in. If so, it will return the status that the card is in. If not, the LED 53 will be flashed to prompt the user to insert a card. If time out (number of seconds stated on the card in command), an error status is returned.
The decision blocks 154 - 159 check for the presence of the following commands and take the following actions: at 154, check for the command being equal to RSTRW, and if present reset reader at 160; at 155 check for the command being equal to RESET, and if present reset the IC card at 161; check for command being CLRCND at 15b, and if present clear the last command at 162; check for command being RWSTS at 157, and if present implement reader status command at 163; check for command being CARDIN at 158, and if present execute this command 164;
and correspondingly check for command being CARDOUT at 159, and if present execute at 165.
If none of these commands are present, then the buffer is set to ~te~, indicative of a transmission error, at 166, and the command dispatcher then ends at 167.
A description of the individual commands will now be given with reference to the following figures:
In figure 11, a reset reader command is shown and again designated by the reference 160. At 169, the state is set to IDLE followed by which the buffer is set to good status at 170, and all flags and pointers are reset at 171. This command then ends.
With reference to Figure 12, the reset IC card command 161 first checks for the card being in at 173, and if the card is not present a bad status is set at 174. If the card is in, then at 175 the buffer is set to ~'ci", 7 ~ ~

indicating that the continuation is under idle, whilst the reset is performed.
Then the Answer To Reset (ATR) is called at 176.
At 177, a good status is awaited from the ATR, and if not received within a set time, a time out occurs.
At 178, a check is made for bad status. If this is not present, then a good status is set up at 179, and the command ended at 180.
If there is a bad status, then the card is powered off at 181 and bad status set up at 182, prior to ending at 180.
The clear current command 162 is shown in Figure 13, and simply comprises setting the state to idle at 184 and setting buffer to good status at 185.
The reader status command 163 is shown in Figure 14. This first checks at 187 whether the IC card is in or not. Where the card is not present, then the status is set to 0 at 188, prior to ending at 192.
Where the card is present, then a check is made for the power being on to the card at 189. If there is no power on, then the status is set to 0x4 at 190 and the command then ends. Where the power is on, then the status is set to 0x0f, indicative of this, at 191. The command then ends at 192.
Turning to figures 15a and 15b, these show the Card In Command 164. At 195, a check is made for whether the IC card is in or not. If it is, then the command continues as indicated at B in Figure 15b, described below.
If the card is not in, a check is made at 196 for a terminate flag, this being a flag that is set inside the floppy disk simulator, to indicate that CARD IN or CARD OUT is to be terminated, and hence prevent the command becoming stuck in an infinite loop. If the terminate flag is set, then the LED is turned off at 197, flags reset at 198 and the command ends at 211.

7 ~ i~

On the other hand, if the terminate flag is not set, then the command continues to check for the presence of the card, as indicated at 199. If the card is not present, then the LED is turned on for a short period and then turned off at 200. At 201, a check again is made for the card being present, and if the card is not present, then the command returns $o the terminate flag set check at 196. Thus, the command can continue in a loop checking for the presence of the card and effectively flashing the LED, to indicate to the user that the card should be inserted.
If at 199 or 201 it is determined that the card is present, then the LED 53 is turned on, and the command waits for a ~ci~ being sent or terminate flag set. It then continues at C in Figure 15b.
Turning to Figure 15b, where the command is continuing from C, then at 203 a che~k is made for the terminate flag, again to prevent the command being caught in an infinite loop. If this is present, then the flags are reset at 204 and the command ends at 211.
On the other hand if the terminate flag is not present, then the command continues at 205. This is also a continuation from B when the first check at 195 determines ~hat a card is present.- At 205, the answer to reset, ATR is called. At 206, the command waits for good status or time out, as in the reset card command 161.
At 207 a check is made for bad status, and if this is not present then good status is set up at 208, prior to terminating or ending at 211.
On the other hand if bad status is present, the card is powered off at 209 and bad status set at 210 for sending to the application, again before ending at 211.
Turning to Figure 16, this shows the card out command 165. At 215, again the first check is whether the card is in or not. If the card is not in, then bad status is set 216, and the command ended at 230.

7 ~ ~

If the card is in, then a check is made at 217 as to whether the power is on or not to the card. If the card is powered then the caxd is powered off at 21~, before returning to the command. Thus, the next action is effected with the card powered off.
At 219, a check is made for the terminate flag from the floppy disk simulator being set. If this is set, then at 220 the LED 53 is turned off and flags are reset at 221, before ending at 230.
If the terminate flag is not set, then again a check is made at 222 for the card being in. If the card is in, then at 223 the LED iS turned off and then back on again. At 224 a further check is made for the card being in, and if the card is still in, then the command returns to the terminate flag set check 219. Thus, comparable to the card in command, this sets up a loop to check for removal of the card with the LED being flashed on, to indicate to the user that the card should be removed.
If the card is determined to have been removed at either 222 or 224, then at 225, the LED 53 is turned off and the command waits for ci, indicative of continuation under idle, or terminate flag set.
At 226, a check is made for the terminate flag being set. If this is the case, then at 227, the flags are reset, otherwise, if the terminate flag is not set, then the buffer is set up with good status at 228, and in either case the command ends at 230.
In order to support and mediate access to an IC
card in the IC card acceptor 15, a communications port driver is provided, this driver being designated as Terminate and Stay Resident (TSR). The TSR accesses the controller 31 via the BIOS floppy disk commands, utilizing the disk drive controller 63 as a transport mechanism. IC
card requests are sent serially to the TSR by an application where they are buffered and sent to the disk drive controller 63 (write sector) in the appropriate format. Data is returned to the application after a -` 2~

sector read is performed on the disk drive control 63.
The TSR i6 detailed below.
Referring to Figure 17, this shows the Terminate and Stay Resident routine generally designated by the reference 233. Here, at 234, the offset of the last memory location is moved to AX, and is divided by 16.
This is to allocate memory in paragraphs of 16 bytes each.
At 235, 10 is added to AX, the size assigned to PSP (Program Segment Prefix), this being the program signal address.
At 236, AX is moved to DX and 1 is added to DX.
The purpose of this is in case there is an odd boundary and one extra paragraph.
At 237, DOS command INT 21h, function 31h is implemented. This is a DOS call which keeps the TSR 233 resident after it terminates. This routine then terminates or ends at 238. -The TSR (Terminate and Stay Resident) is a communication port driver, which is activated when an application sends requests and reads responses to/from the COM report via interrupt 14h. The application library has a global VARIABLE-A-CHANNEL, which is modified by the application to send a virtual device number (41h for the control unit 31), to differentiate a request for communication with the IC card, from actual or ordinary COM port I/O.
The TSR buffers all requests from the application, so as to convert the serial data received from interrupt 14h to block commands to be sent through the disk controller. The block data from the disk controller is similarly returned to the application 1 byte at a time via interrupt 14h. If not enough characters are sent to the TSR from the application in accordance with the T-14 protocol, a "te" is returned.
The TSR installs an interrupt service routine, which traps the application performing interrupt 14h BIOS
calls. This interrupt provides byte stream I/O to the conventional communication port. The following values can be selected for the AH register.
AH = 0-initialize communications port. Ignore.
AH = 1-send character. TSR buffers T-14 request to send to control unit 31.
AH = 2-receive character. Read floppy disk sector and return data to application, one byte at a time.
AH = 3-communication port status. Return good status for DTR (Data Send Ready) and DTR (Data Transmit Ready). Both are set to good status so the TSR will read a good status.
A floppy disk BIOS call is effected using INT 13 (the interface which provides access to the floppy disk drive). For a call to the actual floppy disk drive 61, the INT 13 can function in the usual way.
Where an application requests communication with the IC card acceptor 15, then, the TSR, after capturing the complete request from the application, performs an "out" to the digital-output register (address Ox3F2) of OxlO which sets motor enable line active and then an "out"
of OxO which turns motor enable inactive. Two quick toggles (20 microseconds and 100 microseconds apart) of the motor line are then sent as a signal to the control unit 31 to turn off the conventional floppy disk drive 61, i.e. not allow motor on and drive select lines through to the drive 61. This is also a signal to execute the next command.
Program Summary:
Digital Output Register I/O Address Ox3F2 30 Bit 0 Drive 00 Drive A 01 Drive B
1 Select 2 No~ FDC Reset 3 Enable INT & DMA Requests 4 Drive A motor enable 5 Drive B motor enable 6 Drive C motor enable 7 Drive D motor enable Turn on Drive motor "A" 76543210 OOOlOOOOb = OxlOh.

Drive A motor on Drive A

Turn off Drive Motor "A" 76543210 OOOOOOOOb = OxOh.
Drive A motor off Drive A
Referring to Figure 18, this shows a device handler main line code that are used to install $he interrupt handlers in the PC or other computing device 67.
This is generally denoted by the reference 240.
At 241, interrupt handlers are installed. At 242 a check is made that these have been successfully loaded, and when this has occurred, an appropriate message is displayed. At 243, like the TSR 233, the DOS call INT
21, function 31h is effected, to keep the interrupt handlers resident after this main line code terminates.
This main line code then ends at 244.
Turning to Figure 19, this shows an interrupt 9h handler, which handles hardware keyboard handler interrupts. This is generally designated by the reference 245. At 246, this handler detects whether a key or the keyboard has been pressed. If this is the case, at 247, it checks for Ctrl - Alt keys being pressed. If they have been pressed, then at 248 a reset toggle is effected.
This sends 3 motor on pulses to signal Ctrl - Alt - Del.
This is a key sequence that is used to reboot the machine.
The purpose for inserting this reset toggle is to ensure that the card is powered down correctly. If an illegal power off i8 effected to the IC card, then data can be lost, since it requires a 100 microseconds to power down.
Reset toggle 248 ensures that the card is powered down correctly before the machine 67 is rebooted. After 248, the handler then jumps to the real or conventional interrupt 9h handler.
If no key is detected as having been pressed or if the Ctrl - Alt keys have not been pressed, then as indicated the handler jumps directly to the conventional 9h handler at ~50. The handler then ends.

7 ~ ~

Figure 20 shows the Interrupt 13h interrupt service routine, for floppy disks service interrupt, this being generally designated by the reference 253. At 254, a check is made for dl = 80, this being the address for the hard disk, drives A and B being dl = 0 and dl = 1 respectively. If this is a hard disk call, then the routine jumps to the old or conventional interrupt 13, as indicated at 259. At 255, a check is made for whether disk access request is from the Terminate and Stay Resident routine 233, i.e. a simulated disk access rather than access to the FDD61. If this is the case, then timming out of the floppy disk controller 63 is of no concern, and hence this routine jumps to the old Interrupt 13 at 259. If read or write does not come from the TSR
233, then, at 256, a check is made for whether modified disk parameters have been installed. If not, then again the routine can jump to the old interrupt 13 at 259.
Where the modified disk parameters have been installed, these must be removed; it is important that the disk parameters include the correct set of variables describing the floppy disk drive 61. Accordingly at 257, the modified disk parameters are removed and the original ones replaced. Then at 258 a call is made to the old interrupt 13 to reset floppy disk controller 63, before jumping to the old interrupt 13 at 259.
Turning to Figures 21a and 21b, these show Interrupt Handler for INT 14h, of the TSR, this Interrupt Handler being generally designated by the reference 261.
The interrupt handler 261 first determines whether the request is for conventional serial I/O or for communication with the controller or interface unit 31, as indicated at 262. This is determined by checking for whether the register AH is equal to 4lh or 42h, these being virtual device numbers for the A and B drives. If these device numbers are present, then the handler jumps to the conventional or real INT 14h as indicated at 263.

~3~7~

If this is not the case, then the handler continues, and then checks whether AH equals 0, an indication that the port should be initialized, as indicated at 264. If this is the case, then, as indicated at 265, counters and pointers are initialized and the handler returns AH equals 2120 an indication that it is ready for a character.
At 264 if AH does not equal 0, then at 266, the next check is whether AH equals 3, a check for the communication port status. If AH is equal to 3, then the next check at 267 is whether pause is equal to 1. If it is, then a delay is required between the write and read operations, and this is continued as indicated at F in Figure 21b. Assuming pause is equal to 0, indicating that no pause is required, then as indicated at 268, AH equals 2120 is returned, indicative that a character is ready, and the interrupt handler returns.
Where AH does not equal to 3, then the next check is whether AH is equal to 1, as indicated at 26g.
AH equals 1 is an indication that a character should be sent.
At 273, sending is then equal to 1, and the character is saved and buffer pointer is incremented at 274. At 275, in accordance with a T-14 protocol, the length byte is saved where present. At 276, a check is made as to whether the end of the buffer has been reached.
If this is not the case, then the interrupt returns. On the other hand, if the end of the buffer has been reached, then the handler continues at E on Figure 2lb, described below.
At 269, if it is determined that AH does not equal 1, then the assumption is made that AH should be equal to 2 indicating that a read should be performed.
The next check (not shown) is for whether AH does equal 2;
if this is not the case, then a bad status is returned.
Where AH does equal 2, then at 270, a check is made as to whether pause is equal to 1. This should not be the case as the interface unit 31 acts a slave and consequently read should never be performed before a write operation.
Always, the write operation is performed before read.
Thus, if pause equals 1 there is some error, and line error is returned, as indicated at 271.
Where pause does not equal 1, then as indicated at 272, the character in AL is returned and the interrupt handler then returns.
Turning to Figure 2lb, where pause has been found to be equal to 1 at 267, then, as indicated at 283, INT 15 (device wait) is called to provide a delay between read and write. In this respect, it should be noted that there should be a status state between the write and read of every character or byte.
Following this, the motor toggle sequence is provided for the control or interface unit 31, as indicated at 284. Then sector 1, track 0 is read at 285, and AH equals 2120 is returned at 286, indicating that a character is ready. The interrupt handler 261 then returns.
Where at 276 it is determined that the buffer has ended, then as indicated at 277, the next check is to verify the T-14 buffer. Where this is not within the protocol, then transmission error status is returned, as indicated at 281, and at 282 AH equals 2120 is set, indicating that a character is ready. The Handler 261 then returns.
On the other hand, where the buffer protocol is correct, then the motor toggle sequence for the controller 31 is provided at 278. This is followed by a write to sector 1, track 0 at 279. Then, pause is set equal to 1 and sending set 0 at 280 prior to returning.
Turning to Figures 22a and b, these show the floppy disk simulator, or Notor On Interrupt service routine, generally indicated by the reference 103.
The motor on ISR routine is activated by the motor on interrupt, this being the first of two pulses 2Q~ 7~

received from the TSR. This routine then tests for the second pulse. If these pulses are correct, the floppy disk drive 61 motor on and drive select lines are disconnected. The controller 31 then transmits the S formatted disk track and current data buffer, which it is holding, to the floppy disk drive controller 63. During the address header for the selected sector, the write gate line is monitored. If the write gate line is not active, the track data is continuously dumped until the floppy disk drive motor is turned off.
If the write gate becomes active, the READ FDC
function is called. This function captures the T-14 block (Nax 68 bytes), ignoring the rest of the 512 bytes of data. The Block Control Character (BCC) and Parity Control Bi~ (PCB) of the T-14 protocol are then checked.
If the block type of the PCB is a supervisory block with the control bits set for ~te~ transmission error, the data buffer pointer is set to the last block and returned to the application. If the BCC is incorrect, the data buffer pointer is set to the ~te~ buffer. Next, the state machine flag changes to VERIFY PROTOCOL. Interrupts are then enabled and the firmware returns from interrupt.
The simulator first checks at 301 for the two motor on pulses. If these are not detected, then the real floppy disk drive 61 is enabled at 302.
If two pulses are detected, then at 303 a check is made for a further motor on pulse, this third pulse being sent when the interrupt 9h handler 245 detects the Ctrl - Alt - Del key sequence for rebooting. In this case, as indicated at 304, the card is powered off and returned from interrupt occurs at 305.
Assuming only 2 motor on pulses are detected, then at 306, the real floppy disk drive 61 is disabled, by disconnecting the motor on and drive select lines to that drive. At 307 formatted track data, in usual NFM format is returned.

2 ~

At 308, a check is made for the write gate line being active. If it is not active, then at 309 a check is made for the motor on line still being active, indicative that data should still be returned. If it is still on, then the simulator is looped back to 307 for returning formatted track data. In other words, whilst formatted track data is being returned, there is a continuous loop checking for the write gate line being active and for the motor line still being on.
If at any time the motor on line goes off, then the real floppy disk drive 61 is enabled at 310 and the simulator returns from the interrupt.
If the write gate line becomes active, then data is captured, as indicated at 311, until the T-14 data length LEN is satisfied.
At 312 a check is made for completed equal 1.
This is to cover the case where the TSR activates the Motor On ISR while a CARDIN or CARDOUT command is in process. Completed equals 0 when a CARDIN or CARDOUT
command is in process. If completed is equal to 1, i.e.
there is not card in or card out in process, then as indicated at 313 the state is set to VERIFY. This will cause the T-14 buffer to be verified, as discussed above.
Then at 310, the interrupt returns and the real FDD 61 is enabled.
Where complete does equal 0, then at 314, a check is made for a supervisory block. If there is no supervisory block then the assumption is made that this must be a new command to process. Accordingly, at 315, the card in or card out commands are stopped by setting the Terminate Flag and the state is again set to verify, so that the buffer can be verified in accordance with the T-14 protocol. The simulator then returns from the interrupt and enables the real FDD 61, as indicated at 323 in Figure 22b.
Where a supervisory block is present, this is indicative of something inconsistent, so the simulator continues at H in Figure 22b. Effectively, as indicated at 316, 317 an 318, there is a sequential check for whether the te command, ci command or cn command is present. A te command is indicative of a transmission error and ends at 319 the previous data buffer is returned to the application. At 320, if the ci command is present, then ci is set up for return at 320. If the cn command is present, then the card in or card out command is terminated and cn command is returned.
If none of these three commands are present, then te is set up for return, indicative of a bad T-14 block. Then, at 323, the simulator returns and the real FDD 61 is enabled.
Figures 6a and 6b show the sequence for an application send re~uest and an application read status/data respectively.
In figure 6a, the seven lines show the levels on the following lines: the motor on line; the drive select;
controller 31 write; floppy disk controller 63 write enable; floppy disk controller 63 write data; control unit 31 read; and floppy disk drive 61 disable.
At 380, the controller 31 recognizes the uni~ue motor toggle, i.e. two 45 microsecond pulses separated by 200 microseconds. This is an illegal type floppy disk access, with the Drive select line not enabled, and disables the connection through to the actual floppy disk drive 61. At 381, the motor is turned on and drive select is turned on. At 382, the controller 31 sends track data and index pulse. This may occur a number of times depending on the delay that the floppy disk drive controller 63 uses waiting for the head to load and motor speed up time. At 383, the floppy disk drive controller write enable is turned on and data sent. The control unit 31 buffers the data. At 384, the controller 63 stops writing data and turns off write enable. At 385, the motor on and drive select are both turned off.

Referring to figure 6b, this shows a similar variation of the signal on various lines with time, for an application read status/data. Here, the six lines represent, in order from the top, the motor on line, the drive select line, controller 31 write, disk drive controller 63 write enable, disk drive controller 63 read data, and FDD 61 disable. Here, at 390, the controller 63 recognizes the two pulses of the motor toggle and disables the motor on and drive select connections to the floppy disk drive 61. At 391, the drive controller 63 turns on the motor and drive select lines. At 392, the control unit 31 returns track data and index pulse. At 393, the drive controller 63 reads the data, and the controller 31 then ends the write at 394 when the motor on and drive select are turned off.
The following data is sent for INT 13, during such a read or write operation:
INT 13 (Interface which provides access to floppy disk) AH = 2 (Read) AH = l(Write) DL - Drive Number = 0 DH - Head Number = 0 CH - Track Number = 0 CL - Sector Number = 0 AL - Number of sectors to read/write = 1 ES - Segment of buffer BX - Offset of buffer The function "Write sector" and "Read sector" is used to send and receive data through the FDC using track = 0, head = 0, sector = 0*, drive = 0, number of sectors = 1.
*NOTE: In using the sector number of zero, if the controller 31 misses the motor toggle for any reason, the TSR write sector will NOT overwrite any data on the real disk. Sector ZERO does not exist on a real floppy disk.
Therefore the TSR will be returned the status of "Sector Not Found".
Reference will now be made to Figures 23a, b and c, which show the serial ISR 105, i.e. the serial 7 ~ ~

Interrupt Service Routine. This is for servicing serial I/O requests for the IC card.
The first check at 331 is to determine whether there is power on to the IC card, which clearly requires the card to be present. If there is no such power on, then at 332, any read/write interrupts that are pending are cleared. In other words, this serial ISR discards any interrupts that arise when no card access is possible. At 333, this ISR then returns from the interrupt.
Assuming the power is onto the IC card, then at 334, the LED 53 is flashed.
At 335, a check is made for a transmit interrupt flag. If this is present, indicating that transmission to the IC card should occur, then at 336 a check is made for whether data is currently being sent. If sending is not then occurring, then, at 337, the index is set equal 0 and sending equals 1, to commence sending the first character.
The ISR then continues at 338, where a check i5 made for the index value. If index equals 0, then as indicated at 339, a length is set equal to T-14 LEN, the length o the T-14 protocol. The index is incremented, in known manner, every time a byte is placed in the buffer.
The routine then continues at 340 with a check for whether the index is equal to the T-14 LEN plus 4.
The 4 extra bytes being for the PCB and BCC. If this is the case then there is a return from the interrupt, otherwise the next byte is sent and then there is a return from the interrupt, indicated at 342.
If at 335, it is detected that the transmit flag is not set, then at 343, a check is made for a receive interrupt flag. If this is not present, then at 344, there is a return from the interrupt, since neither the transmit nor receive flags are present.
Assuming the receive interrupt flag is present, then at 345 a check is made for the sending flag being set. If this has been set, then at 346 sending is set 2 ~

equal to FALSE, as a receive should be effected, and the index is set equal to 0.
The routine then continues at 347 and checks for the whether the IC card is in the resetting mode i.e.
whether the ATR is being effected. If this is the case, then the routine continues at J on Figure 23b, whereas if resetting card is not present, the routine continues at K
on Figure 23c.
Referring first to figure 23b, where the IC card is resetting, at 348 a check is made for whether the first byte of the ATR is present. If this is the case, the index is set equal to 0 at 349, and in either case the routine continues at 350. There, a byte is read from the SIO buffer, and at 351 a check is made for this being the correct byte for the ATR sequence.
If this is not the correct byte for the ATR
sequence, then at 352 the error status is set for the CARDIN routine or command, and return from interrupt occurs at 358.
Assuming this is the correct byte, then at 353 a check is made for the last byte of the ATR sequence. If this is not the last byte, then again return from interrupt occurs. Otherwise, the routine continues at 354 and checks the error status. The reason for this is that the Card In Command resets the card, calls the serial ISR
and then checks for the status, as indicated at 207 in Figure 15b.
If the error status is not equal to 0, then there is a return from the interrupt.
Assuming the error status is equal to 0, then routine turns on the LED at 356 and then at 357 sets up return floppy disk drive buffer, which simulates a sector.
Also, the CRC at the end of the sector is calculated.
Where the IC card is not in a reset mode, then the ISR routine continues at 359 (Figure 23c). A check is made for the index being equal to 0. The purpose of this is to ensure that the BCC is set up correctly for receiving. If index equals 0, then at 360, receiving is set equal to true and BCC is set equal to 0. Otherwise, the routine continues at 361 by reading a byte and keeping running BCC.
At 362, a check is made for a parity error, the serial I/O having a parity control byte.
If there is no parity error, then at 363 a check is made for the last byte in the T-14 protocol. If it is not the last byte, then at 364 there is a return from the interrupt.
If the last byte is present, then at 365 a determination is made as to whether BCC equals 0. If this is the case, then at 366 FDD buffer is set up and the CRC
calculated, again to simulate a sector, prior to returning from the interrupt at 369.
Where the BCC does not equal 0, then the serial buffer is set up with a te command and index equal to 0, at 367, indicating that there was a transmission error.
Similarly, if a parity error is detected at 362, then it is returned at 367. In either case, at 368 the first byte is placed into the SIO buffer, prior to returning from the interrupt at 369.
Figure 24 shows the timing sequences that the firmware should follow for IC card access. This shows lines for: CVCC, power to the IC card; SCIN, IC Card in;
INTO, Interrupt 0 of the microcontroller 33; SCCLK, clock signal to the IC card; and SCI/SCO, IC card input/output.
At 270, the IC card is inserted into the IC card acceptor 15 sending SCIN high, which in turn triggers INTO. At 271, the microcontroller 33 powers up the IC
card. Simultaneously, SCCLK commences, as indicated at 272, and SCI/SCO goes high. The IC card is reset, and following reset, SCRST goes high at 273. Then from 274 to 275 data is transferred to or from the card. At 276, SCRST goes down, ready for card removal. At 277, power to card goes down and SCCLK is turned off. At 278, the IC
card is removed, sending SCIN high, and INTO low.

Claims (26)

1. In a computing device, an apparatus comprising:
a disk drive unit; an IC card acceptor unit capable of reading and writing to an IC Card; a disk drive controller; and an access control unit connected between the disk drive controller and both the disk drive unit and the IC card acceptor unit, the access control unit being adapted to selectively connect the disk drive controller to one of the disk drive unit and the IC card acceptor unit, for read/write operation, the access control unit simulating the disk drive unit when providing communication to the IC card acceptor unit.

2. An apparatus as claimed in claim 1, wherein the disk drive unit, the IC card acceptor unit and the access control unit are combined as a single unit.

3. An apparatus as claimed in claim 2, wherein the combined unit comprising the disk drive unit, the IC card acceptor unit and the access control unit is configured to fit within an existing bay of the computing device adapted to receive a mechanically larger disk drive unit.

4. An apparatus as claimed in claim 1, wherein the access control unit comprises a microcontroller, a programmable gate array unit connected to the micro controller, and a memory means connected via data and address buses to both the microcontroller and the programmable gate array unit, with the IC card acceptor unit, the disk drive unit and the disk drive controller all being connected to the programmable gate array unit.

5. An apparatus as claimed in claim 4, wherein the memory means comprises a SRAM unit and a ROM unit.

6. An apparatus as claimed in claim 5, wherein the programmable gate array provides: an interface connected to the microcontroller; both an encoder and a decoder connected to the disk drive controller; a disk control unit connected to both the disk drive controller and the disk drive unit; and an IC card control unit connected to the IC card acceptor unit.

7. An apparatus as claimed in claim 1, wherein the access control unit functions as a state machine and includes: a main loop; a serial I/O Interrupt Service Routine activated by serial I/O requests; and a disk access Interrupt Service Routine that is activated by a request from the computing device for disk access, wherein the computing device is loaded with a communication port driver for intercepting disk access calls to the disk drive controller and for providing a signal indicating when access is required to the disk drive unit and when access is required to the access control unit.

8. An apparatus as claimed in claim 7, wherein the communication port driver installs a serial interrupt handler for intercepting serial I/O interrupts' which interrupt handler passes requests for communication to the disk drive unit to the respective serial I/O interrupt, and which serial interrupt handler sends a predetermined motor on toggle signal to the access control unit when the communication is to or from IC Card Acceptor unit through the access control unit, and wherein the disk access interrupt service routine detects the motor on toggle signal, and upon such detection disables the disk drive unit, whereby data is read to or from the access control unit.

9. An apparatus as claimed in claim 8, wherein the communication port driver converts serial data received from an application to block commands transmitted to the disk drive controller, and converts block data received from the disk drive controller into serial data returned to the application.

10. An apparatus as claimed in claim 9, wherein, upon detection of the motor on toggle signal, the disk access interrupt service routine disconnects motor on and drive select lines to the disk drive unit, converts block commands from the disk drive controller to serial data sent to the IC card acceptor unit and converts serial data from the IC card acceptor unit to block commands sent to the disk drive controller.

11. An apparatus as claimed in claim 10, wherein the motor on toggle signal comprises two pulses of a motor on signal, the disk access interrupt service routine enabling the disk drive unit in the absence of the motor on toggle signal and wherein when the motor on toggle signal is detected, the disk access interrupt service routine disables the disk drive unit and effects read/write operations with the disk drive controller.

12. An apparatus as claimed in claim 11, wherein the disk access interrupt service routine is adapted to sense a third motor on pulse, indicative of a key sequence for re-booting the computing device, the disk access interrupt service routine powering off any IC card present in the IC
card acceptor unit when such a third pulse is detected.

13. An apparatus as claimed in claim 10, wherein the disk access interrupt service routine, upon detection of the motor on toggle signal and after disabling the disk drive unit, returns formatted track data to an application via the disk drive controller, whilst monitoring a write gate line, the disk access interrupt service routine capturing data when the write gate line becomes active, until an appropriate length of data has been captured.

14. An apparatus as claimed in claim 13, wherein the serial interrupt service routine determines which of transmit and receive interrupt f lags have been set, and when the sending interrupt f lag is set, sends bytes sequentially until a predetermined length is satisfied, and when the receive interrupt flag is set the routine checks whether a resetting IC card command has been called, where the reset has been called, the routine checking that the correct bytes for the reset sequence are read from a buffer and where no reset is to be effected, the routine reads bytes sequentially whilst monitoring supervisory blocks until a predetermined length is satisfied.

15. An apparatus as claimed in claim 14, wherein a disk service interrupt service routine is installed in the computing device which interrupt service routine determines whether a disk access request is to the disk drive unit and ensures that appropriate disk parameters are installed for the disk drive controller.

16. An apparatus as claimed in claim 15, which includes an interrupt handler for hardware keyboard interrupt installed on the computing device, which interrupt handler detects a key sequence for rebooting the computing device, and, upon detection of that key sequence, sends a predetermined motor on toggle signal to the disk access interrupt service routine to ensure proper powering off of any IC card present in the IC card acceptor unit.

17. For use in a computing device including a disk drive controller, an apparatus comprising: a disk drive unit; an IC card acceptor unit capable of reading and writing to an IC Card; a port for connection to the disk drive controller; and an access control unit connected between the port and both the disk drive unit and the IC

card acceptor unit, the access control unit being adapted to selectively connect the port to one of the disk drive unit and the IC card acceptor unit, for read/write operation, the access control unit simulating the disk drive unit when providing communication to the IC card acceptor unit.

18. An apparatus as claimed in claim 17, wherein the disk drive unit, the IC card acceptor unit and the access control unit are combined as a single unit.

19. An apparatus as claimed in claim 18, wherein the combined unit comprising the disk drive unit, the IC card acceptor unit and the access control unit is configured to fit within an existing bay of the computing device adapted to receive a mechanically larger disk drive unit.

20. An apparatus as claimed in claim 1, wherein the access control unit comprises a microcontroller, a programmable gate array unit connected to the micro controller, and a memory means connected via data and address buses to both the microcontroller and the programmable gate array unit, with the IC card acceptor unit, the disk drive unit and the disk drive controller all being connected to the programmable gate array unit.

21. An apparatus as claimed in claim 20, wherein the memory means comprises a SRAM unit and a ROM unit, and wherein the programmable gate array provides: an interface connected to the microcontroller; both an encoder and a decoder connected to the disk drive controller; a disk control unit connected to both the disk drive controller and the disk drive unit; and an IC card control unit connected to the IC card acceptor unit.

22. An apparatus as claimed in claim 1, wherein the access control unit functions as a state machine and includes: a main loop; a serial I/O Interrupt Service Routine activated by serial I/O requests; and a disk access Interrupt Service Routine that, in use, is activated by a request from the computing device for disk access.

23. An apparatus as claimed in claim 22, wherein the disk access interrupt service routine is adapted to detect a motor on toggle signal, and upon such detection disables the disk drive unit, whereby data is read to or from the access control unit.

24. An apparatus as claimed in claim 23, wherein, upon detection of the motor on toggle signal, the disk access interrupt service routine disconnects motor on and drive select lines to the disk drive unit, converts block commands from the port to serial data sent to the IC card acceptor unit and converts serial data from the IC card acceptor unit to block commands sent to the port.

25. An apparatus as claimed in claim 10, wherein the disk access interrupt service routine, upon detection of the motor on toggle signal and after disabling the disk drive unit, returns formatted track data to the port, whilst monitoring a write gate line, the disk access interrupt service routine capturing data when the write gate line becomes active, until an appropriate length of data has been captured.

26. An apparatus as claimed in claim 25, wherein the serial interrupt service routine determines which of transmit and receive interrupt flags have been set, and when the sending interrupt flag is set, sends bytes sequentially until a predetermined length is satisfied, and when the receive interrupt flag is set the routine checks whether a resetting IC card command has been called, where the reset has been called, the routine checking that the correct bytes for the reset sequence are read from a buffer and where no reset is to be effected, the routine reads bytes sequentially whilst monitoring supervisory blocks until a predetermined length is satisfied.