CA2037989A1 - Control system for multi-processor system - Google Patents

Control system for multi-processor system

Info

Publication number
CA2037989A1
CA2037989A1 CA2037989A CA2037989A CA2037989A1 CA 2037989 A1 CA2037989 A1 CA 2037989A1 CA 2037989 A CA2037989 A CA 2037989A CA 2037989 A CA2037989 A CA 2037989A CA 2037989 A1 CA2037989 A1 CA 2037989A1
Authority
CA
Canada
Prior art keywords
input
output
information processing
processing modules
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2037989A
Other languages
French (fr)
Other versions
CA2037989C (en
Inventor
Makoto Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CA2037989A1 publication Critical patent/CA2037989A1/en
Application granted granted Critical
Publication of CA2037989C publication Critical patent/CA2037989C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Abstract

An input/output request control system in a multi-processor system includes a plurality of information processing modules (PM). The system comprises a plurality of input/output adapters (ADP) commonly used by each of said information processing modules and a plurality of input/output devices (DVC) divided into groups, each group controlled by one of two input/output adapters. An input/output request maintaining table (LDVC) manages input/output requests from respective information processing modules for each of the input/output devices controlled by said information processing modules by using a queue. Input/output requests from respective information processing modules are processed based on the state of the input/output request maintaining table and the input/output devices.
CA002037989A 1990-03-09 1991-03-11 Control system for multi-processor system Expired - Fee Related CA2037989C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5907090 1990-03-09
JP02-059070 1990-03-09

Publications (2)

Publication Number Publication Date
CA2037989A1 true CA2037989A1 (en) 1991-09-10
CA2037989C CA2037989C (en) 1998-07-28

Family

ID=13102725

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002037989A Expired - Fee Related CA2037989C (en) 1990-03-09 1991-03-11 Control system for multi-processor system

Country Status (6)

Country Link
US (1) US5507032A (en)
EP (1) EP0446077B1 (en)
KR (1) KR950008837B1 (en)
AU (1) AU654268B2 (en)
CA (1) CA2037989C (en)
DE (1) DE69122142T2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371893A (en) * 1991-12-27 1994-12-06 International Business Machines Corporation Look-ahead priority arbitration system and method
US5717950A (en) 1994-01-11 1998-02-10 Hitachi, Ltd. Input/output device information management system for multi-computer system
US5860022A (en) * 1994-07-26 1999-01-12 Hitachi, Ltd. Computer system and method of issuing input/output commands therefrom
JP3042341B2 (en) * 1994-11-30 2000-05-15 日本電気株式会社 Local I / O Control Method for Cluster-Coupled Multiprocessor System
US5592631A (en) * 1995-05-02 1997-01-07 Apple Computer, Inc. Bus transaction reordering using side-band information signals
US5812799A (en) * 1995-06-07 1998-09-22 Microunity Systems Engineering, Inc. Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing
US5675829A (en) * 1995-07-07 1997-10-07 Sun Microsystems, Inc. Method and apparatus for coordinating data transfer between hardware and software by comparing entry number of data to be transferred data to entry number of transferred data
FR2737590B1 (en) * 1995-08-03 1997-10-17 Sgs Thomson Microelectronics INTERRUPTION MANAGEMENT DEVICE
US6021456A (en) * 1996-11-12 2000-02-01 Herdeg; Glenn Arthur Method for communicating interrupt data structure in a multi-processor computer system
US6393455B1 (en) 1997-03-28 2002-05-21 International Business Machines Corp. Workload management method to enhance shared resource access in a multisystem environment
US5960178A (en) * 1997-08-08 1999-09-28 Bell Communications Research, Inc. Queue system and method for point-to-point message passing having a separate table for storing message state and identifier of processor assigned to process the message
US6073197A (en) * 1997-08-21 2000-06-06 Advanced Micro Devices Inc. Apparatus for and method of communicating data among devices interconnected on a bus by using a signalling channel to set up communications
US6085277A (en) * 1997-10-15 2000-07-04 International Business Machines Corporation Interrupt and message batching apparatus and method
USRE42761E1 (en) 1997-12-31 2011-09-27 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US5941972A (en) 1997-12-31 1999-08-24 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US6571206B1 (en) * 1998-01-15 2003-05-27 Phoenix Technologies Ltd. Apparatus and method for emulating an I/O instruction for the correct processor and for servicing software SMI's in a multi-processor environment
US6701429B1 (en) 1998-12-03 2004-03-02 Telefonaktiebolaget Lm Ericsson(Publ) System and method of start-up in efficient way for multi-processor systems based on returned identification information read from pre-determined memory location
US7478185B2 (en) * 2007-01-05 2009-01-13 International Business Machines Corporation Directly initiating by external adapters the setting of interruption initiatives
JP7318423B2 (en) 2019-08-30 2023-08-01 富士通株式会社 COMMUNICATION CONTROL DEVICE, COMMUNICATION CONTROL METHOD AND COMMUNICATION CONTROL PROGRAM

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4276594A (en) * 1978-01-27 1981-06-30 Gould Inc. Modicon Division Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same
US4207609A (en) * 1978-05-08 1980-06-10 International Business Machines Corporation Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system
US4271468A (en) * 1979-11-06 1981-06-02 International Business Machines Corp. Multiprocessor mechanism for handling channel interrupts
FR2470412B1 (en) * 1979-11-19 1986-10-03 Bull Sa METHOD AND DEVICE FOR ACCOUNTING AND MANAGING ASYNCHRONOUS EVENTS TRANSMITTED BY PERIPHERAL DEVICES IN A DATA PROCESSING SYSTEM
US4396984A (en) * 1981-03-06 1983-08-02 International Business Machines Corporation Peripheral systems employing multipathing, path and access grouping
US4562533A (en) * 1981-12-03 1985-12-31 Ncr Corporation Data communications system to system adapter
US4796176A (en) * 1985-11-15 1989-01-03 Data General Corporation Interrupt handling in a multiprocessor computing system
US4783730A (en) * 1986-09-19 1988-11-08 Datapoint Corporation Input/output control technique utilizing multilevel memory structure for processor and I/O communication
US4888691A (en) * 1988-03-09 1989-12-19 Prime Computer, Inc. Method for disk I/O transfer

Also Published As

Publication number Publication date
KR910017306A (en) 1991-11-05
AU654268B2 (en) 1994-11-03
EP0446077A3 (en) 1993-01-07
KR950008837B1 (en) 1995-08-08
DE69122142D1 (en) 1996-10-24
EP0446077B1 (en) 1996-09-18
US5507032A (en) 1996-04-09
DE69122142T2 (en) 1997-01-23
AU7281391A (en) 1991-09-12
CA2037989C (en) 1998-07-28
EP0446077A2 (en) 1991-09-11

Similar Documents

Publication Publication Date Title
CA2037989A1 (en) Control system for multi-processor system
EP0380851A3 (en) Modular crossbar interconnections in a digital computer
CA2283185A1 (en) Assay device processing instrument
YU231088A (en) Device and process for exchanging controlling of resources partitions in system for data processing which has central processing units, which uses different operation systems
EP0359241A3 (en) Control method for distributed processing system
CA2042783A1 (en) Self configuring controller
GB2282244B (en) Integrated circuit
EP0384435A3 (en) Power signal processing system
CA2080401A1 (en) Network system and its software management method
CA2158153A1 (en) Method and apparatus for configuring systems
TW253947B (en) A data processing system
CA2146243A1 (en) General analysis system
EP0147857A3 (en) Parallel data processing system
CA2116826A1 (en) Data Processing System Using a Non-Multiplexed, Asynchronous Address/Data Bus System
ATE218225T1 (en) MULTI-PROCESSOR SYSTEM WITH MULTIPLE COMMAND SOURCES
KR950004022A (en) Distributed Processing Integrated Management System
DE3586988D1 (en) INTERFACE MODULE FOR CONNECTING DATA SOURCES WITH DATA Sinks AND MEDIATION SYSTEMS WITH SUCH INTERFACE MODULES.
EP0201088A3 (en) Parallel computer
JPS6428735A (en) Interruption control system
SU911528A1 (en) Multichannel device for servicing interrogations
JPS56111931A (en) Data transfer device
JPS56129473A (en) Facsimile device with memory device
JPS57105021A (en) Input/output device
JPS5494253A (en) Plurality of electronic computer systems
JPS6488761A (en) Bus connection system

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed