CA2029248C - Dual framing bit sequence alignment apparatus and method - Google Patents
Dual framing bit sequence alignment apparatus and methodInfo
- Publication number
- CA2029248C CA2029248C CA 2029248 CA2029248A CA2029248C CA 2029248 C CA2029248 C CA 2029248C CA 2029248 CA2029248 CA 2029248 CA 2029248 A CA2029248 A CA 2029248A CA 2029248 C CA2029248 C CA 2029248C
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- bit
- framed
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- 238000000034 method Methods 0.000 title claims description 16
- 238000009432 framing Methods 0.000 title claims description 9
- 230000009977 dual effect Effects 0.000 title description 2
- 238000002864 sequence alignment Methods 0.000 title 1
- 230000001131 transforming effect Effects 0.000 claims 13
- 230000004044 response Effects 0.000 abstract description 7
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 101150034533 ATIC gene Proteins 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
ABSTRACT
A dual-framing-bit-alignment apparatus having a communications channel, a data device, an encryptor, a framing-bit device, a decryptor, a first framing-bit repositioner, and a second framing-bit repositioner.
The first data device generates a first data-bit sequence having a first framing-bit sequence. The encryptor encrypts the first data-bit sequence as an encrypted-bit sequence. The framing-bit device substitutes on the encrypted-bit sequence, a second framing-bit sequence, thereby generating a framed-encrypted-bit sequence. The decryptor decrypts the framed-encrypted-bit sequence as a second data-bit sequence. The second data-bit sequence contains errors due to the second framing-bit sequence. A second framing-bit repositioner detects in the second data-bit sequence, the first framing-bit sequence and the errors.
In response to detecting the errors and the first framing-bit sequence, the first framing-bit repositioner aligns the first framing-bit sequence with the second framing-bit sequence.
A dual-framing-bit-alignment apparatus having a communications channel, a data device, an encryptor, a framing-bit device, a decryptor, a first framing-bit repositioner, and a second framing-bit repositioner.
The first data device generates a first data-bit sequence having a first framing-bit sequence. The encryptor encrypts the first data-bit sequence as an encrypted-bit sequence. The framing-bit device substitutes on the encrypted-bit sequence, a second framing-bit sequence, thereby generating a framed-encrypted-bit sequence. The decryptor decrypts the framed-encrypted-bit sequence as a second data-bit sequence. The second data-bit sequence contains errors due to the second framing-bit sequence. A second framing-bit repositioner detects in the second data-bit sequence, the first framing-bit sequence and the errors.
In response to detecting the errors and the first framing-bit sequence, the first framing-bit repositioner aligns the first framing-bit sequence with the second framing-bit sequence.
Description
- 2 0 2 ~ 2 ~ 8 . .
DUAL FRAMIN~ BIT SEQUENCE
ALIGNklENT APPARATUS AND METHOD
BACKGROUND OF THE INVENTION
This invention relates to secure communications, and more particularly to a method and apparatus for aligned a first framing bit sequence on a plain te~t signal with a second framing bit sequence on a ciphertext signal. -DESCRIPTION OF THE PRIOR ART
.
The Tl Network, as shown in FIG. 1, allows the transmission of data between users at 1.~44 Mbps.
Because of the equipment used in the Tl network, i m specifications for the Tl service permit no more than fifteen consecutive O-bits to be sent seriall~ in a data-bit sequence~ without a l-bit. Additionally, in ~ - ;
each and every time window of 8X(n'+l) bits, were n' can equal 1 through 23, there must be at least n' l-bits present, These specifications are called the ones-bit density requirement. This requirement is necessary for keeping equipment, such as repeaters, in the network `-~
O ~ .
~ . `
- 2~292~8 ~;~
from losin~ svnchronization, A user of the T~ network typically meets this requirement using a channel service ;;~
unit (~S~) inserted between the user's equipment and the Tl network.
The specifications for data transmission through the Tl network further include having 193 bit frames, with the frame synchronization bit included as the 193rd bit. The frame synchronization bits typically are ;;
alternating l-bits and 0-bits, and cannot be altered by the channel service unit or other user interface ~ `
equipment.
A problem exists in the prior art when data from a user and his modem are properly formatted for the Tl network. and are encrypted just prior to transmission lS over the channel. While the frame synchronization bits will appear at the receiving end in the decrypted data-bit sequence. the frame synchronization bits are not present in the Tl channel due to encryption. ;~
The problem in the prior art ~ith encryption is ! 20 that all essential information in a data-bit sequence, includin~ the frame synchronization bit-ii. are scrambled -~
~ ;.
i'l `
: , .,.. . ~
2 ~ 2 9 2 4 8 - 3 ~
~-~3 or encrypted, as the data-bit sequence passes through an ~; -., : , ::: :-. encryption device. Due to security requirements, it is ~i not permissible to have a device which bypasses the encryptor or the decryptor for tracking the frame S synchronization bit from the plaintext and substituting the fram~e synchronization bit in the ciphertext. Using such a device would be a security violation.
A ~
~? One prior art solution is to delete the frame synchronization bits prior to encryption~ and then add ;
i. l - :.
one bit per frarne after encryption to the encrypted bit sequence. Before the decryptor, the framing bits, one bit per frame, on the encrypted bit sequence are ~-~'! deleted. This prior art solution does not work. All the essential information in the data bit sequence prior --. 15 to encryption are stcrambled with the encryptor. After -~
l the decryptort where are the fra~ing bits to be `'1 inserted?
j O~JECTS AND SUMMARY OF THE INVENTION
: ::: ::
'~ An object of the present inventlon is to provide a ~ 20 method and apparatus which will automatically track a -''~
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,,:
~ ~:
-` 2~292~8 - 4 ~
frarning-bit data sequence in cipherte~t at a receiver after being deciphered by a decryption unit.
Another object of the present invention is to `-~
provide a method and apparatus which will allow trackillg 5a first framing-bit sequence in plaintext and a second~ - -, i ~ . ~: ~ . .
framing-bit sequence in ciphertext without tampering or bypassing an encryption or decryption unit.
' ' A further object of the invention is to provide a method and apparatus for aligning a first framing-bit 10data sequence present in a first data-bit sequence from a data device, with a second framing-bit sequence present in ciphertext without the need or use of costly and complex equipmen-t such as phase lock loops. first in first out memories and buffers, and other complex 15equipment.
According to the present invention~ as embodied and broadly described herein, a dual-framing-bit-alignment apparatus is provided comprising a communications :: ~:::
channel, generating means, encoding means, substituting 20and transmitting means, decoding means. detecting ~neans.
2~292~8 ~
. . "
DUAL FRAMIN~ BIT SEQUENCE
ALIGNklENT APPARATUS AND METHOD
BACKGROUND OF THE INVENTION
This invention relates to secure communications, and more particularly to a method and apparatus for aligned a first framing bit sequence on a plain te~t signal with a second framing bit sequence on a ciphertext signal. -DESCRIPTION OF THE PRIOR ART
.
The Tl Network, as shown in FIG. 1, allows the transmission of data between users at 1.~44 Mbps.
Because of the equipment used in the Tl network, i m specifications for the Tl service permit no more than fifteen consecutive O-bits to be sent seriall~ in a data-bit sequence~ without a l-bit. Additionally, in ~ - ;
each and every time window of 8X(n'+l) bits, were n' can equal 1 through 23, there must be at least n' l-bits present, These specifications are called the ones-bit density requirement. This requirement is necessary for keeping equipment, such as repeaters, in the network `-~
O ~ .
~ . `
- 2~292~8 ~;~
from losin~ svnchronization, A user of the T~ network typically meets this requirement using a channel service ;;~
unit (~S~) inserted between the user's equipment and the Tl network.
The specifications for data transmission through the Tl network further include having 193 bit frames, with the frame synchronization bit included as the 193rd bit. The frame synchronization bits typically are ;;
alternating l-bits and 0-bits, and cannot be altered by the channel service unit or other user interface ~ `
equipment.
A problem exists in the prior art when data from a user and his modem are properly formatted for the Tl network. and are encrypted just prior to transmission lS over the channel. While the frame synchronization bits will appear at the receiving end in the decrypted data-bit sequence. the frame synchronization bits are not present in the Tl channel due to encryption. ;~
The problem in the prior art ~ith encryption is ! 20 that all essential information in a data-bit sequence, includin~ the frame synchronization bit-ii. are scrambled -~
~ ;.
i'l `
: , .,.. . ~
2 ~ 2 9 2 4 8 - 3 ~
~-~3 or encrypted, as the data-bit sequence passes through an ~; -., : , ::: :-. encryption device. Due to security requirements, it is ~i not permissible to have a device which bypasses the encryptor or the decryptor for tracking the frame S synchronization bit from the plaintext and substituting the fram~e synchronization bit in the ciphertext. Using such a device would be a security violation.
A ~
~? One prior art solution is to delete the frame synchronization bits prior to encryption~ and then add ;
i. l - :.
one bit per frarne after encryption to the encrypted bit sequence. Before the decryptor, the framing bits, one bit per frame, on the encrypted bit sequence are ~-~'! deleted. This prior art solution does not work. All the essential information in the data bit sequence prior --. 15 to encryption are stcrambled with the encryptor. After -~
l the decryptort where are the fra~ing bits to be `'1 inserted?
j O~JECTS AND SUMMARY OF THE INVENTION
: ::: ::
'~ An object of the present inventlon is to provide a ~ 20 method and apparatus which will automatically track a -''~
`j1 , . . .
,,:
~ ~:
-` 2~292~8 - 4 ~
frarning-bit data sequence in cipherte~t at a receiver after being deciphered by a decryption unit.
Another object of the present invention is to `-~
provide a method and apparatus which will allow trackillg 5a first framing-bit sequence in plaintext and a second~ - -, i ~ . ~: ~ . .
framing-bit sequence in ciphertext without tampering or bypassing an encryption or decryption unit.
' ' A further object of the invention is to provide a method and apparatus for aligning a first framing-bit 10data sequence present in a first data-bit sequence from a data device, with a second framing-bit sequence present in ciphertext without the need or use of costly and complex equipmen-t such as phase lock loops. first in first out memories and buffers, and other complex 15equipment.
According to the present invention~ as embodied and broadly described herein, a dual-framing-bit-alignment apparatus is provided comprising a communications :: ~:::
channel, generating means, encoding means, substituting 20and transmitting means, decoding means. detecting ~neans.
2~292~8 ~
. . "
- 5 - ~ -~
and ali~ning means. The encodin~ means may be embodied .~ , . . . .
as an encryptor. the substituting means may be embodied as a framing-bit device, the decoding means may be , embodied as a decryptor, and the detecting means and ';~ 5 aligning means may be embodi~d ~as a first framing-bit repositioner and a second framing-bit repositioner, respectively. The data device is coupled to the first framing-bit repositioner, and the first framing-bit ~l repositioner is coupled to the encryptor. The encryptor `, 10 is coupled to the framing-bit device which is coupled to s, the communications channel. At the receiver, the j communications channel is coupled to the decryptor, which is coupled to the second framing-bit repositioner.
The generating means generates a first data-bit sequence having a first framing-bit sequence. The , encoding means encodes the first data-bit sequence as an ~¦ encoded-bit sequence. The substituting means substitutes on the encoded-bit sequence~ a second framing-bit sequence, thereby generating a framed-encoded-bit sequence. The transmitting means transmits ~a the framed-encoded-bit sequence with the second framing-bit sequence over the communications channel. The ,, .p~
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decod1ng means decodes the ~ramed encoded-bit sequence , as a second data-bit sequence. The second data-bit y sequence contains errors due to the second frarning-bit ~ -I sequence. which was substituted on the encoded-bit i 5 sequence.
~, ~
The detecting means detects, embedded in the second data-bit sequence, the first framing-bit sequence. The detecting means also detects the errors in the second data-bit sequence. The errors were caused by the second ~ 10 framing-bit sequence, for each bit for which it was ;' substituted on the encoded-bit sequence. Thus, the ¦ second framing-bit sequence appears as errors in the second data-bit sequence. In response to detecting. in I the second data-bit sequence, the first framing-bit ~, 15 sequence and the errors from the second framing-bit sequence, the detecting means generates an alignment signal. The alignment signal is sent through the 31 communications channel to the aligning means which is located betwèen the generating means and encoding means.
i 20 In response to receiving the alignment signal~ the aligning means shifts the framing-bit sequence until the detected errors and detected first framing-bit sequence ;
~3 ?
~' ?; ' ~ ~ ,: . . . ' :
.' ' . ' ' : ~ ' --` 2~29~g . :: ,~ :
are aligned at the detecting means. Accordingly, errors -~
appear in the second data-bit sequence only at the locations of the first framing-bit sequence.
The present invention also includes a method using -a dual-framing-bit-alignment apparatus for aligning a ¦
first framing-bit sequence embedded in a firs~ data-bit sequence with a second framing-bit sequence embedded in an encoded-bit sequence. The encoded-bit sequence may be an encrypted-bit sequence. The method comprises the '::
steps of decoding the encoded-bit sequence as a second ~-data-bit sequence; detecting the first framing-bit , . ..
sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to ~
the decoded framing-bit sequence; generating, responsive ~ -~o the detected first framing-bit sequence and the ~ I
¦ detected errors~ and alignment signai; and, aligning the -first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit I sequence.
1 20 Additional objects and advantages of the invention ;~
will be set forth in part in the description which follows, and in part will be obvious from the : :: :
: -: -,. ..
. : : ~
.: : .~ ,:
: .., -: . - .
2~292~
description~ or may be learned by practice of the ;.~ invention, The objects and advanta~es af the invention ,~ also may be realized and obtained by means of the instrumentalities and combinations particularly pointed ~.
out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINC;S - :
'.', :'''~.'''' . The accompanying drawings, which are incorporated , in and constitute a part of this specification, :~ illustrate partioular embodiments of the invention, and i '~ 10 together with the description, service to explain the :; principles of the invention. :
'' . '. ,'~'~ ' FIG. 1 is a block diagram~atic view of a channel service unit coupled to a Tl network; .
FIG. 2 is a bloc'~ diagrammatic view of an ~;~ 15 eMbodiment of a dual-framing-bit-alignMent apparatus according to the present invention;
FIG. 3 is a block diagram of a framing-bit repositioner; and - :
~9 ` ~`.
--` 202~2~8 -~
:
_ 9 _ ~, - - .
FIG. 4 illustrates the timing of the alignment signal.
:
" DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS ~
. .. ~:, Reference will now be made in detail to the present preferred embodiments of the invention, examples of -which are illustrated in the accompanying drawings.
. .
1 . -.
,!~ Referring to FIG. 2~ a preferred embodiment of a ~, dual-framing-bit-alignment apparatus is shown comprising : ::
a communications channel 30, generating means, encoding means, substituting means, decoding means, detecting means, and aligning means. The generating means is coupled to the encoding Means, and the encoding means is coupled to the communications channel. The decoding means is coupled to the communications channel, and the detecting means is coupled to the decoding means. The - -~
: - ': ". '-:
aligning means is coupled between the generating means and the encoding means. -In the exemplary arrangement shown. generating , ' `: " -' `'~:.':'.
means may be eMbodied as a data device 11 encoding --~
::
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~.. ". ~, " ::
2~292~
.. .
.~, . ..
means may be embodied as an encryptor 13, aligning means may be embodied as first framing-bit repositioner 12, substituting means may be embodied as framing-bit device 14 or framing-bit device 24, the decoding means may be --embodied as a decryptor 23. and the dietecting ~eans may be embodied as second framing-bit repositioner 22.
Encoding means, as used herein, includes any device which encodes or transforms the first data-bit sequence -;
to an encoded bit sequence or equivalent. The equivalent of an encoded bit sequence includes any encoded or encrypted version of the first data-bit sequence employing the concepts taught herein.
Decoding means, as used herein, includes any device which decodes or transforms the framed-encoded-bit sequence or equivalent to the second data-bit sequence. ;~
The equivalent of a framed-encoded-bit sequence includes any framed encrypted, transformed, or scrambled version of the first data-bit sequence employing the concepts i taught herein.
i~l 20 A preferred embodiment, as illustratively shown in ~ FIG. 2, uses the data device 11 for generating a first ~- -q :
'~
--`` 21~1292~8 :' ' ' '~.
data-bit sequence have a first framing-bit sequence.
The first framing-bit sequence might be, for example, an alternating sequence of l-bits and 0-bits located in the 193rd-bit position as found in the Tl network. The first framing-bit repositioner 12, wnich is coupled to the data device 11, may be used for aligning the first framing-bit sequence with a second framing-bit sequence.
The encryptor 13 is coupled to the first framing-bit ' repositioner 12 and encrypts the first data-bit sequence as an encrypted-bit sequence. The framing-bit device 14 substitutes a second framing-bit sequence onto the encrypted-bit sequence thereby generating a framed-encrypted-bit sequence, and transmits the framed-encrypted-bit sequence over the communications channel . ~ . - -. ~.- :.
30. The framing-bit device 14 may be embodied as a channel service with (CSU~
,~
I
The decryptor 23 is coupled to the communications channel 30, and decrypts the framed-encrypted-bit ;
sequence as a second data-bit sequence. A second ~ 20 framing-bit repositioner 22 is coupled to the decryptor -~
,l 23. The second framing-bit repositioner 22 detects the . ~ -.
~1 first framing-bit sequence embedded in the second data-,t bit sequence. The second framing-bit repositioner 22 -s ~1 :
'~t~ ' :.~i , :,' ,'' ' ' 2~292~8 :-:
also detects errors in the second data-bit sequence ~hich are due to the second framing-bit sequence t~hich -~
was substituted on the encrypted-bit sequence with :: I
framing-bit device 14. In response to the detected first framing bit sequence and the detected errors, the second framing-bit repositioner 22 generates an alignment signal which is sent to first framing-bit repositioner 12. :~
I ~.
In response to receiving the alignment signal t the :
I 10 first framing-bit repositioner 12 aligns the first ! framing-bit sequence so that in the second data-bit sequence, the first framing-bit sequence is in the same position as the detected errors.
' :
¦ The first framing~bit repositioner 12 may reposition the first framing-bit sequence in the first I data-bit sequence, to any desired bit location in ! response to the alignment signal.
The present invention may further include a second data device 21 and a second framing-bit device 24, for : -~
performing the same cooperative functions and operation as the first framing-bit device 14 and the first data .1 ' ', ~- ~
-- -.
~-` 2~292~8 :
- 13 - -~
device 11 for transmitting data in the reverse direction.
In operation, the first data device 11 generates a , :
first data-bit sequence which is transmitted through the first framing-bit rep~sitioner 12 and which may be buffered in registers or other device for purposes of delaying the first framing-bit sequence. The first ; .~
data-bit sequence includes the first framing-bit sequence as required for a communications network. such as the Tl network. The first data-bit sequence then passes to the first encryptor 13 and is encrypted as an encrypted-bit sequence, The encrypted-bit sequence - -passes to the first framing-bit device 14 wherein the second framing-bit sequence is substituted onto the :
encrypted-bit sequence thereby ~enerating a framed-encrypted-bit sequence. The substitution of the second framing-bit sequence onto the encrypted-bit sequence ;~
will cause errors when the framed-encrypted-bit sequence is decrypted. An assumption for the present invention ~,1 20 is that the encryptor used with this invention employs ~i, stream encipherment, not block encipherment, thus one .1 bit error rnay result for each one bit substituted by the first framing-bit device 14. The frarned-encrypted-bit t~ ' " "`
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j , sequence, which includes the subs-tituted second framing-bit sequence. is passed over comr~unicatit)ns channel 30.
's' :' ;' The decrvptor 23 decrypts the ~ramed-encrypted-bit sequence to a second data-bit sequence. The second data-bit sequence at this point includes errors in the ~ bit locations where the second framing-bit sequence was .', substituted onto the encrypted-bit sequence.
.~
~; The second framing-bit repositioner bit 22 detects the errors in the second data-bit sequence which are due to the second framing-bit sequence. The second frarning-bit repositioner 22 also detects the original first framing-bit sequence in the second data-bit sequence, which was included with the first data-bit sequence ¦ generated by data device 11. Assuming that the errors I 15 in the second data-bit sequence and the first framing- :
i bit sequence have different bit locations, then the second framing-bit repositioner 22 generates an alignment signal which is sent to the first framing-bit ~:
.~ repositioner 12. The alignment signal indicates to the first framing-bit repositioner 12 the amount of delay as , required of the first data-bit sequence~ which will :~.
!, align the first framing-bit sequence with the second :
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framing-bit sequence. The alignment will occur when the l detected errors in the second data-bit sequences are ~ aligned in the same positions as the first framing-bit sequence in the second data-bit sequence.
The first framing-bit repositioner 12 may include a shift re~ister 33 and multiplexer 34, as illustrated in FIG. 3. In normal operation, the first data-bit sequence passes through the shift register 33 through the multiplexer 34. Accordingly, at the output of the 10 rnultiplexer 34 is a delayed data-bit sequence, as illustrated in FIG. 4. In response to receiving the alignment signal. as shown in FIG. 4, the multiplexer switches the shift register 33 out of the circuit, and the data-bit sequence bypasses the shift register 33 and 15 passes through the multiplexer 34. When the alignment ~ signal is discontinued, the framing bit drops from the shift register 33 and the data-bit sequence passes through shift register 33 through multiplexer 34.
Accordingly, the framing bit relocates, as indicated in FIG. 3 from between bit locations 192 and 1 to between -: ~: . ..
~ bit locations 4 and 5. .-: ~
: ::: -: :
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.
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., :
~ The first framing-bit repositioner l2 may relocate -1 the bit locations of the first frarning-b:it sequence to a ~ different bit position in the first data-bit sequence.
`~ In this case. an interceptor of the framed-encrypted-bit sequence will not have knowledge of where the first framing-bit sequence was in the first data-bit sequence.
This relocation denies the crypto-analyst side information of location or bit position of the first framing-bit sequence.
. .
'~ 10 The present invention further includes a method using a dual-framing-bit-alignment apparatus for ;~ aligning a first framing-bit sequence embedded in a first data-bit sequence with a second framing-bit sequence embedded in an encoded-bit sequence. The encoded-bit sequence may be an encrypted-bit sequence.
. The method comprises the steps of decoding the encoded-;~ bit sequence as a second data-bit sequence; detecting l the first framing-bit sequence embedded in the second .
data-bit sequence; detecting errors in the second data- ~
! . . .
bit sequence; generating, responsive to the detected first framing-bit sequence and the detected errors~ an alignment signal; and aligning the first framing-bit sequence in the first data-bit sequence with the ~ `
~3 detected errors in the second data-bit sequence.
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!.' ^ - 17 -The method may additionally include the steps of repositioning the first framing-bit sequence in the first data-bit sequence so that knowledge of the ~ ~;
~; location of the first framing-bit sequence in the first ~-data-bit sequence is not determined by an interceptor of the framed-encrypted-bit sequence which has the second ., . ~ .
~i framing-bit sequence substituted thereon.
~,,, The second framing-bit repositioner of the present invention may have a shift register which can delay or i 10 substitute the framing-bit sequence in any of the bit slots from 0 to 192 bits~ for example, for the Tl network. The dual-framing-bit-alignment apparatus adjusts the length of the delay such that at the output of the second framing-bit repositioner. the first framing-bit sequence is positioned where the second framing-bit sequence has been written over the encrypted-bit sequence.
~Ji The present invention has an advantage where there is a first framing-bit sequence in a first data-bit sequence, the first framing-bit sequence can be preserved when the first data-bit sequence is encrypted for transmission over a communications channel. At the 7~J '` ~ ~' ` - ' ~'. ' -` ""' "`'~`..
' ` ' 7 ' ;,, ~
- 2~2~2~g , same time~ there is no physical device connecting the i~ encrvption chanllel to the plainte~t channel by bypassing ~ the encryptor or decryptor.
3 Errors can be detected in the second data-bit sequence which are due to the second framing-bit sequence, by employing error detection schemes such as cyclic redundancy codes with the first data-bit sequence. Thus. when the first data-bit sequence passes through the encryptor to the decryptor as a second data-~ 10 bit sequence, the errors which are due to the second 'I framinO-bit sequence which was substituted on the ~ encrypted-bit sequence can be detected. Additionally, ; the proper error correcting code and detecting scheme '~ can be used to tell the distance from the actual 1 15 detected first framing-bit sequence detected in the second data-bit sequence, and the detected errors in the second data-bit reference.
l It will be apparent to those skilled in the art I that various modifications can be ~ade to the dual-~ 20 framing-bit-alignment apparatus of the instant invention ¦ without departing from the scope or spirit of the ~1 '' `~,
and ali~ning means. The encodin~ means may be embodied .~ , . . . .
as an encryptor. the substituting means may be embodied as a framing-bit device, the decoding means may be , embodied as a decryptor, and the detecting means and ';~ 5 aligning means may be embodi~d ~as a first framing-bit repositioner and a second framing-bit repositioner, respectively. The data device is coupled to the first framing-bit repositioner, and the first framing-bit ~l repositioner is coupled to the encryptor. The encryptor `, 10 is coupled to the framing-bit device which is coupled to s, the communications channel. At the receiver, the j communications channel is coupled to the decryptor, which is coupled to the second framing-bit repositioner.
The generating means generates a first data-bit sequence having a first framing-bit sequence. The , encoding means encodes the first data-bit sequence as an ~¦ encoded-bit sequence. The substituting means substitutes on the encoded-bit sequence~ a second framing-bit sequence, thereby generating a framed-encoded-bit sequence. The transmitting means transmits ~a the framed-encoded-bit sequence with the second framing-bit sequence over the communications channel. The ,, .p~
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decod1ng means decodes the ~ramed encoded-bit sequence , as a second data-bit sequence. The second data-bit y sequence contains errors due to the second frarning-bit ~ -I sequence. which was substituted on the encoded-bit i 5 sequence.
~, ~
The detecting means detects, embedded in the second data-bit sequence, the first framing-bit sequence. The detecting means also detects the errors in the second data-bit sequence. The errors were caused by the second ~ 10 framing-bit sequence, for each bit for which it was ;' substituted on the encoded-bit sequence. Thus, the ¦ second framing-bit sequence appears as errors in the second data-bit sequence. In response to detecting. in I the second data-bit sequence, the first framing-bit ~, 15 sequence and the errors from the second framing-bit sequence, the detecting means generates an alignment signal. The alignment signal is sent through the 31 communications channel to the aligning means which is located betwèen the generating means and encoding means.
i 20 In response to receiving the alignment signal~ the aligning means shifts the framing-bit sequence until the detected errors and detected first framing-bit sequence ;
~3 ?
~' ?; ' ~ ~ ,: . . . ' :
.' ' . ' ' : ~ ' --` 2~29~g . :: ,~ :
are aligned at the detecting means. Accordingly, errors -~
appear in the second data-bit sequence only at the locations of the first framing-bit sequence.
The present invention also includes a method using -a dual-framing-bit-alignment apparatus for aligning a ¦
first framing-bit sequence embedded in a firs~ data-bit sequence with a second framing-bit sequence embedded in an encoded-bit sequence. The encoded-bit sequence may be an encrypted-bit sequence. The method comprises the '::
steps of decoding the encoded-bit sequence as a second ~-data-bit sequence; detecting the first framing-bit , . ..
sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to ~
the decoded framing-bit sequence; generating, responsive ~ -~o the detected first framing-bit sequence and the ~ I
¦ detected errors~ and alignment signai; and, aligning the -first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit I sequence.
1 20 Additional objects and advantages of the invention ;~
will be set forth in part in the description which follows, and in part will be obvious from the : :: :
: -: -,. ..
. : : ~
.: : .~ ,:
: .., -: . - .
2~292~
description~ or may be learned by practice of the ;.~ invention, The objects and advanta~es af the invention ,~ also may be realized and obtained by means of the instrumentalities and combinations particularly pointed ~.
out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINC;S - :
'.', :'''~.'''' . The accompanying drawings, which are incorporated , in and constitute a part of this specification, :~ illustrate partioular embodiments of the invention, and i '~ 10 together with the description, service to explain the :; principles of the invention. :
'' . '. ,'~'~ ' FIG. 1 is a block diagram~atic view of a channel service unit coupled to a Tl network; .
FIG. 2 is a bloc'~ diagrammatic view of an ~;~ 15 eMbodiment of a dual-framing-bit-alignMent apparatus according to the present invention;
FIG. 3 is a block diagram of a framing-bit repositioner; and - :
~9 ` ~`.
--` 202~2~8 -~
:
_ 9 _ ~, - - .
FIG. 4 illustrates the timing of the alignment signal.
:
" DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS ~
. .. ~:, Reference will now be made in detail to the present preferred embodiments of the invention, examples of -which are illustrated in the accompanying drawings.
. .
1 . -.
,!~ Referring to FIG. 2~ a preferred embodiment of a ~, dual-framing-bit-alignment apparatus is shown comprising : ::
a communications channel 30, generating means, encoding means, substituting means, decoding means, detecting means, and aligning means. The generating means is coupled to the encoding Means, and the encoding means is coupled to the communications channel. The decoding means is coupled to the communications channel, and the detecting means is coupled to the decoding means. The - -~
: - ': ". '-:
aligning means is coupled between the generating means and the encoding means. -In the exemplary arrangement shown. generating , ' `: " -' `'~:.':'.
means may be eMbodied as a data device 11 encoding --~
::
' ~ ,':' -' ' ,' ~
:~ . . ~ :
~.. ". ~, " ::
2~292~
.. .
.~, . ..
means may be embodied as an encryptor 13, aligning means may be embodied as first framing-bit repositioner 12, substituting means may be embodied as framing-bit device 14 or framing-bit device 24, the decoding means may be --embodied as a decryptor 23. and the dietecting ~eans may be embodied as second framing-bit repositioner 22.
Encoding means, as used herein, includes any device which encodes or transforms the first data-bit sequence -;
to an encoded bit sequence or equivalent. The equivalent of an encoded bit sequence includes any encoded or encrypted version of the first data-bit sequence employing the concepts taught herein.
Decoding means, as used herein, includes any device which decodes or transforms the framed-encoded-bit sequence or equivalent to the second data-bit sequence. ;~
The equivalent of a framed-encoded-bit sequence includes any framed encrypted, transformed, or scrambled version of the first data-bit sequence employing the concepts i taught herein.
i~l 20 A preferred embodiment, as illustratively shown in ~ FIG. 2, uses the data device 11 for generating a first ~- -q :
'~
--`` 21~1292~8 :' ' ' '~.
data-bit sequence have a first framing-bit sequence.
The first framing-bit sequence might be, for example, an alternating sequence of l-bits and 0-bits located in the 193rd-bit position as found in the Tl network. The first framing-bit repositioner 12, wnich is coupled to the data device 11, may be used for aligning the first framing-bit sequence with a second framing-bit sequence.
The encryptor 13 is coupled to the first framing-bit ' repositioner 12 and encrypts the first data-bit sequence as an encrypted-bit sequence. The framing-bit device 14 substitutes a second framing-bit sequence onto the encrypted-bit sequence thereby generating a framed-encrypted-bit sequence, and transmits the framed-encrypted-bit sequence over the communications channel . ~ . - -. ~.- :.
30. The framing-bit device 14 may be embodied as a channel service with (CSU~
,~
I
The decryptor 23 is coupled to the communications channel 30, and decrypts the framed-encrypted-bit ;
sequence as a second data-bit sequence. A second ~ 20 framing-bit repositioner 22 is coupled to the decryptor -~
,l 23. The second framing-bit repositioner 22 detects the . ~ -.
~1 first framing-bit sequence embedded in the second data-,t bit sequence. The second framing-bit repositioner 22 -s ~1 :
'~t~ ' :.~i , :,' ,'' ' ' 2~292~8 :-:
also detects errors in the second data-bit sequence ~hich are due to the second framing-bit sequence t~hich -~
was substituted on the encrypted-bit sequence with :: I
framing-bit device 14. In response to the detected first framing bit sequence and the detected errors, the second framing-bit repositioner 22 generates an alignment signal which is sent to first framing-bit repositioner 12. :~
I ~.
In response to receiving the alignment signal t the :
I 10 first framing-bit repositioner 12 aligns the first ! framing-bit sequence so that in the second data-bit sequence, the first framing-bit sequence is in the same position as the detected errors.
' :
¦ The first framing~bit repositioner 12 may reposition the first framing-bit sequence in the first I data-bit sequence, to any desired bit location in ! response to the alignment signal.
The present invention may further include a second data device 21 and a second framing-bit device 24, for : -~
performing the same cooperative functions and operation as the first framing-bit device 14 and the first data .1 ' ', ~- ~
-- -.
~-` 2~292~8 :
- 13 - -~
device 11 for transmitting data in the reverse direction.
In operation, the first data device 11 generates a , :
first data-bit sequence which is transmitted through the first framing-bit rep~sitioner 12 and which may be buffered in registers or other device for purposes of delaying the first framing-bit sequence. The first ; .~
data-bit sequence includes the first framing-bit sequence as required for a communications network. such as the Tl network. The first data-bit sequence then passes to the first encryptor 13 and is encrypted as an encrypted-bit sequence, The encrypted-bit sequence - -passes to the first framing-bit device 14 wherein the second framing-bit sequence is substituted onto the :
encrypted-bit sequence thereby ~enerating a framed-encrypted-bit sequence. The substitution of the second framing-bit sequence onto the encrypted-bit sequence ;~
will cause errors when the framed-encrypted-bit sequence is decrypted. An assumption for the present invention ~,1 20 is that the encryptor used with this invention employs ~i, stream encipherment, not block encipherment, thus one .1 bit error rnay result for each one bit substituted by the first framing-bit device 14. The frarned-encrypted-bit t~ ' " "`
`. ~., ''.' ' ' .'.
:: .
-` 2~2~2~8 q ::
j , sequence, which includes the subs-tituted second framing-bit sequence. is passed over comr~unicatit)ns channel 30.
's' :' ;' The decrvptor 23 decrypts the ~ramed-encrypted-bit sequence to a second data-bit sequence. The second data-bit sequence at this point includes errors in the ~ bit locations where the second framing-bit sequence was .', substituted onto the encrypted-bit sequence.
.~
~; The second framing-bit repositioner bit 22 detects the errors in the second data-bit sequence which are due to the second framing-bit sequence. The second frarning-bit repositioner 22 also detects the original first framing-bit sequence in the second data-bit sequence, which was included with the first data-bit sequence ¦ generated by data device 11. Assuming that the errors I 15 in the second data-bit sequence and the first framing- :
i bit sequence have different bit locations, then the second framing-bit repositioner 22 generates an alignment signal which is sent to the first framing-bit ~:
.~ repositioner 12. The alignment signal indicates to the first framing-bit repositioner 12 the amount of delay as , required of the first data-bit sequence~ which will :~.
!, align the first framing-bit sequence with the second :
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,3 ~
framing-bit sequence. The alignment will occur when the l detected errors in the second data-bit sequences are ~ aligned in the same positions as the first framing-bit sequence in the second data-bit sequence.
The first framing-bit repositioner 12 may include a shift re~ister 33 and multiplexer 34, as illustrated in FIG. 3. In normal operation, the first data-bit sequence passes through the shift register 33 through the multiplexer 34. Accordingly, at the output of the 10 rnultiplexer 34 is a delayed data-bit sequence, as illustrated in FIG. 4. In response to receiving the alignment signal. as shown in FIG. 4, the multiplexer switches the shift register 33 out of the circuit, and the data-bit sequence bypasses the shift register 33 and 15 passes through the multiplexer 34. When the alignment ~ signal is discontinued, the framing bit drops from the shift register 33 and the data-bit sequence passes through shift register 33 through multiplexer 34.
Accordingly, the framing bit relocates, as indicated in FIG. 3 from between bit locations 192 and 1 to between -: ~: . ..
~ bit locations 4 and 5. .-: ~
: ::: -: :
- .-: - - ~
.
-` 2~2~2~
., :
~ The first framing-bit repositioner l2 may relocate -1 the bit locations of the first frarning-b:it sequence to a ~ different bit position in the first data-bit sequence.
`~ In this case. an interceptor of the framed-encrypted-bit sequence will not have knowledge of where the first framing-bit sequence was in the first data-bit sequence.
This relocation denies the crypto-analyst side information of location or bit position of the first framing-bit sequence.
. .
'~ 10 The present invention further includes a method using a dual-framing-bit-alignment apparatus for ;~ aligning a first framing-bit sequence embedded in a first data-bit sequence with a second framing-bit sequence embedded in an encoded-bit sequence. The encoded-bit sequence may be an encrypted-bit sequence.
. The method comprises the steps of decoding the encoded-;~ bit sequence as a second data-bit sequence; detecting l the first framing-bit sequence embedded in the second .
data-bit sequence; detecting errors in the second data- ~
! . . .
bit sequence; generating, responsive to the detected first framing-bit sequence and the detected errors~ an alignment signal; and aligning the first framing-bit sequence in the first data-bit sequence with the ~ `
~3 detected errors in the second data-bit sequence.
'!! . , ,~: ', ' '''!~ ~". ` ' ` '" '` ~
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!.' ^ - 17 -The method may additionally include the steps of repositioning the first framing-bit sequence in the first data-bit sequence so that knowledge of the ~ ~;
~; location of the first framing-bit sequence in the first ~-data-bit sequence is not determined by an interceptor of the framed-encrypted-bit sequence which has the second ., . ~ .
~i framing-bit sequence substituted thereon.
~,,, The second framing-bit repositioner of the present invention may have a shift register which can delay or i 10 substitute the framing-bit sequence in any of the bit slots from 0 to 192 bits~ for example, for the Tl network. The dual-framing-bit-alignment apparatus adjusts the length of the delay such that at the output of the second framing-bit repositioner. the first framing-bit sequence is positioned where the second framing-bit sequence has been written over the encrypted-bit sequence.
~Ji The present invention has an advantage where there is a first framing-bit sequence in a first data-bit sequence, the first framing-bit sequence can be preserved when the first data-bit sequence is encrypted for transmission over a communications channel. At the 7~J '` ~ ~' ` - ' ~'. ' -` ""' "`'~`..
' ` ' 7 ' ;,, ~
- 2~2~2~g , same time~ there is no physical device connecting the i~ encrvption chanllel to the plainte~t channel by bypassing ~ the encryptor or decryptor.
3 Errors can be detected in the second data-bit sequence which are due to the second framing-bit sequence, by employing error detection schemes such as cyclic redundancy codes with the first data-bit sequence. Thus. when the first data-bit sequence passes through the encryptor to the decryptor as a second data-~ 10 bit sequence, the errors which are due to the second 'I framinO-bit sequence which was substituted on the ~ encrypted-bit sequence can be detected. Additionally, ; the proper error correcting code and detecting scheme '~ can be used to tell the distance from the actual 1 15 detected first framing-bit sequence detected in the second data-bit sequence, and the detected errors in the second data-bit reference.
l It will be apparent to those skilled in the art I that various modifications can be ~ade to the dual-~ 20 framing-bit-alignment apparatus of the instant invention ¦ without departing from the scope or spirit of the ~1 '' `~,
Claims (20)
1. A dual-framing-bit-alignment apparatus comprising:
a communications channel;
means for generating a first data-bit sequence having a first framing-bit sequence;
an encryptor coupled to said generating means for encrypting the first data-bit sequence as an encrypted-bit sequence;
means coupled to said encryptor for substituting a second framing-bit sequence onto the encrypted-bit sequence to generate a framed-encrypted-bit sequence and transmitting the framed-encrypted-bit sequence with the second framing-bit over said communications channel;
a decryptor coupled to said communications channel for decrypting the framed-encrypted-bit sequence as a second data-bit sequence;
means coupled to said decryptor for detecting the first framing-bit sequence embedded in the second data-bit sequence, for detecting errors in the second data-bit sequence due to the second framing-bit sequence being substituted on the encrypted-bit sequence, and responsive to the detected first framing-bit sequence and detected errors for generating an alignment signal;
and means coupled through said encryptor. said communications channel and said decryptor, to said detecting means. and responsive to the alignment signal for aligning the detected errors with the first framing-bit sequence in the first data-bit sequence.
a communications channel;
means for generating a first data-bit sequence having a first framing-bit sequence;
an encryptor coupled to said generating means for encrypting the first data-bit sequence as an encrypted-bit sequence;
means coupled to said encryptor for substituting a second framing-bit sequence onto the encrypted-bit sequence to generate a framed-encrypted-bit sequence and transmitting the framed-encrypted-bit sequence with the second framing-bit over said communications channel;
a decryptor coupled to said communications channel for decrypting the framed-encrypted-bit sequence as a second data-bit sequence;
means coupled to said decryptor for detecting the first framing-bit sequence embedded in the second data-bit sequence, for detecting errors in the second data-bit sequence due to the second framing-bit sequence being substituted on the encrypted-bit sequence, and responsive to the detected first framing-bit sequence and detected errors for generating an alignment signal;
and means coupled through said encryptor. said communications channel and said decryptor, to said detecting means. and responsive to the alignment signal for aligning the detected errors with the first framing-bit sequence in the first data-bit sequence.
2. A dual-framing-bit-alignment apparatus comprising:
means for generating a first data-bit sequence having a first framing-bit sequence;
first means for transforming the first data-bit sequence to an encoded-bit sequence;
means for substituting a second framing-bit sequence onto the encoded-bit sequence to generate a framed-encoded-bit sequence;
second means for transforming the framed-encoded-bit sequence to a second data-bit sequence;
means for detecting the first framing-bit sequence embedded in the second data-bit sequence, for detecting errors in the second data-bit sequence due to the second framing-bit sequence, and for generating an alignment signal; and means responsive to the alignment signal for aligning the detected errors with the first framing-bit sequence.
means for generating a first data-bit sequence having a first framing-bit sequence;
first means for transforming the first data-bit sequence to an encoded-bit sequence;
means for substituting a second framing-bit sequence onto the encoded-bit sequence to generate a framed-encoded-bit sequence;
second means for transforming the framed-encoded-bit sequence to a second data-bit sequence;
means for detecting the first framing-bit sequence embedded in the second data-bit sequence, for detecting errors in the second data-bit sequence due to the second framing-bit sequence, and for generating an alignment signal; and means responsive to the alignment signal for aligning the detected errors with the first framing-bit sequence.
3. The dual-framing-bit-alignment apparatus as set forth in claim 2 wherein said first and second transforming means include an encryptor and a decryptor, respectively, and the encoded-bit sequence and framed-encoded-bit sequence include an encrypted-bit sequence and framed-encrypted-bit sequence, respectively.
4. A dual-framing-bit-alignment apparatus for aligning a first framing-bit sequence embedded in a first data-bit sequence with a second framing-bit sequence embedded in an framed-encoded-bit sequence. comprising:
means for transforming the framed-encoded-bit sequence to a second data-bit sequence;
means coupled to said transforming means and responsive to the second data-bit sequence for detecting the first framing-bit sequence embedded in the second data-bit sequence. for detecting errors in the second data-bit sequence due to the transformed second framing-bit sequence, and for generating, responsive to the first framing-bit sequence and the detected errors, an alignment signal; and means coupled to said detecting means and responsive to the alignment signal for aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
means for transforming the framed-encoded-bit sequence to a second data-bit sequence;
means coupled to said transforming means and responsive to the second data-bit sequence for detecting the first framing-bit sequence embedded in the second data-bit sequence. for detecting errors in the second data-bit sequence due to the transformed second framing-bit sequence, and for generating, responsive to the first framing-bit sequence and the detected errors, an alignment signal; and means coupled to said detecting means and responsive to the alignment signal for aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
5. The dual-framing-bit-alignment apparatus as set forth in claim 4 wherein said transforming means includes a decryptor, and the framed-encoded-bit sequence includes a framed-encrypted-bit sequence.
6. A dual-framing-bit-alignment apparatus for aligning a first framing-bit sequence embedded in a first data-bit sequence with a second framing-bit sequence embedded in a framed-encoded-bit sequence, comprising:
means for transforming the framed-encoded-bit sequence to a second data-bit sequence;
means for detecting the first framing-bit sequence embedded in the second data-bit sequence;
means for detecting errors in the second data-bit sequence due to the transformed second framing-bit sequence, and for generating, responsive to the detected first framing-bit sequence and the detected errors, an alignment signal; and means responsive to the alignment signal for aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
means for transforming the framed-encoded-bit sequence to a second data-bit sequence;
means for detecting the first framing-bit sequence embedded in the second data-bit sequence;
means for detecting errors in the second data-bit sequence due to the transformed second framing-bit sequence, and for generating, responsive to the detected first framing-bit sequence and the detected errors, an alignment signal; and means responsive to the alignment signal for aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
7. The dual-framing-bit-alignment apparatus as set forth in claim 6 wherein said transforming means includes a decryptor, and the framed-encoded-bit sequence includes an framed-encrypted-bit sequence.
8. The dual-framing-bit-alignment apparatus as set forth in claim 1 further including means for repositioning the first framing-bit sequence in the first data-bit sequence, prior to encrypting the first data-bit sequence.
9. The dual-framing-bit-alignment apparatus as set forth in claim 2 further including means for repositioning the first framing-bit sequence in the first data-bit sequence, prior to transforming the first data-bit sequence.
10. The dual-framing-bit-alignment apparatus as set forth in claim 3 further including means for repositioning the first framing-bit sequence in the first data-bit sequence, prior to transforming the first data-bit sequence.
11. A dual-framing-bit-alignment apparatus for aligning a first framing-bit sequence embedded in a first data-base sequence with a second framing-bit sequence embedded in a framed-encrypted-bit sequence. comprising:
a decryptor for decrypting the framed-encrypted-bit sequence to a second data-bit sequence;
means for detecting the first framing-bit sequence embedded in the second data-bit sequence;
means for detecting errors in the second data-bit sequence due to the decrypted second framing-bit sequence, and for generating an alignment signal; and means responsive to the alignment signal for aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
a decryptor for decrypting the framed-encrypted-bit sequence to a second data-bit sequence;
means for detecting the first framing-bit sequence embedded in the second data-bit sequence;
means for detecting errors in the second data-bit sequence due to the decrypted second framing-bit sequence, and for generating an alignment signal; and means responsive to the alignment signal for aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
12. A method using a dual-framing-bit-alignment apparatus for aligning a first framing-bit sequence embedded in a first data-bit sequence with a second framing-bit sequence embedded in an framed-encoded-bit sequence, comprising the steps of:
decoding the framed-encoded-bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the decoded second framing-bit sequence;
generating, responsive to the detected first framing-bit sequence and the detected errors. an alignment signal; and aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
decoding the framed-encoded-bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the decoded second framing-bit sequence;
generating, responsive to the detected first framing-bit sequence and the detected errors. an alignment signal; and aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
13. A method using a dual-framing-bit-alignment apparatus comprising the steps of:
generating a first data-bit sequence having a first framing-bit sequence;
encrypting the first data-bit sequence as an encrypted-bit sequence;
substituting a second framing bit sequence onto the encrypted-bit sequence to generate a framed-encrypted-bit sequence;
transmitting the framed-encrypted-bit sequence with the second framing-bit sequence over said communications channel;
decrypting the framed-encrypted-bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the second framing-bit sequence;
generating an alignment signal; and aligning the detected errors with the first framing-bit sequence in the first data-bit sequence.
generating a first data-bit sequence having a first framing-bit sequence;
encrypting the first data-bit sequence as an encrypted-bit sequence;
substituting a second framing bit sequence onto the encrypted-bit sequence to generate a framed-encrypted-bit sequence;
transmitting the framed-encrypted-bit sequence with the second framing-bit sequence over said communications channel;
decrypting the framed-encrypted-bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the second framing-bit sequence;
generating an alignment signal; and aligning the detected errors with the first framing-bit sequence in the first data-bit sequence.
14. A method using a dual-framing-bit-alignment apparatus comprising the steps of:
generating a first data-bit sequence having a first framing-bit sequence;
encoding the first data-bit sequence as an encoded-bit sequence;
substituting a second framing-bit sequence onto the encoded-bit sequence to generated a framed-encoded-bit sequence;
decoding the framed-encoded-bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the second framing-bit sequence;
generating an alignment signal; and aligning the detected errors with the first framing-bit sequence.
generating a first data-bit sequence having a first framing-bit sequence;
encoding the first data-bit sequence as an encoded-bit sequence;
substituting a second framing-bit sequence onto the encoded-bit sequence to generated a framed-encoded-bit sequence;
decoding the framed-encoded-bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the second framing-bit sequence;
generating an alignment signal; and aligning the detected errors with the first framing-bit sequence.
15. A method using a dual-framing-bit-alignment apparatus for aligning a first framing-bit sequence embedded in a first data-bit sequence with a second framing-bit sequence embedded in a framed-encoded-bit sequence, comprising the steps of:
decoding the framed-encoded-bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the decoded second framing-bit sequence;
generating, responsive to the first framing-bit sequence and the detected errors, an alignment signal;
and aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
decoding the framed-encoded-bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the decoded second framing-bit sequence;
generating, responsive to the first framing-bit sequence and the detected errors, an alignment signal;
and aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
16. A method using a dual-framing-bit-alignment apparatus for aligning a first framing-bit sequence embedded in a first data-bit sequence with a second framing-bit sequence embedded in an encoded bit sequence, comprising the steps of:
decoding the encoded bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the decoded second framing-bit sequence; and aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
decoding the encoded bit sequence as a second data-bit sequence;
detecting the first framing-bit sequence embedded in the second data-bit sequence;
detecting errors in the second data-bit sequence due to the decoded second framing-bit sequence; and aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
17. A dual-framing-bit-alignment apparatus comprising:
a data device for generating a first data-bit sequence having a first framing-bit sequence;
an encoder for transforming the first data-bit sequence to an encoded-bit sequence;
a framing-bit device for substituting a second framing-bit sequence onto the encoded-bit sequence to generate a framed-encoded-bit sequence;
a decoder for transforming the framed-encoded-bit sequence to a second data-bit sequence;
a second framing-bit repositioner for detecting the first framing-bit sequence embedded in the second data-bit sequence, for detecting errors in the second data-bit sequence due to the second framing-bit sequence, and for generating an alignment signal; and a first framing-bit repositioner responsive to the alignment signal for aligning the detected errors with the first framing-bit sequence.
a data device for generating a first data-bit sequence having a first framing-bit sequence;
an encoder for transforming the first data-bit sequence to an encoded-bit sequence;
a framing-bit device for substituting a second framing-bit sequence onto the encoded-bit sequence to generate a framed-encoded-bit sequence;
a decoder for transforming the framed-encoded-bit sequence to a second data-bit sequence;
a second framing-bit repositioner for detecting the first framing-bit sequence embedded in the second data-bit sequence, for detecting errors in the second data-bit sequence due to the second framing-bit sequence, and for generating an alignment signal; and a first framing-bit repositioner responsive to the alignment signal for aligning the detected errors with the first framing-bit sequence.
18. The dual-framing-bit-alignment apparatus as set forth in claim 17 wherein said encoder and said decoder include an encryptor and a decryptor, respectively, and the encoded-bit sequence and framed-encoded-bit sequence included an encrypted-bit sequence and framed-encrypted-bit sequence, respectively.
19. A dual-framing-bit alignment apparatus for aligning a first framing-bit sequence embedded in a first data-bit sequence with a second framing-bit sequence embedded in an framed-encoded-bit sequence, comprising:
an decoder for transforming the framed-encoded-bit sequence to a second data-bit sequence;
a second framing-bit repositioner coupled to said decoder and responsive to the second data-bit sequence for detecting the first framing-bit sequence embedded in the second data-bit sequence, for detecting errors in the second data-bit sequence due to the transformed second framing-bit sequence, and for generating, responsive to the first framing-bit sequence and the detected errors. an alignment signal; and a first framing-bit repositioner coupled to said second framing-bit repositioner and responsive to the alignment signal for aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
an decoder for transforming the framed-encoded-bit sequence to a second data-bit sequence;
a second framing-bit repositioner coupled to said decoder and responsive to the second data-bit sequence for detecting the first framing-bit sequence embedded in the second data-bit sequence, for detecting errors in the second data-bit sequence due to the transformed second framing-bit sequence, and for generating, responsive to the first framing-bit sequence and the detected errors. an alignment signal; and a first framing-bit repositioner coupled to said second framing-bit repositioner and responsive to the alignment signal for aligning the first framing-bit sequence in the first data-bit sequence with the detected errors in the second data-bit sequence.
20. The dual-framing-bit-alignment apparatus as set forth in claim 19 wherein said decoder includes a decryptor, and the framed-encoded-bit sequence includes a framed-encrypted-bit sequence.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US43740689A | 1989-11-16 | 1989-11-16 | |
| US437,406 | 1989-11-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2029248A1 CA2029248A1 (en) | 1991-05-17 |
| CA2029248C true CA2029248C (en) | 1994-10-04 |
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ID=23736302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2029248 Expired - Fee Related CA2029248C (en) | 1989-11-16 | 1990-11-02 | Dual framing bit sequence alignment apparatus and method |
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| Country | Link |
|---|---|
| CA (1) | CA2029248C (en) |
-
1990
- 1990-11-02 CA CA 2029248 patent/CA2029248C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2029248A1 (en) | 1991-05-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |