CA2025096A1 - Method of using electronically reconfigurable gate array logic and apparatus formed thereby - Google Patents
Method of using electronically reconfigurable gate array logic and apparatus formed therebyInfo
- Publication number
- CA2025096A1 CA2025096A1 CA2025096A CA2025096A CA2025096A1 CA 2025096 A1 CA2025096 A1 CA 2025096A1 CA 2025096 A CA2025096 A CA 2025096A CA 2025096 A CA2025096 A CA 2025096A CA 2025096 A1 CA2025096 A1 CA 2025096A1
- Authority
- CA
- Canada
- Prior art keywords
- chips
- reconfigurable
- ercga
- interconnect
- interconnected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A plurality of electronically reconfigurable gale array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/417,196 US5036473A (en) | 1988-10-05 | 1989-10-04 | Method of using electronically reconfigurable logic circuits |
US07/417,196 | 1989-10-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2025096A1 true CA2025096A1 (en) | 1991-04-05 |
CA2025096C CA2025096C (en) | 1999-01-19 |
Family
ID=23652972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002025096A Expired - Lifetime CA2025096C (en) | 1989-10-04 | 1990-09-11 | Method of using electronically reconfigurable gate array logic and apparatus formed thereby |
Country Status (1)
Country | Link |
---|---|
CA (1) | CA2025096C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111199128A (en) * | 2018-10-31 | 2020-05-26 | 财团法人工业技术研究院 | Simulation system and method |
-
1990
- 1990-09-11 CA CA002025096A patent/CA2025096C/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111199128A (en) * | 2018-10-31 | 2020-05-26 | 财团法人工业技术研究院 | Simulation system and method |
CN111199128B (en) * | 2018-10-31 | 2023-10-13 | 财团法人工业技术研究院 | Simulation system and method |
Also Published As
Publication number | Publication date |
---|---|
CA2025096C (en) | 1999-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKEX | Expiry |