CA2003603C - Method for controlling a three-phase inverter - Google Patents
Method for controlling a three-phase inverterInfo
- Publication number
- CA2003603C CA2003603C CA002003603A CA2003603A CA2003603C CA 2003603 C CA2003603 C CA 2003603C CA 002003603 A CA002003603 A CA 002003603A CA 2003603 A CA2003603 A CA 2003603A CA 2003603 C CA2003603 C CA 2003603C
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- alternating
- inverter
- voltage
- superimposition
- phase
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/505—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/515—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
- H02M7/525—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency
- H02M7/527—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency by pulse width modulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
Inverters (5.1, 5.2) for feeding a three-phase load such as, for example, an asynchronous machine (6), are controlled by pulse width modulation, in such a manner that they supply output voltages (U5.1R, U5.2R) which are as closely sinusoidal as possible, having few harmonics per alternating-current phase (R, S, T). To achieve the pulse width modulation, a first auxiliary alternating voltage (U~1) of a sawtooth generator (1.1), on the one hand, and a second auxiliary alternating voltage (U~2) of a sawtooth generator (1.2), which is phase-shifted by 180° with respect to the first one, on the other hand, is superimposed by a control signal transmitter (2) on a sinusoidal first superimposition alternating voltage (UStR, UStS, UStT) with the required frequency and phase angle in logic circuits (3.1, 3.2).
Separate inverter groups (5.1, 5.2), the outputs of which are connected via a reactor coil (7), the center tab of which is connected to a stator winding (WR) of the asynchronous machine (6), are controlled in dependence on intersections of the two superimposition voltages in each case. To reduce the turn-on and turn-off losses, the thyristors (T1, T1'; T2, T2 ' ) of the inverter are only switched over at intersections of the rising portion of the auxiliary alternating voltage (U~1, U~2). During this process, the inverter sections of the two phases (R, S, T), the first superimposition alternating voltage of which has been intersected are in each case switched at two successive intersections whilst the inverter sections of the adjacent phases are switched over at the subsequent third intersection. This allows the switching actions to be reduced by 1/3.
Separate inverter groups (5.1, 5.2), the outputs of which are connected via a reactor coil (7), the center tab of which is connected to a stator winding (WR) of the asynchronous machine (6), are controlled in dependence on intersections of the two superimposition voltages in each case. To reduce the turn-on and turn-off losses, the thyristors (T1, T1'; T2, T2 ' ) of the inverter are only switched over at intersections of the rising portion of the auxiliary alternating voltage (U~1, U~2). During this process, the inverter sections of the two phases (R, S, T), the first superimposition alternating voltage of which has been intersected are in each case switched at two successive intersections whilst the inverter sections of the adjacent phases are switched over at the subsequent third intersection. This allows the switching actions to be reduced by 1/3.
Description
2C!~)3603 Rz/SC 14 .12 . 88 88/125 TITLE OF TEIE INVENTION
Method for controlling a three-pha~e inverter BACKGROUND OF THE INV~;~. . ION
Field of the Invention The invention i9 based on a method for control-ling a three-phase inverter in accordance with the pre-amble of claim 1.
Discussion of Back~round The preamble of the invention rela~es to a prior art which is known from CH-A-420.365. In this document, several inverter groups are connected in parallel on the alternating-current side via one or more reactor coils for reducing the hA ~ ~ i G content in each phase in a three-phase inverter circuit for fee~l ng a converter-fed motor, in which sinusoidal alternating voltages corres-po~ing to the required frequency and having a high hA -nic content are generated from direct-voltage c~ - -nts of different polarity. One motor win~ing each is connected to the center of one reactor coil. For controlling the inverter, a sinusoidal voltage of the required motor frequency i8 superimposed on a triangular voltage of higher frequency than the maximum motor frequency, the triangular voltage having different phase angles of 0~ and 180~, possibly also of 90~ and 270~, for the inverter yloups connected in parallel on the alter-nating-current side. The inverter groups of each phase can be connected in series, reactor coils having one win~in~ each for two inverter groups being provided with co on iron core. Inverters of different pha~es can be coupled to one another via reactor coils. Two inverter groups each can be connected to one primary win~ing each of transformers, the secondary win~in~3 of which are connected in series and are connected to an inverter busbar.
With respect to the relevant prior art, reference is furthermore made to CH-A-489,945 in which a similar inverter control method for feeding a variable-speed asynchronous machine is specified.
With each switch-over of the inverter, turn-on and turn-off losses are produced in the converter valves and their damping elements, which must be 1~ -ved as heat from the semiconductor valves by means of cooling devices. The efficiency of the inverter decreases with increasing inverter switching frequency and the the -1 loading of the semiconductor element rises. For ~hese reasons, it is desirable to be able to manage with as low a relative switching frequency as possible. A three-point circuit is known from DE-Al 29 37 995.
From the German ~ournal etz Archiv. Vol. 10 (1988), No. 7, pages 215-220, it is known that the thyristors of a 3-point inverter are 2 converter sections in concept which are in each case operated as 2-point inverters.
From: Control in Power Electronics and Drives, IFAC SYMPOSIUN, DUsseldorf, October 7-9, 1974, Preprints Volume 1, paqes 457-472, it is known that in the 2-pulse control method, the unilaterally sinusoidal pulse width modulation has the most advantageous ratio between harmonics in the current and pulse frequency of the inverter in the lower speed range.
SUMMARY OF THE lNv~ lON
Accordingly, one object of this invention is to provide a novel method for reducinq the turn-on and turn-off losses of an inverter.
One advantage of the invention consists in the fact that the ener~y consumption during the operation of inverters can be reduced. Tha power of given semicon-ductor valves can be better utilized. The e~n~iture for cooling the semiconductor valves is lower. With the same conventional cooling device, the inverter can be operated at higher-~requency output voltages. A reduction of the transitions of the inverter to 2/3 can be achieved, particularly in the lower fre~uency or 6peed range (0% -50%~.
BRIEF DESCRIPTION OF THE- DRAWINGS
A more complete appreciation of the invention and many of the atten~Ant advantages thereof will be readily obtAined as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Figure 1 shows a control circuit for a two-pulse inverter for fee~in~ a three-phase asyn-chronous ~~hin~, which inverter is ~ 30d of 2 2-point inverters, Figure 2 shows a logic circuit of the control circuit according to Figure 1, Figures 3.1-3.14 show signal diagrams for expl~ining the effect of the control circuit according to Figure 1, Figure 4 shows a two-pulse 2 x 2-point inverter with reactor of the same phase and Figure-5 shows a two-pulse three-point inverter for fee~ing an asynchronous machine.
S~RTPTION OF THE Y~nn~ ~MBODl~.S
Referring now to the drawing~, wherein like reference numerals designate identical or corre~pon~inq parts throughout the several views, in the control ~ circuit shown in Figure 1, two inverter groups 5.1 and 5.2, which are arranged in parallel and are of identical construction, of an i~verter section, belonging to pha~e R, of a three-phase inverter arrangament are connected at the direct-voltage side to a posit~ve pole P and to a negative pole N of a direct-current source with neutral ;~C03603 conductor O and are connected together on the alternat-ing-voltage qide via a reactor coil 7 which acts slmilar to a balance coil in rectifier arrangement. The direct-current qource 4 with a direct voltage of 2 ~ UG can be a direct-current power system or a direct-current link circuit of a direct-current converter.
The center of the reactor coil 7 is connected to a stator WinAing WR Of a three-phase asynchronous machine 6 across which a stator wi nA; ng voltage UR_UM is dLopped when current is flowing. R, S and T designate the three phases of the asynchronous machine 6, all three stator wi~ings WR~ WS, WT of which are drawn. UR designates a resultant inverter voltage with respect to the neutral conductor O with reference to phase R and UM of a neutral voltage of a neutral point M of the stator win~ings Wa, Ws and WT. Only the inverter section belonging to phase R of the inverter arrAn~ - t is ~hown in greater detail. The remaining ~tator win~ing~ Ws and Ws must be connected to the direct-voltage source 4 in accordance with the stator 20 W;n~;ng WR. The inverter groups 5.1 and 5.2 exhibit thyristors Tl and T2, the ~no~8 of which are co~le~ed to the positive pole P, and thyristors Tl' and T2', the cathodes of which are co~n~cted to the negative pole N, in each case with ~; 0~9S which are connected in anti-parallel with the thyristors. On the alternating-voltage side, -the thyristors Tl and Tl' and T2 and T2~ are electrically co~ec~ed and are con~ec~ed to oppo~ite ends of the reactor coil 7. Us.~ and U5 ~ designate the output voltages of the inverter groups 5.1 and 5.2 of the inverter section with respect to the ne~L~al con~nctor O
with reference to phase R.
The inverter yLou~s 5.1 and 5.2 are controlled via logic circuits 3.1 and 3.2 of identical construction, one of which i8 shown in greater detail in Figure 2. In the logic circuits, a sinusoidal control voltage Us~
which is supplied by a control signal transmitter 2, i~
compared with a triangular ~nYili~ry alternating voltage U~1 and U~ which are ~rplie~ by sawtooth generators 1.1 and 1.2. The control signal transmitter 2 can be, for , .
2C~)3603 exampiQ, a speed controller, known per se, with secondary current controller which ~et~ the speed for the asyn-chronous machine 6. Ust9 and UstT designate control voltages with reference to phases S and T which exhibit the same amplitude as the control voltage U9~ for phase R but a phase shift by 120~ electrical and 240~ electrical, respectively, with re~pect to this phase. The frequency of these control voltages corresponds to the required frequency of the asynchronous machine 6. The auxiliary alternating voltages U~1 and U~ are equal in their pre-determinable amplitude and frequency but mutually phase-shifted by 180~ electrical; their frequency is higher ~ than the -~i frequency of the a~ynchronous -ch;ne 6.
The inputs of the sawtooth generators 1.1 and 1.2 are supplied with possibly different sawtooth-~hAre~
signals Al and A2 which dete in~ the shape of the a-lY~ ry alternating voltages U~l and U~ in ~penden~e on the mean value of the current in the neutral conductor 0 and~or in ~ep~ndence on the mean value of the neutral-point voltage UM . ~he sawtooth-shaped signals Al and/or A2 can be altered during operation in order to h~lAn~e out any displacements in potential of the neutral-point voltage UM with ~~~ecL to the neutral cond~ctor 0. If the sawtooth-shaped signals Al and A2 ~Yhihit a predeter-minable first potential, the allYi 1 i ~ry alternating voltages U~1 and U~ have the shape shown in Figure 3.1. If Al and A2 eYhihit a ~ladeLs ~n~hle second potential, U~l and U~ are inverted with steep rising and flat f~l l;ng edges (not shown).
The harmonic content of the rectangular alternat-ing voltage Appl;ed to the ~tator Wi~ingg WR~ W5, WT of the asynchronous ~Chin9 6 can be considerably reduced in familiar manner (Figure 3 of CH-A-~20,365) by means of the 180~ phase shift.
3S In the logic circuit 3.1 according to Figure 1, shown in Figure 2, 8 and 9 designate comparators, tha inputs of which are ~upplied, ~n.~v~l with opposite polarity, with the sinu30idal cont-ol voltage and the first superimpo3ition voltage UStR and tha AllYi 1; Ary alternating voltage or second ~uperLmposition voltage U~l.
The output of the comparator 8 is connected to the ~et input SE of an SR flip flop 10 which can be reset to a logical 0 at the output by a predete inAhle pre~et signal Sl applied to the reset input RE. At the output, the SR flip flop 10 is connected via a non-retriggerable flip flop 11 to a trigger input of a counter 13 which e~hihits counting outputs Zl and Z2 and can also be reset to 0 by the reset -~ignal Sl applied to the re~et input RE. The counting outputs Zl and Z~ alternately exhibit the 1 state when a 0-1 transition occurs at the counting input. A 1 state at the counting output Z2 resets the counter 13 to 0 via the reset input RE.
The counting ou~puL9 Zl and Z2 are connected via trigger pulse qenerators 14 and ~5 to trigger pulse amplifiers 16 and 17 at the Gu~uLs of which the trigger signal~ STl and STl' for thyristors Tl and T1~ are present. Approximately 100 ~s before the trigger signal for the thyristor Tl, the trigger pulse generator 14 generates a turn-off signal for the thyristor T1' if the latter is conducting. Correspon~ingly~ approximately 100 ~s before the trigger signal for the thyristor Tl', the trigger generator 15 generates a turn-off signal for the thyristor Tl if the latter i8 con~ncting. The turn-off si~nAls and turn-off signal circuits are not shown for r~A~on~ of better clarity.
The ou~puL of the comparator 9, at the negating input of which the control voltage Us~ is present and at the non-negating input of which the ~llYiliAry alternating voltage U~ is present, is conn~cted via a monostable flip flop 9.1, at the output of which a switch-over signal SR
with refe~ence to phase R is present, and via an AND gate 1~ to the counting input of the counter 13. The switch-over signal SR = 1 for a p-e~e~e in~hle operating time for U~l 2 Us~ and otherwise it is = 0. The switch-over signal SR and similar switch-over signal~ SS and ST which are supplied by logic circuits which belony to phases S
and T are s~rplie~ to counting inputs of a counter 18 having three counting ouLpu~8 Zl - Z3 and a reset input ;~C0~603 RE. The counting outputs Z1, Z2, Z3 successively exhiblt the l state when 0-1 tran~itions occur at the c~unting inputs. A reset signal S1 and/or a 1 state at the count-ing output Z3 resets the counter 18 to 0 via the reset input RE.
Counting outputs Zl and Z2 are connected via non-retriggerable monostable flip flops 19 and 20 and a subsequent OR gate 22 to one input of the AND gate 12. A
further input of the AND gate 12 is connected to the output of the SR flip flop 10. The counting output Z3 is connected via an A~D gate 21 to the counting input of the counter 13. A negated input of the AND gate 21 is connected to the output of the flip flop 9.1. The operat-ing time of the flip flops 9.1, 11, 19 and 20 i~ set to be of such a short time that their output signal i3 0 before an intersection of the auxiliary alternating voltage U~l with a control voltage Usts or UstT of an ad~acent phase S and T, respectively, can be reached.
The effect of the circuits shown in Fisures 1 and 2 will now be expl~ine~ with reference to Figures 3.1 -3.14. Figure 3.1 shows sinusoidal control voltages Us~
Us~s and UstT, which are phase-shifted by 180~ electrical, for controlling the phases R, S, T and alternating voltages ~ and U~, which are phase-shifted by 180a electrical relative to one another, as a function of time t. The voltage U is plotted along the ordinate. ~he amplitudes of the alternating voltages U~l and U~ are greater than the amplitudes of the control voltages Us~
Usts~ UstT, which are mutually identical.
In Figures 3.2 - 3.7, the rectangular output voltage8 U5 ~ U5 ~; U5.15~ U5,~; U5,1~ U5,2~ of inver~er groups 5.1 and 5.2 with respect to the zero conductor 0 with reference to phases R, S, T are shown as a function of time t. Transitions which would occur with con~en-tional control without the measure according to the invention are shown dashed.
At the beginnin~ of the control process, the SR
flip flop 10 and the counters 13 and 18 are reset by the reset signal Sl 80 that their ouLpuL ~ignal~ are a logical O. At a time tO, the vertically falling auxiliary voltage U8~ intersect~ the control voltages Us~. U9t8 and UstT so that the output ~ignal of the comparators 8 of the three phases R, S, T changes from the O to the l ~tate.
This value is ~tored in the respective SR flip flop 10, the output ~ignal of which also changes from O to the l state. This state change results, via flip flop ll, in a counting pulse in the counter 13, the signal output Zl of which changes from O to l. A8 a result, a trigger pulse is generated in the trigger pulse generator 14 which is amplified in the trigger pulse amplifier 16 and triggers the thyristor Tl. As a result, positive potential UG is present across the reactor coil 7 a~d across the stator win~;ng WR. The same applies to phases S and T, cf. output voltages U51S and U5.1T~
At time tl, the rising auxiliary alternating voltage U8l intersects the control voltage Us~, with the effect that the associated inverter 5.1 switche~ from +
to - at the output. This occurs due to the fact that the output signal of the comparator 9 changes from O to l.
Due to this 0-1 chAnge, the switch-over signal SR, and thus also the counting ouLpuL Zl of the counter 18, becomes a logical l during the operating time of flip flop 9.1. Via the flip flop 19 and the OR gate 22, the associated input of the AND gate 12, which is enabled with t~e stored value 1 via the SR flip flop 10 al~o becomes a logical l. This provides the counter 13 with a counting signal 80 that, instead of Z1, Z2 now assumes the logical value 1. As a result, the trigger pulse g~ne-ator 15 generates a trigger pulse for the thyristor T1', the thyristor T1 being tl~rns~ off at the same time (turn-off device not shown). The potential U5 ~ = _UG is now present across the reactor coil 7.
At time t3, the rising ~llYi 1 i ~ry alternating voltage U8l inte~se.~s the con~ ol voltage Us~, with the effect that the associated inverter 5.1 switchss from +
to -. This occurs as a rasult of the fact that the ~ switch-over signal SS becomes l, and the output voltage ; U5 1~ ~ee ~ -U~ in the logic circuit 3.1 ~elonging to ~C03603 g phase S. In the logic circuit 3.1 belonging to pha~e R, the counter 18 also receives a counting pulse so that, instead of Z1, Z2 now becomes 1. However, this 1 ~lgnal cannot pass through the AND gate 12 since SR = O.
5At time t5, the rising auxiliary alternating voltage U~l intersects the control voltage UstT, with the effect that the inverter 5.1 of phase T does not now switch from + to - (as would be the case in the known arrangement), but its two ad;acent inverters 5.1 and 5.2 10of phases R and S each switch from - to ~. This occurs due to the fact that in all three logic circuits 3.1 belonging to phases R, S, T, the counter 18 receives a counting pulse so that, in-qtead of Z1 and Z2, Z3 now becomes 1. The output signal of the OR gate 22 is thus =
150 and the AND gate 12 disabled. In the logic circuit 3.1 belonging to phase T, the AND gate 21 is disabled because of ST = 1 whereas it is enabled because of SR = O and SS
= O in the other two phases R and S. In these two phases, a counting pulse passes via the AND gate 21 to the 20counter 13 so that the latter switches to Zl = 1 after preYious resettin~. Thus, U5 ~ becomes UG and U5 lS becomes UG.
At tLme t6, the voltage of U~l drops again as at time tO. Ho~ r, the intersections with the control 25voltage~ Us~, Us~s, Ust~ do not have any effect whatever, that i8 to ~ay none of the three inverters 5.1 of phases R, S, T switches, since the output state of the SR flip flop 10 remains lln~h~ng~d once it has been set.
The switching sequence specified is now repeated.
30At times t7, t5 and tlO, the rising auxiliary alternating voltage U~1 successively intersects control voltages ~5~
Us~, UstT, a valve switching occuring at pha es S and R
but not at T. Instead of a transition at T, the transi-tions a~ phases S and R are effected as expl~ine~ aboYe 35in con~unction with the switch-over times tl, t3 and t5.
With respect to inverter groups 5.2 of the three phases R, S, T, the same applies as for inverter groups 5.1, except that the second superimposition or ~llYili~ry alternating voltage U~ i8 superi ~_sed on the first 2~03603 superLmpo~ition voltages U9~, U9~, U9tI. At time tO, only US~S ~ UHZ SO that the counter 13 of the logic circuit 3.2 of phase S receives a counting pulse via component~ 8, 10, 11. As a result, Z1 becomes 1 at counter 13 and the associated thyristor T1 receives a trigger pulse via components 14 and 16, with the effect that U5 25 exhibits positive potential, compare Figure 3.5. At pha~es R and S, the 1st thyristor triggering occurs at tLme t2 when Us~ and UstT become > U~. ~efore that, the O output of the respective SR flip flop 10 blocks the AND gate 12. In this connection, the output voltages U5 ~ and U~ 2T Of the inverter groups 5.2 are also set to the same po~itive potential UG at time t2, cf. Figure 3.3 and Figure 3.7.
In Figures 3.8 - 3.10, the resultant inverter output voltages with respect to the zero conductor 0, namely UR~ US and UT~ are shown as a function of time t, where: UR = U5 ~R + U5 2R~ US = U~ 1S + U5 2S and UT = U5.1~ +
Figure 3.11 shows the neutral-point voltage U~ =
20 UR + US + UT Of the c: -n neutral point M of the stator W;~;ngS WR~ WS, WT with respect to the neutral conductor O of the direct-current source 4 as a function of tLme t.
In Figures 3.12 - 3.14, wi n~ i nq voltages UR - UM
and Us - U~ and UT - UM are ~hown as a function of tLme t.
The same voltage conditions effected with 10 transitions according to the invention would have required 16 transi-tions in the co~.v~nLional control method.
Eigures 4 and S show two different inverter circuits in which the 2-pulse control sy~tem can be implemented. In the 2 x 2-point circuit shown in Figure 4, with reactor coil 23 of the same phase, there are no problems with the switching sequence dead time of the inverter. The 3-point circuit according to Figure 5 has the advantage that it manages without reactor coil. In Figures 4 and 5, the inverters are shown simplified as switches.
The method according to the invention can also be used in a single-pulse 2-point inverter which would result from the circuit according to Figure 1 without fiO~3 signal generator 1.2, logic circuit 3.2, in~erter group 5.2 and reactor coil 7, in which arrangement the stator winding WR would be connected directly to the output of the inverter group 5.1.
The invention is based on the finding that 3 synchronous transitions from + to - or from - to + do not have any effect on the winding voltage and that switching in an ad~acent pha~e, for example S or T, ha~ half the negative effect on the winding voltage as in a phase considered, for example R. In~tead of switching the phase R from positive potential to negative potential, the two ad~acent phases S and T can be switched from negative potential to positive potential. Applying these prin-ciples, unnecessary transitions can be avoided. This applies, at least, when the load i ~Ances are identical in the three phases. The load can also be a transfQrmer or a threQ-phase power system.
The switch-over times and the sequence of phases are selected in Ruch a ~nn~r that a three-phase, poss-ibly sinusoidal motor wi n~ i ng voltage or load phase voltage is produced. In this arrangement, the switch-over times of one pulse are offset with respect to those of the other one in such a ~nner that when the voltages of the two pulses are added, as many harmonics as possible are again cancelled out against one another. A further reduction in h~ nics can be achieved, for example, if four differently controlled inverter groups per phase are conn~cted together, the phase shift of the auxiliary alternating voltage being 90~ in each case. Reference is made to the CH-A-420,365 initially mentioned with re~pect to circuits for reducing h~ -nics.
With a rslatively high pulse frequency of the auxiliary alternating voltages U8l and U~, the method according to the invention can be used within the entire speed range of the asynchronous machine 6. Preferably, however, this method is only used within a speed range from 0% to 30% or up to 70~ whilst phase-shifted two-pulse flln~ Lal frequency pulsing is used at higher speeds in order to keep harmonics and transition~ as low 2C~.603 as possibLe at the same t~me.
Naturally, gate-turn-off GTO thyristorfl or transistors can also be used as valves inst~ad of the thyristors Tl, Tl~, T2, T2~ with ring-around circuits, not shown. Instead of the logic circuits 3.1 and 3.2 a computer can be provided which calculates the required switch-over points for the valves and outputs correspond-ing control ~ignals. The auxiliary alternating voltages can be synchronous or asynchronous to the control vol-tages and exhibit sawtooth-~h~pe~ or trapezoidal or sinusoidal or sine-wave-like shape. If the shape of the auxiliary alternating voltages V~1, U~ is changed, the characteristic of intersections i9 also changed, that is to say the valves are switched, for example, in depen-dence on the falling edge of U~1 and V~, respectively.
Instead of initially switching all valve outputsto a positive potential, the outputs can also be switched to negative potential. It i8 of importance that the switching-over of the valves always occurs with the same depen~n~y (except with a ch~n~e in the sawtooth-shaped signals A1 and A2), that is to say always in dependence on a rising-vQltage or a f~lling-voltage part of the ~lYi 1 i ~ry voltage. If it has been decided, for example, to use the rising-voltage edge of a sawtooth-shAre~
auxiliary voltage, there is no further switch-over at the f~lling edge. This overall reduces the ~r of inverter circuits by 1/3 - and this without effects on the varia-tion of the motor win~ing voltage~ with time. Instead of 6 tran~itions per period of the au~rili~ry control vol-tage, there are now only 4.
Obviously, numerous modification and variationsof the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the ~pp~n~ claims, the invention may be practiced otherwise than as ~pecifically described herein.
Method for controlling a three-pha~e inverter BACKGROUND OF THE INV~;~. . ION
Field of the Invention The invention i9 based on a method for control-ling a three-phase inverter in accordance with the pre-amble of claim 1.
Discussion of Back~round The preamble of the invention rela~es to a prior art which is known from CH-A-420.365. In this document, several inverter groups are connected in parallel on the alternating-current side via one or more reactor coils for reducing the hA ~ ~ i G content in each phase in a three-phase inverter circuit for fee~l ng a converter-fed motor, in which sinusoidal alternating voltages corres-po~ing to the required frequency and having a high hA -nic content are generated from direct-voltage c~ - -nts of different polarity. One motor win~ing each is connected to the center of one reactor coil. For controlling the inverter, a sinusoidal voltage of the required motor frequency i8 superimposed on a triangular voltage of higher frequency than the maximum motor frequency, the triangular voltage having different phase angles of 0~ and 180~, possibly also of 90~ and 270~, for the inverter yloups connected in parallel on the alter-nating-current side. The inverter groups of each phase can be connected in series, reactor coils having one win~in~ each for two inverter groups being provided with co on iron core. Inverters of different pha~es can be coupled to one another via reactor coils. Two inverter groups each can be connected to one primary win~ing each of transformers, the secondary win~in~3 of which are connected in series and are connected to an inverter busbar.
With respect to the relevant prior art, reference is furthermore made to CH-A-489,945 in which a similar inverter control method for feeding a variable-speed asynchronous machine is specified.
With each switch-over of the inverter, turn-on and turn-off losses are produced in the converter valves and their damping elements, which must be 1~ -ved as heat from the semiconductor valves by means of cooling devices. The efficiency of the inverter decreases with increasing inverter switching frequency and the the -1 loading of the semiconductor element rises. For ~hese reasons, it is desirable to be able to manage with as low a relative switching frequency as possible. A three-point circuit is known from DE-Al 29 37 995.
From the German ~ournal etz Archiv. Vol. 10 (1988), No. 7, pages 215-220, it is known that the thyristors of a 3-point inverter are 2 converter sections in concept which are in each case operated as 2-point inverters.
From: Control in Power Electronics and Drives, IFAC SYMPOSIUN, DUsseldorf, October 7-9, 1974, Preprints Volume 1, paqes 457-472, it is known that in the 2-pulse control method, the unilaterally sinusoidal pulse width modulation has the most advantageous ratio between harmonics in the current and pulse frequency of the inverter in the lower speed range.
SUMMARY OF THE lNv~ lON
Accordingly, one object of this invention is to provide a novel method for reducinq the turn-on and turn-off losses of an inverter.
One advantage of the invention consists in the fact that the ener~y consumption during the operation of inverters can be reduced. Tha power of given semicon-ductor valves can be better utilized. The e~n~iture for cooling the semiconductor valves is lower. With the same conventional cooling device, the inverter can be operated at higher-~requency output voltages. A reduction of the transitions of the inverter to 2/3 can be achieved, particularly in the lower fre~uency or 6peed range (0% -50%~.
BRIEF DESCRIPTION OF THE- DRAWINGS
A more complete appreciation of the invention and many of the atten~Ant advantages thereof will be readily obtAined as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Figure 1 shows a control circuit for a two-pulse inverter for fee~in~ a three-phase asyn-chronous ~~hin~, which inverter is ~ 30d of 2 2-point inverters, Figure 2 shows a logic circuit of the control circuit according to Figure 1, Figures 3.1-3.14 show signal diagrams for expl~ining the effect of the control circuit according to Figure 1, Figure 4 shows a two-pulse 2 x 2-point inverter with reactor of the same phase and Figure-5 shows a two-pulse three-point inverter for fee~ing an asynchronous machine.
S~RTPTION OF THE Y~nn~ ~MBODl~.S
Referring now to the drawing~, wherein like reference numerals designate identical or corre~pon~inq parts throughout the several views, in the control ~ circuit shown in Figure 1, two inverter groups 5.1 and 5.2, which are arranged in parallel and are of identical construction, of an i~verter section, belonging to pha~e R, of a three-phase inverter arrangament are connected at the direct-voltage side to a posit~ve pole P and to a negative pole N of a direct-current source with neutral ;~C03603 conductor O and are connected together on the alternat-ing-voltage qide via a reactor coil 7 which acts slmilar to a balance coil in rectifier arrangement. The direct-current qource 4 with a direct voltage of 2 ~ UG can be a direct-current power system or a direct-current link circuit of a direct-current converter.
The center of the reactor coil 7 is connected to a stator WinAing WR Of a three-phase asynchronous machine 6 across which a stator wi nA; ng voltage UR_UM is dLopped when current is flowing. R, S and T designate the three phases of the asynchronous machine 6, all three stator wi~ings WR~ WS, WT of which are drawn. UR designates a resultant inverter voltage with respect to the neutral conductor O with reference to phase R and UM of a neutral voltage of a neutral point M of the stator win~ings Wa, Ws and WT. Only the inverter section belonging to phase R of the inverter arrAn~ - t is ~hown in greater detail. The remaining ~tator win~ing~ Ws and Ws must be connected to the direct-voltage source 4 in accordance with the stator 20 W;n~;ng WR. The inverter groups 5.1 and 5.2 exhibit thyristors Tl and T2, the ~no~8 of which are co~le~ed to the positive pole P, and thyristors Tl' and T2', the cathodes of which are co~n~cted to the negative pole N, in each case with ~; 0~9S which are connected in anti-parallel with the thyristors. On the alternating-voltage side, -the thyristors Tl and Tl' and T2 and T2~ are electrically co~ec~ed and are con~ec~ed to oppo~ite ends of the reactor coil 7. Us.~ and U5 ~ designate the output voltages of the inverter groups 5.1 and 5.2 of the inverter section with respect to the ne~L~al con~nctor O
with reference to phase R.
The inverter yLou~s 5.1 and 5.2 are controlled via logic circuits 3.1 and 3.2 of identical construction, one of which i8 shown in greater detail in Figure 2. In the logic circuits, a sinusoidal control voltage Us~
which is supplied by a control signal transmitter 2, i~
compared with a triangular ~nYili~ry alternating voltage U~1 and U~ which are ~rplie~ by sawtooth generators 1.1 and 1.2. The control signal transmitter 2 can be, for , .
2C~)3603 exampiQ, a speed controller, known per se, with secondary current controller which ~et~ the speed for the asyn-chronous machine 6. Ust9 and UstT designate control voltages with reference to phases S and T which exhibit the same amplitude as the control voltage U9~ for phase R but a phase shift by 120~ electrical and 240~ electrical, respectively, with re~pect to this phase. The frequency of these control voltages corresponds to the required frequency of the asynchronous machine 6. The auxiliary alternating voltages U~1 and U~ are equal in their pre-determinable amplitude and frequency but mutually phase-shifted by 180~ electrical; their frequency is higher ~ than the -~i frequency of the a~ynchronous -ch;ne 6.
The inputs of the sawtooth generators 1.1 and 1.2 are supplied with possibly different sawtooth-~hAre~
signals Al and A2 which dete in~ the shape of the a-lY~ ry alternating voltages U~l and U~ in ~penden~e on the mean value of the current in the neutral conductor 0 and~or in ~ep~ndence on the mean value of the neutral-point voltage UM . ~he sawtooth-shaped signals Al and/or A2 can be altered during operation in order to h~lAn~e out any displacements in potential of the neutral-point voltage UM with ~~~ecL to the neutral cond~ctor 0. If the sawtooth-shaped signals Al and A2 ~Yhihit a predeter-minable first potential, the allYi 1 i ~ry alternating voltages U~1 and U~ have the shape shown in Figure 3.1. If Al and A2 eYhihit a ~ladeLs ~n~hle second potential, U~l and U~ are inverted with steep rising and flat f~l l;ng edges (not shown).
The harmonic content of the rectangular alternat-ing voltage Appl;ed to the ~tator Wi~ingg WR~ W5, WT of the asynchronous ~Chin9 6 can be considerably reduced in familiar manner (Figure 3 of CH-A-~20,365) by means of the 180~ phase shift.
3S In the logic circuit 3.1 according to Figure 1, shown in Figure 2, 8 and 9 designate comparators, tha inputs of which are ~upplied, ~n.~v~l with opposite polarity, with the sinu30idal cont-ol voltage and the first superimpo3ition voltage UStR and tha AllYi 1; Ary alternating voltage or second ~uperLmposition voltage U~l.
The output of the comparator 8 is connected to the ~et input SE of an SR flip flop 10 which can be reset to a logical 0 at the output by a predete inAhle pre~et signal Sl applied to the reset input RE. At the output, the SR flip flop 10 is connected via a non-retriggerable flip flop 11 to a trigger input of a counter 13 which e~hihits counting outputs Zl and Z2 and can also be reset to 0 by the reset -~ignal Sl applied to the re~et input RE. The counting outputs Zl and Z~ alternately exhibit the 1 state when a 0-1 transition occurs at the counting input. A 1 state at the counting output Z2 resets the counter 13 to 0 via the reset input RE.
The counting ou~puL9 Zl and Z2 are connected via trigger pulse qenerators 14 and ~5 to trigger pulse amplifiers 16 and 17 at the Gu~uLs of which the trigger signal~ STl and STl' for thyristors Tl and T1~ are present. Approximately 100 ~s before the trigger signal for the thyristor Tl, the trigger pulse generator 14 generates a turn-off signal for the thyristor T1' if the latter is conducting. Correspon~ingly~ approximately 100 ~s before the trigger signal for the thyristor Tl', the trigger generator 15 generates a turn-off signal for the thyristor Tl if the latter i8 con~ncting. The turn-off si~nAls and turn-off signal circuits are not shown for r~A~on~ of better clarity.
The ou~puL of the comparator 9, at the negating input of which the control voltage Us~ is present and at the non-negating input of which the ~llYiliAry alternating voltage U~ is present, is conn~cted via a monostable flip flop 9.1, at the output of which a switch-over signal SR
with refe~ence to phase R is present, and via an AND gate 1~ to the counting input of the counter 13. The switch-over signal SR = 1 for a p-e~e~e in~hle operating time for U~l 2 Us~ and otherwise it is = 0. The switch-over signal SR and similar switch-over signal~ SS and ST which are supplied by logic circuits which belony to phases S
and T are s~rplie~ to counting inputs of a counter 18 having three counting ouLpu~8 Zl - Z3 and a reset input ;~C0~603 RE. The counting outputs Z1, Z2, Z3 successively exhiblt the l state when 0-1 tran~itions occur at the c~unting inputs. A reset signal S1 and/or a 1 state at the count-ing output Z3 resets the counter 18 to 0 via the reset input RE.
Counting outputs Zl and Z2 are connected via non-retriggerable monostable flip flops 19 and 20 and a subsequent OR gate 22 to one input of the AND gate 12. A
further input of the AND gate 12 is connected to the output of the SR flip flop 10. The counting output Z3 is connected via an A~D gate 21 to the counting input of the counter 13. A negated input of the AND gate 21 is connected to the output of the flip flop 9.1. The operat-ing time of the flip flops 9.1, 11, 19 and 20 i~ set to be of such a short time that their output signal i3 0 before an intersection of the auxiliary alternating voltage U~l with a control voltage Usts or UstT of an ad~acent phase S and T, respectively, can be reached.
The effect of the circuits shown in Fisures 1 and 2 will now be expl~ine~ with reference to Figures 3.1 -3.14. Figure 3.1 shows sinusoidal control voltages Us~
Us~s and UstT, which are phase-shifted by 180~ electrical, for controlling the phases R, S, T and alternating voltages ~ and U~, which are phase-shifted by 180a electrical relative to one another, as a function of time t. The voltage U is plotted along the ordinate. ~he amplitudes of the alternating voltages U~l and U~ are greater than the amplitudes of the control voltages Us~
Usts~ UstT, which are mutually identical.
In Figures 3.2 - 3.7, the rectangular output voltage8 U5 ~ U5 ~; U5.15~ U5,~; U5,1~ U5,2~ of inver~er groups 5.1 and 5.2 with respect to the zero conductor 0 with reference to phases R, S, T are shown as a function of time t. Transitions which would occur with con~en-tional control without the measure according to the invention are shown dashed.
At the beginnin~ of the control process, the SR
flip flop 10 and the counters 13 and 18 are reset by the reset signal Sl 80 that their ouLpuL ~ignal~ are a logical O. At a time tO, the vertically falling auxiliary voltage U8~ intersect~ the control voltages Us~. U9t8 and UstT so that the output ~ignal of the comparators 8 of the three phases R, S, T changes from the O to the l ~tate.
This value is ~tored in the respective SR flip flop 10, the output ~ignal of which also changes from O to the l state. This state change results, via flip flop ll, in a counting pulse in the counter 13, the signal output Zl of which changes from O to l. A8 a result, a trigger pulse is generated in the trigger pulse generator 14 which is amplified in the trigger pulse amplifier 16 and triggers the thyristor Tl. As a result, positive potential UG is present across the reactor coil 7 a~d across the stator win~;ng WR. The same applies to phases S and T, cf. output voltages U51S and U5.1T~
At time tl, the rising auxiliary alternating voltage U8l intersects the control voltage Us~, with the effect that the associated inverter 5.1 switche~ from +
to - at the output. This occurs due to the fact that the output signal of the comparator 9 changes from O to l.
Due to this 0-1 chAnge, the switch-over signal SR, and thus also the counting ouLpuL Zl of the counter 18, becomes a logical l during the operating time of flip flop 9.1. Via the flip flop 19 and the OR gate 22, the associated input of the AND gate 12, which is enabled with t~e stored value 1 via the SR flip flop 10 al~o becomes a logical l. This provides the counter 13 with a counting signal 80 that, instead of Z1, Z2 now assumes the logical value 1. As a result, the trigger pulse g~ne-ator 15 generates a trigger pulse for the thyristor T1', the thyristor T1 being tl~rns~ off at the same time (turn-off device not shown). The potential U5 ~ = _UG is now present across the reactor coil 7.
At time t3, the rising ~llYi 1 i ~ry alternating voltage U8l inte~se.~s the con~ ol voltage Us~, with the effect that the associated inverter 5.1 switchss from +
to -. This occurs as a rasult of the fact that the ~ switch-over signal SS becomes l, and the output voltage ; U5 1~ ~ee ~ -U~ in the logic circuit 3.1 ~elonging to ~C03603 g phase S. In the logic circuit 3.1 belonging to pha~e R, the counter 18 also receives a counting pulse so that, instead of Z1, Z2 now becomes 1. However, this 1 ~lgnal cannot pass through the AND gate 12 since SR = O.
5At time t5, the rising auxiliary alternating voltage U~l intersects the control voltage UstT, with the effect that the inverter 5.1 of phase T does not now switch from + to - (as would be the case in the known arrangement), but its two ad;acent inverters 5.1 and 5.2 10of phases R and S each switch from - to ~. This occurs due to the fact that in all three logic circuits 3.1 belonging to phases R, S, T, the counter 18 receives a counting pulse so that, in-qtead of Z1 and Z2, Z3 now becomes 1. The output signal of the OR gate 22 is thus =
150 and the AND gate 12 disabled. In the logic circuit 3.1 belonging to phase T, the AND gate 21 is disabled because of ST = 1 whereas it is enabled because of SR = O and SS
= O in the other two phases R and S. In these two phases, a counting pulse passes via the AND gate 21 to the 20counter 13 so that the latter switches to Zl = 1 after preYious resettin~. Thus, U5 ~ becomes UG and U5 lS becomes UG.
At tLme t6, the voltage of U~l drops again as at time tO. Ho~ r, the intersections with the control 25voltage~ Us~, Us~s, Ust~ do not have any effect whatever, that i8 to ~ay none of the three inverters 5.1 of phases R, S, T switches, since the output state of the SR flip flop 10 remains lln~h~ng~d once it has been set.
The switching sequence specified is now repeated.
30At times t7, t5 and tlO, the rising auxiliary alternating voltage U~1 successively intersects control voltages ~5~
Us~, UstT, a valve switching occuring at pha es S and R
but not at T. Instead of a transition at T, the transi-tions a~ phases S and R are effected as expl~ine~ aboYe 35in con~unction with the switch-over times tl, t3 and t5.
With respect to inverter groups 5.2 of the three phases R, S, T, the same applies as for inverter groups 5.1, except that the second superimposition or ~llYili~ry alternating voltage U~ i8 superi ~_sed on the first 2~03603 superLmpo~ition voltages U9~, U9~, U9tI. At time tO, only US~S ~ UHZ SO that the counter 13 of the logic circuit 3.2 of phase S receives a counting pulse via component~ 8, 10, 11. As a result, Z1 becomes 1 at counter 13 and the associated thyristor T1 receives a trigger pulse via components 14 and 16, with the effect that U5 25 exhibits positive potential, compare Figure 3.5. At pha~es R and S, the 1st thyristor triggering occurs at tLme t2 when Us~ and UstT become > U~. ~efore that, the O output of the respective SR flip flop 10 blocks the AND gate 12. In this connection, the output voltages U5 ~ and U~ 2T Of the inverter groups 5.2 are also set to the same po~itive potential UG at time t2, cf. Figure 3.3 and Figure 3.7.
In Figures 3.8 - 3.10, the resultant inverter output voltages with respect to the zero conductor 0, namely UR~ US and UT~ are shown as a function of time t, where: UR = U5 ~R + U5 2R~ US = U~ 1S + U5 2S and UT = U5.1~ +
Figure 3.11 shows the neutral-point voltage U~ =
20 UR + US + UT Of the c: -n neutral point M of the stator W;~;ngS WR~ WS, WT with respect to the neutral conductor O of the direct-current source 4 as a function of tLme t.
In Figures 3.12 - 3.14, wi n~ i nq voltages UR - UM
and Us - U~ and UT - UM are ~hown as a function of tLme t.
The same voltage conditions effected with 10 transitions according to the invention would have required 16 transi-tions in the co~.v~nLional control method.
Eigures 4 and S show two different inverter circuits in which the 2-pulse control sy~tem can be implemented. In the 2 x 2-point circuit shown in Figure 4, with reactor coil 23 of the same phase, there are no problems with the switching sequence dead time of the inverter. The 3-point circuit according to Figure 5 has the advantage that it manages without reactor coil. In Figures 4 and 5, the inverters are shown simplified as switches.
The method according to the invention can also be used in a single-pulse 2-point inverter which would result from the circuit according to Figure 1 without fiO~3 signal generator 1.2, logic circuit 3.2, in~erter group 5.2 and reactor coil 7, in which arrangement the stator winding WR would be connected directly to the output of the inverter group 5.1.
The invention is based on the finding that 3 synchronous transitions from + to - or from - to + do not have any effect on the winding voltage and that switching in an ad~acent pha~e, for example S or T, ha~ half the negative effect on the winding voltage as in a phase considered, for example R. In~tead of switching the phase R from positive potential to negative potential, the two ad~acent phases S and T can be switched from negative potential to positive potential. Applying these prin-ciples, unnecessary transitions can be avoided. This applies, at least, when the load i ~Ances are identical in the three phases. The load can also be a transfQrmer or a threQ-phase power system.
The switch-over times and the sequence of phases are selected in Ruch a ~nn~r that a three-phase, poss-ibly sinusoidal motor wi n~ i ng voltage or load phase voltage is produced. In this arrangement, the switch-over times of one pulse are offset with respect to those of the other one in such a ~nner that when the voltages of the two pulses are added, as many harmonics as possible are again cancelled out against one another. A further reduction in h~ nics can be achieved, for example, if four differently controlled inverter groups per phase are conn~cted together, the phase shift of the auxiliary alternating voltage being 90~ in each case. Reference is made to the CH-A-420,365 initially mentioned with re~pect to circuits for reducing h~ -nics.
With a rslatively high pulse frequency of the auxiliary alternating voltages U8l and U~, the method according to the invention can be used within the entire speed range of the asynchronous machine 6. Preferably, however, this method is only used within a speed range from 0% to 30% or up to 70~ whilst phase-shifted two-pulse flln~ Lal frequency pulsing is used at higher speeds in order to keep harmonics and transition~ as low 2C~.603 as possibLe at the same t~me.
Naturally, gate-turn-off GTO thyristorfl or transistors can also be used as valves inst~ad of the thyristors Tl, Tl~, T2, T2~ with ring-around circuits, not shown. Instead of the logic circuits 3.1 and 3.2 a computer can be provided which calculates the required switch-over points for the valves and outputs correspond-ing control ~ignals. The auxiliary alternating voltages can be synchronous or asynchronous to the control vol-tages and exhibit sawtooth-~h~pe~ or trapezoidal or sinusoidal or sine-wave-like shape. If the shape of the auxiliary alternating voltages V~1, U~ is changed, the characteristic of intersections i9 also changed, that is to say the valves are switched, for example, in depen-dence on the falling edge of U~1 and V~, respectively.
Instead of initially switching all valve outputsto a positive potential, the outputs can also be switched to negative potential. It i8 of importance that the switching-over of the valves always occurs with the same depen~n~y (except with a ch~n~e in the sawtooth-shaped signals A1 and A2), that is to say always in dependence on a rising-vQltage or a f~lling-voltage part of the ~lYi 1 i ~ry voltage. If it has been decided, for example, to use the rising-voltage edge of a sawtooth-shAre~
auxiliary voltage, there is no further switch-over at the f~lling edge. This overall reduces the ~r of inverter circuits by 1/3 - and this without effects on the varia-tion of the motor win~ing voltage~ with time. Instead of 6 tran~itions per period of the au~rili~ry control vol-tage, there are now only 4.
Obviously, numerous modification and variationsof the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the ~pp~n~ claims, the invention may be practiced otherwise than as ~pecifically described herein.
Claims (10)
1. A method for controlling a three-phase inverter, a) comprising at least one inverter section (5.1, 5.2, 24) per alternating-current phase (R, S, T) of the inverter, b) in which valves (T1, T1'; T2, T2') of the inverter section are controlled in dependence on inter-sections of two superimposition alternating-voltage signals (UStR, UStS, UStT; UH1, UH2), c) of which a sinusoidal first superimposition alternating-voltage signal (UStR, UStS, UStT) has the required frequency and phase angle of the output voltage of the respective inverter section (5.1, 5.2; 24), and d) a second superimposition alternating-voltage signal is at least a first variable-frequency and -amplitude auxiliary alternating-voltage signal (UH1, UH2), wherein e) the valves of the inverter sections of two first and second inverter phases, the first superimposition alternating-voltage signal of which has been intersected, are switched only in the case of two first and second intersections of the superimposition alternating-voltage signals which follow one another in time, and f) at a third intersection which follows in time, it is not the inverter of a third alternating-current phase, the first superimposition alternating-voltage signal of which has been intersected which is switched but the valves of the two inverter sections which belong to the two other alternating-current phases (R, S, T).
2. A method as claimed in claim 1, wherein a) intersections with the same type of intersection characteristic, in which the intersecting auxiliary alternating-voltage signal (UH1, UH2) always exhibits a positive or always exhibits a negative voltage gradient are selected as intersections of the superimposition alternating-voltage signals, b) in particular, it always exhibits a positive voltage gradient.
3. Method as claimed in claim 1 or 2, wherein the auxiliary alternating-voltage signals (UH1, UH2) for all three alternating-current phases (R, S, T) of the inverter (5.1, 5.2; 24) exhibit the same amplitude and the same phase angle.
4. A method as claimed in one of claims 1 to 3, wherein a) the auxiliary alternating-voltage signal (UH1, UH2) is triangular, b) in particular, it exhibits one at least approximately vertical edge.
5. A method as claimed in one of claims 1 to 4, wherein the frequency of the auxiliary alternating-voltage signal (UH1, UH2) is higher than the highest frequency of the output voltages (U5.1R, U5.2R) of the inverter section (5.1, 5.2; 24).
6. A method as claimed in one of claims 1 to 5, wherein all output voltages (U5.1R ... U5.2T) of the inverter section of each alternating-current phase are controlled for the same voltage potential for initializing the control system.
7. A method as claimed in claim 6, wherein a) at least at the beginning of the control process, the inverter valves (T1, T1'; T2, T2') are controlled for all alternating-current phases (R, S, T) in dependence on intersections of the first super-imposition alternating-voltage signal (UStR, UStS, UStT) with the at least one first auxiliary alternating voltage (UH1, UH2), but in dependence on a second intersection characteristic, which is different from the first one, of this first auxiliary alternating-voltage signal, in such a manner that a predeterminable first potential (+) is present at the alternating voltage output (U5.1R, U5.2R) of the inverter (5.1, 5.2), and b) switching-over of the inverter valves is begun only when this first potential is present at all alternating-current phases.
8. A method as claimed in one of claims 1 to 7, comprising a converter arrangement, composed of two inverter sections (5.1, 5.2) per inverter current phase (R, S, T), for generating a single-phase alternating voltage (UR), wherein alternating voltage signals which are phase-shifted by 180° electrical with respect to one another are used as auxiliary alternating-voltage signals (UH1, UH2) of the two inverter sections, the angle of 360°
electrical referring to the duration of a period of these alternating-voltage signals and the first superimposition voltage signals (UStR, UStS, UStT) corresponding to the output voltage of the inverter section having the same phases.
electrical referring to the duration of a period of these alternating-voltage signals and the first superimposition voltage signals (UStR, UStS, UStT) corresponding to the output voltage of the inverter section having the same phases.
9. A method as claimed in one of claims 1 to 8, wherein at least one of the superimposition alternating-voltage signals (UStR, UStS, UStT; UH1, UH2) and the inter-sections of these superimposition alternating-voltage signals are formed as time-dependent quantities of a timer of a computer.
10. A method as claimed in one of claims 1 to 9, wherein the shape of the auxiliary alternating-voltage signals (UH1, UH2) can be switched during the operation of the inverter (A1, A2).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH4617/88-1 | 1988-12-14 | ||
| CH461788 | 1988-12-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2003603A1 CA2003603A1 (en) | 1990-06-14 |
| CA2003603C true CA2003603C (en) | 1998-01-20 |
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ID=4279454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002003603A Expired - Fee Related CA2003603C (en) | 1988-12-14 | 1989-11-22 | Method for controlling a three-phase inverter |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4951187A (en) |
| EP (1) | EP0373381B1 (en) |
| JP (1) | JP2779021B2 (en) |
| CA (1) | CA2003603C (en) |
| DE (1) | DE58905048D1 (en) |
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| DE59008372D1 (en) * | 1990-08-02 | 1995-03-09 | Asea Brown Boveri | Quarter bridge circuit for large currents. |
| JP2954333B2 (en) * | 1990-11-28 | 1999-09-27 | 株式会社日立製作所 | AC motor variable speed system |
| DE59010931D1 (en) * | 1990-12-08 | 2003-03-06 | Abb Schweiz Ag | Switching arrangement for an HF GTO |
| US5153821A (en) * | 1991-09-06 | 1992-10-06 | Otis Elevator Company | Pulse-width-modulation method for providing extended linearity, reduced commutation losses and increase in inverter/converter output voltage |
| CA2087832C (en) * | 1992-01-24 | 1998-06-23 | Satoshi Miyazaki | Method and apparatus for controlling an inverter |
| DE19725629A1 (en) * | 1997-06-17 | 1999-02-04 | Aloys Wobben | Inverters for feeding sinusoidal currents into an AC network |
| DE19843692C2 (en) | 1998-09-24 | 2003-04-30 | Aloys Wobben | Inverter for feeding sinusoidal currents into an AC grid |
| DE19848540A1 (en) * | 1998-10-21 | 2000-05-25 | Reinhard Kalfhaus | Circuit layout and method for operating a single- or multiphase current inverter connects an AC voltage output to a primary winding and current and a working resistance to a transformer's secondary winding and current. |
| JP2006149153A (en) * | 2004-11-24 | 2006-06-08 | Mitsubishi Electric Corp | Controller for motor |
| JP4483899B2 (en) * | 2007-06-21 | 2010-06-16 | 日産自動車株式会社 | AC controller for axial gap type rotating electrical machines |
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| CH420365A (en) * | 1964-04-24 | 1966-09-15 | Bbc Brown Boveri & Cie | Inverter circuit, in particular for feeding at least one converter motor |
| DE1488096C3 (en) * | 1964-04-24 | 1978-10-05 | Bbc Brown Boveri & Cie | Inverter circuit |
| DE1513851C3 (en) * | 1966-03-31 | 1975-09-18 | Brown, Boveri & Cie Ag, 6800 Mannheim | Device for voltage regulation of a converter arrangement for feeding electrical machines |
| DE2423718C3 (en) * | 1974-05-16 | 1978-03-02 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Circuit arrangement for generating an alternating voltage |
| CA1143787A (en) * | 1978-09-21 | 1983-03-29 | Richard H. Baker | Bridge converter circuit |
| DE3161614D1 (en) * | 1980-03-28 | 1984-01-19 | Siemens Ag | Inverter device |
| US4673859A (en) * | 1985-01-31 | 1987-06-16 | Westinghouse Electric Corp. | Induction motor synthesis control apparatus and method |
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-
1989
- 1989-11-16 EP EP89121174A patent/EP0373381B1/en not_active Expired - Lifetime
- 1989-11-16 DE DE8989121174T patent/DE58905048D1/en not_active Expired - Fee Related
- 1989-11-22 US US07/440,360 patent/US4951187A/en not_active Expired - Fee Related
- 1989-11-22 CA CA002003603A patent/CA2003603C/en not_active Expired - Fee Related
- 1989-12-14 JP JP1322794A patent/JP2779021B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0373381B1 (en) | 1993-07-28 |
| JPH02219470A (en) | 1990-09-03 |
| US4951187A (en) | 1990-08-21 |
| EP0373381A1 (en) | 1990-06-20 |
| DE58905048D1 (en) | 1993-09-02 |
| JP2779021B2 (en) | 1998-07-23 |
| CA2003603A1 (en) | 1990-06-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |