CA1336459C - Bus d'entree-sortie pour interface de bus systeme - Google Patents

Bus d'entree-sortie pour interface de bus systeme

Info

Publication number
CA1336459C
CA1336459C CA000616671A CA616671A CA1336459C CA 1336459 C CA1336459 C CA 1336459C CA 000616671 A CA000616671 A CA 000616671A CA 616671 A CA616671 A CA 616671A CA 1336459 C CA1336459 C CA 1336459C
Authority
CA
Canada
Prior art keywords
bus
command
electrically coupled
system bus
information units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA000616671A
Other languages
English (en)
Inventor
Richard W. Coyle
Zenja Chao
Thomas B. Berg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Wang Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/213,401 external-priority patent/US5003463A/en
Application filed by Wang Laboratories Inc filed Critical Wang Laboratories Inc
Priority to CA000616671A priority Critical patent/CA1336459C/fr
Application granted granted Critical
Publication of CA1336459C publication Critical patent/CA1336459C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
CA000616671A 1988-06-30 1993-07-23 Bus d'entree-sortie pour interface de bus systeme Expired - Fee Related CA1336459C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA000616671A CA1336459C (fr) 1988-06-30 1993-07-23 Bus d'entree-sortie pour interface de bus systeme

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US213,401 1988-06-30
US07/213,401 US5003463A (en) 1988-06-30 1988-06-30 Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
CA000604309A CA1325853C (fr) 1988-06-30 1989-06-29 Bus d'entree-sortie pour interface de bus de systeme
CA000616671A CA1336459C (fr) 1988-06-30 1993-07-23 Bus d'entree-sortie pour interface de bus systeme

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CA000604309A Division CA1325853C (fr) 1988-06-30 1989-06-29 Bus d'entree-sortie pour interface de bus de systeme

Publications (1)

Publication Number Publication Date
CA1336459C true CA1336459C (fr) 1995-07-25

Family

ID=25672849

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000616671A Expired - Fee Related CA1336459C (fr) 1988-06-30 1993-07-23 Bus d'entree-sortie pour interface de bus systeme

Country Status (1)

Country Link
CA (1) CA1336459C (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114036096A (zh) * 2021-11-04 2022-02-11 珠海一微半导体股份有限公司 一种基于总线接口的读控制器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114036096A (zh) * 2021-11-04 2022-02-11 珠海一微半导体股份有限公司 一种基于总线接口的读控制器
CN114036096B (zh) * 2021-11-04 2024-05-03 珠海一微半导体股份有限公司 一种基于总线接口的读控制器

Similar Documents

Publication Publication Date Title
US5003463A (en) Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
US5261057A (en) I/O bus to system interface
EP1046111B1 (fr) Transfert de donnees selon des protocoles de transmission de source synchrone et a horloge commune
US6202097B1 (en) Methods for performing diagnostic functions in a multiprocessor data processing system having a serial diagnostic bus
US5919254A (en) Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
EP0425550B1 (fr) Unite de commande de memoire
US5594882A (en) PCI split transactions utilizing dual address cycle
EP0139563B1 (fr) Mécanisme de commande pour système multi-processeur
GB1588807A (en) Power interlock system for a multiprocessor
EP0301610B1 (fr) Appareil de traitement de données pour raccordement avec un bus de communication commun dans un système de traitement de données
JPH0473176B2 (fr)
EP0440662B1 (fr) Bus systeme avec ordres/identifications et donnees multiplexes
US6108735A (en) Method and apparatus for responding to unclaimed bus transactions
US5089953A (en) Control and arbitration unit
US5923857A (en) Method and apparatus for ordering writeback data transfers on a bus
CA1336459C (fr) Bus d'entree-sortie pour interface de bus systeme
US5764935A (en) High speed active bus
EP1306766A1 (fr) Procédé et dispositif pour la vérification de la parité d'adresse pour des régions d'adresse multiples sur un bus partagé

Legal Events

Date Code Title Description
MKLA Lapsed