CA1324638C - Multichannel gas analyzer and method of use - Google Patents

Abstract

MULTICHANNEL GAS ANALYZER
AND METHOD OF USE
ABSTRACT

An improved gas analyzer system and method for detecting and displaying information with respect to gases of interest in a respiratory gas stream, with the system comprising an optical bench further comprising a gas pathway for the flow of a gas stream through the optical bench, a flow shaping inlet at the gas entrance to the optical bench's gas pathway, two infrared detection channel assemblies for measur-ing the partial pressures of the gases of interest in the respiratory gas stream, a pressure sensor for measuring the pressure within the gas pathway, a temperature sensor for measuring the temperature within the optical bench, and a flow rate sensor for measuring the gas flow rate through the gas pathway, circuitry for processing the detected partial pres-sures of the gases of interest and the measured values for pressure, temperature, and flow rate, and for providing output signals indicative of processed measured values, the detected partial pressures of the gas of interest, and characterization infor-mation with respect to the optical bench components;
analog input circuitry for processing the signals output from the optical bench for input to the analog processing circuitry; analog processing circuitry for processing the signals input thereto and correct-ing at least the detected partial pressures of the gases of interest signals for collision broadening, temperature, pressure in the gas pathway, barometric pressure, cross-correction, and characterization of the optical bench components, and providing output signals indicative of the corrected partial pressures of the gases of interest to the display processing circuitry; display processing circuitry for processing the signals input thereto for display of at least the corrected partial pressure of one gas of interest on a cathode ray tube as numerical and/or scrolling graphical data, for output to analog and digital output connections, and for alarms; and a power supply for powering the system.

Description

132~38 ; IMPROVED MULTICHANNEL GAS ANALYZER
AND METHOD OF USE

This is a divisional application of Canadian Patent Application Serial No. 549,442 filed October 16, 1987.

Technical Field The present invention relates to systems for measuring the partial pressures of eonstituent gase~ in a ga~ stream. More specifically, the in-vention relates to improved multichannel gas analyzer systems u~ed to measure the partial pressure~ o constituent gases in respiratory gas streams and display representative gas information on a CRT dis-play.
; Back~round During -qurgery, anesthetized patients are uQually 1ntubated. Measurement of respiratory gase~
is de~lrable when a patien~ i8 mechanically intubated through an endo-tracheal tub¢. An analysi~ of the inhaled and exhaled ga~ mixture provide~ information about the patient's ventilation.
Carbon dioxid- (CO2), nitrous oxide (N20) and the anesthetic agent are the con~tituent ga~es of most interest in mea~uring respiratory gas streams.
It is well known that CO2 in the bloodstream equillbrates rapidly with CO2 in the lungs. Hence, the partial pres~ure of the CO2 in the lungs approaches the amount in the blood during each breath.
Accordingly, the CO2 content at breath's end, termed , -2- 132~3~
end-tidal C02, is a good indication of the blood C2 level.
Abnormally high end-tidal C02 values indicate that an insufficient amount of C02 is being transported away from the bloodstream through the lungs, i.e., inadequate ventilation. Conversely, abnormally low end-tidal C02 valueQ indicate poor blood flow to t~e tissues, inadequate C02 transport through the lungs, or excessive ventilation.
Mass spectrometers are used for measuring the partial pressure of respiratory gases in, for example, operating room suites in which one spectro-meter is shared by many rooms. Mass spectrometers have the advantage of measuring a multiplicity of gases; however, the disadvantages are their cost, maintenance and calibration requirements, slow response time, and noncontinuous measurement.
Gas analyzers using non-dispersive infrared spectrophotometry are also used for partial pressure gas measurement. While these analyzers are less expensive than mass spectrometers and continuously measure partial gas pressure, their disadvantages are poor response time and difficulty in calibration.
Prior art non-dispersive infrared ga~
analyzer~ include features for ma~ing C02 and N20 cross chann-l detection, temperature, and collision broadening corrections to their partial gas pre~sure moasurement~. Some of these corrections are made automatically by the analyzers while other~ are made manually by tho operator.
Non-dispersive inrarod gas analyzers gener-ally have two coniguratlons. Tho first, and most common, i~ ths sampling or side-stream type. This type divert~ a portion o the pationt's rs~piratory ga~ flow through a sample tube to the infrared analyzer.

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The second type mounts on the patient's airway and uses a portion of the airway as the sample chamber. This type is frequently occluded by the mucus and moisture in the patient's airway and its S bulk on the airway can affect the patient' 5 breathing.
Both infrared gas analyzer configurations are characterized by small absorption levels by the constituent gases which lead to small signals and stability problems.
Increasing the analyzer's sample chamber size improves the small signal and stability problems;
however, it also increases the response time. Increas-ing the gas flow rate through the analyzer improves the response time, but occlusions are more frequent and the patient's normal ventilation Yolume is impaired.
In this regard, neonates require sample low rates egual to or less than 50 cc/minute.
However, neonates also require the analyzer's response time to be compatible with breath rates well in excess of 60 breaths per minute. This condition equates to a response time of less than 100 milliseconds.
Another disadvantage o infrared gas analyzers is that they reguire frequent calibration for proper operation. Factor~ afecting calibration of the optical bench portion o~ a gas analyzer include manuacturing tolerance~ relating to the Qample cell dimensions (particularly thicknes~); the brightness of the infrared source~ and sensitivity of the photo-detectors; temperature; barometric pressure; and the accumulation o dirt or moisture in the optical bench gas pathways.
Changes in the optics and electronic cir-cuitry over time require recalibration of infrared gas analyzers. Careul con~truction of th- optics and electronic circuitry minimizes the number of calibration adjustments needed and the period between recalibration. Hence, interchangeability o the 1 3 ~ ?3 optical bench of an analyzer has not heretofore been practical because of the need for recalibration when the optical bench i8 connected to the analyzer.
Calibration of infrared gas analyzers i9 accomplished by various electronic circuit adjust-ments to correct for variations in sample chamber geometry as well as variations and drift of various sensing components.
Calibration usually requires taking the analyzer out of service and passing standard gases through it, in the presence of which the various adjustments are made. Another calibration method is to make a "zero gas" reading for the optical bench and adjust the analyzer's amplifier so that the analyzer's output actually reads zero. A still further method uses a reference cell filled with a non-absorbing gas or a reference filter having a wavelength at which no absorption takes place to stabilize the zero setting of the analyzer.
Prior art non-dispersive infrared gas analyzers also include some automatic calibration features. However, further operator controlled calibration procedures are required before the analyzer~ are ready for u3e.
The pre~ent invention overcome3 these and other problem~ of prior infrared gas analyzers a will be set forth in the remainder of the specifica-tion.
Summarv of the Invention The present invention is an improved non-dispersive infrared ga~ analyzer system for removing a respiratory ga~ stream from a patient, analyzinq the gas stream, and displaying information about detected gasos of intere~t.
The ~ystem includes a patient airway adapter which i~ used to remove a r-spiratory gas stream from ......

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the patient. The airway adapter has valving which allows for backflushing of the airway adapter inlet filter without reversing the flow through the sample gas tube uced for drawins a respiratory gas stream through the system.
The patient module of the system includes an optical bench with associated circuitry. This circuitry generates signals representative of the partial pressures of C02 and N20 present in a respiratory gas stream transiting a gas pathway, the reference optical path, the temperature within the optical bench, and the pressure within the gas path-way.
The system pump module to a large extent controls system pneumatics. The module has means to draw a respiratory gas stream through the optical bench gas pathway for measurement of C02 and N20.
The module also has means for measuring the flow rate of the gas stream through the optical bench gas pathway. The pump module backflush pump provides an air stream to the patient airway adapter for clearing its filter should it become occluded with, for example, mucus. The backflush air steam is supplied to the airway adapter for filter cleaning without the possibility of backflushing any virus or bacteria, for example, contained in gas pathway or the sample tubo bac~ into the patient. Two valves in the pump module redirect the respiratory gas stream through an external device for measurement of other consti-tuents of interest in the gas stream when conigured to do so. Tho module's diagnostic valve together with other valves, the sample pump, and tho flow sensor is u~ed to test the fluid-tight integrity of the gas pathway.
With respect to system pneumatics, the patient module includes a zero valve, which when properly configured, is used with the pump module to 132-~;t~o supply scrubbed room air to the optical bench to make zero gas readin~s. A backflush valve in the patient module controls the 10w of the backflush air stream to the patient airway adapter.
S Analog input circuitry is electrically connected to the patient module including the optical bench. This circuitry receives the signals output from the optical bench and other patient module circuits. Analog input circuitry processes these signals and among other things converts them from analog to digital signals. The analog input cir-cuitry then outputs the digital signals to the analog processing circuitry.
Analog processing circuitry, which includes a microprocessor, performs calculatin~ functions.
The results are output signals indicative of the partial pressure of C02 and N20 corrected for tem-perature, pressure in the gas pathway, collision broadening, cross-correction, and characterization.
These signalq along with those for the measured values of flow rate, pressure, and temperature are output to the display section of the system.
Display section circuitry, according to its programming, processes the signals output from the analog processing circuitry. The signals output from display ection circuitry drive a CRT for dis-play of graphic~ and characters repre~entative of the partial pressures of the gases of interest and other measurod valueQ from th- patient module.
The optical bench has two optical detection channel ~ssemblie~ for measuring C02 and N20 in the respiratory ga~ stream and the reference optical path associated with the C02 and N20 detection channel assemblie~. The bench continuously measures these ! 35 gases at a rate which allow~ -~eparate analysiQ of the inspired and expired gas mixtures. The optical bench circuitry preliminarily proce~ses the signals _7_ 1 3 ~ ~ J !,~ ~

output from the gas detectors and other detectors such as a pressure measurement sensor and a tempera-ture measurement sensor.
The two optical detection channel assem-blies and the connected detection circuitry areincorporated in the optical bench which is part of the small patient module. The patient module con-nects to a larger apparatus constituting the remainder gas analyzer system.
A double lumen tube, preferably one yard long or less, connects the patient module to a side-stream type patient airway adapter. The double lumen tube comprises a sample tube and backflush tube. A
filter in the airway adapter blocks liguids, such as water or mucus, present in the patient's airway from entering the sample tube and, accordingly, the optical bench. The walls of the sample tube absorb water vapor condensing on them and evaporate it into the atmosphere which constitutes one-way water vapor transmission from within the sample tube. An optical bench entrance filter provides redundant protection of the optical bench gas pathway.
A flow shaper at the entrance of the optical bench gas pathway reshapes the sample tube gas flow cro~s-~ection from round to rectangular. In the optical bench ga3 pathway, the ga~ ~tream passes through the C02 and N20 detection channel assemblies in ~ucces~lon a~ it transitJ th- gas pathway.
Aftor leaving the optical bench gas pathway, the gas ~tream enters an absolute-type pressure trans-ducer. The gaJ stream then leavo~ the absolute-type pres~ur- transducer and enters tho pump module. In thi~ module the gas Jtream pasqes through the flow ~en~or and the ~ample pump. After leaving the pump module, the ga~ stream enter a scavenging tube and iJ exhausted from the system.

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The C02 and N20 detec~ion channel assem-blies are configured to measure the amount o C02 and N20 in the respiratory gas stream, respectively, and measure the reference optical path associated S with each a~sembly. The optical paths of the C02 and N20 detection channel assemblies each contain the gas pathway and contain respectively the C02 reference cell and the N20 reference cell. The reference cells can be filled, for example, with room air.
The detection channel assemblies include sapphire windows that replace opposinq wall sections of the reference cell and the gas pathway in the assembly's optical path. An infrared light source lS is disposed behind one of the windows and a source aperture is disposed adjacent the opposing window.
A detector aperture is disposed spaced away from the source aperture. Both apertures have openings that align with the optical path through the reference cell and gas pathway. The two apertures shield the optical paths from ingress of bac~ground infrared light.
A chopper wheel, common to the two detector channel assemblies, rotates in a plane between the source and d-tector apertures. The chopper wheol chops the inrared light passing through the openings in the sourco aperture aligned with the reference cell and gas pathway at a predetormined frequency.
The chopped liqht passes through openinqs in the det-ctor ap-rture aligned with tho reference cell and gas pathway to the remaining portions of the assembly .
Adjacent an oppo~ito side of the detector ap-rturo is a narrow-band infrared filter. The filter is aliqnod to receive light that ha~ pas~ed throuqh either the reference cell or the qas pathway.

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A lead selenide detector is disposed on the other side of the infrared filter. The detector is aligned to receive light that has passed through either the reference cell or the gas pathway.
The chopper wheel together with other detection channel circuitry generate waveform pat-terns to control the timing and position of certain events during a timing cycle. These waveform pat-terns are used for, among other things, the syn-chronous detection and demodulation of the C02 and N20 gas and C02 and N20 reference signals output from the respective detectorc representative of the partial pressures of these gases.
The optical bench circuitry includes an electrically erasable programmable read-only memory (EEPROM) which stores characterization information for the specific optical bench. The characterization information corrects optical bench measurements for system component performance that deviates from ideal theoretical performance. The characterization informa-tion obviates the need for calibration of the optical bench. Characterization information includes coeffi-cients for temperature, collision broadening, cross-correction, span factor, offset for a system component, and pressure. Span factor is for translatinq the output voltage of the a component into desired param-eter, such as pressure. Offset i~ to corroct an in~trument 1 8 readinqs to zero. Characterization information iJ used by the analog procossing cir-cuitry and the display circuitry in carrying outsignal proeessing function~.
Tho analoq input circuitry and the analog processor circuitry process the analog signals gen-orated by the optical bench circuitry. The proces~ed ~ignals, now digital, are transmitted to the display section. The display section processes the signals for display on a CRT.

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The main circuits of the display ~ection are the display processor circuitry and pixel circuitry. The display proce~sor circuitry bi-direc-tionally communicates with the analog processor circuitry and controls the pixel circuitry. This control result~ in driving the CRT to display both the fixed characters and scrolled information, e.g., a capnogram.
Preferably, the CR~ displays numerical and graphical data. The numerical data normally displayed are the inspired and expired values for CO2 and N20, and respiration rate. The graphical data normally displayed is the C02 waveform. This waveform is an indication of the patient~J respiratory cycle. Super-imposed on, for example, the C02 waveform are thetransition points between inspiration and expiration, and between expiration and inspiration. The~e points are marked with an "I" and an "En, respectively.
The "I" and "E" markings provide the physician with the locations of selected transition points in both normal and abnormal capnograms.
An ob~ect of the present invention is to provido a system for displaying the part$al pres~ure~ of gases of intere~t in a patient's respira-tory gas stream, scrolling waveorm~ acros~ thedisplay Jcreen and mar~ing in~pired and expired transition points of a patient'~ broathing cycle.

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Accordingly in one aspect there i8 provided a real-time ~ethod of marking a dis-play means to distinguish the occurrence of respira-tory events in a continuous waveform representative of the amounts of constituent gas in a respiratory gas stream being displayed on the display means, comprising generating in real-time a sign21 indica-tive of the amounts o the constituent gas displayed on the display means based on the signals generated in the generating step, and marking the continuous waveform in substantially real-time with a labeling means the occurrences of predetermined events along the continuous waveform.
These and other asp~ct6 of the invention will be dewribed more fully in the remaininq por-tions of tho specification.
Brief Descri~tion of the Drawinqs Figure 1 is a block diagram of the multi-channel gas analyzer system of the present invention.
Figure 2A i~ a cros~-sectional view of the connector for connecting a double lumen tube to the patient airway adapter of t.he multichannel gas analyzer system of tho present invention.
. Figur-s 2B and 2C aro two different cros~-sectional viows of tho patient airway adaptor of the -12- 1 3 2 ~ v ~ ~
multichannel gas analyzer system of the present inven-tion.
Figure 3A is an exploded view of the optical bench of the multichannel gas analyzer system of the present invention.
Figure 38 shows the optical detection channel assemblies with their components shown in an exploded view.
Figure 3C shows the C02/N20 detection channel assembly of the optical bench of ~he multi-channel gas analyzer system of the present invention.
Figure 4A is a block diagram of the pneu-matics of the multichannel gas analyzer system of the present invention.
Figure 4B shows schematic diagrams of drive circuits for various components associated with control of the pneumatics.
Figure SA is a schematic diagram of the optical bench circuitry of the multichannel gas analyzer system of the present invention.
Figure SB shows schematic diagrams of drive circuits in the optical ~ench for various com-ponents a~sociated with control of the pneumatics.
Figure 6A is a top view of the chopper wheel of the optical bench o the multichannel gas analyzer system of the present invention.
Eigure 6B is a top view of the chopper whe-l o~ Figure 6A associated with selected portion~
in the optical bench o the multichannel gas analyzer systom of the present invention.
Figuro 6C aro wavoform~ associated with gas and reference optical path detection, and demodula-tion.
Figur- 7A-7D compri~- a ~chomatic diagram of the analog input circuitry of tho multichannol gas analyzer y~tem of tho prosent invention.

-13- ~3 2 ~ 3~ 3 Figures 8A-8C comprise a ~chematic diagram of the analog processing circuitry of the multichan-nel gas analyzer system of the present invention.
Figures 9A-9E comprise a schematic diagram of the circuitry on the motherboard of the multi-channel gas analyzer system of the presént invention.
Figure 10 is a schematic diagram of the display processor circuitry of the multichannel gas analyzer system of the present invention.
Figures llA-llC comprise a schematic dia-gram of the pixel circuitry of the multichannel gas analyzer system of the present invention.
Figures 12A-12C comprise a schematic dia-gram of the scroll/pixel gate array of the pixel circuitry shown in Figure llB.
Figure 13 is a schematic diagram of the CRT memory control gate array o the pixel circuitry shown in Figure llB.
Figure 14 is a schematic diagram of the digital output section of the display section of the multichannel gas analyzer system of the present invention.
Figure lS is a schematic diagram of the system control~ and alarms for the multichannel gas analyzer system of the present invention.
Eigure 16 is a block diagram of the so~tware or controlling the multichannel gas analyzer ~ystem of the present invention.
Figure 17 ~hows a repre~entative CRT scroen display for the multichannel gas analyzer system of the present invention.
Detailed Deseription of the Preerred Embodiments The present invention i~ an improved multi-channel gas analyzer system for measuring the partial pre~sure~ of gases of intere~t in a respiratory 1 3 ~ ~t, gas stream. The analyzer system also displays numeri-cal and graphical information about detected gases.
The figures reer to electronic components, or circuitry which consist of a group of components, which carry out a known specific function. Those components or circuit elements that are well known by those skilled in the art will be referred to generally by their common names or functions and are not explained in detail.
Analog section 102 and patient airway adapter 106 are described generally and in detail in discussing Figures 2A through 8C. Display section 104 is described generally and in detail in discuss~
ing Figures 9A through 15.
Figure 1 is a schematic diagram of the multichannel gac analyzer system of the present invention. The system comprises patient airway adapter 106, analog section 102, and display sec-tion 104. Analog section 102 deteets and measures certain constituent gases in a respiratory gas stream. This section also detects and measures other physical properties which affect the determina-tion of the partial pressures of constituent gases, e.g., C02, and N20. The measured values for C02, N20, and the other physical properties are combined to calculate the "real" partial pressure of C02 and N20. The ~real" partial pressures o~ these gases are corrected for barometric pressure, optical bench pressure, temperaturo, collision broadening, cross-correction, and charactorization of the detectioncircuitry and other detection compononts.
The calculated values for the partial pressure~ of C02 and N20 are output from analog Jection 102 in digital form to display section 104.
Analog section 102 also transmits measured values or flow rate, pressure, and temperature to the display ~ection.

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Display section 104 processes the analog section signals. The C02 and N20 signals are processed for display on the CRT as numeric charac-ters. The display section also processes at least the C02 signals for graphic display as, for example, a scrolling capnogram. The display section processes the pressure, flow rate, and temperature signals for display or as historical data.
The display section has system controls for opera~or interface. These controls select system operation and choice of screen displays. The display section also has both digital and analog output ports for communicating with peripheral equipment. The display section includes visual and audible alarms to indicate alarm conditions or improper system operation.
The analog processor circuitry can receive input signals from another optical bench for proces-sing for display on the CRT. The other optical bench is dedicated to measurement of the partial pressures of other gases of interest in the respiratory gas stream.
Analog section 102 comprises patient module 109 which includes optical bench 111 (whose electronics include optical bench circuitry 118); pump module 112;
analog input circuitry 122; and analog processing circuitry 124.
Di~play section 104 comprises display processing circuitry 128; pixel logic circuitry 130 ~which include analog outputs); digital outputs 140;
speaker driv~r 152; alarm and knobs 144; S-button panel 148; and display motherboard 137 (which includes a CRT driver). The powering system include~ power supply 158, rectifier 160, and DC-DC converter 162.
Patient airway adapter 106 and tube-~ 172 and 174 ~which form a double lumen tube that connects adapter 106 and patient module 109) are not part of . . .

I~2~ ~ t.3~'3 analog section 102 The airway adapter can be detach-ably fixed to tube~ 172 and 174 The adapter nd tubes, besides being u~ed in-part aa a gas pathway from the patient to the patient module, provide~ a .5 novel mean~ for backflushing the adapter without risk of contaminating a patient with viru~ or bac-teria that may exist in th~ optical bench gas path-way or sample tube 174 Measurement accuracy increase3 the closer to the patient gas detection i~ made For this reason, the length of the double lumen i~ preferably one yard or le~s Referring to Figure~ 2A, 2B, and 2C, the double lumen tube, its as30ci~t-d connector, and patient airway adapter 106 will be de~cribed The double lumen tube containing sample tube 174 and backfluJh tube 172 connect~ airway adapter 106 and patient module 109 The serie3 of dot~ at 170 represent the outer cover which enca~e~ ga~ sample tube 172 ~nd backflush tub¢ 174 The walls of the sample tube, preferably constructed of Nafion, ab~orb and then evaporate condens-d water vapor in the tube N~fion is commer-cially available from E I du Pont d- Nemour~ and Company, Wllmington, Delawate ~aion i~ a trad-mark of E I du Pont and Company, Wilmington Delaware Connector body 178 ha~ gr$pping member~ 180 wh~ch along with locking cap 176 secur- outer cover 170 of th- double lum-n tube to connector body 178 Conncctor body 178 ha~ annular bea~ 188 whlch aJ~ist~
ln locklng th- connector body w~thin airway adapt-r 106 0-ring 190 1~ dl~po~ed in annular groove lB6 0-rlng 190 1- u~-d to provide a fluld-tlght ~eal betweon conn-ctor body 178 and alrway adapter ~ection 210 Connoctor ~ody 178 har central bore 182 Plug 184 i~ dl~po~ed in one end o the connector body and r-ceive~ tub-~ 172 and 174 Pluq 184 h~

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separate openings for receiving backflush tube 172 and sample tube 174 therethrough.
The other end of central bore 182 has insert 192 disposed therein. Insert 192 ha~ centrally dis^
posed orifice 196 which,connects to a larger diameter end opening 194. The end of sample tube 174 is dis-posed in ori~ice 196 so that it is in fluid communica-tion with end opening 194.
Backflush tube 172 passes through plug 184 and is in 1uid communication with central bore 182.
Channels 198 and 200 are for fluid communication between central bore 182 and annular channel 201 in the end of connector body 178. Channel 201 is con-centric with end opening 194. Accordingly, backflush tube 172 is in fluid communication with the end of the connector body.
~igures 2B and 2C show two different cross-sectional views of airway adapter 106. Accordingly, the ollowing description applies to both figures.
Connector body 178 mates with section 210 o airway adapter 106. Section 210 has central cavity 212 which has disposed within it valve body 216 and valve member 226. Valve body 216 and valve mem-ber 226 are disposed on annular ledge 224 within cavity 212. Valve member 226 i~ disposed between valve body 216 and annul ar ledge 224.
Valve body 216 ha~ centrally aligned nipple 217 on the side acing cavity 212 and centrally aligned nipple 219 on the opposite side. Oriice 218 extends through the center o the centrally aligned nipples. Concentric with nipple 217 i8 annul ar channel 220. Orifices 222 extend rom the bottom annular channol 220 through the remaining thickne~s o valve body 216.
Valve member 226 has an opening in the center through which nipple 219 extends. In the valvo's clo~ed position, the edgo o the opening in 3 2 ~
valve member 226 rests against the sides of nipple 219 and in cross-section forms an acute angle~ with the side of that nipple. This i8 necessary for proper operation of the valve.
S Annular ledge 228 is fixed to the walls o opening 230 at the end nearest the valve. ~ydrophobic filter 232 is disposed across opening 230 on the side of ledge 228 closest airway adapter section 238.
~ydrophobic filter 232 can be fixed to annular ledge 228. However, in the preferred embodiment, annular ledge is not included and the filter is fixed to ledge 229. When annular ledge 228 is included, it seals the filter in place and prevents valve member 226 from contacting filter 232 when it is open and portions thereof move toward the filter.
Second section 238 of airway adapter 106 ha~ opening 236 into which first section 210 is fixed.
Section 238 has passage 240 through which respiratory gas to be sampled flows. Section 238 is usually disposed in the patient's airway.
When connector body 178 ie inserted into cavity 212, annular bead 214 at the end o the cavity moves ovor annular bead 188 on connector body 178.
Accordingly, annular bead 188 rests in annular depres-sion 215. This locks the connector body within theairway adapter. 0-ring 190 rest~ against the interior wall o section 210 to seal against fluid leaks.
End opening 194 of connector body 178 fits over nipple 217 o valve body 216. This place~ sample tube 174 in fluid communication with the respiratory ga~ flow in passage 240 through oriice 218 and ilter 232.
When connector body 178 i Q locked in sec- -tion 210, annular channel 201 in the end of connector body 178 i~ in 1uid communication with annular channel 220 in valve body 216. Since oriflce~ 222 are in 1uid communication with pas~age 240 through valve member 226 and filter 232, back1ush tube 172 is in -19- ~32~ 8 uni-directional fluid communication with passage 240 of section 238.
In normal sampling operations, sample pump 358 (Figure 4A) in the pump module draws the ga~
sample through filter 232, orifice 218, and sample tube 174. Valve member 226 prevents the sample gas from entering backflush tube 172.
When filter 232 becomes occluded with mucus or other material requiring a backflush to clear it, zero valve 376 (Figure 4A) has its flow configura-tion chanqed so that the flow through sample tube 174 is cut off. Backflush pump 394 is activated and pumps filtered room air at a desired rate into back-flush line 172 toward airway adapter 106. The fi~tered room air passes from backflush tube 172 through central bore la2, channels 198 and 200, and into annular channel 201 in the end of connector ; body 178. Erom the connector body, the backflush air enters annular channel 220 in valve body 216 and passes through orifices 222 in valve body 216. When the pressure of filtered room is great enough, valve member 226 lifts from its seat against the sides of nipple 219 allowing the filtered room air to clear filter 232 o~ the obstruction. Hence, the airway ; 25 adapter can b- backflushed without the possibi1ity of backElushing any contamination that exists in the sample tube or the optical bench gaQ pathway into the patient when back1ushing filter 232. Preferably, filter 232 is constructed of expanded PTFE with a 1 micron pore size.
The airway adapter has been described as involving the joining two separate sections, speci-fically, sections 210 and 238. Howev-r, it is under-stood that the airway adapter can be of unitary con-struction.
Eigures 3A-3C show optical bench 111.
Referring to Figure 3A, an explod-d elevation view ,, .

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of the optical bench is shown Each o the board~, blocks, or plates has a centrally dispo~ed opening to accommodate the chopper wheel and it~ a~sociated driving asQembly; therefore, those openings will not be discusscd separately End plate 250 forms the first end of the optical bench and is also a heat sink to dissipate heat genexated in the optical bench Detector board 252 is disposed inward of end plate 250 The detector ~o-rd has ~ilicon photo-diodes 254 and 256 fixed in openings 253 and 255, respectively, and lead selenide detectors 258 and 262, and thermistor 260 mounted on the board Photodiodes 254 and 256 d~t-ct the amount of infrared light illuminating them from LEDs in their respective optical paths D-tectors 258 and 262 deteet the amount of infrared light illuminating them from infrared light sources in their respective optical paths Thermistor 260 senses the optical bench temperature through resistance changes and conventional circuitry converts thc resistance changes to a voltage Preferably, the photodetectors are model OP900 commereially availablo from TRW Optron, Carrollton, Texas; the lead elenide detector~ r~
commercially available from OP~O Electronics, Inc , Sants Rosa, California; and, preferably, the th-rmistor i~ model B43PB103K commercially availabl-rom Thermometrics, Metuchen, New J~r~ey Filter block 264 is di~posed lnward of detector board 252 Th- f~lter block ha~ C02 optical filter 266 fix-d in opening 265 and N20 optieal filtor 268 fixed in opening 267 Tho C02 ilter and N20 filterc ~r- commercially vaila~le from Optical Coating La~oratorl-s, Inc , P-taluma, California Detector aperture 270 is dispo~d inward of the fllter block Th- detector aperture has open-ings 272 and 273, and openings 274 and 275 for ~hi-ld-1 3 2 !~
~21-ing against background light ingressing the C02 and N20 optical paths, respectively. Opening 272 is associated with the C02 reference optical path and opening 273 is associated with the C02 gas optical path. Opening 274 is associated with the N20 refer-ence optical path and opening 275 is associated with the N20 gas optical path.
The series of closely spaced openings indicated generally at 276 are for shielding the timing track optical path against ingress of back-ground light. The single opening 277 is for shield-ing the position track optical path against the ingress of background light.
Spacer 278 serves the conventional purpose of a spacer. It sDaces apart detector aperture 270 and source aperture 282 so that chopper wheel 280 can rotate in a plane between the two apertures.
The chopper wheel assembly comprises chopper wheel 280, bearing 292, jack shaft and bearing 322, and motor 336 with flexible coupling shaft 338.
Preferably, the motor i8 model 2312-910-21141-010 commercially from Maxon Precision Motors, Palo Alto, California.
The chopper wheel will be discussed fully when describing Figurcs SA, 6A, 6B, and 6C.
Source aperture 282, like detector aporture 270, ~hields the C02 and N20 optical paths against ingres~ of background light. Openings 283 and 284 ar- the openings for the C02 reference optical path and tho C02 qa~ optical path, respectively. Open-ings 285 and 286 are for the N20 r-ference optical path and the N20 gas optical path, respectively.
Opening 290 i~ a~sociated with the timing track optical path; and opening 288 is as~ociated with the position track optical path.
Block 294 contains respiratory gas pathway 298 and the reference gas cells. Block 294 has also .

-22~ J
gas inlet 310 and outlet 316. Preerably, gas path-way 298 is rectangular in cross-section. The gas pathway will be discussed in detail when describing Figure 38.
~lock 294 has opening 306 associated with the position track optical path and opening 304 associated with the timing track optical path.
Block 294 has also alignment members 308 for proper alignment of the various component boards, blocks, and plates of the optical bench.
~ Block 294 has opening 299 into which ; sapphire window 295 is fixed. Although not shown here, sapphire window 342 is fixed in an opening on the other side of block 294. These sapphire windows form opposing walls of C02 reference cell ~96 and gas pathway 298.
In like manner, block 294 has opening 301 into which sapphire window 297 is fixed. Although not shown here, sapphire window 344 is ixed in an opening on the other side of block 294. These sapphire windows form opposing walls of N20 reference cell 300 and gas pathway 298.
A~30ciated with block 294 are inlet flow shaper 311, entrance line 314, and in-line filter 312, 25 exhaust fitting 317, and exhaust line 318. Filter 312 is disposed at ga~ inlet 310. Flow shaper 311 and ilter 312 reshape the incoming ga~ stream croso-section rom round to rectangular. Exhaust fitting 317 i~ adapted to it gas outlet 316. Preferably the entrance and exhaust lines are constructed o ethyl vinyl alcohol copolymer .
Pressure transducer 320 is disposed on exhaust line 318 for moasuring the pre~sure in the gas pathway. Thc mea~ured pressure value i8 usod for correction o the detected qas 3ignal~.
Lamp block 324 has opening 325 in which iR
source 326 is ixed, opening 327 in which IR source 132~ 3~

328 is fixed, and openings 329 and 331 in which LEDs 330 and 332 are fixed, respectively. IR source 326 is associated with the C02 reference and sample gas optical path and IR source 328 is associated with the N20 reference and sampls gas optical path. LED
330 is associated with the timing track optical path and LED 332 is associated with the position track optical path. Preferably thP IR sources are model 4115-2, commercially available from Gilway Company, Woburn, Massachusets, and the LEDs are model SFH-487 commercially available from Siemens Components, Inc., Cupertino, California.
Motor block 334 is used to mount motor 336.
Motor block 334 also serves as the second end of the optical bench. Bolts 340 are used to connect the various components, boards, blocks, and plates of the optical bench.
Figure 3B shows half racetrack-shaped gas pathway 298 that is used for passing a respiratory gas stream through the optical bench. This figure shows in-part the elements of the C02 and N20 optical paths. These are IR sources 326 and 328, sapphire windows 342 and 295 associated with the C02 reference and C02 gas optical paths and sapphire windows 344 and 297 as~ociated with the N20 reference and N20 gas optical paths, C02 reference cell 296 and N20 reference cell 300, a portion of chopper wheel 280, C2 optical filter 266 and N20 optical filter 268, and C02 detector 262 and N20 detector 258. These elements when combined form a ma~ority o the C02 and N20 detection a~semblie~.
Opt~cal filter 266 has a eenter frequency of 4.265 microns and a bandwidth of 2.0%. This coincides with the ab~orption band of C02. Optical filter 268 has a center wavelength of 4.50 micron~
with a bandwidth of 2.5%. Thi coincide~ with absorption band of N20.

-2~- ~ 3 2 ~ ~ ~30 Detectors 258 and 262 are leAd ~el-nide infrared deteetor~ Prefera~ly, the deteetors have a 3 mm sguare aetive area Referring to Figure 3A, the re~piratory S gas stream enters the optical benoh at ga~ inlet 310 from flow shaper 311 and pa~ses through in-line filter 312 The entering ga~ flow hn3 a circular cross-~ectional shape Flow 3haper 311 and inline filter 312 reshape the gas flow to the rectangular cross-sec*ional shape of ga~ pathway 298 without turbulence Flow ~haper 311 ha~ an inlet with a eircular cros~-sectional ~hape and outlet with a rectangular cros~-~ectional ~hape that matche~
gas pathway 298 Ihe center port$on o the flow ~haper makes a smooth transition from the circular to the rectangular cro~s~aectional ~hape A lon-gitudinal cro~ ection of th- 10w shaper rev~al~
that the interior walls are either straight or curved There i5 a pre~ure drop acro~ in-line filter 312 This pre~sure drop aYs$st in turbulence free re-~haping of the cro~ ectional ~hape of th~ gas fitream However, other configuration~ for the inlet to accomplirh flow shaping without a filter may be u~ed In-lin- filt-r 312 1~ preferably con~tructed of expanded PTFE wlth a 1 micron pore ~lze The fllt-r pr-v-nt~ for-ign material from entQring tbe ga~ pathway Th- h~l~ racetrack-shaped of gas pathway 298 acco~modat-- tb- u~e o~ chopper wh~-l 280 for ~iqnal chopp$ng If oth-r cbopplng m-thod~ ar-used, ga~ pathway 298 may hav- oth-r ~hape~
Figur- 3C d-pict~ th- C02 and N20 d-tec-tion chann-l a~sembll-~ in the optical bench Th-refQrenc- numb-r~ ln F~gur- 3C a~o for th~ C02 det-ction ch-nn-l a~mbly Th~ C02 and N20 det-c-tlon ehannel a~-mblie~ ~r- ~u~tantially identical -25- 13 2 ~ 3 3 3 Hence, in the description of Figure 3C, the N20 detection assembly component reference numbers fol-low in parentheses those for the C02 detection assembly where appropriate.
IR source 326 (328) is fixed within opening 325 (327) of lamp block 324. Disposed adjacent to the lamp block is block 294. Block 294 has opening 299 (301) into which sapphire window 295 (297) is fixed and opening 343 ~not shown for N20) into which sapphire window 342 (344) is fixed. The sapphire windows form part of the walls of C02 reference cell 296 (300) and sample gas pathway 298.
Disposed adjacent to block 294 is source aperture 282. Source aperture 282 has opening 283 (285) aligned with the C02 reference optical patn and opening 284 (286) aligned with the C02 gas optical path.
Spaced away from the source aperture i9 detector aperture 270. The detector aperture has opening 272 (274) aligned with the C02 reference optical path and opening 273 (275) aligned with the C2 gas optical path.
Disposed between source aperture 282 and detector aperture 270 is chopper wheel 280. Chopper wheel rotates in a plane between the source and detector apertures. Opening 281 in chopper wheel 280 i~ shown aligned with the C02 gas optical path.
Chopper wheel 280 also has openinqs that align with the C02 reference optical path which will be described subseguently.
Filter block 264 i8 disposed ad~acent an opposite ~ide of detector aperture 270. Optical filter 266 (268) is fixed within opening 265 (267) of the filter block. Optical filter 266 (268) i~ in the C02 refcrence optical path and the C02 ga optical path.

~32~

Detector board 252 i8 disposed adjacent filter block 264. C02 detector 262 (258) is fixed to the detector board. Detector 262 (258) is in the C2 reference optical path and the C02 gas optical path.
Preferably, the optical path lengths of gas pathway 298, Co2 reference cell 296, and N20 reference cell 300, as part of the Co2 and ~2 gas optical paths and the C02 and N20 reference optical paths, respectively, are 0.1 inches.
Figure 4A shows the pneumatic system which includes pump module 112 and certain components and inter-connected tubing in the patient module 109.
The pneumatic system's purpose is to draw a respira-tory gas stream through the gas pathway at the pre~ferred rate of 50 cc/min., backflush the system with filtered room air at a 10w rate of approximately 300 cc/min., draw scrubbed room air at a-50 cc/min.
flow rate through the gas pathway for making zero gas measurements, and provide means for determining whether or not the gas pathway is fluid-tight.
The main components of pump module 112 includes flow sensor 3S6, sample pump 358, external valve 1, 424, external valve 2, 436, backflush pump 394, C02 scrubber 410, and diagnostic valve 412.
~he main components of the pneumatic system in patient module 109 are pressure sensor 374, zero valve 376, and back1ush valve 382.
~n normal operation, sample pump 358 is used to draw the respiratory gas stream through the patient module 90 that optical bench 111 can make mea~urements of the partial pressures of C02 and N20 in the re~piratory qas stream. SAMPLE PUMP~
line 360 and SAMPLE PUMP- line 362 are the power lines for sample pump 358. Thc voltaqe across these lines control the speed of thi~ pump. Preferably, the pump will run at ~ speed ~ufficient to maintain 132~

a 50 cc/min. respiratory gas flow rate through the gas pathway comprising sample tube 174, patient module sample gas pathway 372, optical bench gas pathway 298 (Figure 3~, and pump module sample gas S pathway 368. When this is the case, sample pump 358 is activated and a respiratory gas stream is drawn through airway adapter 106 and into sample tube 174.
The gas then passes through filter 384 in connector 352 and through filter 386 across the inlet of the patient module sample gas pathway.
The respiratory gaQ stream proceeds through zero valve.376, which is configured for receiving the flow from sample tube 174. As it moves along the patient module sample gas pathway, it passes through optical inlet filter 312 and enters the optical bench gas pathway 298 (Figure 3) where mea~
surements o the partial pressure~ of the gases of interest are made.
The respiratory gas stream leaves the optical bench and pa~ses through pressure sensor 374.
Pressure sensor 374 measures the pressure of the gas stream in the optical bench. The respiratory gas then flows through the remainder o patient module sample ga~ pathway 372 and enter~ pump module 112 through connector 370.
Once inside the pump module, the gas stream enters pump module sample gas pathway 368. First the gaJ stream passe~ through external valve 1, 424, and external valvo 2, 436, conigured or flow along pump module gas pathway 368 without redirection.
After this, it passes through flow sensor 356 and sampl- pump 358. After leaving sampl- pump 358, the gas ~tream pas~es through connoctor 366 and enter~
a tube whlch carries the gas stream to a qcavensins sy tem.
When it i8 desired to make a zero ~as read-ing, the direction o ~luid flow through the zero ., . . ` .

-28- 13~ ~3~ ~
valve is changed. During the time when zero gas readings are being made, barometric pressure readings are also made. The barometric pressure value $s stored for use later in calculating ~he partial pressures on the gases of interest. Barsmetric pres-sure measurements are made with pressure sensor 374.
ZER0+ line 378 and ZERo- line 380 power zero valve 376. The voltage across these lines deter-mines whether the zero value is configured to provide scrubbed room air from patient module zero gas path-way 404 or the respiratory gas stream from sample tube 174. Accordingly, the proper voltage is placed acros~ ZER0+ line 378 and ZER0- line 380 to cause zero valve to close off gas flow from sample tube 174 ~S and open to the air flow in patient module zerc gas pathway 404. Preferably, sample pump is powered to draw 50 cc/min. of scrubbed room air through the pneumatic sys~em.
When zero valve 376 i8 so aligned, sample pump 358 is properly activated and draws the scrubbed room air through the patient and pump modules' sample gas pathways. During this time, zero gas readings are made. The purpose of making zero gas readings is to clear the analyzer electronics 80 subsequent gas reading~ will be accurate.
When zero gas readings are being made, room air i~ draw through filter 414 and two-way diagnostic valve 412. The use of diagnostic valve 412 will bo described subseguently. After diagnostic valve 412, the room air enters C02 ~crubbor 410. The C02 scrubber prevents, for example, exhaled C02 from a sy~tem operator from entering the pneumatic system during zero ga~ readings.
Following the C02 scrubbing, the room air enters pump module zero gas pathway 408, goe~ through connector 406 and enter~ patient module zero ga3 pathway 404. After passing through zero valve 376, -2g- ~ ~ 2 ~
the scrubbed room air enters optical bench lll where zero gas readings are made Following this, the scrubbed room air goes through the remaining portion~
of the sample gas pathway in the patient and pump modules and enters the scavenginq system During, or subsequent to, zero gas read-ings, or when it is determined that the patient adapter filter is clogged, a backflush ic performed To accomplish a backflush, first, zero valve 376 i8 configured to close off the sample gas 10w from sample tube 174, and second, backflush valve 382 must be opened BAC~FLUSH+ line 420 and BAC~USH-line 422 are the power lines or backflush valve 382 Accordingly, the appropriate voltage is applied across the power lines to open it Now, backflush pump 394 must be activated The backflush pump 394 is activated by the voltage across BACKFLUSH PUM~+ line 396 and BACRFLUSH PUMP-line 398 Once backflu~h pump 394 is properly powered, room air i~ drawn through filter 402 and enters pump module backflush pathway 392 The room air next passes through pump 394 After passing through the backflush pump, the room air goes through remainder o pump module backflush pathway 392 and connector 390, and entors patient module backflush pathway 388 Once the room air ha~ pa~sed through backflush valve 382, it then enterQ the backflush tube 172 enroute airway adapter 106 Tho filtered room air enters airway adaptor 106 and clears the filter Two-way diagno~tic valv- 412 togethor with tho zero valve, sampla pump and pre~sure sen~or is usod to d-termine if the pnoumatic Jystom tubing or components aro fluid-tight When it i8 desired to check the fluid-tight intogrity, two-way diagnostic valve 412 i~ configurod to close of room air from entering the ystom Two-way diagnostic valve 412 i8 powerod by the voltage acro~ DIAG~ line 416 and : - ~

DIAG- line 418. After properly powering the valve, the system is set-up as if zero gas readings were to be made. The sample pump is activated to draw a vacuum in the sample and zero gas pathways of the S patient and pump modules. Once a predetermined pressure is reached, the sample pump is deactivated.
The pressure readings are monitored to see if there is a pressure change over time which would indicate that there are leaks in the system.
The partial pressures of other gases of interest in the respiratory gas stream are also measured. This is accomplished by external module 430. The pneumatic system of the present invention is such that the respiratory gas stream and the zero gas stream can be routed through external module 430.
External valve 1, 424, and external valve 2, 436, are disposed along pump module sample gas pathway 368 between connector 370 and flow sensor 356. Both valves are two-way valves.
EXT l+ line 432 and EXT 1- line 434 are ; the power lines for external valve 1. EXT 2+ line 442 and EXT 2- line 444 are the power lines for the external valve 2. The voltages across these pair~ determine whether the ~ample respiratory gas stream or zero gas stream are directed through pump module sample gas pathway 368 without redirection through external module 430.
When it is de~ired to route the respiratory gas stream or zero gas stream through external module 430, the proper voltage is placed acros~ EXT l+ line 432 and EXT 1- line 434, and placed acro~s EXT 2+, line 442 and EXT 2- line 444 to configure external valve 1 and external valve 2 for thi~ purpose. When these valveJ have this configuration, external value 1 clo~e~ off the direction o ga3 flow through pump module gas pathway 368 toward external valve 2, and open~ toward external-in ga pathway 425; and 132~

external valve 2 closes off pump module gas pathway 368 in the direction of external valve 1 and opens toward external-out gas pathway 437.
Once ex~ernal valve 1 and external valve 2 S are powered to the above configuration, the re~pira-tory gas stream or zero gas stream passes through external valve l and enters external-in gas path-way 425 in the pump module. The gas stream then passes through connector 426 and enters external module-in ~as pathway 428. The gas stream upon leaving this gas pathway enters the external module 430's internal gas pathway. Measurements of the partial pressures of other gases o interest are made as the gas stream transits the external module's internal gas pathway.
When the gas stream exits the external module, it enterQ external module-out gas pathway 440.
The gas stream then passes throu~h connector ~38 and enters external-out gas pathway 437 in pump module 112.
The gas stream then enter~ external valve 2 where it is routed to pump module sample gas pathway 368.
Flow sensor 356 measures the flow rate of the sample respiratory gas stream or zero gas stream that passes through patient module 109. Flow sensor 356 i~ a dierential pressure transducer. This transducer is commercially availablo from IC Sensors, Inc., Sunnyvale, Cali~ornia. For a 50 cc/min. flow rate, restriction in pump module gas pathway 368 that precede~ flow sensor 356 produc-s a pressure drop of approximately 0.5 p~i. Tho reference side of the pre~ur- transducer connect~ to one side of tho re~triction and tho mea~urement side connects th- othor. A change in tho flow rate cause~ a change in th- pres~ure drop which iJ measured by the transducer. Such changes generate representative voltages which aro output as the FLOW PRS qignal on ~2~

line 391. The FLOW PRS RTN signal on line 3~3 i~
tied to ground.
Within flow sensor 356, prior to output therefrom, the detected voltage is input to a fixed gain differential amplifier circuit. This amplifier circuit includes a poten~iometer which is set to correct for span factor. The amplified and span factor corrected voltage representation to flow rate is output on line 391 as the FLOW PRS signal. The FLOW PRS signal and the FLOW PRS RTN signal (groundj are input to the analog processing circuits 124 for further pr.ocessing as will be described.
Eigure 4B shows the powering circuits for backflush pump 394, diagnostic valve 412, external valve 1, 424, and external valve 2, 436. The cir-cuit for powering sample pump 358 is in the analog processing circuitry and will be discussed subse-quently.
The circuits for powering the backflush pump, the diagnostic valve, the external valve 1, and the external valve 2 are subtantially the same.
Therefore, the generation of the powering voltageQ
for the backflush pump will be described and the signal name~ and reference numbers for the other three will follow in parenthe~eY in the following ord-r: tho diagnostic valve, the external valve 1, and external valve 2.
Tho BAC~FLUSH (DIAGNOSTIC, EXTERNAL
VALVE 1, and EXTERNAL VALVE 2) signal on lin- 417 (411, 431, 441) is input to the baso of transi~tor 413 ~415, 433, 443). The BACKFLUSH ~DIAGNOSTIC, EXTE~NAL VALVE 1, and EXTERNAL VALVE 2) signal voltaga dot~rmines whethar tho BAC~FLUSH PUMP-(DIAG-, EXT 1-, and EXT 2-) signal is grounded to e~tablish a voltage difference betwaen tho BACKF~USH
PUMP~ ~DIAG~, EXT 1~, and EXT 2~) and the BACKFLUSH
PUMP- ~DIAG-, EXT 1-, and EXT 2-) signals. Diode -33_ 1 3 2 ~
423 (419, 435, 445) protects the transistor when it is turned off.
Figure 5A is a schematic diagram of the circuitry and selected components of optical bench S 109. Figure 5A shows cross-section views of sample gas pathway 298, C02 reference cell 296, and N20 reference cell 300. It is understood that the sample gas flow enters gas pathway 298 at the C02 detection channel assembly and exits at the N20 detection channel assembly. Accordingly, the gas stream irst travels past tne C02 detection channel assembly comprising infrared liqht source 326, sap-phire windows 342 and 295, source aperture 282, detector aperture 270, optical filter 266 and lead selenide detector 262. Next it passes the N20 detec-tion channel assembly comprising infrared light source - 328, sapphire windows 344 and 297, source aperture 282, detector aperature 270, optical filter 268, and lead selenide detector detector 258. Chopper wheel 280, common to both detection channel assemblies, has openings for simultaneous detection of the C02 and N20 gas signals, simultaneouQ detection of the C2 and N20 reference optical path signals and simul-taneous detection of a dark period for the C02 and N20 channe1s.
Broad band optical energy from each in~rared source is passed through the ga~ ~tream. The optical filters only pass a narrow infrared band a~sociated with the absorption characteristic~ of the specific gas of intere~t when the choppor wheel has its open-ings aligned with the gas optical path and reference optical path of each detection channel assembly.
The energy streams exlting tho respective filter~
issue on the associated detector. A representation three-~tep waveform output from a detection channel aS5embly i8 shown at 466 in Figure 6C. The dark signal i~ ~hown at 468, the reference signal is -, . . . . .

1 ~ 2 ~ !~ 3 ~3 shown at 470, and the gas signal is shown at 472.
The amplitude of the gas and reference signals are indicative of the amount of energy within the filter' 3 ~and transmitted through the gas stream in the gas pathway and the reference cell.
The output signal from C02 detector 262 on line 520 is input to low noise preamp 522. The out-put of low noise preamp 522 is input to amplifier 524.
The output of amplifier 524 is the C02/Co2 REF signal on line 526 which input to the analog input circuitry.
The output signal from N20 detector 258 on line 540 is input to low noise preamp 542. The output of low noise preamp 542 is input to amplifier 546.
The GUtpUt of amplifier 546 is the N20/N20 REF signal on line 548 which is input to the analog input circuitry.
Also generated are the POSITION TRAC~ and TIMING ~RACK signals which are uced for determining the occurrence of certain events during a timing cycle and providing the basic timing cycle based on one revolution of chopper wheel 280.
The position track optical path comprises LED 332, source aperture 282, detector aperture 270, and photodiode 256. Tho.timing track optical path compri~e~ LED 330, source aperture 282, detector aperture 270, and photodiode 254. The position track path i~ chopped by the gas signal openings in chopper wheel 280. The timing track optical path is chopped by the 90 timing track openings in chopper wheel 280.
The chopped infrared energy from LEDs 332 and 330 is~ue on position track photodiode 256 and timing track photodiode 254, re~pectively. The output of position track photodiode 256 on line 528 i~ input to amplifier 530. The output of amplifier 530 i8 tho POSITION TRAC~ signal on line 532. The output of timing track photodiode 254 on line 534 i~ input to amplifier 536. The output of amplifier 536 i~

1 3 2 ~

th- TIMING T~AC~ signal on line 538 A repr-sentative POS~TION TRAC~ ~ignal is shown at 460 in Figure 6C
and a representative TIM~NG TRACR ~ignal ls shown t 46~ in Figure 6C The POSITION TRACK nd TIMING
S TRACX ~ignal~ are input to the analoy input circultry or the generation of the GAS GATING, REF GATING, and DEMOD SYNC ~ignal~ for demodulating and proces~ng of the C02/C02 REF and N20/N20 REF signals Reerring to Figures 6A and 6B, a top view of chopper wheel 280 is shown In Figure 6A th- top of the chopper wheel is shown alon- and in Figure 6B
it is shown in relation tc certain other component~
of the optical bench From the center of chopper wheel 280 out-ward, the first chopping means i~ timing track 452Timinq track 452 is in the optical path comprising of LED 330, source apertur- 282, detector apcrtur-270 and photodiode 254 As ~tated, the output of the timing trac~ optical path i8 shown at 464 of Figure 6C The series of opening repre~enting the timing track total 90, thereby giving a timing track cycle count of 90 The next chopping m~ans are on the g-~channel opening~ at 281 There are three gas chan-nel openinqs ach of whieh ~ubtend~ 40 and they are space-120 apart Th- opening~ are ~ituated such that thor~ imultaneous det-ction of the partial pre~sures for C02 and N20 as ~hown ln Fisuro 6B
Rad$ally outward from th~ ga~ chann-l chopping m-an~, th- chopper wheel ha~ three op-nings at 450 for chopping th- C02 and N20 refer-nc- optical paths Each r-forenc- chann~l opening subtend~ 40 and th-y are ~pac-d 120 apart The opcning~ ar~
situated uch that ther- is simultaneous detection of the C02 and N20 ref~rence optic-l p-th~

-36- 1 3 ~
In the rotation of the chopper wheel 280, there is 40 portion that precedes each reference opening and follows each gas channel opening. During this period, referred to as the "dark" period, a signal is detected whereby no infrared light issues on the C02 or N20 detector. This is the base line signal from which the gas channel and reference channel signals are measured. This signal is removed from the gas channel and reference channel signals during signal processing resulting in the detected signals which are due only to the partial pressures f C2 and N20 in respiratory ~as stream and the C2 and N20 reference optical paths.
Each timing cycle, or single rotation, of chopper wheel 280 has three detection subcycles com-prising dark detection period, reference detection period, and qas detection period. A representative repeating three-stepped waveform pattern is shown at 466 in Figure 6C.
The position track optical path comprises LED 332, source aperature 282, detector aperture 270 with single slit 277 and photodiode 256. The gas channel openings are used to chop the position track optical path. The resultant signal is the square wave signal shown at 460 in Figure 6C. The POSITION
TRACK signal, as will be de~cribed, i-~ used to mark gas channel detection events.
Th- TIMING TRACK and POSITION TRACK signals in conjunction with PROM 656 (Figura 7A) are used to generate the GAS GATING, REF GATING and DEMOD SYNC
signal waveform~ ~hown in Figure 6C at 500, 488, and 476, rospectively. The~a signals will be usod to obtain use~ul information with re~pect to the detected C2 partial pre~sure and the N20 partial pressure, and the reference optlcal path signal associated with each.

132 i~ ~3~ ?i At this point the only ~ignal~ d$scu~ed which are ready ~or output from the optical bench arc the detected C02/C02 REF signal N20/N20 REF
signal the TIMING TRACK ~ignal and the POSITION
TRACK signal The remainder of the slgnal~ output from the optical bench circuitry are the ~ignals output from multiplexer 558 and the powering voltaqes for the backflush valve and the zero valve The multiplexer and it5 associated ~ignal~ will be dis-cussed then the generatio~ of the powering voltag~s will be discussed The first input to multiplexer 558 i~ the output of EEPROM 580 EEPROM 580 stores coefficient~
relating to characterization of the optical bench The characterization coeficient~ do not adju~t or change thc oporat$on o any component of th- optical bench or the apparatu~ a~ a whole Thes~
coeficient~ correct the bench $ mea~urement~ for ~ystem component deviation from ide-l The inputs to EEPROM 580 are the data bu~
Dl ~ignal on line 574 the SK (serial data clock) signal on line 576 and th- ~S (chip ~elect) ~$gnal on line 578 The CS and SK ~ignal control the EEPROM'~ output Th- Dl ~$gnal is the dat~ input to th~ EEPROM ~he~e thre- signals are output from quad fl$p flop 572 Th- dat~ input~ to quad flip ~lop 572 ar~ optical bench d~ta bus ~ignal~ D9-D2 on l$nc~ 567 568 and 570 respect$vely The DO-D2 ~ignal~ aro thre~ of th- four output~ of line dr$vcr 560 who~o $nput- ar~ the 4 b~t parall-l PREDO-PRED3 $gnal~ on l$ne- 561 562 564 ~nd 566 Th-~e ~$gnals ar- rom th~ an~log $nput clrcu$try Qu~d flip flop 572 1~ clocked by th~ output of decoder 598 on line 600 The $nput~ to d~cod-r 598 ar- th- BUS STROBE ~$gnal on l$ne 592 the Al ~lynal on l$ne 594 and the A2 ~ignal on lin~ 596 Th~e ignal- ar- output rom l$ne driver 584 T~e input~

~ .

-38- ~ 32~ ~8 to line driver 584 are the PRESTB signal on line 586, the PREAl signal on line 588, and the PREA2 signal on line 590. These signals are received from the analog input circuitry. Decoder 598 is enabled by the BUS STROBE signal and the output depends on the logic ætates of the ~1 and A2 signals. When properly instructed, the EEPROM outputs the characterization coefficients to multiplexer 558.
The second input to multiplexer 558 is the OB TEMP (optical bench temperature) signal on line 556. The bench temperature is sensed by tempera-ture sensing and control circuit 554. The sensed temperature (in volts) on line 555 is input to difer-ential receiver 557. The second input to differential receiver 557 on line 553 is tied to ground. The output of differential receiver 557 is input to multi-plexer 558. Unlike many prior art optical benches which actively control optical bench temperature for accurate readings, the optical bench of the present inventions does not control the optical bench tempera-ture.
The third input to multiplexer 558 i~ the signal represententive of the pressure in ga~ pathway 298 ~ensed by pressure sensor 374. The sensed signal is amplified by amplifier 551 and the amplified pres-sure signal on lino 552 i-~ input to multiplexer 558.
Pressure ~ensor 374 i8 an ab~olute pressure measuring type pressur- sensor. The pres~ure sensor i8 commercially available from IC Sensor~, Inc., Sunnyvale, California.
The pre~ure is continuously monitored during sy~tem operation. Rapid pressure change~ may indicata various problems in the optlcal bench. The pr-ssure within the opticsl bench mu~t be considered in calculating gas partial pr-ssur-s for display, as more fully discussed.

- -.
.

132~

The pressure sensor also measures barometric pressure at system start up. This value is stored in memory for later use. The stored value for baro-metric pressure is updated during every zero gas reading.
The fourth input to multiplexer 558 i 8 the output of voltage reference 614. The input to volt-age reference 614 is a ~lOv signal. Its output is the +5V R~F signal on line 615 which is input to multiplexer 558.
The DO-D3 signals of the optical bench data bus output from line driver 560 are input to quad. flip flop 606. This flip flop is clocked by the output of decoder 598 on line 602. When clocked, quad. flip flop 6n6 provides a parallel 3-bit signal on lines 608, 610, and 612 which is input to the control inputs to multiplexer 558. 8ased on the logic states of this 3-bit signal, a multiplexed signal i5 output from multiplexer 558 on line 559.
The multiplexed signal on line 559 is processed by buffer amplifier 616 and output therefrom as the AMUX OUTPUT signal on 618. The AMUX OUTPUT signal is then sent to the analog input circuitry for further processing. Also output from multiplexer 558 and sent to the analog input circuitry i9 the AMUX RTN signal on line 620. This signal is tied to ground.
The D3-D3 siqnals on line 566, 568, 570, and 572 are input to quad. 1ip flip 585. This 1ip flop i8 clocked by the output of demultiplexer 598 on line 604. The outputs of guad. 1ip flop 585 are the BACKFLUSH VALVE DRIVE signal on line 628, the ZERO VALVE INITIAL signal on line 636, and the ZERO
VALVE HOLD signal on line 632. These siqnals con-trol poworing the backflush and zero valves.
Figuros SB shows the circuits for powering backflush valve 382 and zero valve 376 shown in _40_ 1 32~
Figure 4A. The BAC~FLUSH VALVE DRIVE signal is input to the base of transistor 624. The BAC~FLUSH VALVE
DRIVE signal voltage determines whether the BACKFLUSH-signal on line 422 is grounded to establish a voltage difference between the ~AC~FLUSH+ signal on line 420 and the BAC~FLUSH- signal on line 422. Diode 626 protects transistor 624 when it is turned off.
The circuit for powering zero valve 376 is for powering the zero valve initially, which requires a greater voltage, and for holding the valve in the changed position after initially powering it, which requires less voltage. The ZERO VALVE INITIAL
signal on line 636 is input to the base of tran-sistor 634. The ZERO VALVE INITIAL signal voltage determines whether the ZERo- signal on line 380 is grounded to establish a voltage difference between the ZERO~ signal on line 378 and the ZERO- signal on line 380. Diode 638 protects the transistor when it is turned of.
After initially powering zero voltage 376, the zero voltage is held in position by the following:
The ZERO VALVE HOLD cignal on line 632 is input to the base of transistor 630. The ZERO VALVE HOLD
signal voltage determines whether or not the ZERO-slgnal on line 380 is grounded to establish a voltage difference between the ZERO~ signal on line 378 and the ZERO- signal on line 380. There is a voltage drop across resistor 631 thereby reducing the voltage difference between the ZERO~ llne and the ZERO- line from what it would be normally without the resistor.
Similarly, diode 638 protects the transistor when it is turnod off.
Figures 7A-7D are schematic diagrams of analog input circuitry 122 (Figure 1). The inputs to thi~ circuitry are primarily the analog outputs from optical bench 111 and signals from analog proce~sing circuitry 124.

~ 3 ~ 8 Referring to Figure 7A, the temperature of the analog circuitry is de~ermined by REF-02, 690.
The output of REF-02 i3 amplified by amplifier 694 and output therefrom as the VT (Box temperature) signal on line 696. Also output from REF-02 i8 the VOFF signal on line 692. This signal is used for insuring that the outputs associated with the gated gas and reference signals are at least zero. REF-02 is commercially available from Precision Monolithics, Inc., Santa Clara, California.
The generation of the gating signals and demodulation signals for use in obtaining useful information rom the detected gas and reference signals, will be discussed. The TIMING TRACK signal lS on line 538 is the first inPut to differential receiver 640. The second input is the GAS RTN signal on line 668. This signal i8 tied to ground. The output of differential receiver 640 is input to pulse shaping circuit 642 which processes the incoming signal so that clean sguare waves are produced at its output. The output of pulse shaping circuit 640 on line 644 i~ input to the clock inputs of 4-bit counters 646 and 660, flip flop3 672 and 676, and input to the clock input to octal flip flop 658.
The POSITION TRACK signal on line 532 is input to differential receiver 666. The second input i8 the GAS RTN signal on line 668. The output of differential receiver 666 is input to pulse ~haping circuit 669, which like pulqe shaping circuit 642, processe~ the incoming signal -~o that clean square wave~ are producod at its output. The output o pulse ~haping circuit 669 is input to the data input of flip flop 672.
The negative-trua Q bar output of flip flop 672 on line 674 i8 input to the data input of flip flop 676 and 1~ al80 input as the fir~t input to NAND gate 678. Tho nogative-true Q bar output of 1 3 2 ~ .J

flip flop 676 is the second input to NAND gate 678.
The output of NAND gate 678 on line 680 i 8 input to the "clear" inputs of counters 646 and 660. ~The "bar" designation after a signal or input name indicates the inverted state of the signal or input without the bar designation, as is known by those skilled in the art).
Flip flops 672 and 676 are clocked by the processed TIMING TRACK signal. Accordingly, this serves to synchronize the POSITION TRACK signal with the TIMING TRACK signal.
The two flip flops and NAND gate cause clearing of the counters during the period from one TIMING TRACK signal after the beginning of the posi-tion track pulse to one TIMING TRACK signal afterthe end of a position track pulse. Therefore, the counters will count from the end of the position track pulse to the beginning of the next. Since the carryout output of counter i8 input to the enable inputs to counter 660, there is a continuous count until the counters are cleared.
Outputs of counter 646 on lines 648, 650, 652 and 654, and the outputs of counter 660 on lines 662 and 664, are input to PROM 656. PROM 656 is programmod for the waveform patterns for the GAS
GATING, REF GATING, and DEMOD SYNC signals. There-fore, ba~ed on the logic values of tho cignals output from tho counters, PROM 656 providos outputs to octal flip flop 658 that will produce the programmed wave-form pattern~ for these ~ignals. Accordingly, whenoctal flip flop 658 is clocked ~y the processed TIMING TRAC~ ~ignal, its outputs are the GAS GATING
signal on line 684, whose representative wavoform is shown at 500 ln Figur- 6C; the REF GATING signal on line 686, whose representative waveform is ~hown at 488 in Figure 6C; and the DEMOD SYNC signal on ~~3~ 1 3 ~ (3 line 688, whose representative waveform is shown at 476 in Figure 6C.
The FLOW PRS signal on line 391 i8 input to the diferential receiver 702. The second input to the differential receiver is the FLOW PRS RTN
signal on line 393. These signals are from flow sensor 356 in pump module 112. The output of differ-ential receiver 702 is the FLOW PRS SIC signal on line 704.
The circuit in Figure 7A comprising high pass filters 708, peak detector 710, comparator 715, ; level buffer 716, and flip flop 718 is for detecting if the patient module has impacted something with such severity that the apparatus may need to perform a zero gas reading to continue to make accurate measurements.
The BUFFERED C02 signal on line 706 i8 input to high pass ilters 708. The output of the high pass filters is input to peak detector 710.
The peak detector provides outputs on lines 712 and 714 which are input to comparator 715. The output of comparator 715 is processed by the level buffer 716 and input to the clock input of flip flop 718. The Q output of flip flop 718 is the IMPACT signal on line 722.
When the system is turned on, the IMPACT
RESET bar ~ignal on line 720 has a logic "O" value to reset the flip flop 718. Accordingly, the Q output of the flip flop, which i~ tho IMPACT signal, ha~ in logic "O" value. The signal input to the data input of flip flop 718 is the ~5v signal which, therefore, place~ a logic "1" value at the data input.
In operation, the BUFEERED C02 signal i~
first paQsed through the high pas~ filters. In the peak detector, the signal i5 divided down and the outputs of the peak detector 'chat are input to the comparator are the basic ~ignal and the divided down _44_ ~32~
signal. The output of the co~parator is a relatively steady state signal which is input to the clock input to the 1ip flop after level buffering.
When the apparatus suffers an impact of sufficient severity, there i8 a rapid change in the high frequency component. This will cause the com-parator to provide an output which will clock 1ip flop 718. When the flip flop i~ clocked, the logic "1" value at its data input i~ output from the Q
output as the IMPACT signal indicating that the apparatus has impacted something with suficient severity that the apparatus may need to do a zero gas reading. When the IMPACT signal has a logic "1"
value, it ultimately will cause an alarm to indicate this condition.
In the circuit in Figure 7B, the CO2/CO2 REF signal on line 526 and the N20/N20 REF signal on line 548 are similarily demodulated, have the dark period signals removed thereform each, and have each signal separated into the gas signal and the reerence 3ignal beore input to multiplexer 838 (Figure 7C). Accordingly, the C02/CO2 REF channel path will bo described and the signal names and reerence numbers for the N20/N20 REF channel path will follow in parenthese~.
The CO2/C02 REF (N20/N20 REF) signal on lino 526 (548) i9 input to differential receiver 738 (750). Tho ~econd input to di~ferential receiver 738 (750) i~ the GAS RTN signal on line 668. The GAS RTN ~ignal iJ tiod to ground. The output of differontial receiver 738 (750) i~ input to electronic ~witch 740 (752). The control input to olectronic ~witch 740 ~752) i~ tho C02 CAL (N20 CAL) ~ignal on line 726 (734). The C02 CAL (N20 CAL) sisnal will hav- th- proper logic state to open the ~witch whon it i~ desirad to determino tho ~y~tem'~ offset -1~2~

voltage as will be descri~ed ~ubsequently otherwi-e the switch is closed The output of electronic witch 740 ~752) is input to variable gain amplifier 744 (756) The control inputs to variable gain amplifier 744 (756) are the DACEN A ~ar (3ACEN ~ bar) signal on line 728 (736) the A~WR bar signal on line 730 and the parallel 8-bit data bu6 signals AIDO-7 on line 732 The DACEN A bar (DACEN B bar) ign-l 18 input to the CE
bar input the AIWR ~ar ~ignal i~ input to the WR
bar input and the AID~-7 i~ inp~t to tne parallel 8-bit input of the amplifier Accordingly when the AIDO-7 signals are written $nto the amplifier le will have a gain from O to 64 ba~ed on these values The output of vari~ble gain amplifier 744 (756) is input to synchronou~ rectifler 748 (758) ~in~ 706 connects to the output of variable gain amplifier 744 L$ne 706 contain~ th~ BUFFERED C02 signal that is input to the impact circuit in Figure 7A
Synchronou~ rectiier 748 (758) demodul-teQ
the C02/C02 REF (N20/N20 REF) signal by removing tho dark period ~ignal from tho gas and referenc- ~gnals The demodulating ~ignal input to ~ynchronou~ recti-fier 748 ~758) i~ the DEMOD SYNC ~gnal on line 6B8 The DEMOD SYNC ~lgnal wav-form i- hown at 476 of Figure 6C A~ can be ~een ln Figur- 6C the DEMOD
SYNC ~lgn~l has a ~1 valu- during the reerence and ga~ perlods and -1 valuo during th- dark period Accordlngly th- dark period signal 1~ lnv-rted whil-r-fer-nc- and ja~ per~od $gnal~ v~lue- ~r- not Th~ 8 r-~ult~ in the demodulated ignal hown at 480 ln Eigur- 6C wher- th- lnvert-d dark perlod ~lgn~l i- shown at 482 nd th- non-invert~d referenc~ and 3S ga~ ~ignal~ ar~ shown ~t 484 and 486 respectlvely Th- demodulat-d C02/C02 REE (N20/N20 REF) slgnal output from synchronou~ rect~fler 748 (75B) 1 3 2 ~

on line 760 (761) is input to double switches 762 and 774 (788 and 802). As is shown for each, the switches are oppositely disposed: in double switch 762 (788), switch 770 (790) is open and switch 772 (792) is closed; and in double switch 774 (802), switch 776 (804) is open and switch 778 (806) is closed. When the value input to the control inputs o double switches 762 and 774 (780 and 802) changes, then switches pairs will be change their respective - 10 open or closed conditions.
The control input to double switch 762 (788) is the GAS GATING signal on line 684 and the control input to double switch 774 (802) is the REF
GATING signal on line 686. The GAS GATING signal controls the disposition of switches 770 (790) and 772 (792) according to the waveform shown at 500 in Figure 6C, and the REF GATING signal controls the disposition of switches 776 (804) and 778 (806) according to the waveform shown at 488 in Figure 6C.
The signal output from double switch 762 (788) is input to low pass filters 764 (796). The signal i5 output from the low pass ilters and input to low pass filter 766 (798). The second input to low pass filter 766 (798) i8 the BUFFERED VOFF signal on line 818. The 8UEFERED VOFF signal is input to low pass filters 766 (798) to in~ure that output is never le~s than zero.
The signal output from double switch 774 (802? is input to low pass filters 782 (810). The signal i~ output from the low pa~s filter~ and input to low pass filter 784 (812). Tho second input to low pa~s filter 784 (812) is the BUFFERED VOFF ~ignal on line 818. Thi~ signal insuros that the output of low pass filt-r 784 (812) is never les~ than zero.
After gating, the C02(N20) signal has a waveform substantially as shown at 506 of F~gure 6C, with the pulse at 508 being attributed to the dark 132~$~

period and the pulse at 510 being attributed to the partial pressure of C02 in the gas pathway. Simi-larly, after gating the C02 REF (N20 REF) signal has a waveform substantially as shown at 494 in Figure 6C, with the pulse at ~96 being attributed to the dark period and the pulse at 498 being attributed to the reference optical path. After filtering, the waveform outputs for C02 on line 768 and N20 on line 800 are changing waveforms corresponding to the detected value for each gas. The C02 reference signal on line 786 and N20 reference signal on line 814 are the current values for each reference optical path.
The inputs and outputs to interface 820 will now be discussed. The inputs to interface 820 are the MISC SEL bar signal on line 822, the AIRD
bar signal on line 824, the AIWR bar signal on line 730, the IORESET signal on line 826, the analog input circuitry address bus signals ArAl-2 on line 828, and the analog input circuitry data bus signals AIDO-7 on line 732.
The MISC SEL bar signal is input to the chip select input of interface 820. The AIRD bar and AIWR bar signal~ are input to the RD and WR
inputs respectively to interface 8ZO. The IORESET
signal is input to the reset input to interface 820.
The AIAl-2 ~ignal and the AIDa-7 signal aro input respectively to addres~ bus input~ and the data bu~
inputs .
The outputs of interface 820 are the 4-bit parallel PAO-3 ~ignal on line 830, the parallel 4-bit parallel ASO-3 signal on line 832, the C02 CAL ~ignal on line 726, the N20 CAL signal on line 734 and the IMPACT ~ESET bar signal on line 720, and the IMPACT
signal i~ input on line 722.
The PAO-3 signal on line 830 is input to the control inputs to analog switch 926 (Eigure 7D~.

~ 3 2 ~

The ASO-3 signal on line 832 is input to the control inputs to ~ultiplexer 838 (Figure 7C). The C02 CAL
and N20 CAL signals are input to ele~tronic ~witches 740 and 752, respectively, for use in determining the offset voltages for the C02 and N20 gas channel~
and the C02 REF and N20 REF channels (Figure 7B).
The IMPACT RESET bar and IMPACT signals are for use in the impact detection circuit (Figure 7A).
Referring to Figure 7C, placement of the certain analog signals on the analog input circuitry data bus will be described.
The inputs to multiplexier 838 are the AMUX signal on line 840, the 3ATT SEN signal on line 842 (from power supply circuitry 158, Figure 1), the C02 signal on line 768, the N20 signal on line ~00, the FLOW PRS SIG signal on line 704, the C02 REF
signal on line 786, the N20 REF signal on line 814, the VT signal on line 696, the V MOT DRV signal on line 844, the VOBspEED signal on line 846, the V
signal on line 692, and the MOT CURR SEN signal on line 848. (Certain of these signals have been described while others have not; those that have not will be described subseguently).
The AMUX OUTPUT signal on line 618 and the AMUX RTN signal on line 620, both o which are output from multiplexer 558 (Figure 5A), are input to differ-ential receiver 887. The output of diferential roceiver 887 on line 840 i8 the AMUX signal which i~
input to the multiplexier 838.
The parallel 4-bit signal ASO-3 on line 832 from interface 820 is input to the control inputs of multiplexer 838. Ba~ed on tho logic ~tates these control ~ignal~, multiplexer 838 provides an output to bufer amplifier 850. The multiplexed analog output s$gnal include~ the analog values for the detected partial pressures o C02, C02 REF, N20, and N20 REF; the 10w rate o the gas through the optical ~ ''3 bench; the pressure and temperature in the optical bench; the temperature of the apparatus containing the analog input circuitry; the speed of the chopper motor; the chopper motor drive voltage; the voltage for maintaining a positive amplifier output values for selected amplifiers; the sensed battery voltage;
the sensed motor current, the ~5v reference; and the characterization information.
The signals input to interface 876 are the A/D SEL bar signal on line 874, the AIRD bar signal on line 824, the AIWR bar signal on line 730, the RESET signal on line 825, the parallel 2-bit address signal AIAl-2 on line 828, and the parallel 8-bit signal AIDO-7 on line 732. The outputs of interface 876 will be discussed subse~uently in discussing the circuit. Line 826 is connected to line 825 containing the RESET signal. Line 826 is redesignated the IORESET signal for use in the analog input circuitry.
The ANALOG OUTPUT signal on line 852 is input to differential receiver 854. The second input to differential receiver 854 is the system offset signal VDAC on line 856 which is an output of digital to analog (D/A) converter 879.
Tho offset signal for each of the four gas ; 25 or reference channels is generated by opening switcheR
740 or 752 at the appropriate time (Figure 7B). The voltage output by D/A coverter 879 when the~e switches are open ls that gas or reference channel's voltage offset. This channel offset is subtracted from the measured value for each ga~.
Tho voltage difference output from diff~ren-tial receiver 854 iQ input to variabl~ gain amplii-r 860. The gain of the ampliier ls controlled by the parallel 8-bit signal PAO-PA7 output from interace 876. These signals are rom analog input circuitry data bus 732.

-50- 1~2~
The output of variable gain amplifier 860 is input to sample and hold circuit 862. The sample and hold circuit control signal is the S~H (H bar) signal output from interface 876 on line 882. The control signal will hold the sample and hold output signal long enough for conversion of the current data in successive approximation register 870; place-ment o that data on data bus 880; and inpu~ of the present sample and hold signal into the successive approximation register for conversion.
The ou~put of the sample and hold circuit is input to comparator 866. The second input to comparator 866 is the VDAC signal on line 856. The output of comparator 866 is input to successive approximation register 870. The START SAR bar signal on line 886 is input to successive approximation register 870 to start the analog to digital conver-sion process. The SELSAR signal 884 is input to the output enable input of successive approximation register 870. The logic value of this signal con-trols placement of the converted data on data bus 880.
Another output of successive approximation register 870 i8 the CC INT bar signal on line 872 which will be discussed in connection with Figure 8A.
The SARCLK ENB signal output from interface 876 on line 888 is for generating the SARCLK signal on line 890 aR will ~e discussed in connection with Figure 8B. This is the first input to NAND gate 1110 for thi~ purpose. The other input to that gate is the CLK 400 Qignal output rom microprocessor 960 on line 970. The states of these signals control the output of NAND gate 1110. The output of NAND
gate 1110 after inversion, the SARCLK signal, i~
used to turn the internal sUcCeQQiVe approximation register clock on and off.

, .... ..

-51- 132'~
Figure 7D shows the remaining circuits of the analog input circuitry.
The PREAMP SEL bar signal on line 892 is input to NAND gate 894. The other input to this gate is the AIWR bar signal on line 730. The output of NAND gate 894 on line 898 clocks 8-bit latch 896.
The inputs to 8-bit latch 896 are the AID9-3 signals from the analog input circuitry data bus on line 732 and AIAl-2 signals from the analog input circuitry 10 address bus on line 828. The output of 8-bit latch 896 is input to 8-bit latch 900.
The signal that clocks latch 900 is the PCLK signal on line 902. The generation of the PCLK
siqnal will be described when discussing Figure 8C.
Also input to 8-bit latch 900 is the Q output of flip flop 918. Flip flop 918 i8 preset by the PSTRB
on signal on line 916 and cleared by the output of NAND gate 894 on line 898.
The outputs of 8-bit latch 900 are the PD0 signal on line 904, the PD1 signal on line 906, the PD2 signal on line 908, the PD3 signal on line 910, the PAl signal on line 912, the PA2 signal on line 914, and the PSTRB signal on line 916.
The parallel 4-bit input to line driver 922 from 8-bit latch 900 comprises the PD0 signal, .. the PDl signal, the PAl signal, and the PSTRB signal.
The parallel 4-bit output of this driver iQ the PRED0 signal on line 561, the PREDl signal on line 562, the PREAl signal on lino 588, and the PRESTRB s~gnal on line 586.
The paral1el 3-bit input to line driver 924 comprises the PD2 signal, the PA2 signal, and the PD3 signal. The parallel 3-bit output of this driver is the PRED2 ~ignal on line 564, the PREA2 signal on line 590 and the PRED3 signal on 566.
PDP-PD3/PRED0-PRED3 are the data lines to the optical bench 4-bit data bus. PAl and PA2/PREAl ~ 3 2 ~ .~ ~? ~3 and PREA2 are lines to the parallel 2-bit optical bench address bus. PSTR8/PRESTRB is the data line to the optical bench address bus and data bus strobe.
The VDAC signal on line 856 from D/A con-verter 879 is representative of the 12-bit converted data bus information. The VDAC signal is input to analog switch 926. The output signal from analog switch 926 on line 928 iS processed by sample and hold circuit 930. The output of this circuit on line 932 is the OB MOTOR SPEED signal.
The output signal o analog switch 926 on line 934 is processed by sample and hold circuit 936.
The output of this circuit is the AIR PUMP SPEED
signal on line 938. The parallel 4~bit signal PA~-3 on line 830 output from interface 820 is input to the control inputs of analog switch 926.
; The TIMING TRACK signal on line 538 output from the detector circuitry is input to frequency to voltage converter 944. The frequency to voltage converter output voltage, VoBspEED~ p analog processing circuitry and to error amplifier 945- The VOBSPEED Signal is a voltage signal pro-portional to the chopper motor speed.
Tho second input to error amplifier 945 is the OB MOTOR SPEED signal on line 932 from analog switch 926. This signal is the voltage set point for the chopper motor speed. The differenco in the signals is input to the base of transistor 952. The ba~e of tran~istor 948 is tied to log 953 of tran-sistor 952. When transistor 952 is in the "on"
condltion, this, under the propor conditions, will caus- a voltage difference between the MOTOR DRIVE
iino 844 and tho MOTOR RTN lino 950, thereby providing the proper power to drive the chopper motor. When transi~tor 952 turns off, voltage i~ returned on line 844 which turns on transistor 948. ThiR cau~es a braking action to help slow down the motor.

53 132~8 The MOT C~RR SEN signal on line 848 is tied to leg 955 o~ the source side of transistor 952. The V MOT DRV signal is also designated 844 since it contains the same signal as the MOTOR l~RIV~ signal.
Diode 946 blocks returned current on line 844 allowing transistor 948 to be turned on for braking.
The inputs to decoder 942 are the GAIN SEL bar signal on line 940 and the parallel 2-bit signal AIA1-2 f~om address bus 828. The GAIN
SEL bar signal is input to the output enable input and the 2-bit address .signal is input to the two control inputs of decoder 942. The logic values of the 2-bit address bus signal determine selection of the output. The ou~uts of decoder 942 are the DACE~N A bar signal on line 728 and the DACEN B bar signal on line 736. These signals are the output erlable signals for the variable gain arnplifiers associated with processing the CO2/CO2 REF signal and N20/N20 REF signal in Figure 7B.
Fig~res 8A~ 8B and 8C show analog processing circuitry 124 (Figure 1). First the circuits of the analog processing circuitry will be described, then their calculating functions will be described.
Referring to Figure 8A, one component of analog processing circuit~y 124 is microprocessor 960. Microprocessor 960 is a model 80186 CPU, commercially available from Intel Corp., Santa Clara, California The signals input to microprocessor 960 are from the circuit~y in Figures 8B and 8C, and the analog input circuitry. These are the UART
INT signal on line 962, the CC INT bar signal on line 872, the DRQ~
signal on line 964, the DRQ1 signal on line 966 and the FST A signal o~
line 972.
The UART INT signal is an ineerrupt signal from controller 1059 to indicate the transmission or receipt of data The CC INT signal is an interrupt input from successive appro~mation register 870 to indicate completion of the conversion of an analog ~ 3 ~

signal input and that the converted signals can be put on the data bus 880 (Figure 7C). The DRQ9 and DRQl signals are direct memory access request inputs indicating that a character is ready to be tranamitted S rom memory or that a character has been received and must be transferred to memory. The FST A signal is the fail safe timer signal to indicate whether or not that the microprocessor has drifted off into an improper loop and is no longer performing its required functions.
The output signals of microprocessor 960 are the PATT SEL signal on line 974, the UCS bar signal on line 976, the PREAMP SEL' bar signal on line 978 the GAIN SEL' bar signal on line 980, the PATIENT SIDE OFF signal on line Y82, the P~MP/VALVE
SEL signal on line 984, the PCS5 signal on line 986, the ALE signal on line 988, the RESET signal on line 825, the UART CLK signal on line 968, the CLK 400 signal on line 970, the DT/R ~R bar) signal on line 996, the DEN bar signal on line 997, the UART SEL
signal on line 998, the A/D SEL' bar signal on line lOOO, the MISC SEL' bar signal on line 1002, the CL~8 signal on line 1012, the WR bar signal on 1004, the RD bar signal on line 1006, the LCS bar signal on line 1008, and the BHE bar signal on line 1010.
The PATT SEL signal is or generating the PCLK signal on line 902. The PCLK signal clocks latch 900 (Figure 7D) which contains values to be the placed on the optical bench data bus.
The UCS bar signal on line 976 enables decodor 1040.
The PREAMP SEL' bar signal, the GAIN SEL' bar signal, the A/D SEL' bar ~ignal, the MISC SEL' signal, WR bar signal, and the RD bar signal are used for generating the PREAMP SEL ~ignal on line 892, the GAIN SEL ~ignal on line 940, the A/D SEL bar signal on line 872, tha MISC SEL bar signal on _55_ ~3~ ?~
line 822, the AIWR bar signal on line 830 and the AIRD bar signal on line 824, respectively, for use by the analog inpu~ circuitry shown in Figures JA-7D.
The PREAMP SEL bar signal, the GAIN SEL
bar signal, the A/D SEL bar signal, and the MISC SEL
bar signal are chip selection inputs for components of the analog input circuitry. The AIWR bar and AIRD bar signals act as conventional write and read signals.
10The CLK 400 signal is used in generating the SAR CLK signal on line 890 and the PCLK signal on line 902 (Eigure 8C).
The DT/R (R bar) signal controls the direc-tion of data flow through bus transceivers 1024, 151025, and 1106.
The DEN bar signal is the output enable signal for bus transceiver 1024 and 1025.
The PUMP/VALVE SEL signal is one of the signals controlling the selection among powering the diagnostic value, the backflush valve, the external valve 1, and~or the external valve 2.
The PCs5 signal is one of the signals used to generate the FST A signal on line 972 for deter-mining if the microprocessor has entered an improper loop.
The LCS bar signal enables decoders 1032 and 1036.
The BHE bar signal is one of the control inputs to decoder 1036.
30The UART SEL signal i~ input to the chip select input of controller 1059.
The ALE signal is for clocking address latches 1014, 1016, and 1018.
The CLK8 signal i~ the 8 MHZ clock signal for clocking variouQ circuit components of the pro-ce 8 sor circuitry.

3 ~

The WR bar signal is the write timing signal indicating that the processor is writing data into memory or into an input/output device.
The RD bar signal is a read timing siqnal indicating that the processor is reading data.
Memory in Figure 8A consists of four read only memories (ROMs) 1046, 1048, 1054, and 1056; and two random access memories (RAMs) 1050 and 1052.
This memory is conventionally connected to address 10 bus 1022 and data bus 1028.
Figure BA shows three address latches, 1014, 1016, and 1018. These latches are clocked by the ALE (address latch enable) signal input to their respective clock inputs. Hence, when the ALE signal has the proper logic state, the three latches are clocked simultaneously.
Latch 1014 receives a parallel 4-bit input from address outputs A16/S3-A19/S6 on line 990. The clocking of latch 1014 will place these values on address bus 1022.
The parallel 8-bit inormation signal AD8-15, output from microprocessor 960 on line 992, is input to latch 1016. The AD8-15 ~ignal can contain either address or data information. However, when it i5 handling address information and thoso values are input to latch 1016, when that latch is cloc~ed, the latched address values are placed on address bu~ 1022.
Similarly, the parallel 8-bit signal, AD0-7, 30 output from microproce~sor 960 on line 994, is input to latch 1018. The AD0-7 signal may contain address or data information. When it contains address infor-mation and the values are input to latch 1018, when that latch i~ clocked, the latched values are placed on address bus 1022.
Tho AD0-15 signals al~o connect to data bus 1028 via bus 1020 and bu~ transceivers 1024 and :

~ 3 2 ~ J~

1025. Bus transceiver 1024 controls transfers between the ADP-7 signals on bus 1020 and the data bus. Bus transceiver 1025 controls transfers between the AD8-15 signals on bus 1020 and the data bus. Bus tran~ceivers 1024 and 1025 are enabled by the DEN bar signal on line 997. The direction of the data transfer i9 controlled by the DT/R (R bar) signal on line 996.
Decoders 1032 and 1036 are used to enable RAMs 1050 and 1052, respectively. The LCS bar signal on line 1008 enables both decoders. The first control : signal input to decoder 1032 i~ the AO signal from the address bus. The ~econd control input is tied to ground. These signals are decoded to provide an input to the chip enable input of RAM 1050. Whether reading or writing is the proper action is determined by the logic states of the RD bar and WR bar signals input to RAM 1050.
The first control signal input to decoder 1036 is the the BHE bar signal on line 1010. The , 20 ~econd control input is tied to ground. These signals are decoded to provide an input to the chip enable input of RAM 1052. Similarly, whether reading or writing is accomplished depend~ on the logic states of the RD bar and WR bar signals input to RAM 1052.
Third decoder 1040 enables ROMs 1046, 1048, 1054, and 1056. The UCS bar signal output from microproces~or 960 on line 976 enables decoder 1040.
The control input~ to decoder 1040 are the A17, A18 and Al9 ~ignals from addr-sQ bus 1022. When the control input~ are decoded, decoder 1040 provide~
output~ to enable the ROM~. Whether an enabled ROM
can be read depend~ on the logic state of the RD bar ~ignal lnput to the OE bar lnput of each ROM.
R-ferring to Figure 8B, controller 1059 will be discussed. Tbe Q output of 1ip flop 1058 clocks controller 1059. The CLK8 signal on line 1012 clock~ flip flop 1058. The Q bar output and data .

-58- ~2~
input of this flip flop are tied. Hence, the Q output will have a posi~ive-going edge to clock controller 1059 every two CL~8 pulses.
The RESET signal on line 825 output from microprocessor 960 is input to to inverter 1007.
Inverter 1007 changes the logic state of the RESET
signal; accordingly, the RESET bar cignal is input to the RESET bar input of controller 1059.
The WR bar ~ignal on line 1004 and the RD
bar signal on line 1006 are input to controller 1059.
These signals control whether data is transmitted from or received by controller 1059.
The UART SEL signal on line 998 is input to controller 1059 for chip selection and enabling readin~ from and writing int~ memory.
The parallel 2-bit address bus signal, A12 and A13, from address bus 1022 is input to controller 1059. These are the address bus bits tbat control data low. The parallel 8-bit data bus signal, D0-7, on line 1028 is input to controller 1059. These are the data bus bits which are either read from or written onto.
The DRQ0 signal on line 964 and the DRQl signal on line 966 are input to microprocessor 960 for notifying the microproCe~Qor that data is ready to be transmitted from memory or that data is ready to be sent to memory.
The other signals that are output from or input to controller 1059 are primarily as~ociated with communicating with the display section or an external device.
The INT C~K signal on line 1060 i~ the internal baud rate clock for synchronous serial com-munications b-tween the analog and display proces~ors.
3S The TxD INT slgnal on line 1062 i9 the line on whlch data is transmitted from the analog processor to the display processor.

.

.
.

1 3 2 ~

The RxD INT signal on line 1064 i8 the line on which data is received from the display processor.
The information in the TxD INT signal on line 1062, the RxD INT signal on line 1064, and the INT CLK signal on line 1060 is communicated between analog processing circuitry 124 and display processing circuitry 128 using these signals because the analog ; and the display sections are electrically isolated.
The TxD INT signal is input to inverters 1080 and 1082 and then opto-isolator 1084. The TxD
INT signal on the display side of opto-isolator 1084 is renamed the RXD INT signal on line 1086. A portion of data contained in the TxD INT signal is ultimately displayed on the CRT.
The RxD INT signal on line 1064 contains data received rom the display processing circuitry.
The signal starts as the TxD INT signal on line 1094 on the display side. The signal is input to inverters 1092 and 1090, and then opto-isolator 1088. At the output of opto-isolator 1088, the signal is renamed the RxD INT signal on line 1064.
The INT CLK signal on line 1060 i3 used to synchronously control transfer of data between the analog and display processing circuitry. The INT
CLK signal on line 1078 on the display side is input to inverters 1074 and 1072, and then input to opto-isolator 1070. The signal is output from the opto-i~olator on line 1060 for input to controller 1059.
The UART CLK signal on line 968 i8 input to controller 1059 and along with TxDB signal on line 1066 and the RxD8 signal on line 1068 are for communication~ with external module 430 (Figure 4A).
The UART CLK signal on line 968 is tho baud rate clock for serial communication~ with the external module. The TxD8 bar signal i3 for trans-. -- .

, .. , . , -: : .
.

mitting data to the external modulc The Rx~B bar signal is for receiving data from the ~xternal modul~
The UART INT signal on line 962 i~ the UART IN~ bar signal output rom controller 1059 after inversion by inverter 963 This signal ls an inter-rupt signal to microprocessor 960 to indicate that data is ready to be sent or receiv-d The BATT SEN signal on line 842, and the FLOW PRS signal on line 391 and ELOW PRS RTN ~ignal on line 393, cross the analog processing circuitry - enroute to the analog input circuitry where they are proces~ed The AIR PUMP SPEED signal on line 938 from analog switch 926 (Figure 7D) i~ input to the base of transistor 1114 Shis signal controls the SAMPLE
PUMP~ voltage on line 1122 The SAMPLE PUMP- ~ignal on line 1124 is tied to ground The power delivered by the circuit is limited by fuse 1116 in lino 1122 and by zener diodes 1118 and 1120 The voltage across the~e line~ controls the speed of ~ample pump 358 (Figure 4A) The DO signal rom data bu~ 1028 and tho PCS5 ~ignal rom microproces~or 960 are input to the protection circuit 1125 according to ~ preset rate and duty cycle The protection c$rcuit, according th- clock rate o the PCS5 ~ignal, evaluate~ the D~
signal I D0 ha~ value~ indicativ- of improp-r operation or th- PCS5 signal i~ abs-nt, it indicate~
that tho microproe-ssor is in an improper loop and not carrying out lt~ requir-d function~, tb- FST A
~ignal on lln- 972 will change logic stat~s Thl~
will cau~- th- actlvation o th- appropriat- alarmr to lndicat- thi~ condition Th- SAR CL~ signal on lin- 890 (Fi~ur- 8A) which turns th- internal clock o ~ucce~siv~ approxl-mation r-gi~t-r 870 on and of i~ g-nerated by the CL~ 400 ~ignal ~nd th- SAR CL~ ENBL ~ignal Th- CL~

~ 3 s~, L~ 3 3 o 400 signal on line 970 and the SAR CL~ ENBL signal on line 888 are input to NAND gate 1110. The logic states of these signals control the output of NAND
gate 1110. The output of NAND gate 1110 is inverted by inverter 1112 whose output is the SAR CL~ signal on line 890.
The analog processing circuitry generates the control signals for powering certain components of the pump module. These are the diagnostic valve, the external valve 1, the external valve 2, and the backflush pump. The WR bar signal on line 1004 and the PUMP/VALVE SEL signal on line 984 are input to negative-true AND gate lO9S. The output of nega-tive-true AND gate 1095 is inverted by inverter 1096 and input to the cloc~ input of 8-bit flip flop 1098 of which only 4-bits are output lines. The data input to flip flop 1098 are the DP-7 signals from the data bus. When the flip flop is clocked, the data bus logic values determine which valves will be powered. Accordingly, the outputs of flip flop 1098 which are destined for the pump module are the DIAGNOSTIC VALVE signal on lines 411, the EXTERNAL
VALVE 1 signal on line 431, the EXTERNAL VALVE 2 signal on line 441, and the BAC~FLUSH signal on line 417.
The analog processing circuitry qenerates "select" signal~, and the RD bar and WR bar signals for use by the analog input circuitry. The analog processing clrcuitry provides the 2-bit address bus signal for uQe by the analog input circuitry and bi-directionally communicates with analog input circuitry data bus.
The ADSEL' bar ~ignal on line 1000, the GAIN SEL' bar ~ignal on line 980, the PRE~MP SEL' bar signal on line 978, and the MISC SEL' bar signal on line 1002 are input to OR gate 1100 and to octal buffer 1108. The other four inputs to octal buffer , , , ~;,- . ~:
.

1 3 2 ~

1108 are the Al and A2 signal~ from addre~ bus 1022, the RD bar signal on line 1006, and the WR bar ~ignal on line 1004 The data bus signals D~-7 on line 102B ar-input to bu~ transceiver 1106 The DT/R (R bar)signal controls the direction of data flow through the transceiver The output of OR g~te 1100 i~
inverted by inverter 1102 and input to the output enable inputs to bus transeeiver 1106 and octal buffer 1108 When at least one of the four ~elect"
signals has the proper logic ~tato, th~ bu~ tran~-ceiver and the octal bufer are output enabled;
accordingly, data, control ~ignal~, and elect signals are communicated b-tween the analog input and analog proces~ing c$rcuitry On the an~log input side, the~e signal~ ar- the AIDO-7 data ~u~
signal on line 732, the AIAl-2 ddre~ has ~ignal on line 82B, the AIRD bar ~ignal on lin- 824, the AIWR
bar signal on line 830, the ADSEL bar signal on lin~
872, th- GAIN SEL bar signal on line 940, the PREAMP
SEL bar signal on line 892, and the MISC SEL si~nal on line 822 Figur- 8C show~ the circuit for generating the PCLK ~ignal u ed to clock latch 900 for placing information on the optical bench d~ta bu~ Tho PATT SE~ signal on lin- 974 18 input to invert-r 1130 Th- output o thi~ lnverter i~ the first input to NAND gat- 1132 Th- WR bar signal on line 1004 i~ $nput to invertor 1134 Th- output of thl~
inverter 1- the ~econd input to NAND gat- 1132 m-output of NAND gate i- input to the clock input to 8-bit fllp 10p 1136 Th- data bu~ ~iqn~l D~-7 ~
input to th- data input~ of the flip flop The output of the fllp flop on lin- 1138 i~ a parallel 4-~it ~ignal to th- addres~ input~ of EPROM 1142 -~ 3 ~ t3~

The other input to EPROM 1142 1- the parallel B-bit output from 8-bit counter 1140 which i~ input to the data inputs 8-~it counter 1140 is clocked by the CLK 400 signal output from micro-processor 960 8-bit counter 1140 compri~es two 4-bit counters The terminal count of one 4-bit counter is ti-d to the clock tnput of the other 4-bit counter Thus, th~ ~econd 4-bit counter $s clocked every sixteen clocks The parallel 8-bit output of EPROM 1142 is input to 8-bit flip flop 1144 8-bit flip flop 1144 is clocked by the same ~ignal that clock~ the first 4-bit counter of 8-bit countcr 1140 The PCLK
15 signal output on line 902 clock3 latch 900 (Figure 7D) The primary function o~ microproce~sor 960 of analog processing circuitry 124 i~ calculating tho partlal pressure~ o the ga~e~ of interest In calculating these, the microproce~sor correcta for collision broadening, temperature, pre~ure in the gas pathway, cro~-corr-ction, barometric pr-~sure, and ehar-cterization Characterization allows for th~ inter-change-blllty of optical bench-~ without tho need for calibration Ch~rw terization co-fficient~ of an optical bench ar~ ba--d on the fact that a manu-facturer con~truct~ each optical bonch o a p~rtl-cular typ- with the samo component~ Bowev-r, corr-~pond~ng component~ ln two dlf-r-nt benches h~v- diferent ro~ponae~ Th- re-ult i- that two dler-nt b-nche~ making partlal pro~uro mea~ure-mont~ can doriv- two di~f-rent valu-- ev~n though both ar- opor-tlnq prop-rly Accordingly, each b-nch ha~ lt~ own specl-1c characterization eoef1cicnt~ The~ coe1-clent~ ar- ~tored in EEPROM 580 (Figure SA) ~enc-, ~ 3 ~ ~ s~

the application of each bench's characterization coefficients to raw meaRurements of a known gas standard ~ring about the same result. This result is consistent with industry standards and made with-out any calibration to the bench's components.
Specific characterization coefficients for each gas channel are stored in EEPROM 580. The other values stored in the EEPROM 580 are the temperature transducer voltage at the reference temperature, the collision broadening coefficients, the cross-correc-tion coefficients, and the span factor and ofset for correcting pressure measurements.
The calculation of the partial pressure and gas concentration of C02 and N20 will now be discussed.
The C02 and N20 scale factors are measured and stored every time a zero gas measurement is calculated. Scale factors are determined by the following expression:
Scale Factor ~Xl = VIXgasl/VlXref] (1) where, X = C02 or N20.
VIXgasl = the measured gas channel output of the detector with zero gas.
VIXrefl = the measured reference channel output of the detector with zero gas.
Scale Factor lXl ~ is a real number valuo.

At predetermined interval~, the system calculates updates for temperature related values used in calculating the partial pre~ure of each ga~. These values are calculated according to the following three expressions:

~ T = VITmpl - RefTmpVolts (2) where, .

-65_ 1 3 2 ~
VlTmpJ = the current measured voltage from the temperature sensor.
RefTmpVolts = The voltage for the referénce operatinq temperature of the optical bench stored in EEPROM 580.

tcB~XI = BolX] l ((Bl[X])(~T)) + ((B2[X])(~T )) (3) where, X = C02 or N20.
BolX]~ Bl[X]~ B21X] = the B characterization coefficients for each gas stored in EEPROM 580.
tc~[Xl = the B temperature correction for each gas.
tcC[N20l = ColN2l + ((Cll 2 1)( ( (C2 1N20] ) (~T2 ) ) where, Co[N20], CllN2ol~ C21N20] = the C charac-terization coefficients for N20 stored i in EEPROM 580.
` 20 tcC[N201 = the C temperature correction for ,, N20' The C temperature correction is only calcu-lated for N20. The C temperature correction for C2 ha~ neqligible effect on the final partial pre~sure of C02, so it is not used.
At predetermined intervals, colli 5i on broadening calculations are performed. These calcula-tions aro carried out according to the following tbroe oxpressions:

I~ PPIN20] ~ 76 mmHg, then CB[N2/021 = ~ (5) where, ~PIN20l = the average PP [N201 over the updated time interval.
.

~ 3 2 '~

CBIN2/02] = the csllision broadening factor N2 and 2 Else, C8lN2/021 = ((cbL)(1 - ~02%/100)) (6) where, CB~N2/02] = the collision broadening factor for N2 and 2 cbL = the collision broadening coefficient stored in EEPROM 580.
%2 = the measured %2 from a peripheral device, or a manually set percentage, or 50% as a default value in the programming.

CB~N_Ol = ((cbM)(PP[N20~ /SampleCellPrs (7) where, CBIN20] = the collision broadening factor for N20.
cbM = the collision broadening coefficient for N20 stored in EEPROM 580.
PP[N201" = the current N20 calculation (mmHg).
SampleCellPrs = the pressure measured in the sample cell (optical bench) when the gas voltages are measured.

CBICO2] = ((cbN)(PPICO2]''))/SampleCellPrs (8) 25 where, CBICO2] = the collision broadening factor for C02.
cbN = tho collision broadening coefficient for C02 stored in EEPROM 580.
PPICO2''l = the current C02 calculation Hg ) .
SampleCollPrs = the pressure measured in the sample cell (optical bench) when the gas voltaqos are measured.

~32 ~J~ ~

The absorption of light by the C02 and N20 gas is continuously calculated accordinq to the expression:

R[X] = -ln (Vgaslx]inst)/(~vref[~]inst) ( ) (Scale Factor lX])) where, X = C02 or N20.
VgaS[Xlinst = the instantaneous demodulated gas voltage for C02 or N20.
Vref[X]inst = the instantaneous de~odulated reference voltage for C0~ or N20.
Scale Factor IXI = the current scale factor value for C02 and N20.

Having made the above calculation, micro-processor 960 calculates the partial pressure of C2 and N20. In the expressions that follow, a partial pressure shown as PP[X] is a final partial pressure corrected for cross-correction and collision broadening; a partial pressure shown as PP[X]' is a partial pressure corrected for collision broadening only; and a partial pressure shown as PPlX]Il is corrected or neither.
The partial pressure of C02 and N20 are calculated according to expressions (10)-(22). The uncorrocted C02 partial pres~ure i~ calculated according to the expreqsion:

PPICO2]" = ~tcBlco2l)(Rtco2l)) + (10) ( ~ColC02 1 ) (Rtco2 1 ) ) +
~DICo2])~Rlco2l3)) where, tcB[C02] = the B temperature correction or C02.
RICO2] = C02 light absorption.

-68- ~ 3 2~
CO1C21 = the C characterization coefficient for C02 stored in EEPROM 580.
D[CO2l = the D characterization coefficient for CO2 stored in EEPROM 580.

The uncorrected N2O partial pressure is calculated according to the expression:

PP~N201 = ( (tCBlN20J ) (RIN20l ) ) + (11) ( ~tCclN20] ) (R[N20]2 ) ) ((D[N201)(RIN20]3)) where, tcB[N2O] = the B temperature correction for N20-R[N2OJ = N20 light absorption.
: tcC[N20] = the C temperature correction for N20.
D[N20] = the D characterization coefficient for N2O stored in EEPROM 580.

The uncorrected C02 partial pressure is now corrected for collision broadening by the 20 expression:

PPIC02] = ((PPlC02]')(1 ~ CB¦N20~ CBIN2/02]))/
( (1 - CB[N20] ) (CBlC02 1 ) ) S12 where, CBlN2O] = the collision broadening factor for N20.
CBlC02l = the collision broadening factor for CO2.
CBlN2/02] = the collision broadening actor for N2 and 2 The final C02 partial pressure, corrected for cross-correction, i~ calculated by the expression:

-69_ ~ 3 ~
PPlCO2l = PPlC02] ~ ((PPlN21 ) (13) (CCrsCorrlN2O])) where, CCrsCorr[N2OI = the cross-correction for N2O in the Co2 channel stored in EEPROM 580.

The uncorrected N2O partial pressure is now corrected for collision broadening by the expression:

PP[N2Ol = ~(PPIN2OI )(1 + CB[CO2]))/ (14) ((1 - C~3[N201)(CB[C021)) where, CBlCO2] = the collision broadening factor for CO2.
CBIN2O] = the collision broadening factor for N2O.

The final N2O partial pressure, corrected for cross-correction, is calculated by the expression:

PPlN2O] = PPIN2O]' - ((PP[CO2]) (15) (NCrsCorrl CO2 ] ) ) where, NCrsCorr[CO2] = the cross-correction for C2 in the N2O channel stored in EEPROM 580.

Once the final partial pressures for CO2 and N2O are calculated, each i8 corrected to baro-metric pre~sure. The baromotric pressure value that is normally used in correcting the final partial pressure o CO2 and N2O is calculated by the follow-ing expre~sion:

Barometric PrsN = ((VIPrslNp)(prsspn)) ~ (16) PrsOset -70~ $ ~ ~
where, VIPrs~Np = the voltage from pressure tran~-ducer 374 at system start-up or an update with the sample pump off that is stored in memory.
PrsSpn = the pressure span factor to characterize pressure transducer 374 that is stored in EEPROM 580.
PrsOffset = the offset for pressure transdu~er 374 that is stored in EEPROM 580.

However, in certain situations, for example, when the optical bench is used in an open military field hospital in a high humidity area, the barometric pressure calculated according to expression 16 must be further corrected to be accurate. Under such circumstances, the baremetric pressure is calculated by the following two expressions:

H20 VaporPrs = ((RelHum)(SatPrs)(Barometric Prs Samplecellprsaver))/ls2o (17) where, RelHum = the relative humidity which is normally the deault value of 45%.
This can also be the measured value of relative humidity which is manually input by the operator SatPrs = the vapor pressure o water at standard pressure which is normally the deault value of 11.837 mmHg.
The vapor pre~sure can also be a determined value of the vapor pres-sure of water at standard pressure which is manually input by the operator.

~32~

3arometric PrsN = last measured barometric pressure stored in memory.
SampleCellPrsaver = the average pressure measured in the cample cell (optical bench) when the barometric pressure measurements were taken.

The further corrected barometric pressure is calculated by the following expression:

Barometric Prss = Barometric PrsN - H20 VaporPrs (18) 10 where, Barometric PrsN = last measured barometric pressure stored in memory.
H20 VaporPrs = the vapor Dressure of water calculated according to expres-sion 17.

The final partial pressure of a gas of interest is corrected for (normal) barometric pres-sure according to the ollowing expression:

PPmmHglXI = ( PP~Xl ) (Barometric PrsN) (19) (SampleCeLlPrs) where, X = C02 or N20.
SampleCellPrs = the pressure measured in the sample cell (optical bench) when the gas voltages are measured.
Baromotric PrsN = tho last measured baro-metrlc pressure stored in memory.

The X concentration of C02 and N20 can be cho~en for di~play rather than th~ PPmmHglXI cal-culated according to expression 19. The % concentra-tion is calculated according to the expression:

-72- 132 ~3~
((PPmmHG~XI) (100~ (20) % ConclX] = (Barometric PrsN) where, X = C02 or N20.
Barometric PrsN = the last barometric pressure stored in memory.
PPmmHg[X] = the final partial pressure of C2 or N20 in mmHg corrected for barometric pressure.

For the purpose of calculating the final partial pressure of C02 or use in generating the scrolling waveform on the screen display (Figure 17), the detected C02 gas signals are corrected only for N20 collision broadening. However, this collision broading is diferent from the collision broadening factor discussed previously in, for example, expression 12. For the scrolling waveform, collision broading is determined by the following expression:

CBIN20lwave = (cbM)(conclN2o]aver) (21) where, cbM = the collision broadening coefficient for N20 ~tored in EEPROM 580.
CnCIN2]aVer = the average end-tidal N20 from the last breath stored in memory.

Tho final partial pressure o C02 for use in generating the ~crolling C02 coprogram is calculated according to the following expression:

PPICO2l = (PPlco2l'')(l ~ C3tN2]wave) ( whero, 13 2 ~ ~3 ^~, PP[C02]" ~ the uncorrected partial pressure f C2 according to expression 10.
CBlN20lwave = the collision broadening factor for generating the scrolling C2 waveform according to expression 21.

As stated, the above calculations are made by microprocessor 960. Once these calculations are made, they are transmitted to the display section for display.
The measured values for optical bench pres-sure is also corrected by microprocessor 960 and sent to the display section. Further, the measured temperature (in volts) is sent to the display sec-tion. These values are used for diagnostic purposesonly.
The pressure within the optical bench pathway can vary between + 12.2 psia and ~ 9.7 psia.
When the sample respiratory gas stream or zero gas stream is drawn through optical bench 111 by sample pump 358 the pressure is within this range. The expression for calculating pressure within optical bench 111 i 8:

Press = ((VlPrql)(PrsSpn)) ~ PrsOffset (23) where, V(Prs) = the instantaneous voltage from pressure transducer 374.
PrsSpn = the pressure span factor to characterize the pre~sure transducer that is stored in EEPROM 580.
PrsOf~set = the offset for the pressure transducer tha~ is stored in EEPROM 580.

Figures 9A-E show the circuits contained on motherboard 137 (Figure 1). The circuitry on motherboard 137 communicates between the analog processor circuitry 124 and display processor circwtry 128, between two or more elements in the display section circuitry and between the display processor 128 and the knob board 144.
Referring to Figure 9A, the signal~s input to speaker driver circwt 1354 are the VVOL signal on line 1350 and VB}~eP signal on line 1352.
The VB~ signal is the principal signal driving speaker driver circuit 1354.
The VVOL signal adjusts the SPK+ voltage on line 1356. The SPK- output on line 1358 connects to ground. The SPK+ and SPK- lines connect to an external speaker.
The video amplifier circuit 1364 is for driving the CRT cathode.
The signals input to the video amplifier circuit are the VIDEO OUT signal on line 1360 and the VCONTR signal on line 1362~ The VIDEO OUT signal on line 1366 is the signal for driving the display screen. The VCoNrR signal on line 1362 controls the voltage supplied to the cathode for the purpose of screen contrast. The output of this circuit to the CRT cathode is on line 1366.
The H DRIV~ (horizontal drive) signal on line 1371 from CRT
controller 1998 of pixel circuitry 130 is input to horLzontal drive circuit 1372. Following conventional processing by this circwt, the signal is input to horizontal output circuit 1376. The outputs of the holizontal output circuit are to the CRT anode on line 1380, to CRT grids 1, 2, and 4 on lines 1382, 1384 and 1388, respectively, and the HORlZ+ and HORIZ-signals on lines 1340 and 1342 to the horizontal yoke.
The V.SYNC (vertical sync) signal on line 1344 is input to vertical output circuit 1347. The VDE~, (de~ection voltage) signal on line 1345 is ~3~'~$30 input to voltage regulator 1349. The output of the voltage regulator is input to the control voltage inputs to the vertical output circuit. Following conventional processing by this circuit, the output signals are the VERT- and VERT+ signals on lines 1346 and 1348, respectively. These signals are input to the vertical yo~e.
The apparatus cooling fan supply voltage is supplied from the CRT mother board. The FAN+
signal on line 1361 is connected to a ~12v supply voltage. ~he FAN- signal on line 1363 is tied to ground. Accordingly, a 12v supply voltage is across the fan terminals to power it.
Figures 9B-9E show signals which transit the motherboard without being processed bY its circuitry. Figure 9B shows signals communicated between display processing circuitry 128 and pixel circuitry 130. Figure 9C shows signals communicated between display processing circuitry 128 and digital output board 140. Figure 9D shows signals communi-cated between the display processing circuitry and knob board 144. Figure 9E shows signals communicated between analog processing circuitry 124 and display processing circuitry 128.
Figures lOA and lOB aro schematic diagrams o display proce~sing circuitry 128. The principal unction~ o the display proce~sing circuitry are proce~sing the incoming data from analog processing circuitry 124, transmittal of the data back to the analog proce~ing circuitry, and control of pixelcircuitry 130.
The partial pressuro of C02 and N20, the pre~sure within the optical bench, the ga~ low rate through the optical bench and other information for di~play are received a~ the RxD INT siqnal on line 1086 by controller 1776. Data ~ent to the analog -76- 13 ~
processing circuitry is sent via the TxD INT signal on line 1094 from controller 1776.
When the control signals input to con-troller 1776 have the proper states, data is trans-mitted to or received from the 8-bit data bus shown as DP-7 on line 1414.
The INT CLK si~nal on line 107~ synchron-izes the transmission of data between the analog and the display processing circuitry.
The DRQO and DRQl signals output from the controller on lines 1730 and 1732, respectively, the 2 address bus signals A12 and A13 input to the con-troller, the COMM INTR signal output on line 1706, the COMM SEL signal input on line 1778, and the RD
bar and WR bar ~ignals on lines 1402 and 1404, respectively, all operate conventionally in a manner known by those skilled in the art. The TxD signal on line 1510, the RxD signal on line 1512, the DTR
bar si~nal on line 1514, the DSR bar signal on line 1516, the RTS bar signal on line 1518 and the CTS
bar signal on line 1520 all connect to the digital output board 140. These cignals are for communica-tions with and control of an external device.
The EXT CLK signal on line 1734 is a clock signal for controlling serial communications between the controller and an external device.
Microprocessor 1702 is a model 80186 CPU, commercially available from INTEL Corporation, Santa Clara, California. The signals lnput to and output from microprocessor 1702 will now be discussed.
When microprocessor 1702 i-~ powered on, the RESET OUT signal on line 1704 is asserted. The RESET OUT signal on line 1704 i8 input to inverter 1707. The output of the inverter i Q the RESET bar signal on line 1705. This signal is input to the RESET bar input of controller 1776.

-77- 13~ 3 The VERT INTR signal on line 1408, the V.SYNC bar signal on line 1344, and the SLAVE INTR
signal on line 1506 are all interrupt signals. The VERT INTR signal is the interrupt signal to micro-processor 1702 to indicate when the end of the scrolled window is reached. The V.SYNC bar signal on line 1344 indicates the end of a display field on the CRT. The SLAVE INTR signal on line 1506 is the interrupt signal from an external device.
The COMM INTR signal on line 1706 is the signal input into the microprocessor from the con-troller through inverter 345 to indicate that data is being transferred from or received by the con-troller.
The DARDY signal on line 1410 is the asynchronous ready signal.
The UCS bar signal output on line 1710 enables decoder 1746. The signal~ output from this decoder based on the logic values of the address bus bits A17 and A18 enable ROMs 1760, 1762, 1764 and 1766.
The D. SIDE OFF signal on line 1712 is output to the battery control circuit to indicate shut down of the display side of the system.
The DISP SEL signal on line 1602 is output to the knob board for placing the button and knob status on the data bus and or the display and activation of the system' 5 audible and visual alarms.
Th- VID FCN SEL signal on line 1418, the CRT SEL signal on line 1416, the A/D SEL signal on line 1424, the SCROLL SEL signal on line 1420, and the ANALOG SEL signal on line 1422 aro output to the motherboard or input to and control of pixel circuitry 130.
Th- CRT SEL signal on line 1416 is input to CRT controller 1998 (Figure llA) for chip selec-tion. The VID FCN SEL signal is input to decoder -78- i 3 2 ~ ~ ~ o 2032 (Figure llA) to select a proper video display function for the CRT screen. The A/D SEL signal on line 1424 is used to put ECG information or battery comparison information on the data bus for transfer S to memory (Figure llC). The ANALOG SEL signal on line 1422 is used to control selection among various analog output ports.
The FST B signal on line 1709 is input to microprocessor protection circuit 1717. This changes logic states when the microprocessor is not perform-ing its required functions, e.g., the microprocessor is improperly looping. This circuit is similar to protection circuit 1125 that protects microprocessor 960 (Figure 8B).
The other siqnals associated with micropro-cessor 1702 yet to be described are signals for one of the busses or signals associated with accessing memory to read or write data.
The signals A16/S3-Al9/S6, a parallel 4-bit output on line 1713, are the high order address bits.
These bits are input to latch 1740. When this latch is clocked by the ALE (address latch enable) signal on line 1718, the address information is placed on the address bus since the OE bar input is tied to ground.
The DEN bar (data enable) signal on line 1714 i~ the output enable signal for bus transceiver~
1752 and 1754. The DT/R (R bar) (data transmit/
receive) signal on line 1428 determines the direction of data flow through bus transceivers 1752 and 1754.
Together, these two signals control the data trans-mitted to and received from memory on address/data bu~ses 1720, 1722 and 1723.
When address/data busses 1722 and 1720 are used for addres~ rather than data transfer, address bit~ ~-7 are input into latch 1744 and address bits 8-15 are input to latch 1742. When these latche~ are .. ~, . . .

.

~79 3 `~
loaded and then clocked by the ALE signal on line 1718, the latched values are placed on the address bus.
RAM 1768 is enabled by the output of decoder 1794. This decoder is enabled by the output of decoder 1784. Decoder 1784 is enabled by the output o OR gate 1780, address bit A19 and the BHE
bar (bus high enable) on line 1724.
: RAM 1770 is enabled by the output of decoder 1804. This decoder is enabled by the output : of decoder 1796. The signals that enable decoder 1796 are the output of OR gate 1780, and the AO and Al9 signals on line 1412 from the address bus.
The inputs to OR gate 1780 are the MCS9-~5 MCS3 bar signals output rom microprocessor 1702 on line 1726. As stated, the output of OR gate 1780 output enables decoders 1784 and 1796. The states of the outputs from these decoders are controlled by high-order address ~its A17 and A18 on line 1412.
The other outputs of decoder 1784 are the TRNDH (trend high) signal on line 1786, the CHRENH (character~enhancement plane high) signal on line 1788 and the GRPHH (graphic plane high) signal on line 1790. These signals aro also input to OR
gate 1792. The word high in these signal names indi-cates the high-order address bits, 8-15, for a particular memory circuit in pixel circuitry 130.
The other outputs of decoder 1796, ar~ the GRPHL (graphic plane low) signal on line 1802, the CHRENL (character/enhancement plane low) signal on line 1800 and the TRNDL (trend low) signal on line 1798. These signals are also input to OR gate 1792.
The word low in these signal name~ indicates the low-order address bits, ~-7, for a particular memory circuit in pixel circuitry 130.
The output of OR gate 1792 i~ the DRAM SEL
(dynamic RAM select) ~ignal on line 1406. The DRAM

, .

~ ~ 2 ~

SEL signal is used in conjunction with other signals to select and write from a particular DRAM to the pixel memory circuits.
~ecoder 1804 has three other outputs.
These are the FST SE~ signal on line 1711, and the previously discussed COMM SEL signal on line 1778 and SLAVE SEL signal on line 1504. These signals are output from the decoder when it is not being used to enable RAM 1770 and the respective cirucit is activated.
The FST SEL (fail safe timer select) signal is input to the protection circuit 1717. The second input to this circuit is the D3 signal from the data bus. At a clock rate determined by the FST SEL signal the D0 signal is checked. This is done to determine if microprocessor 1702 is not performing its required functions. The FST B signal on line 1709 is output from the protection circuit and input to micropro-cessor 1702.
The BHE bar (bus high enable) signal on line 1724 also assists in enabling RAM 1768 when the high order bits D8-15 are written onto or read.
The CLK OUT signal on line 1508 is the main clock signal for operating the display processor circuitry. The CLK OUT signal, through flip flop 1781, clock~ controller 1776. ~owever, because the data input and the Q bar output are tied, the con-troller is clocked every two CL~ OUT pulses.
ROMs 1760, 1762, 1764 and 1766 and RAMs 1768 and 1770 are connected to data bus 1414 and addreqs bus 1412 conventionally.
Figure~ llA, llB, and llC show pixel cir-cuitry 130. Figure llA shows the circuitry that generates a majority of the signals used by the circuitry ~hown in Figure llB.
The graphic plane refers to the scrolled information on the display screen. The character ~_ ~ 2 and enhancement planes refer to the fixed characters on the di~play ~creon Re~erring to Figuro llA the output o~ 24 MHz o$eillator 1902 after being inverted ~y lnverter 5 1904 is the PIX CL~ signal on line 1906 Thi~ i~
the clock siqnal for elocking most of the pixel circuitry The ~IX CL~ si~nal clocks 4-bit counter 1908 The output signals ~rom the ~-bit counter are input to PROMs 1910 and 1912 and latch 1926 The Q outpu~ of flip flop 2020 i8 also input to PROMs 1910 and 1912 PROM~ 1910 and 1912 are enabled ~y a pull-up signal inverted by inverter 1940 Tho parallel 8-bit output of PROM 1910 is input to latch lS 1938 This latch i~ clocked by the PIX CL~ signal The following signal~ are output from thi~ latch wh-n clocked PROCRDWR bar (line 1946) - proces~or read/write Thi~ provides a time window in which the proce~sor can read rom or write into memory PRCALST ~line 1950) - proce~sor address-latch ~trobe It strobe~ the processor addre~s latch-s DSPALST ~line 1952) - display proces~or address-latch ~trobe It strobe~ the display address latches.
CAS b-r ~line 1954) - column addres~ latch trobo It strobes the column addres~ l~tche~
RAS bar (line 1956) - row addr~ss latch ~trobe It ~trobe~ th~ row-addre~s latcho~
THS/CHRST (l$n- 1958) - thi~/charactor ~trobo It ~trobe~ dlffer-nt latches wlth data from th- ~erl-~ m~morio~ or tho ~raphic and charact~r planos NXT/ENHST ~lin~ 1960) - next/onhancement ~trob~ It trobe~ to latch the noxt graphic plan~
and onhancement plane data -82- 132~3~
GLSEL ( line 1962) - a graphic latch select.
It selects which graphic data latch is used for a 16-pixel area of the display screen.
The 8-bit output o EPROM 1912 is input to latch 1964. This latch is clocked by the PIX CLR
signal on the same clock pulse that latch 1938 is clocked. The 8-bit output of latch 1964 is input to latch 1968. This latch is clocked a half-clock pulse after latch 1964 because inverter 1936 is disposed in the clock line to latch 1968. The following siqnals are output by latch 1968:
RCSELP (line 1970) - row/column select for the processor memory.
RCSELD (line 1972) - row/column select for the display memory.
RCLCH (line 1974) - row/column select latch clock.
PROCWR bar (line 1976) - processor write.
This signal is for writing data into the processor memory.
CEPS (line 1978) - character/enhancement plane select. This signal selects the proper char-acter/enhancement plane.
ADVRFCT (line 1980) - the advanced refresh count. This signal is used by the DRAMs.
HORIZ ADV (line 1982) - horizontal advance.
This signal runs the graphic plane address counter.
WNDWSTRB (line 1984) - window strobe.
Thi~ signal strobes the current graphic display addresse~.
The inputs to CRT controller 1998 will now be discussed.
The RD bar and WR bar signals on lines 1402 and 1404, re~pectively, are input to OR gate 1986.
The output of thi~ gate i~ inverted by inverter 1988.
Tho output of the inverter is input to the data strobe input to the CRT controller l99B. Once con~igured, -83- 3~ ~ 2 ~
CRT controller 1998 outputs the horizontal address bits HI~-7 on line 2004 and the vertical address bits VI~-7 on line 2006. The contents of these signals are deterrnined by the parallel 8 bit data bus signals D~7 on line 1414 and parallel 4 bit address A1-A4 on line 1412.
The CRT SEL signal on liue 1416 is input to controllèr 1998 a*er inversion by inverter 1992. T~is signal selects the controller for access.
The CHAR CLK (character clock) signal on line 2000 is generated by the terminal count of 4 bit counter 1908. The CHAR CLEC signal is used for clocldng at a rate of 1/16th of the pixel rate. After being inverted, the CEIAR Cl,K signal is ~put to the character clock input of controller 1998. It is also input to a data input of latch 1926 and the clock inputs of fli~ flops 2020 and 2024.
The data input to ~ip flop 20Q0 is the BLANK signal from controller 1998 on line 20û2. This signal indicates the non-active portion of the horizontal and vertical scans. As stated~ the Q output of flip flop 2020 is input to PROMs 1910 and 1912. The Q bar outp'ut of flip flop 2020 is input to the data input of flip flop 2024. T~e Q output of flip flop 2024 is the H/V BLANE~ bar signal on line 20Q6. This signal indicates the blank portions of the horizontal and vertical scans.
There are two other outputs from CRT controller 1998. The first is the V.SYNC bar signal on line 1344 (after being inverted by inverter 2010). The second is the H.SYNC signal on line 137Q The H.SYNC
signal output on line 1320 is input to protection circuit 1373. This circuit prevents the H.SYNC si~al from over driving the horizontal drive circuit.
The output of the protection circuit is the H.DRIVE signal on line 1371.
These signals are input to the CRT driver (Figure 7A) for driving the screen display.

.;.

1 3 ~

The H/V BLANK bar signal is also a data input to latch 2028. This latch is clocked by the PIX CLK signal. The output of the latch i8 delayed 3 clock pulses by a series of tied inputs and outputs of the latch. The output of this latch is input to OR gate 2046.
The other data input to latch 2028 is the GST signal on line 2018. When the latch is clocked by the PIX CLK signal the GOLST signal on line 2016 is output from the latch based on the logic value of the GST signal. The GOLST signal is the graphic plane output latch strobe signal. This strobes the current graphic plane output word.
The other input to OR gate 2046 is the Q bar output of ~lip 1Op 2042. This flip flop is clocked by the output of decoder 2032 on line 2040.
This decoder selects the display video function.
The enabling input to decoder 2032 is the VID FCN SEL signal on line 141B. Depending on the state of address bits Al-3, one of the four functions is selected.
If line 2034 is selected, flip flop 2050 is clocked. The Q output of flip Elop 2050 is the GPS (graphic plane select) signal on line 2052.
If Iine 2036 is selected, flip flop 2054 is clocked. The Q output of flip flop 2054 is the BLINK (display blink) signal on line 2056.
If line 2038 i~ selected, it will clock flip flop 2058. The Q bar output of flip flop 2058 is input to the SEL A/B (A bar) input of multiplexer 2068. The signals input to the data inputs of multi-plexer 2068 are the VID signal on lino 2062 (input to the A0 input) and it~ complement (input to the B0 input). The state of the selection input deter-mine~ whether the A0 or B0 inputs is selected foroutput as the VIDEO OUT si~nal on line 1360.

-85- ~ 3 ~ J ~3 ~
If line 2040 is selected, flip flop 2042 is clocked. The Q bar output of flip flop 2042 is the second input to OR gate 2046.
The output of OR gate 2046 is the signal that enables multiplexer 2068 for output of the VIDEO OUT signal on line 1360.
The signal input to the data inputs of flip flops 2050, 2054, 2058 and 2042 is the DO signal from the data bus.
The inputs to latch 1926 are the 4-bit output of 4-bit counter lgO8 and the CHAR CLK signal on line 2000. This latch is clocked by the inverted PIX CLK signal. When clocked, the outputs of the latch are the pixel address PIXO-3 signals on line Z012 and the FRST PX si~nal on line 2014. The FRST PX
signal represents the first pixel position for a word on the screen.
Figure 11B shows CRT memory control gate array 2102, scroll/pixel gate array 2190 and a series of DRAMs and latches used by both gate arrays. Many of the signals input to and output from both gate arrays have been described. Those signals will not be redescribed here~
Again referring to Figure 11B, DRAMs 2118, 2120, 2122 and 2124 are used for the graphic plane.
DRAM3 2146, 2148, 2150, 2152, 2186, 2188, 2191, and 2200 are shared memory by the character and enhance-ment planes, and by the trend section.
The parallel 8 bit GRO-7 (graphic plane address) signal i5 input to latch 2114. When clocked, the latch places the latch address values on address bus 2116. The parallel 8 bit CERO-7 (character/
enhancement plane address) signal is input to latch 2142. When this latch i~ clocked, it places the latched addres~ value~ on address bus 2144. Both latches are clocked by the RCLCH signal on line 1974.

. ' . :

~32l~s~

The parallel 16 bit GM00-15 signal on line 2126 is the 16 bit data bus that connects convention-ally to the graphic plane DRAMs. The parallel 16-bit CETOO-15 signal on line 2160 i~ the 16-bit data bus that connects conventionally to the character/
enhancement/trend DRAMs. The CAS bar (column address strobe) signal on line 1954 and RAS bar (row address strobe) signal on line 1956 connected to each o the DRAMs and strobe them conventionally.
The high order data bits, D8-15, for the graphic plane DRAMs and the character/enhancement/
trend DRAMs have separate output enable (OE bar) and write enable (WR bar) controls. This is also true for the low order bits, DO-7, for the graphic plane DRAMs and the character/enhancement/trend DRAMs.
The following are the separate write enable and output enable signals for the DRAM~.
OEGL (line 2104) - output enable graphic plane low (low means bits GM00-7).
WEGL (line 2106) - write enable graphic plane low.
OEGH (line 2108) - output enable graphic plane high (high means bits GM08-15).
WEGH (line 2110) - write enable graphic plane high.
OECEL (line 2130) - output enable character/
enhancement plane low ~low means bits CET00-7).
WECEL (line 2132) - write enable character/
enhancement plane low.
OECEH (line 2134) - output ena~le character/
enhancement plane high (high means bits CET08-15).
WECEH (lino 2136) ^ write ena~le character/
enhancement plane high.
OETL ~line 2170) - output enable trend low (low mean~ bits CETo0-7).
WETL (line 2172) - write enable trend low.

... , . '' ~

.

-87- ~32'~ ~3~
OETH (line 2174) -output enable trend high (high means bits CET08-15).
WETH (line 2176) - write enable trend high.
The additional lines between CRT memory gate array 2102 and scroll/pixel gate array 2190 are the parallel 8 bit horizontal address bus HA9-7 on line 2182; the parallel 8 bit vertical address bus VA0-7 on line 2180; and the parallel 8 bit horizontal graphic address bus HGA9-7 on line 2184. The func-tion of these address busses are known by one skilled in the art without further explanation.
Figure llC is a schematic diagram of the analog output section of pixel circuitry 130.
The inputs to decoder 2302 are the WR bar signal on line 1404, the ANALOG SEL signal on line 1422 and the control inputs address bits A4-6 on line 1412.
The WR bar and ANALOG SEL signals enable the decoder. The address bits A4-6 select the output of the decoder.
The output of decoder 2302 on line 2306 is input to the WR bar input of analog switch 2316.
This signal cause~ the analog inputs to the switch to be output. This output depends on the states of the eontrol inputs. The control inputs are the the Al-3 signals from the address bu~. The switch is enabled by the DO signal on line 1414.
The decoder output on line 2308 is input to the WR bar input o~ analog switch 2780. Similarly, the analog inputs to the switch are output according 'o the states of the control inputs, the Al-3 qignals from ths addre~s bus. The ~witch i~ enabled by the D~
signal on line 1414.
The docoder output on line 2304 i3 input tolthe WR bar and CS bar inputs of D/A convertor 2310.
Data bits D9-11 from line 1414 are the data inputs to the converter. D/A converter 2310 convert~ the -g data bus inputs to analog signals which are output from the converter on line 2311. The output of D/A
convertor 2310 on line 2311 is amplified by amplifier 2312 and input to the data inputs of analog switches S 2316 and 2780.
When analog switch 2316 is enabled by the Dp signal and the wR bar input has the proper logic state, the latched value-Q are output to the selected analog output lines. This energizes at least one of analog output ports 1-7, shown generally at 2322, after the signal has been processed by the appro-priate sample and hold circuit, shown generally at 2320. The eighth analog output port is an I/O
port for ECG signals.
Analog switch 2780 operates in the same manner as analog switch 2316, if line 2308 is selected by decoder 2302. Analog switch 2780 can select among four output lines; however, only three are actual output lines. The fourth, which is associated with ECG signals, is connected to the eighth analog output port. This port is for bi-directional communication of ECG information.
The first output of analog switch 2780 is associated with the VBEEp signal on line 1352, the second is associated with the VVOL signal on line 1350, and the third i~ associated with the VCONTR ~ignal on line 1362. Each of the three outputs is processed by the appropriate sample and hold circuit ~hown generally at 2390.
When the ECG TR~G OUT ~ignal 1s output rom analog switch 2780, it i9 input to sample and hold circuit shown generally at 2390. The ECG TRIG OUT
signal i~ output from the sampl- and hold circuit on line 2400 and input to the ECG SYNC IN/OUT port for transmission to the xternal ECG device.
The amplified output of D/A convertor 2310 ~s also input to comparator 2412. The other input -89- 1 3 ~ g to the comparator is the VBATT signal from the battery. The comparator determines if the proper battery voltage is present. The output of the com-parator 2412 is input to line driver 2408.
The other input to driver 2408 is the out-put of comparator 2404. The inputs to this comparator are ECG TRIG IN signal received from an external device and the ECG TRIG IN signal after processing by peak detector 2401. When the ECG SYNC IN/OUT
port is used as an input port, the ECG TRIG IN
signal is on line 2400. This signal is input to peak detector 2401 and follower 2403. The output of follower 2403, on line 2405, is the same as the input signal plus a delay. ~he peak detector detects the peak of the ECG TRIG IN signal and divides the peak signal in half. This signal is output from the peak detector on line 2407 and input to comparator 2404.
Comparator 2404 compares these two valves so that the R-wave in the ECG TRIG IN signal can be detected. The output of comparator is input to the data input to line driver 2408.
When the line driver is enabled by the A/D
SEL signal on line 1424, the signals input ~o the line driver are placed on the D0 and D7 bit~ of the data bus on line 1414.
Figures 12A, 12B and 12C show scroll/pixel gate array 2190 shown in Figure llB.
Referring to Figure 12A, generation of the horizontal and tho vertical address bit~ is now de~cribed.
Th- parallel 8-bit Qignal HI~-7 on line 2004 i5 input to the data inputs of latch 2502. The latch i8 enabled by the CHAR CLK signal on line 2000.
The latch i~ clocked by th~ PIX CLK ~ignal on line 1906. When the latch is enabled and cloc~ed, the output i8 the parallel 8-bit signal HA0-7 (horizontal addre~ bits) on line 2182.

go ~32~
The ADVRFCT signal on line 1980 is input to the clock inputs of 4-bit counters 2506 and 2508.
4-bit counter 2506 will count out, then its terminal count will start 4-bit counter 2508.
The 4-bit output of counter 2506 is input to multiplexer 2530. Also input to this multiplexer are the parallel 4-bit vertical addresses VI0-3 on line 2006. Similarly, the 4-bit output of counter 2508 and the parallel 4-bit vertical addresses VI4-7 on line 2006 are input to multiplexer 2530.
The selection of the 4-bit counter input or the VI0-3 input as the output o multiplexer 2530 is determined by the state of the Y/V BLAN~ bar signal on line 2026. In like manner, whether the 4-bit counter input or the VI4-7 input is selected as output of multiplexer 2532 is determined by the state of the H/V BLANK bar signal.
The RCCLR signal on line 2504 is input to counters 2506 and 2508. This signal clears the counters.
The outputs of multiplexers 2530 and 2532 are input to latch 2536. When this latch is clocked by the PIX CLK signal, the latched values are output as the VA0-7 (vertical addres-~ bits) signals on line 2180.
Referring to Figure 12B, the generatio~ of the Y.GA3-7, the GST, and the VERT INTR signals will be described.
The SCROLL SEL signal on line 1420 and the WR bar signal on line 1404 are the enabling inputs to decoder 2590. Address bits Al-3 input on line 1412 control the output from decoder 2590.
Ono output of decoder 2590 is the RCCLR
signal on 2504. This i8 used in Figure 12A to clear counters 2506 and 2508.

-gl~
The first input to NAND gate 2660 i~ the output of the OR gate 2556. The inputs to this gate are the outputs of 8-bit magnitude comparator 2552.
The first input to comparator 2552 i9 the parallel 8-bit signal VIO-7 on line 2006. This signal i8 input to the P data inputs of 8-bit magnitude comparator 2552. The parallel 8-bit signal D~-7 from the data bus on line 1414 is input to latch 2554.
This latch is clocked by an output of decoder 2590.
When clocked, the DO-7 signal are input ~o the Q
data inputs of 8-bit magnitude comparator 2552.
The output of the comparator is based on satisfying the conditions P>Q bar or P=Q bar. These outputs are input to OR gate 2556. The output of this OR gate is input to NAND gate 2660.
The second input to NAND gate 2660 is the output of 8-bit magnitude comparator 2568. The output of this comparator is determined as follows:
The parallel 8-bit signal Dp-7 from the data bus is input to latch 2604. The second output of decoder 2590 clocks latch 2604. When clocked, the 8-bit output of latch 2604 is input to the Q
data inputs of 8-bit magnitude comparator 2568.
The parallel 8-bit signal VIO-7 on line 2006 i~ input to the P data inputs of comparator 2568.
The output of thi~ comparator is conditioned on satis-faction of P>Q bar. When this condition is satis~ied, the signal output from the comparator changes ~tate and is input to NAND gate 2660.
The third input to NAND gate 2660 is the output o 8-bit magnitude comparator 2614. The output of this comparator is determined aQ follow~:
The parallel 8-bit Rignal HAO-7 on line 2182 i~ input to the P data inputs o 8-bit magnitude 35 comparator 2614. The parallel 8-bit signal D3-7 from the data bu~ is input to latch 2613. The latch is clocked by the fourth output of decoder 2590.

, .

1~2~

When clocked, the parallel 8-bit output of latch 2613 is input to the Q data inputs of comparator 2614.
The 8-bit output of latch 2613 on line 2610 is also termed HEND~-7 (horizontal end of the graphic plane window address).
The output of 8-bit magnitude comparator 2614 is determined by satisfaction of the condition P>Q bar. When this condition is satisfied, the state of the output changes. The output of comparator 2614 is input to NAND gate 2660.
The fourth input to NAND gate 2660 is the output of OR gate 2626. The inputs to the gate are the outputs of 8-bit magnitude comparator 2624. The states of the comparator' Q outputs are determined as follows:
The parallel 8-bit signal HAP-7 on line 2182 i~ input to the P data inputs of comparator 2624.
The parallel 8-bit signal DO-7 from the data bus is input to latch 2623. This latch is clocked by a third output of decoder 2590. When the latch is clocked, the parallel 8-bit output is input to the Q
, data inputs of comparator 2624. The outputs of com-parator 2624 are conditioned on satisfying P>Q bar or P=Q bar. Satisfaction of these condition~ changes the logic ~tate~ of the output~. The comparator's outputs are input to OR gate 2626. The output of OR
gat~ 2626 i~ the ourth input to NAND gate 2660.
The output of latch 2623 i~ al~o termed HBEC~-7 (horizontal beginning of the graphic plane window addre~s). The parallel i-bit signal HBEGO-3 i8 on line 2620 and the parallel 4-bit ~ignal B EG4-7 is on line 2622.
The output o 8-bit magnitude comparator 2568 is al~o input to the data input of flip 10p 2562. Thi~ flip flop is clocked by the WNDWSTRB
15~1 o~ 1984.

_93_ 1 3 ~ 3 The Q bar output of flip flop 2562 is the VERT INTR signal on line 1408. The VERT INTR signal is input to display processor 1702 (Eigure 10).
The output of NAND gate 2660 is input to flip flop 2670. This 1ip 1Op is clocked by the WNDWSTRB signal on line 1984. The preset input to flip flop 2670 is controlled by the Q output of flip flop 2662. The data input to flip ~lop 2662 is the D~ signal on line 1414. The clock input is the SSEL-7 output from decoder 2590.
The Q output of flip flop 2670 is input to the selection inputs of multiplexers 2644 and 26580 The Q bar output is input to the selection inputs of multiplexers 2726 and 2728. The Q bar output is also input to NAND gate 25B2.
The Q output of flip flop 2670 is input to the data input of 1ip 1Op 2676 and to AND gate 2686.
Flip flop 2676 is clocked by the ERST PX signal on line 2014. The preset input to the flip flop is connected to the Q output of flip flop 2662.
When flip flop 2676 is clocked, its Q bar output is input to AND gate 2686. This signal also enables 4-bit counter 2692 and i~ input to the selection input of multiplexer 2694.
Having de~cribed each input to AMD gate 2686, the output of thi~ gate is the GMVE (graphic memory video enable) ~ignal on line 2688. Thi~
Jignal causes blanking of the memory at the end o the graphic plane window.
The inputs to 4-bit counter 2692 will now be de~cribed.
The parallel 8-bit signal D0-7 on lino 1414 i~ input to latch 2639. This latch is clocked by an output o decoder 2590. Whon clocked, the first 4-bits are input to 4-bit counter 2692. The remaining 4-bits are input to multiplexer 2644. `

_94_ ~32~
The PIX CL~ signal on line 1906 is input to the clock input of 4-bit counter 2692. The parallel 4-bit output of counter 2692 is input to multiplexer 2694. The other input to multiplexer 2694 is the parallel 4-bit signal PIX~-3 on line 2012.
Based on the control input to this multiplexer, either the parallel 4-bit PIXa-3 signal or the parallel 4-bit output of 4-bit counter 2692 is selected for output to latch 2708. The last input to latch 2708 is the FRST PX signal on line 2014.
When latch 2708 is clocked by the PIX CBK
signal on line 1906, the output is the GPXP signal on line 2718, the GPXl signal on line 2716, the GPX2 signal on line 2714 and the GPX3 signal on line 2712.
These signals are the graphic plane pixel select line~.
The final output of latch 2708 is the ~PXL
signal on line 2710. This signal is for latching the first pixel word.
The GPXO-3 signals are input to NAND gate 2720. The output of NAND gate 2720 is input to OR
gate 2724. The second input to that gate is the FPXL signal on line 2710. The output of OR gate 2724 i~ the GST ~graphic plane strobe) ~ignal on line 2018.
4-bits of the output of latch 2639 are input to multiplexer 2644. The other parallel 4-bit signal input to multiplexor 2644 is the HBEGa-3 signal on line 2620. The output ~election input to multi-plexer 2644 is the Q output of flip flop 2670.
30 - The output of multiplexer 2644 is input to 4-bit counter 2702. This counter i8 enabled by tho output of NOR gate 2682. The inputs to the NOR gate are as follow :
A first input i~ the Q bar output of flip flop 2670.
With respect to the second input, the parallel 8-bit siqnal SC~-7 on lino 2576 is input to .

.
.

_95_ ~32'~
the P data inputs of 8-bit magnitude comparator 2572.
The parallel 8-bit signal HEND0-7 is input to the Q
data inputs of the comparator. The output of the comparator is conditioned on the satisfaction o P>Q
bar. The satisfaction of this condition changes the signal's logic state.
The output of 8-bit magnitude comparator 2572 is input to inverter 2580. The inverter's output is input to NAND gate 2582. The second input to this gate is the WNDE~ bar signal on line 2581. The WNDEF bar signal determines if the current window available for scrolling is scrolled or not.
The third input to NAMD gate 2582 is the Q
bar output of the flip flop 2670. The output of NAND gate 2582 is the second input to NOR gate 2682.
Once enabled by the output of NOR gate 2682, the 4 bit counter 2702 is clocked by the PIX CLK
signal on line 1906. This signal is inverted by inverter 2659. As such, counter 2702 is clocked one half clock pulse after other components clocked by the PIX CLK signal.
The parallel 4-bit output of 4 bit counter 2702 i~ input to multiplexer 2726. The output is also the parallel 4-bit signal SC0-3 on line 2576.
These are used as the graphic plane count bit~ for the scrolled areas.
The other input to multiplexer 2726 is the parallel 4 bit signal HAO-3 on line 2182. Based on the state o the Q bar output o flip flop 2670, one of the 4-bit inputs is output as the HGAO-3 signal.
These are 4 bits of the 8-bits of the horizontal graphic plane address.
Tho parallel 8-bit signal, DO-7 on line 1414 is input to latch 2652. The latch i~ clocked by an output of decoder 2590. When clocked, the first 4-bito are input to multiplexer 2658. The other 4-bit input to multiplexer 2658 is the parallel 4-bit ~ 3 2 ~

signal HBEG4-7 on line 2622. According to the state of the Q output of flip flop 2670, one of the 4-bit inputs is selected and output from the multiplexer.
The output o multiplexer 2658 is input to 4 bit counter 2704. The terminal count of 4 bit counter 2702 starts counter 2704. The output of NOR
gate 2682 enables 4-bit counter 2704.
The HORIZ ADV signal is input to the enable trickle input of counter 2702 or controlling the count.
The output of 4-bit counter 2704 is input to multiplexer 2728. This output is also the 4 bit SC4-7 signal (on line 2576). These are the remaining horiæontal graphic plane count bits for the scroll areas.
The second input to multiplexer 2728 is the parallel 4-bit signal HA4-7 on line 2182. Based on the state of the Q bar output of flip flop 2670, one of the 4-bit inputs is output as the HGA4-7 signal on line 2184.
Figure 12C shows generation of the VID
signal on line 2062. The VID signal controls the information on the display screen.
With respect to the character plane, the parallel 4-bit signal P~XO-3 on line 2012 i~ input to latch 2802. Thi~ latch i8 clocked by the PIX CLK
~ignal on line 1906. When clocked, the parallel 4-bit output i8 input to the control inputs of the 16-bit data selector 2822. The signals output by latch 2802 are also termed the P~XOL-3L signals on line 2804.
The data inputs to 16-bit data selector 2822 are the CETOO-15 signals on line 2160 after being latched twice.
The CETOP-7 signals on line 2160 are input to latch 2806 and the CET08-15 signal~ on line 2160 are input to latch 2814. Both latches are clocked 1 3 2 ~ 3 3 ~
-g7-by the THS/CHRST signal on line 1956. The output of latch 2806 is input to latch 2808 and the output of latch 2814 is input to latch 2818. ~atche~ 2808 and 2818 are clocked by the FPXL signal on line 2710.
When clocked, the outputs of thece latches are input to the sixteen data inputs of 16-bit data selector 2822. Bas~d on the states of the PIXOL-3L signals, an output is selected. The selected output is input to latch 2852.
With respect to the enhancement plane, the CETO~-7 signals are input to 16-bit data selector 2848 after first being latched by latches 2826 and 2830.
Similarly, the CET08-15 signals input to 16-bit data ~elector 2848 are irst latched by latch 2840 and t~en by latch 2844.
The first set of latches, 2826 and 2840, are clocked by the NXT/ENHST signal on line 1960.
The second set of latches, 2830 and 2844, are clocked by the FPXL signal on line 2710.
The parallel 4-bit signal PIXOL-3L on line 2804 is input to the control inputs of data selector 2848. The output of 16 bit data selector 2848 is input to latch 2852.
A third input to latch 2852 is the BLINK
signal discussed previously.
The fourth input to latch 2852 is associated with the graphic plane.
The control input to 16 bit data selector 2888 is th- 4 bit GPX0-3 3ignal on lines 2718, 2716, 2714 and 2712.
The graphic plane data is double latched liXo the character and the enhancement plane data.
The GMOO-7 signals on line 2126 are latched fir~t by latch 2860 and then by latch 2884 beore input to data selector 2888. Tho GM08-15 signals on line 2126 are latchod first by latch 2864 and then by latch 2886 before input to data ~elector 2888. The 3 ., TH~-15 signals (on line 2862), shown at the outputs of latches 2860 and 2864, are signal designations to show the connection of the first set of latches to the input lines the latches 2884 and 2886 when this first set of latch is clocked by the THS/CHRST signal on line 1956.
The second set of latches, 2884 and 2886 are clocked by the GOLST signal on line 2016. When the second set of latches are clocked, their data is input to the 16-data inputs of 16 bit data selector 2888.
In a second instance, the GMo0-7 signal are latched first by latch 2880 and then latch 2884.
The GM08-15 signals are first latched by latch 2882 and then latch 2886.
In this case, the first sets of latches, 2880 and 2882, are clocked by the NXT/CHRST signal on line 1960. The second set of latches, 2884 and 2886, are clocked by the GOLST signal on line 2016.
The two first sets of latches, namely 2860 and 2864, and 2880 and 2882, are output enabled by an asynchronous flip flop consisting of NAND gates 2868 and 2872, and inverter 2866. One output of the flip flop connects to the output enable inputs of latche~ 2860 and 2864. The other output of the flip flop connect~ to the output enable inputq of latches 2880 and 2882. The GLSEL is input to the flip flop on line 1962. The state of the GLSEL signal deter-mines which first set of latchos i~ output enabled.
Once the data ls input to 16-bit data selector 2888, tho output of the data selector i~
enabled by the GMVE signal on line 2688. When enabled, tho selected output i~ input to latch 2852.
The PIX CLK signal on line 1906 clocXs latch 2852. The outputs of latch 2852 are input to a ~eries of logic gates. These gates are inverter~~, 2B94 and 2902, NAND gates 2898 and 2910, and NOR
-- .,.' `~

,;

~324~3~

gate 2922. Processing of the outputs of latch 2852 by these gates is known by one skilled in the art without further explanation.
The output of NOR gate 2922 is input to the data input of flip flop 2930. The PIX CLK signal on line 1906 clocks flip flop 2930. When clocXed, the Q output is the VID signal on line 2062.
Figure 13 shows the CRT memory control gate array.
The DRAM SEL signal in line 1406 clocks flip flop 3058. The Q output of flip flop 3058 is the data input of flip flop 3062 which is clocked by the PIX CL~ signal on line 1906.
The Q output of flip flop 3062 is input to the data input of flip flop 3059. This output is also input to the data input of multiplexer 3078.
This multiplexer's output is the DARDY signal on line 1410.
The Q bar output o flip flop 3062 is input to the preset input of flip flop 3059, to NAND gate 3074 and to the clear bar input of flip flop 3070.
The clock input to flip flop 3059 is the PROCRDWR
signal on line 3002.
The Q output of 1ip flop 3059 is tied to two inputs of NAND gate 3055. The other input to NAND gate 3055 i9 the WR bar signal on line 1404.
The output o NAND gate 3055 i~ the ACTWR bar signal on line 3001. The ACTWR bar signal indicate~ that the microproce~or i9 actively writing into a DRAM.
Tho Q bar output of 1ip flop 3059 i9 input to the data input o flip Elop 3070. The PROCRDWR
bar signal on line 1946 clocks flip flop 3070. The Q output of flip flop 3070 i~ the ~econd input to NAND gate 3074. The output of NAND qate 3074 is input to the preset input o the flip flop 3058.
Generation of the high and low output enable and write enable signal~ for the graphic ~ 3 2 ~
1oo-plane, character/enhancement plane and trend section will be described.
Referring to Figure 13, the write enable signals for the graphic plane, character/enhancement plane and trend section are determined by the outputs o NAND gates 3004, 3006, 3008, 3010, 3012 and 3014.
Two inputs to each gate are the same. These inputs are the ACTWR bar signal on line 3001 and the PROCWR
bar signal on line 1976. The third signal input to a particular NAND gate is one of the six signals generated by the display processor for use in deter-mining the selection of the graphic plane high or low, character/enhancement plane high or low, and trend section high or low.
The GRPHH signal on line 1790 is the third input to NAND gate 3004, whose output is the signal WEGH on line 2110. The GRPHL æignal on line 1802 i8 the third input to NAND gate 3006, whose output is the WEGL signal on line 2106. The CHRENH signal on line 1788 is the third input to NAND gate 3008, whose output is the WECEH signal on line 2136. The CHRENL
signal on line 1800 is the third input to NAND gate 3010, who~e output is the WECEL signal on line 2132.
', The TRNDH signal on line 1786 is the third input to NAND gate 3012, whose output is the WETH signal on line 2176. The TRNDL signal on line 1798 is the third input to NAND gate 3014, whose output i~ the WETL signal on line 2172.
The first input to NOR gates 3016, 3018, 3020 and 3022 is the PROCRDWR signal on line 3002.
The second input to NOR gate 3016 is the GRPHH signal.
The output of NOR gate 3016 is the OEGH signal on lino 2108. Tho ~ocond input to NOR gate 3018 is the GRPHL signal. The output oE NOR gate 3018 i~ the OEG~ ~ignal on line 2104. The second input to NOR
gate 3020 i8 the CHRENN ~ignal. The output of NOR
gate 3020 is the OECEH signal on line 2134. The --lol- 1 3 ~ o second input to NOR gate 3022 is the CHRENL signal.
The output of NOR gate 3022 is the OECEL signal on line 2130.
The first two inputs to NAND gate 3024 are the PROCRDWR bar signal on line 1946 tied to two inputs. The third input is the TRNDH signal on line 1786. The first input to NAND gate 3026 is the PROCRDWR bar signal on line 1946. The second and third inputs are the TRNDL signal on line 1798 tied to two inputs.
The output o NAND gate 3024 is the OETH
signal on line 2174. The output of NAND gate 3026 is the OETL signal on line 2170.
The inputs to NOR gate 3034 are the CHRENH
signal on line 1788 and the TRNDH signal on line 1786. The output o NOR gate 3034 is the OECETH
signal on line 3042.
The inputs to NOR gate 1038 are the CHRENL
signal on line 1800 and the TRNDL signal on line 1798. The output of NOR gate.3038 is the OECETL
signal on line 3044.
Bus buffers 3045 and 3047 are or transfer-ring data from the data bus, DO-15, to the graphic plane memory outputs, GMOO-lS. The low order bits are handled by bus buffer 3045 and the high order bits are handled by bus buffer 3047. In like manner, bus buffers 3102 and 3112 ar* for transferring data from the data bus, DO-15, to the character/enhancement/
trend memory outputs, CET03-15. The low order bits are handled by buq buffer 3102. The high order bits are handled by bus buffor 3112.
The signal enabling bus buffer 3045 i~ the output of NAND gate 3032. The inputs to NAND gate 3032 are the WR bar signal on line 1404, the PROCRDWR
bar signal on line 1946 and the GRPHL ~ignal on lina 1802.

.
, ` -102_ ~ 32~
The signal enabling bus buffer 3047 i8 the output of NAND gate 3030. The inputs to this gate are the WR bar signal on line 1404, the PROCRDWR bar signal on line 1946, and the GRPHH signal on line 1790.
The signal enabling bus buffer 3102 i~ the output of NAND gate 3040. The inputs for the NAND
gate 3040 are the WR bar signal on line 1404, the PROCRDWR bar signal on line 1946 and the OECETL signal on line 3044.
The signal enabling bus buffer 3112 is the output of NAND gate 3036. This gate's inputs are the WR bar signal on line 1404~ PROCRDWR bar signal on line 1946 and the OECETH signal on line 3042.
Latches 3090 and 3096 are to transfer data from the graphic plane memory outputs to the data bus. Latches 3104 and 3110 are to transfer data rom the character/enhancement/trend memory outputs to the data bus. All four latches are clocked by the PROCRDWR bar signal on line 1946. However, each of the four latches are output enabled by a different NAND gate. One input to the our NAND gates is the DT~R ~R bar) signal on line 1428. The second signal input to each gate will now be described.
NAND gate 3080 output enables latch 3090.
This latch transfers data ~rom the low order bits of the graphic plane memory output~, GM09-7, to the low order bitC of the data bus, DO-7. The second signal input to NAND gate 3090 is the GRPHL signal on line 1802.
NAND gate 3092 output onables latch 3096.
Tho latch transfers data from the high order bits o tho graphic plane memory output~, GM08-15, to the high ordor bits o tha data bus, D8-15. Tho ~econd signal input to NAND gate 3096 iB the GRPHH signal on line 1790.

, , ,,, . ., - .

;'' :

-103- 132~$3~, NAND gate 3098 output enables latch 3104.
Latch 310~ transfers data rom the low order blts of the character/enhancement/trend memory output~, CETO~-7, to the low order bits of the data bus, DO-7. ~ -.
5 The second input to NAND gate 3098 is the OECETL ..
signal on line 3044.
NAND gate 3106 output enables latch 3110.
Latch 3110 transfers data from the high order bit~
of the character/enhancement/trend memory outputs, CET08-15, to the hig~ order bits of the data bus, D8-15. The second input to NAN~ gate 3106 is the OECETH signal on line 3042.
Latch 3130 transfer~ the vertical address information in the VAO-7 signals to the graphic plane 15 addresse~, GRC-7. Latch 3146 transfers the vertical address inormation in the VAO-7 signals to the character/enhancement plane addresses, CERO-7.
Latch 3140 transfers the horizontal address information in the HGAO-6 signals and the GPS signal 20 to the graphic plane addre~ses, GRO-7. ~atch 3148 transfers the horizontal address information in the HA0-6 signal~ and the CEPS signal to the character/
enhancement plane addresses, CERO-7 .
The slgnal that clock~ latches 3130, 3140, 25 3146 and 3148 is the DSPALST signal on line 1952.
Enablement of these four latches is deter-mined by an asynchronous flip flop comprising NAND
gates 3116 and 3120, and inverter 3114. The output of NAND gate 3116 of the 1ip flop i8 input to NAND -. ;
30 gate 3124. The output of NAND gate 3120 o~ the flop ;:~
flop i5 lnput to NAND gate 3128. The second input ~
to NAND gateQ 3124 and 3128 i8 the DSPALST signal on . ~ P
line 1952.
The output of NAND gate 3124 i~ input to ;:
35 the output enable inputs of latche~ 3140 and 314B
(for the horizontal addres~e~). The output of NAND
v~` :'`

.

.:

- \
-104- 132~3~
gate 3128 is input to the output enable inputs of latches 3130 and 3146 (for the vertical addresses).
The RCSELD signal on line 1972 is input to the flip flop. When the DSPALST signal has the proper state, the state o the RCSELD signal determines whether row or column address information is trans- -ferred.
Latch 3142 transfers the row address infor-mation in the Al-8 signals to the graphic plane addresses, GR~-7. Latch 3150 transers the row address information in the Al-8 signals to the character/enhancement plane addresses, CERa-7.
Latch 3144 tran~ers the column address information in the A9-16 signals to the graphic plane addresses! GRO-7. Lateh 3175 transfers the column address information in the A9-16 signals to the character/enhancement plane addresses, CER0-7.
The signal that clocks latches 3142, 3144, 3150 and 3175 is the PRCALST signal on line 1950.
Enablement of the four latches is deter-mined by an asynchronous flip flop comprising NAND
gates 3162 and 3166, and inverter 3180. The output of NAND gate 3162 of the flip flop is input to NAND
gate 3170. The output of NAND gate 3166 of the flip flcp is input to NAND gate 3172. The Qecond input to NAND gates 3170 and 3172 i8 the PRCALST signal on line 1950.
The output of NAND gate 3170 is input to the output enable inputs of latches 3144 and 3175 (for the column addresses). The output of NAND gat~
3172 i8 input to the output enable inputs of latche~
3142 and 3150 (for the row addresses).
The RCSELP ~ignal i~ input to the flip flop on line 1970. When the PRCALST signal has the proper state, the state of the RCSELP ~ignal determines whether row or column addres~ information is ~ran~-ferred.

-105~ ,r3 ~
Figure 14 shows the digital output board 140 (Figure 1). The TxD signal on line 1510, the RxD signal on line 1512, the DTR signal on line 1514, the DSR signal on line 1516, the RTS signal on line 1518 and the CTS signal on line 1520 are for com-munications between controller 1776 (Figure 10A) and an external device connected to digital connector 3302.
The optional digital output connector 3304 is also shown in Figure 14. The RD bar signal on line 1402, the WR bar signal on line 1404, the parallel 8 bit data bus signal D0-7 on line 1414, the DT/R (R bar) signal on line 1428, the parallel 3 bit address bus Al-3 on line 1412, the SLAVE SEL
signal on line 1504, the SLAVE INTR slgnal on line 1506 and the CL~ OUT signal on line 1508 are for communications with and control of an external device by the microprocessor 1702 (Figure 10A).
Referring to Figure 15, the knob board 144 and five button panel 148 for control of the system of the present invention are shown.
Manual movement of knob 3410 changes the output to flip flops 3416 and 3426. The knob output to flip 1Op 3416 i~ proces~ed by Schmitt trigger 25 3414 before input. The knob output to flip flop 3426 i8 proces~ed by Schmitt trigger 3424 before input.
Flip flop~ 3416 and 3426 are clocked by the output of NAND gate 3417. When flip flop 3416 i8 clocked, the Q output i8 input to the data input of flip flop 3420. The output of flip flop 3416 is also one of the inputs to exclusive OR
gate 3438.
When flip flop 3426 i9 clocked, the Q bar output i~ input to the data input of flip flop 3430.
The Q bar output is also input to exclusive OR gates 3436 and 3440. -- . .

-106~
Flip flops 3420 and 3430 are clocked by the output of NAND gate 3417 Wllen these flip flops are clocked, the Q bar output of flip flop 3430 i8 the second input to exclusive OR gate 3440 and the Q
bar output of flip flop 3420 is the second input to exclusive OR gates 3436 and 3438 The outputs of exclusive OR gates 3438 and 3440 are input to exclusive OR gate 3~46 The output of exclusive OR gate 3446 is input to buffer 3204 The output of exclusive OR
gate 3436 is also input to buffer 3204 Another data input to buffer 3204 is the-Q bar output of flip flop 3403 The Q bar output is tied to four inputs of buffer 3204 The D0 signal on line 1414 from the data bus i8 input to the data input of the flip 1Op Flip flop 3403 is clocked by the output of NAND gate 3415 The inputs to this NAND gate are the WR bar signal on line 1404 and the DISP SEL signal on line 1602 The output of NAND gate 3417 also enables bufer 3204 The inputs to NAND gate 3417 are the RD bar signal on line 1402 and the DISP SEL signal on line 1602 When the buffer is enabled, the output~
rom exclusive OR gates 3436 and 3446 are placed on the data bu~, D8 and D9 The output from flip flop 3403 is input to alarm circuitry 3408 and used to driv- s-lected alarm~
The output of NAND gate 3417 is also the output enable input to buffer 3484 The data inputs to bufer 3484 are the output of alarm switch 3452, tho output of ON/STBY switch 3456 throuqh isolation diode 3455, the output o HELP switch 3460 and the outputs o BUTTONS 1-5, shown at 3464, 3468, 3472, 3476 and 3480, respectively The buttons and ~witchos are the operator interface or ~ystem operation and -107~ n~ n control When the buffer is enabled, the value~ of above-described input~ are placed on th~ data bu~
for tran~mi~sion to microproce~or 1702 Referrinq to Figure 1, th~ syst~m pow~ring the improved gas analyzer ~ystem i~ power supply 158, rectifier 160 and DC-DC eonverter 162 It ls a ~plit system with a fir t half pow-ring the di3play ~ection and the ~econd half powering the analog 3ection Each half o the system has it~ own battery backup This system is conventional and known to those ~killed in the art Figure 16 show~ a block diagram of the software modules or the display and analog proces-sors For reference purposes, the software program listing, attached as ApDendix 1, is divided into seven ~ections MAIN, ACQ, AOUT, AMENU, ALARM, COMM, DISPhAY, GAS, ~ISTORY, NENU, MENU 2, POUT, SYS, and WF The ~odules will be described and the areas of the sotware program that correspond to A particular module will be indicated An example of a code citation for identifying the location of a specific module is as follows MAIN pp 29-40 In Figure 16, the solid lines indicate data flow nd the dashed lines indicate control flow The Initialization ~ubroutine~ or both the display ~ide and analog side power up the sy~tem and carry out initial ~t-rt function~ and test~
Analog Initialization subroutine~ 3508 are found at MAIN pp 1-14 Di~play Inltialization ~ubroutine~
3572 are located at MAIN pp 5-29 The m~-ter Control Server i~ diaplay Control S-rv-r 3566 Analog Control Server 3522 i~ ~laved to ma~t-r Control Server 3566 The Control Serv-r~
control ov-r~ y~t-m operations The ~u~routine~
of di~play Control Servor 3566 monitor the button , knob~ nd ~witche~ o the control panel and appropri-~tely dju-t ~ystem oporation~ ba~d on their po~i-o tions. Both the analog and display Control Servers provide data to their respective Scheduler subroutines 3506 a~d 3562 on ~VHAT TO RUN".
Analog Control Server subroutines 3522 are found at AM~NU pp. 1~3.
Display Control Server subroutines 3566 are found at M~NU pp.1-277,<, ~s and MENUZ pp. 1-156. -:
Analog Scheduler 3506 and display Scheduler 3562 manage the processes and events for ~eir respective sides. The Schedulers insure the programmed functions for each side are carAed out. Analog Scheduler subroutines 3506 are located in the code at SYS pp. 81-104. Display Scheduler subroutines 3562 are also located at SYS pp. 81-104.
The Scheduler subroutines for both the analog and display side also include Clock Server subroutines. The Clock Server subroutines manage system timing of all events. Analog C lock Server subroutines 3507 are found at SYS pp. 7-18. Display Clock Server subroutines 3563 are also found at SYS pp. 7-18. ' -Acquisition SeIver 3504 accesses the raw data ~om the A/D
converter. It provides this data to Analog Meas~ement Tasks (AM'I~
subroutines 3528 to produce numerical output values. It also pro~ndes this data to Waveform Server subroutines 3530 to produce waveforms.
Acquisition Server subroutines 3504 are found at ACQ pp. 1-1Z7.
Waveform Server 3530 is the programming for transforming raw data into waveform data. The Waveform Server subroutines acquire data ` .
from Acquisition Server subroutines 3504, process it and transfer the data to Communications Se~ver subroutines 3552 that links the analog alld display sides. Waveform Server subroutines 3530 are found at WF pp. 1 26. `
Analog Measurement Tasks (AMI~ 3528 transform the raw data to ~ -usable information for display ''' ..'-`` ~v ' ~

'`'`'' ~'`' `` ~

-log- l~ 3~
and output purposes. AMT subroutines 3528 are found at GAS pp. 1-133.
Display Measurement Tasks (DMT) 3560 carry out data distribution to Trend Server cubroutines 3584, Alarm Server subroutines 3588, Display Server subroutines 3592, Digital Output Server subroutines 3596, and Analog Output Server subroutine~ 3600.
The DMT subroutines are found at GAS pp. 134-165.
Analog Data Distribution Buffer (ADDB) 3531 and Display Data Distribution Buffer (DDDB) 3561 serve as common locations or access to fast data. ADDB structures 3531 are found at COMM
pp. 1-92. DDDB structures are also found at COMM
pp. 1-92.
Communications Server 3552 communicates data between the analog and the display ~ides.
These subroutines are found out at COMM pp. 1-92.
Display Server 3592 lin~s to DMT subrou-tines 3560 and DDDB structures 3561. The Display Server subroutines receive the data from the DMT
subroutines and the DDDB structures, and process the data for numerical and graphical display. The Display Servor subroutines can be found at DIS~LAY
pp. 1-360.
Trend Server 3584 stores historical data from the DMT subroutines and provides lt to Display Server subroutines 3592, Digital Output Server sub-routine~ 3596 and Analog Output S-rver subroutines 3600 when ordered by Control Server ~ubroutines 3562 via Scheduler ~ubroutines 3562. Trend Server sub-routines 3584 can be found in the code at HISTORY
pp. 1-22.
Alarm Server 3588 links to the DMT sub-routinos and receives data rom those subroutines.
For output purposes, the Alarm Server ~ubroutine~
provide data for both audible and vi~ual alarms to --110~ r ~
the Display Server subroutines. Alarm Server sub-routines 3588 are found at ALARM pp. 1-37.
Digital Output Server 3596 processes the data from DMT subroutines 3560 and DDDB structures 3561 for digital output to external devices. This server's subroutines can be ~ound at COMM
pp. 64-81, POUT pp. 1-12.
Analog Output Server 3600 processes streams of output waveform and value data from the DMT sub--- 10 routines and DDDB structures 3561 for output to external devices. The subroutines for thiQ server are found ~OUT pp. 1-68.
The software operations will now be dis-cussed.
At system start up, Initialization sub-routines 3508 and 3572 initialize values for the system and conduct certain tests. In this proce-dure, data about the system is sent to Scheduler subroutines 3506 and 3562. Initialization sub-routines 3508 and 3572 also start the Clock Servers subroutines 3567 and 3563, respectively.
The initialized Analog Scheduler subrou-tines 3506 are directed what proces~e~ to run by the analog Control Server subroutines 3522. Analog Control Server subroutines 3522 determine the system configuration at system start-up and pass this information to the display Control Server subroutine~
3566. Tho di~play Control Server runs a subroutin-for a buttons and knobs check. As tho result o~ the buttons and knobs check, analog Control Server sub-routines 3522 determine the AMT ~ubroutines to run and ~end data to the Analog Scheduler subroutines a~
to the AMT ~ubroutine~ to run.
Analog Scheduler ~ubroutine~ 3506 and AM~
subroutines 3528, based on the data from analog Control Server ~ubroutines 3522, provide control lnformatlon to Acguisition Server subroutines 3504.

132~$

The Acquisition Server subroutines, when commanded, access the A/D converter data on line 3502. Acguisi-tion Server subroutine 3504 buffers the data until the Analog Scheduler subroutines direct that the S data be sent to AMT subroutines 3528 and Waveform Server subroutines 3530. AMT subroutines 3528 and Waveform Server subroutines 3530 transform the data according to their respective programming.
The Analog Scheduler subroutines acknowledge that data is being sent to AMT subroutines 3528 and Waveform Server subroutines 3S30. The Analog Scheduler subroutines command the AMT subroutines to run for slow data and command Waveform Server sub-routines 3530 to run for fast data.
AMT subroutines 3528 calculate the common equations used by all of the gases, e.g., the flow rate, pressure in the optical bench and temperature in the optical bench. These subroutines also calcu-late the partial pressure for each gas. Further, these subroutines calculate the position for super-imposing the "I" and "E" on the capnogram to indicate the transition points betweon inspiration/expiration and expiration/inspiration.
Tho AMT subroutines can have other sub-routines which can be commanded to run othor typo3of mea~uromont calculationq, e.g., SaO2 measurement tasks (oxygen saturation).
Analog Schedulor ~ubrout$nes 3506 contin-uously dir-ct Waveform Serv-r ~ubroutine~ 3530 to run for fast data. Wavoform Server subroutines 3530 send the transformed fast data to ADDB ~tructures 3531.
Analog Scheduler subroutine~ 3506 command Communica-tion~ Server subroutines 3552 to acquire the fast data in th- ADDB structuros and transmit it to DDDB
tructures 3561.
Analog Clock Server subroutines 3507 provide for the timed operation of the AMT subroutine~ and -112~ V 3 ~
Waveform Server operations by providing timed suspen-sions o processes and timed calls to subroutines.
Analog Scheduler subroutines 3506, based on the subroutines of Clock Server subroutines 3507, instruct Communications Server subroutineR 3552 to buffer data from Waveform Server subroutines 3530 and AMT subroutines 3528. Communications Server subroutines 3552 buffer data, and when time-out is reached, transfer the data to DMT subroutines 3560 and DDDB structures 3561 on the display side.
Now referring to the display side:
DMT subroutines 3560 receive data from the Communications Server subroutines as commanded by Display Scheduler subroutines 3562 and display Control Server subroutines 3566. The DMT subroutines carry out their required measurement tasks on the slow data.
The data output by DMT subroutines 3560 is input to the five output type servers. Scheduler subroutines 3562 command Trend Server 3ubroutines 3584, Alarm Server subroutines 3588, Display Server subroutine~ 3592, Digital Output Server subroutines 35g6, and Analog Output Server subroutines 3600 to receive specific data according to their programming.
Once the data is received, the respective server subroutines process the the data for output, or in the case of the Trend Server, process the data for historical purposes.
Di~play Scheduler ~ubroutine~ 3562 command Display Server ~ubroutines 3592, Digital Output Server subroutines 3596 and Analog Output Server subroutine~
3600 to acce~s the fast data in the DDDB structure~
3561. After acces~ing the data, each processe~ it according to it~ programming.
~igure 17 show a representative screen display of the multichannel gas analyzer system of the invent~on with respect to gas detection infor-mation.
The end-tidal and inspired C02 in mmHg are shown at 3602 and 3604, respectively; the end-tidal and inspired percent concentration of N20 are shown at 3606 and 3608, respectively; and the breath rate is shown at 3610.
A C02 capnogram is shown generally at 3612.
Superimposed on the capnogram at the inspiration and expiration transition points are the "I" and "E"
markings referred to previously. The positions of the "I" and "E" poin s are determined by the software ~ based on the measured value for the scrolling C02 ; capnogram.
The remainder of the screen display is ~or other measurements not as~ociated with the re~pira-tory gas ~tream. Accordingly, the scrolling waveform - `~ at 3620 i8 not a display of ga~ detection information.
The terms and expression~ which are employed - ` 20 here are terms of description and not o limitation.
There i~ no intention, in the use of such terms and expres~ions, to exclude the equivalents of the features shown and described, or portions thereof, it being recognized that variou~ modifications are po~ible within the 3cope of the invention a~ claimed.
Appendix I attached hereto sets forth the computer program used in conjunction with the embodiments of the invention as described.

. . ~

', '~

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN
EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE
DEFINED AS FOLLOWS:

1. A real-time method of marking a display means to distinguish the occurrence of respiratory events in a continuous waveform representative of the amounts of constituent gas in a respiratory gas stream being displayed on the display means, comprising generating in real-time a signal indicative of the amounts of the constituent gas displayed on the display means based on the signals generated in the generating step, and marking the continuous waveform in substantially real-time with a labelling means the occurrences of predetermined events along the continuous waveform.

2. The method as recited in claim 1, wherein the marking step includes marking an end-tidal event.

3. The method as recited in claim 1, wherein the marking step includes marking an inspired event.

4. A real-time method of marking a display means to distinguish the occurrence of respiratory events in a continuous waveform representative of the amounts of constituent gas in a respiratory gas stream being displayed on the display means, comprising the steps of generating in real-time said continuous waveform indicative of the amounts of the constituent gas displayed on the display means, and marking the continuous waveform in substantially real-time with a labelling means, whereby the labelling means marks the occurrences of predetermined events separate from and along the continuous waveform with symbols indicative of the predetermined event.

5. The method as recited in claim 4 wherein the waveform is substantially symmetrical.

6. the method as recited in claim 4 wherein the marking step includes marking an end-tidal event and an inspired event vertically displaced from one another.

7. The method as recited in claim 4 wherein the constituent gas is CO2.

8. A real-time method of marking a display means to distinguish the occurrence of respiratory events in a continuous waveform representative of the amounts of CO2 in a respiratory gas stream being displayed on the display means, comprising the steps of:

measuring the amounts of CO2 to determine its concentration with respect to the gas stream;

generating in real-time said continuous waveform indicative of the concentration of the CO2 displayed on the display means; and, marking the continuous waveform in substantially real-time with first and second characters, said first character being placed adjacent each of a plurality of inspired events in the continuous waveform and said second character being placed adjacent each of a plurality of end-tidal events in the continuous waveform.

9. The method as recited in claim 8 wherein the first and second characters are vertically displaced from each other on said display means.