CA1301241C - Feedback circuitry for d.c. motor speed control - Google Patents
Feedback circuitry for d.c. motor speed controlInfo
- Publication number
- CA1301241C CA1301241C CA000606429A CA606429A CA1301241C CA 1301241 C CA1301241 C CA 1301241C CA 000606429 A CA000606429 A CA 000606429A CA 606429 A CA606429 A CA 606429A CA 1301241 C CA1301241 C CA 1301241C
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- Prior art keywords
- motor
- voltage
- delay
- signals
- driving
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Abstract
Abstract of the Disclosure A circuit for controlling the speed of a DC motor pro-vides delay and sampling means in the feedback loop to delay the triggering of the SCRs driving the DC motor and measures the motor armature voltage during the period of the delay, thereby eliminating errors in the armature motor voltage caused by the SCR motor excitation.
Alternatively, the current to the motor is measured to generate a pulse output for initiating an interval dur-ing which the measured armature voltage is sampled and transmitted to a summator for generating an error signal controlling application of power to the DC motor whereupon the aforesaid interval is terminated upon receiving a pulse indicative of power application to the DC motor.
Alternatively, the current to the motor is measured to generate a pulse output for initiating an interval dur-ing which the measured armature voltage is sampled and transmitted to a summator for generating an error signal controlling application of power to the DC motor whereupon the aforesaid interval is terminated upon receiving a pulse indicative of power application to the DC motor.
Description
~;~U~Z41 Y~E~AC~ CI~CUITKY F~ D.C. I~TO~ SP~D C~NT~OL
~AC~ UND ~F T~E INVENTI~N
Fleld of the Invention Tnls lnventlon relates to the speed control of D.C.
motors, ana more partlcularly to such speed control using a feedbac~ slynal representatlve of the D.C. rnotor armature voltage for generatlng an error slgnal lndicatlve of the error ln the motor spee~ whereln tne motor armature voltage lS accurately measurea during a time interval in which the l~ motor excltation lS delayea or alternatlvely samp1ed at an optlrmum tlme.
Prlor Art U. ~ patent 3 t 55~,551, Dlgltal Speed Control Apparatus lssued to Arnold àlscloses the applicatlon of pulses, the frequency of whlch are representative of the motor velo-city, to both a variable time delay circuit and to a switch-lng circuit. A predetern,lned time delay lS used, the length of whlch corresponas to the tlme between the pulses of a pulse traln representatlve of the correct motor speed.
The ~elayea feedbacK pulse traln is compared wlth that of tne measurea pulse train. The rrlotor lS tnen caused to elther speea up or slow cown in aepenaence upon whlcn of the pulses ls first sensea.
~3(~24~
U.S. patent 3,950,6~2, Digital DC Motor Velocity Control System, issued ~o Dohanich, Jr. utilizes a delay to ensure that a counter has had time to respond to a feedback signal, thP period of which represents velocity. The motor pulse drive width is adjusted to maintain a constant motor speed.
U.S. patent 4,288,729, Control System for DC Electric Motor, issued to Anzai et al, discloses a time delay for opening a switching circuit controlling the energization of the motor to eliminate noise components in the power input to the motor. The time delay is preferably approximately one-fourth of the natural oscillation period of the system.
Prior art will be discussed with reference to the accompanying drawings, wherein:
Figure 1 illustrates a known prior art feedback control loop for regulating the speed of a DC motor;
Figures 2a and 2b respectively show voltage waveforms for a running DC motor and a stalled DC motor;
Figure 3 is a block circuit diagram of the feedback speed control loop incorporating the delay feature of the present invention;
Figure 4 is a schematic diagram of the delay circuitry of the present invention; and Figure 5 shows another embodiment wherein the current to the motor is monitored to determine the optimum time when the motor armature voltage can be accurately sampled.
~3u~4~
Figure 1 shows a known typical feedback control loop for controlling the speed of a DC motor. In such a typical feedback control loop the motor armature voltage is compared to a reference voltage representing the desired speed of motor 10 in summator or comparator 12. The error signal E is amplified by amplifier 14 and power amplifier 16, the latter including an SCR
controlled power circuit and the necessary firing circuits therefor. Typical waveforms of the SCR drive circuit representing rotation of the DC motor and a stalled DC motor are respectively illustrated in Figures 2a and 2b. The complsx waveform shown in Figure 2a is the armature voltage signal that is fed back to the summator 12 of Figure 1. The only region in Figure 2a that shows the actual motor speed is region f.
However, it is readily apparent that the average voltage is somewhat higher than the actual voltage produced by the motor armature. Even in Figure 2b, where the DC motor is stalled, it is apparent that the armature voltage is not zero due to the presence of the SCR pulse excitation signals. The aforementioned voltage errors cause errors in the speed of the DC
motor from the desired speed as represented by the reference voltage at summator 12.
One known method of overcoming the foregoing problem is to use a separate tachometer/generator 18 shown in phantom lines in Figure 1. However, such a tachometer/ generator adds cost along with the benefits it provides in DC motor speed regulation.
13~
SUMMARY OF THE INVENTION
The primary object of the invention is to provide an accurate signal representative of the speed of a DC mctor without the necessity of special sensing transducers such as tachometer/generators.
Another object of the invention is to provide accurate measurement of the speed of a DC motor at least equivalent to that obtained by tachometer/generator type feedback control systems.
Yet a further object of the invention is to provide delay and sampling circuitry enabling modification of the feedback loop for existing DC motor speed control systems.
The modified feedback loop of one embodiment of the invention provides a delay to prevent motor excitation, such as the firing of SCR drivers, during which delay interval the armature motor voltage can be sampled to obtain an accurate measure of the true DC motor speed.
In accordance with that one embodiment of the invention the feedback loop for controlling the speed of a DC motor is modified to include delay and sampling circuitry which prevent5, for example, an SCR power circuit from being actuated for a short interval such as 10 micro-seconds, and the generation of a sample pulse to measure the armature voltage of the DC motor and thereby obtain an accurate measurement of the true motor speed.
~u~
In another embodiment of the invention the current in the motor, the speed of which is being controlled, is monitored to determine the optimum time when the motor armature voltage can be accurately sampled.
The above features, advantages and objects of the present invention are readily apparent from the following description taken in conjunction with the above drawings representing a preferred embodiment of the best mode of carrying out the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 3 illustrates a block diagram of the essential delay and sampling circuits of a first embodiment of the present invention and the manner in which they are included in a feedback loop for controlling the speed of a DC motor. In Figure 3 the power amplifier 26 of the prior art speed control loop has been disassembled and the line that would normally fire or trigger the SCRs is routed to delaying and sample circuit 18. Delaying and sampling circuit 18 functions to prevent the SRCs in circuit 26 from being triggered for a short time, for example 10 microseconds. During that delay interval, delay and sampling circuit 18 generates a pulse to sample the armature voltage of motor 20. Because the SCRs in circuit 26 are OFF during the ~3U~
sample perlo~, an accurate nleasurement of the true motor speed lS o~talna~le because the DC motor armature voltage lS proportlonal to motor spee~ slnce tne ~C motor produces its own voltage ~acting as a generator) when lts armature is rotating. ~elay an~ sampling clrcult 1~ rece1ves zero-crossing pulses from ~C~ flring circuit 24, and in turn provldes a delaye~ triggering signal to SCR power circuit 2~ for triggerlng the SC~s to ~rlve the motor accoraing to a deslre~ speed represented by the reference voltage input 1~ to comparator or summator 21. Surllmator 21 generates an error signal ~ lnput to ampllfier 22 as descrlbe~ prev-iously w1th respect to the feedback speed control loop of Fiyure 1.
Figure 4 represents an exemplary preferre~ em~oaiment of ~elay an~ sampllng clrcuit 1~ illustrate~ 1n F1gure 3.
The ~C rrlotor armature voltage appears at term1nal Tl.
~hen a tr1gger pulse from SC~ firing circuit 24 of Figure 3 appears at term1nal T2, ~-type fllp-$`10p 28 lS SWltChed SO
that the ~ output thereof lS hlgh. The ~ output of flip-flop 2~ passes throuyh ~ yate 30 to the clocK input of monostable flip-flop 32 to open sample ano hold circuit 3~ thereby enabling a sampling of the motor armature volt-age at terrninal T1. Thus the ~ output of monostable fl1p-flop 32 has a pulse wi~th equal to the desired sampling per1o~ an~ the ~elay 1n the firlng of the SC~ drlvers in SC~ drive clrcuit 24.
~3~
When monostable fllp-flop 3~ swltches, the ~ output goes hlgh ana the ~ output goes low. After the delay, wlll return to a hlgh state ana ~ will return to a low state. The translstlon of ~ from low to hlgh is used to trlgger the SC~s ln the ~C~ power clrcu1t of ~'lgure 3, an~
the aelayea trlgger pulse lS ~ellverea through AND gate 34.
The zero-crossing pulses from ~C~ flrlng clrcult 24 of Flgure 3 appear at termlnal T3 ana perform the aual func-tlon of resetting D-type fllp-flop 28 as well as to clock monostable fllp-~-lop 32 throuyh ~ gate 30, wnlch affords a sarnpllng of the ~C motor armature voltage in that case where a trl~ger pulse has not been received from terminal T~. The trlgger pulse mlght be absent if the input spee~
reference has been reduced and the DC motor is coasting uown to a new spee~. The zero-crossing slgnals at term-inal T3 reset the D-type flip-flop 28 at the start oi a new power line cycle.
Anot~ler emboairnent oi the lnventlon lnvolves the monl-torlng of tne motor current ana then sampllng the ~notor armature voltage at an optlmulll time as aetermine~ by the rnonltoring of t~le motor current as shown in Flgure 5~ In thls embodlment there lS no delay as wlth the flrst embo~l-ment, but the motor current i5 lnsteaa monltored, an~ when the motor current is substantially zero, a sample of the ~3~
motor arnlature voltage lS taken as the nnotor ~rlve circults are ~FF.
In Flgure 5, lf ampllfier 4~ measures the voltage across reslstor 4~, the voltage wlll be zero when the current through lt ~and motor 44) is zero. Ampllfier 40 lS
designe~ to nave a very hlgh galrl, such that it is effect-lvely a swltcnlng ampllfler, and thereby cause a sample of the voltage of motor 44 to be taken at that tlme by con-trolllng sample ~ hola clrcult 4~. The gatlng can be terrn-lnated wnen tne motor arlve clrcultry ~not shown), lnclua-lng elther ~C~s or power translstors is again triggerea.
Tnus, wnen swltcnlng amplifler 40 swltches, sampllng of the armature voltage of motor 44 can ~egin under control of sample ~ nold clrcult 4~. When the motor drlve circuit 48 is agaln trlggered as a result of the feedback control, for example as described, supra with respect to the emboaiment of Flgures 3 ana 4, an SC~ trigger signal from motor arive clrcuit 48 causes sample ~ hold circuit 4~ to close, there-by preventin~ the measurea armature voltage of motor 44 from belng sample~ ana lnput to surnrnator 50. ~un~lator 5U
recives a reference voltage to provlde an error slgnal to rnotor ~rlve clrcuit 48, whlch operates ln a well known manner to control the excitation of nlotor 44 to control its speed.
_~,_ ~3~1Z~l From tne above aescrlption it lS apparent that elther the delay and sampllng clrcult of the ~irst emboalment, or the current monltorlng and voltage sampllng of the second embo~lrllent, ln the feedback control loop of a DC motor spee~ control circult ellmlnates the presence of the effects of power to the DC rnotor, thereby obtaining a more accurate measurement of the armature voltage of the DC
motor and lts speea. Ivloreover, the enhanced armature volt-age measurement lS obtainea by the use of well Known, inex-1~ penslve circu1try whlch can be easily lncorporatea lnto thefee~back loop of a ~C motor speeà control circuit.
~ oth the first an~ secon~ erll~odiments of the invention are capa~le of belny used wltn motor drive circultry otner than that incorporatlng ~C~s. ~'or example, a power ampll-fler uslng transistors in a pulse wldth modulated ~P~M) system can ~e use~ wlth ~otn embodlments oi the lnventlon.
~owever, both embo~lments require a perlod during the motor power cycle wherein the motor lS not being excited.
The above emboalments of the invention have been de-scrlbed solely to illustrate the function and operation of the invention, and those skilled in the motor speed con-trol art wlll recogni~e moaifications of the invention as being equivalents of the components set forth in the append-e~ clalrms, such tnat tne lnvention is not to be limited to tne particular emboalrnents describe~ herein, but is to be accoraed the equivalents of the clalrned components.
_g_
~AC~ UND ~F T~E INVENTI~N
Fleld of the Invention Tnls lnventlon relates to the speed control of D.C.
motors, ana more partlcularly to such speed control using a feedbac~ slynal representatlve of the D.C. rnotor armature voltage for generatlng an error slgnal lndicatlve of the error ln the motor spee~ whereln tne motor armature voltage lS accurately measurea during a time interval in which the l~ motor excltation lS delayea or alternatlvely samp1ed at an optlrmum tlme.
Prlor Art U. ~ patent 3 t 55~,551, Dlgltal Speed Control Apparatus lssued to Arnold àlscloses the applicatlon of pulses, the frequency of whlch are representative of the motor velo-city, to both a variable time delay circuit and to a switch-lng circuit. A predetern,lned time delay lS used, the length of whlch corresponas to the tlme between the pulses of a pulse traln representatlve of the correct motor speed.
The ~elayea feedbacK pulse traln is compared wlth that of tne measurea pulse train. The rrlotor lS tnen caused to elther speea up or slow cown in aepenaence upon whlcn of the pulses ls first sensea.
~3(~24~
U.S. patent 3,950,6~2, Digital DC Motor Velocity Control System, issued ~o Dohanich, Jr. utilizes a delay to ensure that a counter has had time to respond to a feedback signal, thP period of which represents velocity. The motor pulse drive width is adjusted to maintain a constant motor speed.
U.S. patent 4,288,729, Control System for DC Electric Motor, issued to Anzai et al, discloses a time delay for opening a switching circuit controlling the energization of the motor to eliminate noise components in the power input to the motor. The time delay is preferably approximately one-fourth of the natural oscillation period of the system.
Prior art will be discussed with reference to the accompanying drawings, wherein:
Figure 1 illustrates a known prior art feedback control loop for regulating the speed of a DC motor;
Figures 2a and 2b respectively show voltage waveforms for a running DC motor and a stalled DC motor;
Figure 3 is a block circuit diagram of the feedback speed control loop incorporating the delay feature of the present invention;
Figure 4 is a schematic diagram of the delay circuitry of the present invention; and Figure 5 shows another embodiment wherein the current to the motor is monitored to determine the optimum time when the motor armature voltage can be accurately sampled.
~3u~4~
Figure 1 shows a known typical feedback control loop for controlling the speed of a DC motor. In such a typical feedback control loop the motor armature voltage is compared to a reference voltage representing the desired speed of motor 10 in summator or comparator 12. The error signal E is amplified by amplifier 14 and power amplifier 16, the latter including an SCR
controlled power circuit and the necessary firing circuits therefor. Typical waveforms of the SCR drive circuit representing rotation of the DC motor and a stalled DC motor are respectively illustrated in Figures 2a and 2b. The complsx waveform shown in Figure 2a is the armature voltage signal that is fed back to the summator 12 of Figure 1. The only region in Figure 2a that shows the actual motor speed is region f.
However, it is readily apparent that the average voltage is somewhat higher than the actual voltage produced by the motor armature. Even in Figure 2b, where the DC motor is stalled, it is apparent that the armature voltage is not zero due to the presence of the SCR pulse excitation signals. The aforementioned voltage errors cause errors in the speed of the DC
motor from the desired speed as represented by the reference voltage at summator 12.
One known method of overcoming the foregoing problem is to use a separate tachometer/generator 18 shown in phantom lines in Figure 1. However, such a tachometer/ generator adds cost along with the benefits it provides in DC motor speed regulation.
13~
SUMMARY OF THE INVENTION
The primary object of the invention is to provide an accurate signal representative of the speed of a DC mctor without the necessity of special sensing transducers such as tachometer/generators.
Another object of the invention is to provide accurate measurement of the speed of a DC motor at least equivalent to that obtained by tachometer/generator type feedback control systems.
Yet a further object of the invention is to provide delay and sampling circuitry enabling modification of the feedback loop for existing DC motor speed control systems.
The modified feedback loop of one embodiment of the invention provides a delay to prevent motor excitation, such as the firing of SCR drivers, during which delay interval the armature motor voltage can be sampled to obtain an accurate measure of the true DC motor speed.
In accordance with that one embodiment of the invention the feedback loop for controlling the speed of a DC motor is modified to include delay and sampling circuitry which prevent5, for example, an SCR power circuit from being actuated for a short interval such as 10 micro-seconds, and the generation of a sample pulse to measure the armature voltage of the DC motor and thereby obtain an accurate measurement of the true motor speed.
~u~
In another embodiment of the invention the current in the motor, the speed of which is being controlled, is monitored to determine the optimum time when the motor armature voltage can be accurately sampled.
The above features, advantages and objects of the present invention are readily apparent from the following description taken in conjunction with the above drawings representing a preferred embodiment of the best mode of carrying out the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 3 illustrates a block diagram of the essential delay and sampling circuits of a first embodiment of the present invention and the manner in which they are included in a feedback loop for controlling the speed of a DC motor. In Figure 3 the power amplifier 26 of the prior art speed control loop has been disassembled and the line that would normally fire or trigger the SCRs is routed to delaying and sample circuit 18. Delaying and sampling circuit 18 functions to prevent the SRCs in circuit 26 from being triggered for a short time, for example 10 microseconds. During that delay interval, delay and sampling circuit 18 generates a pulse to sample the armature voltage of motor 20. Because the SCRs in circuit 26 are OFF during the ~3U~
sample perlo~, an accurate nleasurement of the true motor speed lS o~talna~le because the DC motor armature voltage lS proportlonal to motor spee~ slnce tne ~C motor produces its own voltage ~acting as a generator) when lts armature is rotating. ~elay an~ sampling clrcult 1~ rece1ves zero-crossing pulses from ~C~ flring circuit 24, and in turn provldes a delaye~ triggering signal to SCR power circuit 2~ for triggerlng the SC~s to ~rlve the motor accoraing to a deslre~ speed represented by the reference voltage input 1~ to comparator or summator 21. Surllmator 21 generates an error signal ~ lnput to ampllfier 22 as descrlbe~ prev-iously w1th respect to the feedback speed control loop of Fiyure 1.
Figure 4 represents an exemplary preferre~ em~oaiment of ~elay an~ sampllng clrcuit 1~ illustrate~ 1n F1gure 3.
The ~C rrlotor armature voltage appears at term1nal Tl.
~hen a tr1gger pulse from SC~ firing circuit 24 of Figure 3 appears at term1nal T2, ~-type fllp-$`10p 28 lS SWltChed SO
that the ~ output thereof lS hlgh. The ~ output of flip-flop 2~ passes throuyh ~ yate 30 to the clocK input of monostable flip-flop 32 to open sample ano hold circuit 3~ thereby enabling a sampling of the motor armature volt-age at terrninal T1. Thus the ~ output of monostable fl1p-flop 32 has a pulse wi~th equal to the desired sampling per1o~ an~ the ~elay 1n the firlng of the SC~ drlvers in SC~ drive clrcuit 24.
~3~
When monostable fllp-flop 3~ swltches, the ~ output goes hlgh ana the ~ output goes low. After the delay, wlll return to a hlgh state ana ~ will return to a low state. The translstlon of ~ from low to hlgh is used to trlgger the SC~s ln the ~C~ power clrcu1t of ~'lgure 3, an~
the aelayea trlgger pulse lS ~ellverea through AND gate 34.
The zero-crossing pulses from ~C~ flrlng clrcult 24 of Flgure 3 appear at termlnal T3 ana perform the aual func-tlon of resetting D-type fllp-flop 28 as well as to clock monostable fllp-~-lop 32 throuyh ~ gate 30, wnlch affords a sarnpllng of the ~C motor armature voltage in that case where a trl~ger pulse has not been received from terminal T~. The trlgger pulse mlght be absent if the input spee~
reference has been reduced and the DC motor is coasting uown to a new spee~. The zero-crossing slgnals at term-inal T3 reset the D-type flip-flop 28 at the start oi a new power line cycle.
Anot~ler emboairnent oi the lnventlon lnvolves the monl-torlng of tne motor current ana then sampllng the ~notor armature voltage at an optlmulll time as aetermine~ by the rnonltoring of t~le motor current as shown in Flgure 5~ In thls embodlment there lS no delay as wlth the flrst embo~l-ment, but the motor current i5 lnsteaa monltored, an~ when the motor current is substantially zero, a sample of the ~3~
motor arnlature voltage lS taken as the nnotor ~rlve circults are ~FF.
In Flgure 5, lf ampllfier 4~ measures the voltage across reslstor 4~, the voltage wlll be zero when the current through lt ~and motor 44) is zero. Ampllfier 40 lS
designe~ to nave a very hlgh galrl, such that it is effect-lvely a swltcnlng ampllfler, and thereby cause a sample of the voltage of motor 44 to be taken at that tlme by con-trolllng sample ~ hola clrcult 4~. The gatlng can be terrn-lnated wnen tne motor arlve clrcultry ~not shown), lnclua-lng elther ~C~s or power translstors is again triggerea.
Tnus, wnen swltcnlng amplifler 40 swltches, sampllng of the armature voltage of motor 44 can ~egin under control of sample ~ nold clrcult 4~. When the motor drlve circuit 48 is agaln trlggered as a result of the feedback control, for example as described, supra with respect to the emboaiment of Flgures 3 ana 4, an SC~ trigger signal from motor arive clrcuit 48 causes sample ~ hold circuit 4~ to close, there-by preventin~ the measurea armature voltage of motor 44 from belng sample~ ana lnput to surnrnator 50. ~un~lator 5U
recives a reference voltage to provlde an error slgnal to rnotor ~rlve clrcuit 48, whlch operates ln a well known manner to control the excitation of nlotor 44 to control its speed.
_~,_ ~3~1Z~l From tne above aescrlption it lS apparent that elther the delay and sampllng clrcult of the ~irst emboalment, or the current monltorlng and voltage sampllng of the second embo~lrllent, ln the feedback control loop of a DC motor spee~ control circult ellmlnates the presence of the effects of power to the DC rnotor, thereby obtaining a more accurate measurement of the armature voltage of the DC
motor and lts speea. Ivloreover, the enhanced armature volt-age measurement lS obtainea by the use of well Known, inex-1~ penslve circu1try whlch can be easily lncorporatea lnto thefee~back loop of a ~C motor speeà control circuit.
~ oth the first an~ secon~ erll~odiments of the invention are capa~le of belny used wltn motor drive circultry otner than that incorporatlng ~C~s. ~'or example, a power ampll-fler uslng transistors in a pulse wldth modulated ~P~M) system can ~e use~ wlth ~otn embodlments oi the lnventlon.
~owever, both embo~lments require a perlod during the motor power cycle wherein the motor lS not being excited.
The above emboalments of the invention have been de-scrlbed solely to illustrate the function and operation of the invention, and those skilled in the motor speed con-trol art wlll recogni~e moaifications of the invention as being equivalents of the components set forth in the append-e~ clalrms, such tnat tne lnvention is not to be limited to tne particular emboalrnents describe~ herein, but is to be accoraed the equivalents of the clalrned components.
_g_
Claims (7)
1. A circuit for controlling the speed of a DC motor from a measured armature voltage and a reference voltage signal representing desired motor speed, comprising:
means for comparing said measured armature voltage with said reference signal and generating an error signal;
means for driving said motor;
means responsive to said error signal to generate signals for triggering the excitation of said means for driving, and providing signals indicating the zero crossover of an AC power source providing power for said means for driving; and delay and sampling means responsive to said zero crossover signals and said triggering signals to delay the triggering of said means for driving and gating a signal representative of said armature voltage during the period of said delay.
means for comparing said measured armature voltage with said reference signal and generating an error signal;
means for driving said motor;
means responsive to said error signal to generate signals for triggering the excitation of said means for driving, and providing signals indicating the zero crossover of an AC power source providing power for said means for driving; and delay and sampling means responsive to said zero crossover signals and said triggering signals to delay the triggering of said means for driving and gating a signal representative of said armature voltage during the period of said delay.
2. The circuit as claimed in claim 1 wherein said delaying and sampling means includes means responsive to said triggering signals to generate pulse output having a pulse width defining said delay period.
3. The circuit as claimed in claim 1 wherein said delaying and sampling means includes means responsive to said triggering signals to generate pulse outputs including delayed trigger pulse outputs at the termination of said delay for triggering said means for driving.
4. The circuit as claimed in claim 3 wherein said means responsive to said triggering signals includes a flip-flop for receiving said triggering signals and providing at least a Q output and an OR gate for gating the Q output of said flip-flop, a monostable flip-flop receiving the output gated by said OR gate to generate Q
and NOT Q outputs, said NOT Q output being said pulse output and AND gate receiving said NOT Q output and said triggering signals to produce a delayed trigger pulse output.
and NOT Q outputs, said NOT Q output being said pulse output and AND gate receiving said NOT Q output and said triggering signals to produce a delayed trigger pulse output.
5. The circuit as claimed in claim 4 wherein said OR
gate also receives said zero-crossing signals to enable measurement of the armature motor voltage.
gate also receives said zero-crossing signals to enable measurement of the armature motor voltage.
6. Circuitry for controlling the speed of a DC motor from measured armature voltage and a reference voltage representing desired motor speed, comprising:
means for comparing said measured armature voltage with said reference voltage and generating an error signal;
means responsive to said error signal for driving said motor and for providing a first pulse output indicative of the application of power to said motor;
means electrically connected between said motor driving means and said motor to measure the current provided to said motor and to generate a second pulse output representing a substantially zero current measurement; and sample and hold circuitry sequentially responsive to said second and first pulse outputs to receive and transmit signals representative of the measured armature voltage of said motor by the measuring means to said means for comparing only during the interval between said second and said first pulse outputs.
means for comparing said measured armature voltage with said reference voltage and generating an error signal;
means responsive to said error signal for driving said motor and for providing a first pulse output indicative of the application of power to said motor;
means electrically connected between said motor driving means and said motor to measure the current provided to said motor and to generate a second pulse output representing a substantially zero current measurement; and sample and hold circuitry sequentially responsive to said second and first pulse outputs to receive and transmit signals representative of the measured armature voltage of said motor by the measuring means to said means for comparing only during the interval between said second and said first pulse outputs.
7. The circuitry as claimed in claim 6 wherein the means for measuring substantially zero current to said motor includes a resistance serially connected between said motor driving means and said motor and an amplifier responsive to the voltage across said resistance for generating said second pulse output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000606429A CA1301241C (en) | 1989-07-24 | 1989-07-24 | Feedback circuitry for d.c. motor speed control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000606429A CA1301241C (en) | 1989-07-24 | 1989-07-24 | Feedback circuitry for d.c. motor speed control |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1301241C true CA1301241C (en) | 1992-05-19 |
Family
ID=4140380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000606429A Expired - Lifetime CA1301241C (en) | 1989-07-24 | 1989-07-24 | Feedback circuitry for d.c. motor speed control |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1301241C (en) |
-
1989
- 1989-07-24 CA CA000606429A patent/CA1301241C/en not_active Expired - Lifetime
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