CA1291815C - Offset for protection against amorphous pips during write verify - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
Provided is a read signal offset during write verify which prevents the false detection of amorphous pips from an optical disk recorder. Amor-phous pips are the signals caused by the drop in reflection from an optical disk after the laser has caused the surface material to change from its crystalline state to an amorphous state, but not to a hole. When a hole is not formed in the material, the amorphous material later recrystallizes, the drop in reflec-tion no longer occurs and information is lost.

Description

"` 1291815 This invention relates to the field of optical disk recorders and, more particularly, to means for verifying the proper writing of data on the optical disk.
Write verify apparatus for verifying the correct writing of data on optical media immediately after writing does so by detecting the pip, which is caused by a drop in reflection due to the hole just formed when the laser writing the hole is returned to read power. All current recording materials have a crystalline form which is reflective. When the laser impinges in the material, it wldergoes a transformation to an amorphous state and then melts.
When it melts, surface tension causes the formation of a hole in the media which is not reflective. These holes comprise information which can be read by the optical system by detecting the loss in reflection they cause.
Occasionally, write verify systems detect the presence of a "correctly" recorded hole due to the presence of a pip only to have the "hole"
later disappear during reading.
u mary of the Inventiorl __ Tlle reason for this disappear~ g holc has been discovcred. tt sometimes happells that the laser erlergy inl)ut is insuEficiellt to complete the process of melting and hole Eormatlon, arld the nledi.- remains in its amorphous state. Tn the amorl)llous state, tllerc is a drop in reElectivity whicll may be detected by a write veriEy systenl detecting a pip. Later, the media re-crystallizes. The "hole" thell disappears.
The inventiorl overcomes the problem of the amorphous pip by inject-ing an offset into the read detection and amplification electronics during write verify at the occurrence of a write pulse. The offset is approximate-ly the same signal strength as that of an amorphous pip, but inverted ~2~La~5 therefrom.
Thus, in accordance with a broad aspect of the invention, there is provided an optical recording apparatus provided with means for scanning an optically writeable medium with radiation pulses in order to form optically detectable marks on the medium, with radiation sensitive detector means for detecting the radiation of the radiation beam reflected by the medium and for converting the radiation detected into a corresponding read signal, with write verify means for verifying the forming of an optical detectable mark on the basis of the read signal, and means for offsetting the read signal by a predetermined offset value in response to the generation of a radiation pulse so as to prevent the detection of an amorphous pip .
Brief Description of the Drawings Figure 1 shows a block diagram of the read channel of the optical recording system of the preferred embodiment.
Figure 2 shows the TOON code and its corresponding binary equivalent.
Figure 3 shows a timing diagram of various signals and pulses of the apparatus of the present invention over two symbols and showing the signal levels associated with two possible hole patterns.
Figure 4 shows a schematic of the present invention showing the apparatus which detects by comparison the location of the odd and the even symbol positions having the highest hole associated signal levels and which compares the locations of the ;;~r 12~1~5 64869-17 write pulse signals with the locations of the detected holes.
Figure 5, on the second sheet of drawings, shows the relative time spacing between a number of clocks and other symbols employed by the preferred apparatus.
Figure 6 shows a graph of the offset during a typical read of a pip.
Description of the Preferred Embodiment -2a-....~,~

8~i The read signal offset for protection against amorphous pips is in-tended to be used in conjurlction with a differential write verify system in the preferred embodiment. In this regard, the write verification system will first be described. The modification to it to inject the offset on the read signal will be described next.
An optical recorder reading the information from an optical disk does so conventionally by means of a laser opcrated at read power. The beam reflects from the disk, and the drop in reflection normally indicates the pres-ence of a hole. Because reflected spot derlsity distributions have a Gaussian shape, the hole associatc?d power of the reflected beam (the hole associated power meails the inverse of the reflected power from the disk) spreads a sig-nificant distancc? beyond the bowldaries of the holes themselves. Indeed, the hole power present at the center of the next possible position of a hole in closely spaced systems may be significallt. I~or this reason, differc?lltial de-tection is used to detect the location of the plps from the newly written holes in the preferred embod:iment.
I igUrC? 1 S]IOWS a block cliagrcLlll of the read charlllel of the opt:ical recording systenl according to the prc?-fcrrecl embodimerlt. lhe pre-a1llplified signal from the read detector (not S]IOWII) i.S input to the AGC 110 showll in l:ig-urc? 1, which outputs the arllplified and limitecl signal on Read 1 and Read 2 out-puts. IVhell the optical system writes a ilole in the media, it issues a write pulse, and a signal indicative of the write pulse is input to a delay 130, which will be discussecl below, and a voltage offset means 10~, which causes the AGC and read amplifier 110 to offset its Read 2 output by a predetermined vol-tage. This predetermined voltage is approximately the voltage caused by an amorphous pip as detected by the write verify system, but inverted therefrom.

~s The Read 1 output is input to a phase lock loop 112 which tracks a prerecord~ed clock inscribed ;n the optical disk, or if the code is self-clock-ing, the clock information present in the code. The phase lock loop outputs several clock signals, the most important of which is a 2CK clock at a fre-quency twice that of the prerecorded clock of the preferred embodiment. This 2CK is input to a Timing Chip 44 and to a TOON cowlter ~6. TOON is the name of the fixed hlock code of the preferred embodiment. The TOON counter's es-sential purpose is to count the number of symbol positions to generate a sym-bol position address. The function of the Timing ~hip 44 will be discussed infra.
___ The Kead 2 signal is input to four gated sample and hold cells 114, two each for the respective even and ocld symbol positions of the 'I`OON cocle.
'I'he sampling of the cells is controlled by Timing Chip 44. The outputs of the cells are input to two comparators 116, an even and an odd comparator respec-tively, which determine which of the two has the highest hole associatc~d signal power. The comparator outputs are first latchecl and then fed back to Timillg Chip 44 and to a transitioll clctector circu:it 118. 'I'he trans:itiol~ detectors detect a change in the state oF the coml7arators 11( out[-uts alld signals that challge to several locations: 1) to a l~nir of billclry registers 120, 2) to write verify apl)aratus 132 and 3) to a Syllc register 122 which forms part of a sector mark decodcr circuitry. rl'he outl)uts to the hirlclry registe-rs and to the write verify registers are differentiatecl betweell the even and the odd symbol posi-tions.
For the reading of data, the apparatus convert the "address" of the change in the state of the comparators into binary. The address of the change is represented by the count on the TOON Counter 46. This count is recorded by binary registers 120 and later becomes the binary value of the symbol. Each lB~S

symbol of the TOON code erlcodes four bits. After two symbols have beerl re-corded in the registers 120 the optical disk recorder reads the eight binary bits of data just decoded out of the registers along a data bus 196.
The sytem is also used for the detection of sector marks. An LDOS
signal indicative of a change in one of the comparators is supplied to a sync register 122 which in combination with sector mark decoder 124 decodes the presence of sector marks and initializes the TOON counter 46 and a nibble counter 126. The nibble counter 126 counts up by one each symbol until the next sector mark. The lowest order bit of this nibble counter nibble COWIt 0 is output on output 128 and is used by the billary registers 120 to signal the lapse of two symbols.
Ihe write veriEy apparatus 132 will be clescribed below.
The present inverltion pertaills to optical recording systems writ-ing data Orl the optical disk in fixecl-block format whercirl binary data is en-coded irlto a symbol having a predeterll~ ed rlulllher of pos:itions in whicll a pre-determinod numbcr of holes are recorded. The l-referrcd embodiment uses a so-called IOON code whi.cll has c:igllt positions in whictl holcs may be written and one pOsitiOlI in which no holes are writtcll. Ihe latter position is normally reserved at the encl of the syml)ol. Ihe IOO~ cocle is Eurtller constrained to have one hole wr:itten at an evon pos:ition and one hole written at arl ocld po-sition. Only two lloles arc written in the symbol.
Figure 2 shows the TOON code. It has nine positions numbered in the Figure from zero to eight. The eighth position is the one constrained to never have a hole recorded in it. The other eight positions have one hole in an even position and one ho]e in an odd position. The code is shown in the Figure and the corresponding binary bit values are shown in the table to the 129~1~15 right. Each symbol of the TOON code encodes four bits of information.
The code is recorded on the media in such a malmer that four and one half clock periods, T , span the symbol. Referring to Figure 3a, the clock is illustrated as the sinusoidal line 10. It is from this signal that the phase lock loop generates the 2CK signal shown in Figure 3b.
The fall of 2CK denotes the beginning of a symbol position and the rise of 2CK denotes the center of a symbol position. There are exactly nine 2CK clocks in a symbol. In the preferred embodiment, the phase lock loop ad-iusts the phase of 2CK such that the si~nal SCK, discussed infra, which is de-rived from 2CK but delayed therefrom by a matter of 20 to 30 nallosecollds, is in phase with the prerecorded clock such that SCK's positive transitions occur at the center of a symbol position. With this in milld, furtller discussion of symbol pOsitiolls will be in refererlce to 2CK.
Figure 3c corresponds to the TNCO bit out of the TOON Counter 46.It undergoes eight transitiolls during a symbol and the transitiotls occur at the center of a given symbol position. The numbers in the ligure correspond to the number of the symbol l)os:iti.on in which the next transitioll occurs. Tllere is no transitioll in nilltil svml-ol position, number 8, primar:ily l)ecause no llole will ever be recognized in this position even :iE a hole is somehow recordc-l tllereill.

I-loles are preferably writtell at tlle center o:E a symbol position.
To write a llole, the optical recording device ~enerates a write pulse from a laser beam of approximately 60 nanosecorlds in length. The symbol pOsitiOIl length or the length of time for a symbol position to pass past a fixed loca-tion at typical operating speeds of the optical recording system of the pre-ferred embodiment is 1~0 nanoseconds. The hole burned into the optical re-12918~5 cording medium by such a write pulse is typically much larQer than 60 nano-seconds in length and may be larger than the 180 nanoseconds length of a symbol pcsition. After the laser beam has been pulsed at write power the optical re-cording system of the preferred embodiment returns it to a read power level used conventionally to read the prerecorded clock on the optical recording surface. The laser beam continues to be focused for a shortl)eriod of time on the hole just burned in the optical recordin~ medium. The loss of reflectivity caused by the hole can be detected by the read detectors employed in the read apparatus of a conventional oPtical disk recorder system.
Ei~ure 3a shows the inverse of thc power of the reflected laser beam for two typical symbols on the optical recording medillm. Tlle drop in re-flection caused by the presence o:E a hole is ShOWII as a positive si~nal, wllile the rise in reflection due to a write pulse is indicated by a negative sigllal.
Tllc vertical daslled lines in the Pigure represent the boulldaries at the edges of the symbols.
Again referr;n~ to Figure 3a, the opticfll recordin~ apParatus is SIDWII writillg a hole at the cellter of symbol i~oslt:ions numbers 1 and 4 of the first symhol. [n tllis re~arcl, tlle write pulse occ-lrs 30 n.lllosccollds before the risin~ ed~e of the S(K ancl is clcsiglled to reacll its peflk power precisely at the center of sylllbol position llullll)er 1, approximately at the ris:in~ ed~e of the S~K. 30 nallosecorlds later the wr:ite r~ulse :is turned off. The write pulse in the Figure is denoted by the ne~ative ~oing waveform 12 and also by the l-data NOT signal at Figure 3m.
After the write pulse has been terminated and the laser beam re-stored to its "read" nower the laser beam will remain over a portion of the hole just formed in the optical recording medium, assuming, of course, a ho]e ~$

was in fact formed by the write pulse. In this regard, the hole does not re-flect the laser beam and the inverse of the signal detected by apparatus de-tecting the reflected beam will generate a high signal at 14 in the Figure.
This is a so-called pip. The solid line 20 in the Figure represents the act-ual signal, correspondin~ to the hole associated signal power During a norm-al read where the apparatus reads the hole from ed~e to ed~e, the hole as-sociated signal would appear as in the dotted line 18 and would peak at a peak 16 which is of greater amplitude than peak 14 of the read after write signal 20. As can be seen by inspectioll of the Figure, the hole associated power 20 of a hole written at symbol position 1 will be present to a si~nificant degree at symbol position 2.
'Ihe second negative going pulse in Figure 3a represents a second hole being written in the symbol at the center of symbol position 4. Ilere again, the dotted line 28 represents the hole associated signal power wllich would have been received by the read system were it to detect tl~c holc ullder normal reading conditiolls. Ilowever, as tlle laser bcam detects tlle hole at least 30 nallosecollds after the center oE the hole has passed, thc signal strength is again detected at a pcclk 32 somewhat less tllan it woukl have beerl ullder norlnal read conditiolls.
2() Assuming a dcfcct in the medià or perllaps a defect in the writing system~ a hole may not be formcd in the media. Whell the write pulse is turn-ed off, the hole associatecl power of the read signal will therl not follow line 30 but will instead follow the line 34 which corresponds to the signal of the prerecorded clock. The subject of amorphous pips will be discussed infra.
The second symbol shows holes 40, 42 being written by write pulses 36 and 38 at symbol positions 6 and 7.

~9~

Figure 4 shows ap~aratus first for detection of the location of a hole and secondly for comparin~ the location of the detected hole with the act-ual location of the write pulse.
Referring to the top right-most part of Figure 4, the 2CK clock de-rived from the phase lock loop 112 is provided as an input to both a Timing Chip 44 and a TOON counter 46. TOON counter 46 counts once for each cycle of the 2CK with its four-bit COUIIt on outputs TNCO, TNCl, INC2, and TNC3, re-spectively. A count of 8, TNC3. resets the counter to zero due to the invert-er 48 feedinE TNC3 back into master reset NOT 50 of the TOON counter 46.
The Timing Chip 44 also outputs an RER signal, whlch is inverted by inverter 54, to become an RER NOT signal. The signal RER is output once per symbol during the last half period of symbol position 0. The purpose of RER is to signal the end of a symhol to various registers as w:ill be discussed infra, and also to reset other registers.
_ As can be seen from l:igure 31, the Timing Chip OUtpllts all S-clock ("SCK") which corresponcls directly with the 2CK signcll. SCK is delayed from 2CK by appro~imately 22.5 nanosecollcls as can l-e seen from ligure 5.
Tlle liming Chil) 44 also OUtp~lts through rcgistcr 52 signals Sl, S2, S3 ancl S4 and an REM signcLl. Slgnals Sl - S4 and I~EM are set by the rising edge of SCK clocking register 52. Signal SAR NOT resets register 52 and signals Sl through S4 and I~EM. SAR NOI is norlllally triggercd at the Ealling edge of SCK, see Figure 5 where it can be seen that at the fall of the SCK signal, which occurs 22.5 nanoseconds afier the fall of the 2CK signal, causes the Timing Chip 44 to output an SPS signal, which when coupled with REM and NAND gate 51, generates the SAR NOT signal (see Figure 5d) which resets register 52 and there-by resets signals Sl through S4 and REM as can be seen from Figure 5e, which ~291815 shows the resetting of theSlsig~ .The resetting of REM also resets SAR NOT.
Thus, the Sl signal is rlormally "onl' for a period of approximately 90 nano-seconds from a point approximately 30 nanoseconds after the rise of the 2CK
signal to approximately 30 nanoseconds after its fall.
Referring to the upper left-most of Figure 4, the signals Sl to S4 control corresponding FET gates 58 between the Read 2 input 56 and respec-tive grounded capac:itors 60. The combination of a gate and a capacitor forms a sample ancl hold cell as is known to the art, and the respective sample and holcl cells will hellceforth be referred to by the respective signals controlling their gates, Sl, S2, S3 and S4. Tlle signal input on Read 2 line 56 corresponds to the hole assoc:iated power of the reflected laser beam as discussed .-bove.
~ach of the capacitors 6() is also connected two each to respective comparators 62 and 64. Comparator 62 operatos on the even pOsitiOIls oE a TOON symbol and comparator 64 operates on the odd pOsitiOIls. Comparator 62 compares the sig-nal value on the Sl sample llold with tho sig~lal value therl preserlt on the S3sample and hold, while the comparator 6~1 comparos the s:igncll value ill tlle S2 sample ancl ho]cl with tho signal valllo on tlle S4 sample and hold. Tlle compara-tors output the results of the comp.lrisoll on outl)uts (i6 ancl 6~, respectively.
'Ihese outputs are latched by Flip flops 74 and 75, the outputs of whicll are provided as respective inl-uts 70 alld 72 to the Timillg Chip ~14.
The write beam is syncllroll:iæed to write for 60 nanoseconds center-ed on the zero crossing of the prerecorded clock, the center of a symbol posi-tion. Sl through S4 go high about 30 nanoseconds after the rise of 2CK, just about the center of the symbol position. When a write pulse has just occurred, Timing Chip 44 synchronizes the issuance of the SAR NOT signal to the write pulse by responding to the sWP and dWP signals. These two signals, sWP and dWP, J ;~ 815 are the outputs of registers 96 and 98, which will be discussed ;JI more detail infra, but their function is essentially to generate a delay signal responsive to the write pulse. The purpose of this delay is to delay the turning off of the signals Sl through S4 until the peak of the hole associated signal is sam-pled. This generally occurs a measureable time after the occurrence of the write pulse, and will be a predetermined time. Signals sWP ~nd dWP are pro-vided as inputs to Timing Chip 44. Their timing in relation to a write pulse are shown in Figures 3m through 3O. The write pulse corresponds to the l-data NOT pulse, Figure 3m.
Referril1g again to Figure 4, the 'I`imillg C11ip 44 initially turns Sl and S2 on during the last half-period of symbol position 8 of every symbol po-sition, see l~'igures 3e and 3f. Because symbol position 8 ;s the symbol posi-t:ion in wl1ich no hole is ever written, this samplil1g is intended to initialize these sample and hold cells to a reference value. An alternative method of initializatioll would be to include circuitry to initialize these sample Llld holds from a fixed refcrel1ce equivalent to thc average sigt1al strengtl1 oE the no-11ole condition.
Durillg tl1e first sy1Dbol pOsitioll of the imn1cdiately foLlowing sym-bol, symbol position (), ar1 even position, sample and l1old cell S4 is turned to sample tl1e si.gnal at tilC first evel1 cell. Durir1g the first odd pos;tion, position numbcr l, sample and hold S3 is turned on to sample the signal at the first odd cell. 'I'he signals present on the Read 2 line 56 during these symbol positions are copied into the corresponding capacitors 60 of the sample and hold cells and compared wi-th the signal in the Sl and S2 sample and hold cells, which contain the reference level. If for example, the results of the compari-son indicate that the Sl sample and hold value exceeds the S3 sample and hold value, the output 66 of the comparator 62 will be low. Output 68 will be low 129~8~LS

if S2 exceeds S4. The 'I'iming Chip 44 then saves the higher of the two values, Sl (S2). It does this at the next occurrence of an odd (or even) ce]l by triggering the S3 (S4) sample and hold, which then holds the lowest vallled sig-nal of the two. If again the Sl (S2) sample and hold contaills the highest value, at the next occurrence of an odd (even) symbol posit:ion, the S3 (S4) sample and hold is again triggered. This process contillues throughout the sym-bol with the highest valued sample and hold cell retained and compared with the next sampled value. At the end of the symbol, one of the sample and holds of eacll comparator will contaill the highest valued signal, and this signal cor-responcls to the hole witllill the symbol, if there is a hole recorded there.
I`ce-Eerring to the example ShOWII in Figure 3a, whell the S3 sample and hold cell is triggered at pOsitiOIl 1 in the Eirst symbol, it samples the signal caused by the hole just ~ritten. Tlle sample and hold samples a reacl signal at approximately the level indicated at pOillt 14 on ligure 3a. As can he seen by inspectioll of Figll-re 3a, the s:ignal level at tllis pOillt 14 is h:igher than thc signal samplecl by the Sl sampLe alld hold at the previous sym-bol pOsitioll 5. 'I'he sigllaL ;n the S3 salllple allcl hoLcl is h:igher thall the s:ig-nal on thc Sl salllplc and hold alld is retaillcd. At the next occurrellce of an ocld symbol at sylnbol pOsitiOIl 5, the 'I':imillg (,hil) ~14 cleterlllillc~s that S3 IIOW COII-tUills the highest signal and triggers the Sl saml)le and hold. By insl)ectioll ofligure 3a, :it can be seen that the signal level at this point 30 is higller than the reference signal level but lower thall the peak value 14 of the signal at position 1. Thus, S3 contillues to contain the higher of the two values. Tim-ing Chip 44 triggers Sl at the last odd position number 7. This value is again less than the value in sample and hold cell S3. (The sequence of triggering of Sl and S3 just described is shown at Figures 3f and 3g.) ~29~315 If at arly time the two signal levels present in the respective samp-le and holds are about equal, which may occur when the holes are recorded later in the symbol, the state of the comparators 62 or 64 is indeterminate. Either one of the two is retained for the next symbol. This feature is illustrated by the dashed lines shown in Figures 3d and 3e which show the triggering of the S2 and S4 sample and hold cells.
Timing Chip 44 recogni~es the finding of a new higher valued signal by the charlge in the outputs of the latched comparators 62 or 64, whicll are connectecl to Timing Chip 44 via flip flops 74 and 75 on lines 70 arld 72. Pig-10 ures 3h and 3i show the state of the outputs of the even and odd flip flops 74and 75, respecti,vely.
'rhe OUtpllts of the comparators 62 and 64 are provided as inputs to respective flip flops 74 ancl 75, whose outputs are in turn provided to register 7G and as one input to exclusive-OR gates 78 and 80. The outputs o f register 76 are provided as the other inputs to exclusive-OR gate 78 alld 80. Flip Elops 74 arld 75 are clocked by Olc gates 71 and 73 respectively, which forlll the log-ical OR of the signals S2 ancl S4, ancl Sl and S3 respectively. This method of clocking these Elip flops assllres tllat the outputs o:t` the comparators are sampled after the comparators have challgc,~cl by sam;)ling an even position at the 20 next odd posit:ion and all odd posit;orl at tlle llext even position~ Fllrther tlle state of the fli.p flops remains steady for a predetermined clock period. Reg-ister 76 is clocked by the inversiorl of SCK approximately 90 nanoseconds after the clocking of flip flop 74. The exclusive-OR gates 78 and 80 compare the outputs of the comparator 62 and 64 from one symbol position to another and gelerate a pulse of approximately 90 nanoseconds duration if the outputs change.
~xclusive-OR gate 78 is indirectly connected to the output 66 of comparator 62.
Figure 3j shows the pulse LDO out of exclusive-OR gate 78 indicative of the changes in the relative signal levels in the Sl and S3 sample and holds dis-~91~3~S

cussed heretofore. Exclusive OR gate 80 is indirectly connected to the output 68 o:E the comparator 64. Figure 3k shows the pulse out of exclusive-OR gate 80 indicative of the changes in the relative signal level of sample and hold cells S2 and S4 discussed above. The load odd and load even pulses LDO and LDE occur when a new "higher" signal level has been recognized by the respec-tive comparators.
A l-data NOT signal which the optical recording system uses to issue a write pulse is provided as an input to the SET NOT input of a flip flop 92 and also to variable delay circuit 94. Tlle de1ay of the circuit 94 is ad-justable to a maximum delay o:E 100 n~nosecorlds so that the circuits of the pre-ferred embodiment can be fine tuned to a particular machine. The delay notollly adjusts tlle scttillg of the turn-off time of Sl througll S4, but also the timing in relation to the LDO and LDI. pulses. An l-data NOT pulse sets :Eilp flop 92 and a pulse from the 100 nallosecond variablc delay circuit 9/~ resets the flip :Elop 92 as tlle 1) input :is latched below. Ihe output o:E this flip ~Elol) is the dWP signal ShOWII :ill Figure 3n and is prov:ided botll to limillg Chip 4'l and to a flip Elop 96. Fl;p -Elop 96 is clockcd l)y the 2CK signal so th~lt the rising edge o:E 2CK scts the Elip flop allcl the next rising edge resets it. Ihe output o:E
this filp Elop 9G is the slVI' signcll sho\vll in l:;gure 20 allcl is provided to both 2() limillg Chip 44 and to a -Elip flop 98. I:lip Elop 98 is clocked by the invert-ed S(:K clock such that thc fall of SCK sets the flip flop wld the next fall resets. The signal out of this filp :Elop is the sWP* signal shown at Figure 3p.
Prom inspection of the Figure, it can be seen that sWP* is delayed about 120 nanosecollds form sWP. The output of this flip flop 98 is provided as an input to flip flops 100 and 102. These are clocked respectively by the LDE signal and the LDO signal. The delays of the 100 nanosecond delay 94 and flip flops 96 and 98 delay the write pulse from reaching flip flops 100 and 102 until a time corresponding to the "90" nanosecond sampling time of Sl through S4 sig-nals, the delays through the comparator 62, delays through the flip flops 74 and 75 and register 76, and the delays through exclusive OR gates 78 and 80.
If a hole has been properly written onto the optical recording sur-face, a write pulse will be presellt at the D input to flip flop 100 at the occurrence of the last load even and load odd pulses, LDE and LDO respectively.
If, and only if, there is a correspondellce between the last occurrellce of an l.DE sigllal and a~ LDO signal and respective write pulses in the even and odd pOsitiolls will the outputs of the flip :Elops 100 and 102 be simultaneously at a logical one state. Tlle output of flip flop 100 is S]IOWII at Figure 3s and the output of flip flop 102 is shown at Figure 3t. I:E the second write pulse of the first symbol did not write a pulse correctly or i-E a media defect caused ahigh level at anotller even pOsitioll, flip flop 100 will remaill ofE and this is shown in ligure 3s l-y the dashed lines. This same analysis pertaills to LDO and flip flop 102.
Ihe outputs o-E tllese Elip Elops 10() alld l()2 are input to a NANI) gate 104. The output of NANL) gate 104 is low i-f, and only if, Elip flops 100 and 102 lli-ve recorded the simultalleolls occurrence oE write pulses and load CVCII ànd load od~ signa1s.
A nibble count 0 (128) ;ssued by the nibble counter 126 and a ~1`1'2 pulse 140, which comprises a delayed TNC3 pulse from dclay 142, are inputs to a NAND gate 144, the output of which resets a JK flip flop 106. Nibble COUIIt 0 occurs every other symbol, and TP2 occurs at symbol position count 2. After the end of a symbol, the Timillg Chip 44 outputs an RER NOT signal which clocks JK flip flop 106. The RER NOT signal is shown at Figure 3r. If the state of the inputs to the JK input are zero, the Q output of the JK flip flop 106 re-mains unchanged. Thus, during the time oE two symbols comprising a byte of data with correctly wri-tten holes, the output of the flip flop 106 will remain 0. I-lowever, if either one of the two symbols between the resetting of the flip flop is incorrectly written, a 1 will be present at the inputs of the flip flop 106. T]lis will cause the Q output to changes to a 1 and remain in that state.
The state of the output of the JK flip :Elop is shown in Figure 3u. If the first symbol hada~l crror, the flip flop will have a high output at the occurrence of RER NOT at symbol position n of the second symbol as indicated by the dashed lines in the l`:igure.
In either case, the output of f~ip flop 106 is provided to a count input of cowltcr 108. Coullter 108 is init:ialized to a predetermined count by inl)uts DET0 to ~T3. The COUIlt can be varied to tolerate a certain level of errors. A clock input decrements the counter 108. At a count of 0, counter 108 outputs on the rc output an error status indiccltillg that the error toler-ance has been exceeded.
Ihe reasorl that the flip flop 1()6 indicates the presence of an error in oither o:E two syn~bols is l~ccause cach syml~ol oE a 'l'OON code encodes 4 bill.lry b:its of dutù. Ihus two symhols encode 8 bits o-E data. Ihe prefcrr-ed optical codillg systclll operates on l~ytes oE 8 bits.
Tlle above apllar.ltus was descr-ibed in conjunctioll with a T00N code.
Other codes having a null in the frequency spectrum are compatible with a pre-recorded clock. 0ne such code is a so-called 4/15 code in which there are 4 holes, two each in the even positions and two each iJI the odd positions. 0ne pOsitioll is left empty at the boundary. With this code, means must be pro-vided to detect the highest signal for both the even and the odd positions, and the second highest. To do this, one merely has to have three sample and holds instead of two, as well as three comparators. One sample and hold would hold the highest value, the second would hold the next highest and the third would hold the new sample to be compared with the other two. The results of the comparison would indicate whether we had a new highest or a new second highest value. These results would be la-tched and fed back through to the Timing Chip, as well as to write verify registers, the number of which would continue to correspond to the number of latched comparators. The method of the preferred embodiment is intellded to be general with respect to the class of codes havlng a null in the frequency spectrum at the frequency of the prere-corded clock.
An amorpllous pip occurs wllen the recording medium is not burned, but only trallsformed into its amorphous state. The amorpllous area has less re-flectivity than the medium in its crystalline state, but the reflectivity is still greater than that oE a hole. Figure 6 compares a read signal from an amorphous pip with that of a convclltiollal pip due to a hole. r['he first pip 150 in thc figure is that o~ the amorpllous pip. rllc sccond is that o:E the convelltiorlal pip 152. lt C.lll l)e SCCII th..Lt the amorpllous pip is about one-fiftll as strong as a convclltiollal pip, l~ut :it is still stronger than the sigll.Ll from the prerccorded clock 10. ~ system using differential detection where t~ signal form the symbol positions is compclred to a reference which is tlle signal of the prerecorded clock, will recognize the amorphous pip as a new higher signal. Further, if an amorphous pip occurs at a location where it should be, that is, at a location at which the write pulse attempted to write a hole, the write verify apparatus will incorrectly recognize that a true hole was written.

` `` ~29~

A solution to this problem lies in providing an offset voltage on the Read 2 signal in response to a write pulse. The offset is the same magni-tude as an amorphous pip, but opposite in polarity. With the offset inject-ed into the Read 2 signal, both the amorphous pip and a conventional pip will appear as the dotted lines 154 and 156 in Figure 6 respectively. It can be seen that the peak voltage of the amorphous pip does not rise above that of the prerccorded clock, and thus will not cause the write verify system to recog-nize it as a hole. I-lowever, the convelltiollal pip 156, which is five times as strong as the amorphous pip to begin with, remains much stronger than the sig-nal of the prerecorded clock 10, and w;ll continue to be recognized as a holeby the write verify system.
ln the preferred embodiment, the offset is provided by offset means 108 responsive to a wr:ite pulsc delayed by delay 107, Figure 1, which causes the AGC and Read Amplifier lln to offset the Read 2 pulse by the predetermined amount heretofore discussed. The delay 107 delays the o:Efset until after the write pulse on the media llas been turllecl oEf. The offset mealls 108 maintaills tlle offset for a fi~od period of time, sufficient to pcrmit the write veriEy apparatus ]32 to compiete tho sam~ lg oF the pip. Tlle actual circuitry for l ~formillg this functioll is not a i)art of the presellt 1nvelltioll, and any circui-try within the skiLl of those skilled in the art whicll performs the offsetfwlctioll is contelllplcLted.
The enlmleration of thc elements of the preferred embodiment are not to be taken as a limitation on the scope of the appended claims.

Claims (4)

1. An optical recording apparatus provided with means for scanning an optically writeable medium with radiation pulses in order to form optically detectable marks on the medium, with radiation sensitive detector means for detecting the radiation of the radiation beam reflected by the medium and for converting the radiation detected into a corresponding read signal, with write verify means for verifying the forming of an optical detectable mark on the basis of the read signal, and means for offsetting the read signal by a predetermined offset value in response to the generation of a radiation pulse so as to prevent the detection of an amorphous pip.

2. An optical recording apparatus of claim 1, wherein said offset means comprise means connected to read signal automatic gain control and amplifier means for causing it to offset the read signal output to the write verify means by a predetermined value.

3. An optical recording apparatus of claim 1, wherein said predetermined offset value is approximately equal in magnitude to the read signal input to the write verify system caused by an amorphous pip, but opposite in polarity to the polarity of the amorphous pip read signal.

4. An optical recording apparatus of claim 2, wherein said predetermined offset value is approximately equal in magnitude to the read signal input to the write verify system caused by an amorphous pip, but opposite in polarity to the polarity of the amorphous pip read signal.