CA1283955C - Method and arrangement for adjusting and regulating the frequency of a signal generator - Google Patents
Method and arrangement for adjusting and regulating the frequency of a signal generatorInfo
- Publication number
- CA1283955C CA1283955C CA000465237A CA465237A CA1283955C CA 1283955 C CA1283955 C CA 1283955C CA 000465237 A CA000465237 A CA 000465237A CA 465237 A CA465237 A CA 465237A CA 1283955 C CA1283955 C CA 1283955C
- Authority
- CA
- Canada
- Prior art keywords
- voltage
- frequency
- deviation
- counter
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000001105 regulatory effect Effects 0.000 title 1
- 230000000737 periodic effect Effects 0.000 claims abstract description 4
- 230000001419 dependent effect Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229940035564 duration Drugs 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
ABSTRACT
Disclosed is a process to control the frequency of a voltage-controlled oscillator in which the frequency of the voltage-controlled oscil-lator is counted for a constant gating time to generate a binary pattern which is compared with a stored nominal-value pattern. From this a sign valve (+/-) and a binary pattern for the size of the deviation are determined. The binary pattern for the size is used to pre-set a deviation counter which is then stepped back to null by means of a periodic input signal, an adjustment voltage being passed to the adjusting element of the voltage-controlled oscillator through a switch for the duration of the step-back procedure.
Disclosed is a process to control the frequency of a voltage-controlled oscillator in which the frequency of the voltage-controlled oscil-lator is counted for a constant gating time to generate a binary pattern which is compared with a stored nominal-value pattern. From this a sign valve (+/-) and a binary pattern for the size of the deviation are determined. The binary pattern for the size is used to pre-set a deviation counter which is then stepped back to null by means of a periodic input signal, an adjustment voltage being passed to the adjusting element of the voltage-controlled oscillator through a switch for the duration of the step-back procedure.
Description
~39~i5 The present invention relates to a process for adjusting and controlling the Erequency of a signal generator with a voltage-controlled oscillator, a check stage, and at least one counter, with the aid of a microprocessor having a PROM and a RAM . ' ' A layout for carrying out such a process is known from DE-OS 32 32 519, published on April 14, 1983 wherein the duration of at least one period of the actual signal is measured and a manipulated variable computed from this with the aid of a microprocessor, this variable bringing a voltage-controlled oscillator to the nominal frequency through a digital-analog con-verter. The control characteristic of the voltage-controlled oscillator must be programmed into the processor when this is done. Furthermore, the capture range of the known layout is ~
very restricted, which means that prior to adjustment the :
oscillator must first be brought to approximately the desired frequency.
It is the task of the present invention to provide a process of the klnd described above, in which the control chara-cteristic of the oscillator plays no part in the generation of the manipulated variable and the capture range is greatly expanded.
The solution of this problem is characterized by the fact that the frequency of the voltage-controlled oscillator is counted by thec;~eck : stage during a constant gating time generated by the microprocessor;
.
in that a binary pattern generated by the counting process is com-: ~ pared:with a stored nominal-value pattern and a sign (+/-) ~: :
~: : ,.
- ~ .
839~
and a binary pat-tern for -the value of the deviation is determined therefrom; in that a deviation counter is pre-set with the binary pattern for the value of the deviation and then, with the help of a periodic input signal, is stepped back to zero; and in that at the start of this reset procedure a switch is closed and then opened at tne end of the step-back procedure, a voltage, the polarity of which is a function of the sign of the deviation, being passed to an RC element and then to the adjusting element of the voltage-controlled oscillator.
The process may be used through the microprocessor for the simultaneous frequency control of a plurality of vol~age-controlled oscillators.
The nominal value pattern may be altered by way of a keyboard.
The present invention is described in greater detail below, on the basis of the drawing appended hereto which illustrates a circuit arrangement witn which the process according to the invention can be carried out.
A microprocessor RF is used for input, control and comparison of actual and nominal values. The test frequency i.e. the frequency of the VCO, is counted by a binary counter FM, the step count of which is determined by the required degree of precision. The gating -time for counter FM is derived -from the reference oscillator of the microprocessor RF that is provided ~; ~ with a super-accurate quartz crystal. The input E can be converted ~ ~ .
very restricted, which means that prior to adjustment the :
oscillator must first be brought to approximately the desired frequency.
It is the task of the present invention to provide a process of the klnd described above, in which the control chara-cteristic of the oscillator plays no part in the generation of the manipulated variable and the capture range is greatly expanded.
The solution of this problem is characterized by the fact that the frequency of the voltage-controlled oscillator is counted by thec;~eck : stage during a constant gating time generated by the microprocessor;
.
in that a binary pattern generated by the counting process is com-: ~ pared:with a stored nominal-value pattern and a sign (+/-) ~: :
~: : ,.
- ~ .
839~
and a binary pat-tern for -the value of the deviation is determined therefrom; in that a deviation counter is pre-set with the binary pattern for the value of the deviation and then, with the help of a periodic input signal, is stepped back to zero; and in that at the start of this reset procedure a switch is closed and then opened at tne end of the step-back procedure, a voltage, the polarity of which is a function of the sign of the deviation, being passed to an RC element and then to the adjusting element of the voltage-controlled oscillator.
The process may be used through the microprocessor for the simultaneous frequency control of a plurality of vol~age-controlled oscillators.
The nominal value pattern may be altered by way of a keyboard.
The present invention is described in greater detail below, on the basis of the drawing appended hereto which illustrates a circuit arrangement witn which the process according to the invention can be carried out.
A microprocessor RF is used for input, control and comparison of actual and nominal values. The test frequency i.e. the frequency of the VCO, is counted by a binary counter FM, the step count of which is determined by the required degree of precision. The gating -time for counter FM is derived -from the reference oscillator of the microprocessor RF that is provided ~; ~ with a super-accurate quartz crystal. The input E can be converted ~ ~ .
: . , . . ~ ~ ' , ! -: ~' ~ - ' ,~ ', " ' ' ' ' ', ,'' ~ ' ' ' ': ,. '' ' . ~ ' ~2~339S5 by converter SR directly to a binary nominal value SK in any form such as frequency, channel number, or the like, and this can then be compared with the tes-t value in the nominal value/actual comparator SIV. The amount of discrepancy that is determined and the sign evaluation control a control-voltage converter (D/A converter) KS. In its turn, this converter adjusts the voltage-dependent oscillator VCO to its nominal frequency through the loop ~ilter RC. If preeision greater than a factor of 103 is sought, an A/D converter having greater than usual resolution will be needed. As an example, a 20-step counter will provide precision of 22, i.e., approximately 106. For this reason, another path has been seleeted to obtain a control voltage from the differential bit pattern. Tne bit pattern obtained from the nominal value/actual value comparitor SIV is stored in a eounter.
This counter is then stepped back with the periodic signal from the referenee oscillator in microprocessor RF until -2a-. . . ~ , ..
1- ' : - - ~- ~: - . ' .' . . : . , ' .
:
~83~
this sends a signal on reaching the null counter status. The time differential from the start of the s-tep-back procedure until the counter passes through null (FM) is a measure of the cleviation of the actual frequency from the nominal frequency. The amount and direction of the control-voltage correction is determined together with the sign information gained from the comparison of the actual/nominal value comparison. This is passed to the oscillator ~VCO) through an analog channel switch (contact mechanism) and a subsequent RC element.
Only when the frequencies have changed by more than one bit, by self-discharge of the RC element, temperature deviation or change in the supply voltage will an adjustment be made, i.e., the actual frequency varies from the nominal frequency by ~/- one bit. In order to keep circuit costs to a minimum the same frequency counter is used for frequency count and to obtain the time differen-tial, this being done in sequential processes. The capture range of the frequency-control loop constructed according to the present invention is large from the null frequency to the maximum limit frequency of the counter component blocks, with an appropriately selected gating time, so that the range depends, in the main, on the tuning range of the voltage-controlled oscillator.
The nominal value/actual value comparator SIV is a logic device at whose one input the binary pattern of the nominal frequency is applied and at whose other input the binary pattern of the actual frequency is applied.
The difference between the two binary patterns, which is applied to the sub-assembly KS, is formed through SIV. The analog channel switch is a digitally controlled analog switch. The sign information of the frequency deviation is applied at a data input and a pulse is applied to a control input, its dura-tion being determined by the time difference between start and zero-axis crossing of the deviation counter in the sub-assembly KS, whereby the deviation . . ..
This counter is then stepped back with the periodic signal from the referenee oscillator in microprocessor RF until -2a-. . . ~ , ..
1- ' : - - ~- ~: - . ' .' . . : . , ' .
:
~83~
this sends a signal on reaching the null counter status. The time differential from the start of the s-tep-back procedure until the counter passes through null (FM) is a measure of the cleviation of the actual frequency from the nominal frequency. The amount and direction of the control-voltage correction is determined together with the sign information gained from the comparison of the actual/nominal value comparison. This is passed to the oscillator ~VCO) through an analog channel switch (contact mechanism) and a subsequent RC element.
Only when the frequencies have changed by more than one bit, by self-discharge of the RC element, temperature deviation or change in the supply voltage will an adjustment be made, i.e., the actual frequency varies from the nominal frequency by ~/- one bit. In order to keep circuit costs to a minimum the same frequency counter is used for frequency count and to obtain the time differen-tial, this being done in sequential processes. The capture range of the frequency-control loop constructed according to the present invention is large from the null frequency to the maximum limit frequency of the counter component blocks, with an appropriately selected gating time, so that the range depends, in the main, on the tuning range of the voltage-controlled oscillator.
The nominal value/actual value comparator SIV is a logic device at whose one input the binary pattern of the nominal frequency is applied and at whose other input the binary pattern of the actual frequency is applied.
The difference between the two binary patterns, which is applied to the sub-assembly KS, is formed through SIV. The analog channel switch is a digitally controlled analog switch. The sign information of the frequency deviation is applied at a data input and a pulse is applied to a control input, its dura-tion being determined by the time difference between start and zero-axis crossing of the deviation counter in the sub-assembly KS, whereby the deviation . . ..
~.. ~ ,, ;' : ~ . -~ : .. , , -., -:, - - . - . :
.:. .- ~ . : : . . . : . ,. : .
, ~ , , :
.
:: - . . - .: .
:: . . :
s counter is pre-set by the binary pattern for the size (value) of the deviation and is then reset in steps to zero, for example in the cycle of the reference frequency. A direct voltage then lies at the output of the channel switch which serves to adjust the VCO. ~-All of the individual functions described before, 1. conversion of the input values into nominal frequency values, 2. subtraction of nominal value/actual value ~:
3. control of counter FM
.:. .- ~ . : : . . . : . ,. : .
, ~ , , :
.
:: - . . - .: .
:: . . :
s counter is pre-set by the binary pattern for the size (value) of the deviation and is then reset in steps to zero, for example in the cycle of the reference frequency. A direct voltage then lies at the output of the channel switch which serves to adjust the VCO. ~-All of the individual functions described before, 1. conversion of the input values into nominal frequency values, 2. subtraction of nominal value/actual value ~:
3. control of counter FM
4. actuating the contact mechanism with the counter in a realized circuit arrangement are brought about by a microprocessor system.
:-' : ~' : ~ :
~ .
.
:-' : ~' : ~ :
~ .
.
Claims (4)
1. A process to adjust and control the frequency of a signal genera-tor with a voltage-controlled oscillator, a measuring circuit, and at least one counter, with the aid of a microprocessor having a ROM and RAM, character-ized in that the frequency of the voltage-controlled oscillator is counted by the measuring circuit during a constant gating time that is generated by the microprocessor; in that a binary pattern generated by the counting pro-cedure is compared with a stored nominal-value pattern, the sign and a binary pattern for the size of the deviation being determined therefrom; in that a deviation counter is pre-set with the binary pattern for the size of the deviation and then stepped back to zero with the help of a periodic input sig-nal; in that at the start of the step-back procedure a switch is closed and opened at the termination of the step-back procedure, a voltage, the polarity of which is dependent on the sign of the deviation being passed through this switch, to an RC element, and then to the adjusting element of the voltage-controlled oscillator.
2. A process according to claim 1, characterized in that it is used through the microprocessor for the simultaneous frequency control of a plurality of voltage-controlled oscillators.
3. A process according to claim 1, characterized in that the nominal value pattern can be altered by way of a keyboard.
4. A layout for effecting the process according to claim 1, character-ized in that the counter in the measuring stage for counting the frequency of the voltage-controlled oscillator and the deviation counter are one and the same.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3337283.7 | 1983-10-13 | ||
| DE19833337283 DE3337283A1 (en) | 1983-10-13 | 1983-10-13 | METHOD AND ARRANGEMENT FOR ADJUSTING AND REGULATING THE FREQUENCY OF A SIGNAL GENERATOR |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1283955C true CA1283955C (en) | 1991-05-07 |
Family
ID=6211762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000465237A Expired - Fee Related CA1283955C (en) | 1983-10-13 | 1984-10-12 | Method and arrangement for adjusting and regulating the frequency of a signal generator |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0138008B1 (en) |
| AT (1) | ATE38304T1 (en) |
| CA (1) | CA1283955C (en) |
| DE (2) | DE3337283A1 (en) |
| DK (1) | DK489884A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5117756A (en) * | 1989-02-03 | 1992-06-02 | Atlas Powder Company | Method and apparatus for a calibrated electronic timing circuit |
| FR2726921B1 (en) * | 1994-11-16 | 1997-04-25 | Ela Medical Sa | METHOD FOR ADJUSTING AN ELECTRICAL PARAMETER OF AN ELECTRONIC DEVICE, IN PARTICULAR A PACEMAKER OR A CARDIAC DEFIBRILLATOR, AND DEVICE IMPLEMENTING IT |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2853842A1 (en) * | 1977-12-14 | 1979-07-19 | Hitachi Ltd | Electronically tuned receiver with oscillator drift correction - compares output of frequency monitor with stored output at end of channel selection operation to alter code signal |
| DE2818529A1 (en) * | 1978-04-27 | 1979-10-31 | Philips Patentverwaltung | Automatic tuning of TV or radio receiver - has oscillator output digitally compared with reference to provide adjustment of frequency |
| US4298988A (en) * | 1979-02-08 | 1981-11-03 | Jerrold Electronics Corp. | Digital channel selection and fine tuning system |
| FR2497027B1 (en) * | 1980-12-23 | 1985-06-14 | Thomson Csf | FREQUENCY CORRECTION DEVICE OF AN OSCILLATOR AND TRANSCEIVER INCLUDING SUCH A DEVICE |
| JPS5847331A (en) * | 1981-09-04 | 1983-03-19 | テクトロニクス・インコ−ポレイテツド | Signal generator |
-
1983
- 1983-10-13 DE DE19833337283 patent/DE3337283A1/en not_active Withdrawn
-
1984
- 1984-08-31 AT AT84110371T patent/ATE38304T1/en not_active IP Right Cessation
- 1984-08-31 DE DE8484110371T patent/DE3474891D1/en not_active Expired
- 1984-08-31 EP EP84110371A patent/EP0138008B1/en not_active Expired
- 1984-10-12 CA CA000465237A patent/CA1283955C/en not_active Expired - Fee Related
- 1984-10-12 DK DK489884A patent/DK489884A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0138008B1 (en) | 1988-10-26 |
| EP0138008A2 (en) | 1985-04-24 |
| DK489884A (en) | 1985-04-14 |
| DE3337283A1 (en) | 1985-04-25 |
| DK489884D0 (en) | 1984-10-12 |
| DE3474891D1 (en) | 1988-12-01 |
| EP0138008A3 (en) | 1985-06-12 |
| ATE38304T1 (en) | 1988-11-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |