CA1280168C - Fault indicator having delayed trip circuit - Google Patents
Fault indicator having delayed trip circuitInfo
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- CA1280168C CA1280168C CA000556530A CA556530A CA1280168C CA 1280168 C CA1280168 C CA 1280168C CA 000556530 A CA000556530 A CA 000556530A CA 556530 A CA556530 A CA 556530A CA 1280168 C CA1280168 C CA 1280168C
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- reset
- fault
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- trip
- capacitor
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Abstract
FAULT INDICATOR HAVING DELAYED TRIP CIRCUIT
Abstract of the Disclosure A reset coordinated fault indicator for indicating the occurrence of a fault current in a monitored conductor includes an electrically actuated indicator flag. A trip circuit within the fault indicator impulses the indicator flag from a normal reset-indicating state to a fault-indicating state following the occurrence of a fault current in the conductor. A reset circuit periodically impulses the indicator flag to the reset-indicating state upon restor-ation of power to the conductor. To preclude simultaneous actuation of the trip and reset circuits and consequent failure of the indicator flag to register a fault, the trip circuit, upon the occurrence of a fault, first actuates the reset circuit to render the reset circuit inoperative, and then actuates the trip circuit to provide a fault indication.
Abstract of the Disclosure A reset coordinated fault indicator for indicating the occurrence of a fault current in a monitored conductor includes an electrically actuated indicator flag. A trip circuit within the fault indicator impulses the indicator flag from a normal reset-indicating state to a fault-indicating state following the occurrence of a fault current in the conductor. A reset circuit periodically impulses the indicator flag to the reset-indicating state upon restor-ation of power to the conductor. To preclude simultaneous actuation of the trip and reset circuits and consequent failure of the indicator flag to register a fault, the trip circuit, upon the occurrence of a fault, first actuates the reset circuit to render the reset circuit inoperative, and then actuates the trip circuit to provide a fault indication.
Description
SP~CIFICATION
Backqround of the Invention The present invention relates gener~lly to fault indicaeors for alternating current electrical distribution 5 systems, snd more particularly to ~elf-resetting fault indicators wherein upon occurrence of a fault the reset circuit of the indicator i8 actuated before the trip circuit thereof to preclude simultaneous actuation of the two circuits.
Fault indicators of various types have been con~tructed for detecting faults in electrical power distribution systems. Such indicators include cl~p-on type indicators, which clamp directly over cables in the system, and test point-type indicator~, which are mounted on te~t points provided on connector~ or component~ of the system.
Fault indicators of both types may be either of the manually reset type, wherein it i~ necessary that the indicator be phy ically reset following each fault, or of the automat$cally reset type, wherein a fault lndication is reset upon restoration of line current. Examples of such fault indicators are found in products manufactured by E. O.
Schweitzer Manufacturing Company of Mundelein, Illinois, and in U.S. Patent No~. 4,063,171, 4,234,847, 4,251,770, 4,236,550 4,438,403 and 4,458,198 of the present $nventor.
Self-re~etting fault indicaeors typically employ an indicator device, a trip circuit for conditioning the indicator device to indicate a fault upon occurrence of ~280i68 fault current in a monitored conductor, and a perlodically-actuated reset circuit powered by the monitored conductor for conditioning the indicator device to a reset state upon occurrence of normal current in the monitored conductor.
S Because the reset circuit i~ actuated at periodic intervals in the presence of current on the monitored conductor, there exists the possibility that the reset circuit will actuate at the same time the trip circuit actuates in response to a fault current, and the indicator will therefore fail to respond to the fault, providing the user with erroneous information that a fault did not occur.
Summarv of the InYention The invention is directed to a fault indicator for indicating the occurrence of a fault current in an electrical conductor of an alternating current po~er distribution system. The indicator includes status indicating means having reset-indicating and fault-indicating state6. Trip circuit means condition the ~tatus indicating means to the fault-indicating state in response to the occurrence of a fault current in the conductor.
Reset circuit means periodically condition the status indciating mean~ to the reset-indicating state in the presence of voltage on the conductor. The trip circuit means actuate the reset circuit means upon occurrence of a fault prior to conditioning tbe status indicator ~eans to the fault-indicating state to preclude simultaneous actuation of the reset and trip circuit means.
~280168 Briel DescriDtion of the Dra~in~
The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The invention, together with the further S objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several figure~ of which like reference numeral~ identify like elements, and in which:
Figure 1 is a side elevational view, partially in section, illustrating an reset-coordinated ~elf-resettinq fault indicator constructed in accordance with the present invention mounted on the test-point terminal of a conventional elbow-type terminal connector.
Figure 2 is a fragmentary perspective view of the fault indicator of Figure 1 in a partially disa~sembled state.
Figure 3 is an electrical schematic diagram of the fault indicator illustrated in Figure6 1 and 2.
Figures 4a and 4b are diagrammatic views of principal indicator components of the fault indicator in a reset state.
Figures 5a and Sb are diagrammatic views similar to Figure 4a and 4b, respectively, showing the indicator components of the fault indicator in transition between a reset state and a tripped state.
Figure~ 6a and 6b are diagrammatic view8 simil~r i280168 to Figure 4a and 4b, re6pectively, showinq the indicator components of the fault indicator in a tripped state.
Figure 7 is an electrical schematic diagram of an alternate reset-coordinated circuit for use in the fault S indicator illustrated in Figure 1.
Fiqure 8 is an electrical scbematic diagram of an alternate two-winding reset coordinated circuit for use in the fault indicator illustrated in Figure 1.
Figure 9 is a per~pective view illustratinq a reset-coordinated fault indicator constructed in accordance with the present invention installed on a high voltage cable of a power distribution system.
Figure 10 is a cross-sectional view of the fault indicator taken along line 10-10 of Figure 9.
lS Figure 11 i8 a cross-sectional view taken along line 11-11 of Figure 10.
Figure 12 is a cross-sectional view taken along line 12-12 of Figure 10.
Figure 13 is an electrical schematic diagram of the fault indicator lllustr~ted in Figure 9.
Figures 14a and 14b are diagrammabic views of principal indicator components of the fault indicator illustrated in Figures 9 and 10 in a reset state.
Figures 15a and l5b are diagrammatic views similar to Figure~ 14a and 14b, respectively, showing the indicator components of the fault indicator in transition between a reset state and a tripped ~tate.
~Z80~68 Figures 16a and 16b are diagrammatic vie~6 similar to Figures l~a and 14b, respectively, showing the indicator components of the fault indicator in a tripped state.
Figures 17a and 17b are diagrammatic views similar to Figure~ 14a and 14b, respectively, showing the indicator components of the fault indicator in transition between a tripped state and a re~et state.
Figure 18 is a per~pective view of an indicatively coupled reset-coordinated ~elf-resetting fault indicator constructed in accordance with the invention.
Figure 19 i8 an electrical schematic diagram of the fault indicator illustrated in Figure 18.
DescriPtion of the Prfeferred embodiment Referring to the drawing~, and particularly to Figures 1 and 2, a trip-inhibited fault indicator 10 constructed in accordance wi~h the invention i8 shown inctalled on a plug-in elbow connector 11 of conventional construction for use in high voltage alternating current system for establishing a plug-in connection to a transformer (not sbown) or other device. As shown, the connector 11 includes generally an axial conductor 12 extending through an electrically insulating body portion 13 encased in an electrically-conductive sheath 14, the 6heath being grounded in accordance with conventional practice. An 25~ arcuate member 16 having ends anchored in ~heath 14 extends from the connector to receive the hooked end of a lineman's tool commonly used to remove plug-in connectors fro~ ~uch :
. ;- .
~280~L68 devices.
Elbow connector 11 includes a test point terminal 17 for receiving a circuit condition indicating device, in this case fault current indicator 10. The test point i8 formed by a portion of the insulating body layer 13, which projects radially through the conductive sheath 1~.
Embedded in the test point terninal 17 is an electrically conductive contact 18 which i8 exposed at its outer end to provide for an electrical connection to the contact, and which at its inner portion is positioned in proximity to conductor 12 to capacitively couple the contact to the conductor.
The housing of fault indicator 10 includes an electrically conductive semi-flexible rubber outer shell 20 which i6 open and dimensioned at one end for engaging test point 17. The shell 20 receives a corre~pondingly sized cylindrical plastic housing 21 in which the electrical components of the fault indicator device are contained. The cylindrical housing includes an integral partition 26 ~hich serve~ as a mask and spacing element, and a tran~parent end cap 27 which is sonically welded to the end of the housing.
At the closed end of ~hell 20, an apertured tab 29 is provided to facilitate installation and removal of the fault indicator with a conventional hooked lineman'~ tool.
Referring to Figure 2, a disc-shaped circuit board 31 i& positioned within housing 21 perpendicular to the axis of the housing at a location intermediate the ends thereof.
~280168 Ihe circuit board, which ~ay be secured in position by an eposy material 32, serves as mounting mean~ for the electrical components of the fault indicator. An electrical connection is established between this circuitry and test point contact 18 by means of a helical 6pring 33, the spring being connected at one end to a wire conductor extending from the circuit board, and being resilien~ly pressed at the other end against contact 18. An electrical ground connection is established to the circuit board by means of an additional electrical conductor 35 compressively wedged between housing 21 and the electrically conductive outer shell 20 grounded through sheath 14.
To provide an indication of the occurrence of a fault current in conductor 12, the fault indicator include~
within the lower end of housing 21 a disc-shaped target member 34 which is mounted for rotation on a pivot 6haft 36.
The face of the target disc ha~ a red ~egment 34a (Figures 4-6) and a white segment 34b, each comprising one-half of the target face, and only one of which is visible at a time through a window 37 provided in shell 20 and the end cap 27 of housing 21.
Secured ~o and pivotal with target 34 member i~ a disc-shaped target actuator maqnet 38, which is formed of a magnetic material having a high coercive force, sucb as ceramic, and which i6 magnetically polarized to form two magnetic poles of opposite magnetic polarity, as indicated in Figures ~-6. 5he actuator uagnet 38, and bence the ~280168 target member 34, are rotated between reset-indicating and fault-indicating positions by rotational force~ e~erted on the magnet by means of a stationary generally U-shaped magnetic pole piece 39, which is located within housing 21 with the projecting poles thereof diametrically opposed and adjacent the edge of the magnet.
When the fault indicator is in a reset-indicating state, pole piece 39, which i8 preferably formed of a magnetic material having a relatively low coercive force, such as a chrome steel, is magnetized at its projecting poles to the magnetic polarities ~ndicated in Figures 4a-4b.
As a result, the opposite polarity magnetic poles of the target magnet are attracted to position the target member 34 as shown. In this position the red ~egment 34a of the target disc is not visible through window 37, and only tbe white segment 34b is visible to indicate to an observer that the indicator i~ in thea re~et condition.
On the occurrence of a fault current in conductor 12, which current may, for e~mple, eYceed ~00 amperes, pole piece 39, and an adjacent au~iliary pole piece ~0 of similar construction, are remagnetized to the magnetic polarities æhown in Figures 5a-5b and 6a-6b by momentary energization of a magnetic winding 41 on the center section of pole piece 39. As a result, the poles of magnet 38 are repelled by the adjacent like-magnetic polarity poles of the pole pieces and the target disc iB caused to rotate 180 counter-clockwise to the tripped position shown in Figures 6a-6b. In tbi8 position, the red segment 34b of the target disc is visible through window 37 (Figure 2) and a lineman viewing the fault indicator i8 advised that a fault current has occurred in conductor 12.
Target di~c 34 remains in the fault indicating position until the poles of pole pieces 39 and 40 are ~ubsequently remaqnetized to tbe magnetic polarities shown in Fiqure~ 4a-4b by momentary energiation of winding 41 with a current in the opposite direction. As a reQult, the target magnet 38, and hence the target disc 34, are cauæed to rotate from the tripped position shown in P$gures 6a-6b to the reset position shown ln Fiqures 4a-4b, and the fault indicator is conditioned to respond to a subseguent fault current.
Energization of winding 41 in one direction upon occurrence of a fault current in conductor 12, and energization of winding 41 in the other direction upon re~toration of current in the conductor following a fault, is accomplished by means of e~ternally-powered circuitry contained within the fault indicator. Referring to the schematic diagram shown in Figure 3, operating power for energizing winding 41 i8 obtained by means of a bridge :rectifier network 43, con~isting of four diodes ~6-49. One input terminal of this networ~, formed at the juncture of the anode of diode 46 and the cathode of diode 47, is connected through the helical spring 33 to te~t point contact 18. The other ~nput terminal, formed at tbe anode of diode ~8 and the cathode of diode ~9, i~ connected to ground through the electrically conductive outer shell 20 of the faul~ indicator housing. With this arrangement. high voltage alternating current carried in conductor 12 is capacitively coupled to the bridge rectifier network, resulting in the production of a pul~ating unidirectional current at the output terminals of the network.
The positive polarity output terminal of the bridge rectifier network i6 formed at the cathodes of diodes ~6 and 48, and the negative polarity output terminal of the rectifier network is formed at the juncture of the anodes of diodes 47 and 49. To provide the trip and re~et functions of the fault indicator, a trip capacitor 50 and a reset capacitor ~1 are connected to the output terminals to receive a charge current from the rectifier network. Trip capacitor 50 is directly connected, and reset capacitor 51 i8 connected through winding ~1, and an isolation resistor 52. A zener diode 42 i8 connected across the network output terminals to limit rectifier output voltage.
To provide for energization of winding 41 in one direction upon occurrence of a fault current in conductor 12, the winding ig connected to receive discharge current from trip capacitor 50 through a gilicon controlled rectifier (SCR) 53 connected in series with the winding and the capacitor. Upon occurrence of a fault current, a reed switch 54, positioned within housing 21 in close proximity to conductor 12 80 a~ to close ln response to the magnetic ~280~68 field produced by a fault-level current, cause~ an enabling current to be applied from rectifier network ~3 through a resistor 55 and bilateral d~ode 56 to the gate electrode of SCR 53 to initiate conduction through the SCR. A capacitor 57 and re~istor 58 in the SCR gate circuit provide a predetermined ti~e delay to the trip function following closure of switch 54. A resi~tor 59 provides a drain circuit to qround for the gate electrode.
To maintain fault indicator 10 in a reset condition in the absence of a fault current, reset capacitor 51 i~ periodically discharged into winding 41 in a reverse direction to the discharge current of trlp capacitor 50 in the presence of voltage on conductor 12. To this end, winding 41 i8 connected through a s~licon controlled rectifier (SCR) 60 to re~et capacitor 51. Periodic conduction through SCR 60 i~ obtained ffl connecting the gate electrode of that device to tbe positive polarity output terminal of bridge rectifier U through a resi~tor 61 and a pair of series connected bilateral diodes 62 and 63. A
resistor 64 provides a ground return for the gate electrode.
~nder normal current flow condition~, a~ trip capacitor 50 i8 charged by the pulsating direct current output of bridge rectifier network, reset capacitor 51 i~ charged through winding 41 and resistor 52. Ihe voltage developed across the capacitor~ progressively increases with time, until the threshold voltage of the bilateral diode~ i8 reached, at which time conduction i8 initiated through 8CR 60 and ,~
~280168 c~pacitor 51 discharges througb winding 41. Resistor 52 prevents trip capacitor 50 from being discharged with reset capacitor 51, leaving this capacitor available for powering the trip circuit. Following the discharge, SCR 60 i8 rendered non-conductive until tbe voltage level acros~
capacitor S2 increa~e~ to the threshold voltage level of the bilateral diodes, at which time another reset cycle occur~.
With the periodic energization of winding 41 in the manner magnetic pole assembly 39 ic magnetized as shown in Figures 4a-4b with the presence of voltage on conductor 12, and flag indicator 34 i8 positioned as shown to indicate a reset mode.
In practice, the breakdown voltage of bilateral diodes 62 and 63 may be in order of 34 volts, and the time required for capacitor 51 to reach this threshold level with a typical voltage level of 4,400 volts on conductor 12 may be approxiamtely 2 minutes or less. Ihe voltage level within conductor 12 i8 not critical to the operation of the reset circuit, and has only the effect of changing the repetition rate of the reset cycle.
Upon occurrence of a fault current in conductor 12 trip capacitor 50 is discharged through SCR 53 and trip winding 41. The resulting magnetic flux in pole piece 39 reverces the magnetic polarities of the pole piece and causes rotation of indicator flag 34 to a trip-indicating position as previously described. In particular, the ~agnetic polarities of pole piece 39 are reversed as shown ~280~68 in Figures Sa-5b, causing the magnetic poles of the pole piece to repel the like pole~ of magnet 38 and induce a 180 rotation of the indicator flag. The auxiliary pole piece ~0 a~ists in this rotation.
S To preclude the possibility of ~imultaneou~
actuation of the trip and reset circuits and consequent failure of flag indicator 34 to regi~ter a fault, a reset coordination feature i8 provided in accordance with the invention to actuate and thus disable the reset circuit for a predetermined period of time following the fault, and to delay the actuation of the trip circuit until ~fter actuation and disablement of the reset circuit. To this end, switch 54 iQ connected through a diode 65 and resistor 66 to the juncture of bilateral diodes 62 and 63. ~pon lS closure of switch 54, an enabling signal i8 applied to the gate electrode of SCR 60, resi~tor 66 serving to l~mit current flow and diode 65 ser~ing to prevent actuation of SCR 53 with application of normal reset signals to SC~ 60 through bilateral diode 62. Since the enabling signal will ordinarily exceed the threshold of diode 63, tbe result i8 immediate conduction through SCR 60 and discharge of reset capacitor Sl through winding ~1. Resistor 52 prevents any appreciable discharge of trip capacitor 50 at this time.
Capacitor 51 continues to discharge through ~ winding 41 in a direction whicb resets the indicator flaq for a finite reset period until the voltage across the ~280168 capacitor falls to a level where SCR 60 ceases to conduct.
The cluration of this reset period is dependent on a nu~ber of circuit components and circuit parameters, including capacitor 51, windin~ 41 and tbe voltage developed by S rectifier network 43 across capacitor 51, and in practice may typically be in the order of .16 millisecond.
Following the reset period the reset circuit is inoperative, and doe~ not again become operative until capacitor 51 is charged sufficiently to exceed the voltage thre~hold of bilateral diodes 62 and 63. As previously developed, this recovery period may be in the order of two minutes or more.
During the recovery period of the reset circuit SCR 53 i8 rendered conductive to cause trip capacitor 50 to discharge through winding 41 in a direction which conditions indicator flag 54 to a fault-indicating state. mi8 is accomplished by connecting switch 54 to the gate electrode of SCR 53 through an R-C network comprising resi~tors 55 and 58, capacitor 57, and bilater~l diode 56, which introduce~ a predetermined delay period to the trip signal greater than the duration of the reset cycle. By reason of re6istor 55 being connected between the gate and switch 54 the network is prevented from having a delaying effect on the ~ignal applied to the gate electrode of SCR 60.
Thus, upon occurrence of a fault and closure of ~witch 54, the reset circuit i~ immediately actuated, and the trip circuit i~ only actuated after a predetermined 1~
1280~68 delay period which i8 greater than the operating period of the re~et circuit.
An alternate circuit for use in a trip-coordinated fault indicator constructed in accordance with the invention S is shown in Figure 7. In ~uch trip-coordinated fault indicators the trip circuit is inhibited upon re~toration of power on the monitored conductor to prevent initial surge current~ from cau~ing a fault indication. To this end, the circuit includes an additional trip inhibit capac~tor 67 in series with trip capacitor. A diode 57 is connected acros~
capacitor 54 in a direction forward-bia~ed to the charging current produced by rectifier network 43.
The ~uncture of capacitors S3 and 54 is connected to one principal electrode of an enhanced ~ET-type transistor 60. The remaining principal electrode of transistor 60 i~ connected through a resistor 61 to the positive polarity output terminal of rectifier network 43.
The gate electrode of transistor 6~ is connected through a resistor 62 to the negative polarity output ter~inal of the ~20 network.
In operation, in the presence of voltage on conductor 12 the voltage developed across trip inhibit capacitor 67 by the pulsating charge current developed by bridge rectifier network 43 is limited to the forward voltage drop of diode 68. By reason of re~istor 71, thi~
limited voltage appear~ as a reverse bias on the gate ~Z80168 electrode of transistor 70, causing that device to be conditioned to a non-conductive state. Consequently, the transistor and resistor 72 have no effect on the charge contained on trip capacitor 50.
S ~owever, upon 1088 of voltage on conductor 12, and the consequent absence of output from bridge rectifier network 43, a portion of the charge contained in trip capacitor 50 is transferred tbrough resistor 73 to trip inhibit capacitor 67, causing that capacitor to be rapidly charged in a reverse direction. A~ the capacitor receive~
the charge the voltage across the capacitor reverses polarity, and progressively increases in a rever6e direction which tends to bias FET transi~tor 70 into conduction.
Eventually the threshold level required for conduction in transistor 70 i8 reached, and that device i8 rendered conductive. This causes capacitor 50 to be discharged through resistor 72, rendering the trip circuit inoperative.
Since the charge tran~fer bet~een capacitor S0 and capacitor 67 takes place relatively quic~ly, typically in the order of 0.1 second, and resistor 72 bas a relatively low resistance, trip capacitor S0 is discharged almo~t immediately following a voltage loss in the monitored conductor. Trip inhibit capacitor 67 i8 eventually also discharged through re~istor 72.
The absence of charge in capacitor 50 precludes operation of the trip circuit, since it is this charge that i8 supplied to winding ~1. Consequently, the fault 1~80168 ind$cator iB de~irably rendcred lnoperatlve for the detection and ~nd$cation of f-ult currents follo~lng -volt~ge 1088 in conductor 12 ~pon regtorat~on of voltage in the conductor, capacitors 50 and 67 ~re again ch~rged by the pulsating unidirectional currcnt from bridge rcctif$er network 43 Since transistor 70 is rendered non-conductive at this time by the reverse-bias forward voltage drop of diode 68 appearing acros~ trip inhibit capacitor 67 ~nd applied to the tr~n6istor control clectrodes, tr$p capacitor 50 is quickly recharged to its qulescent charge state and the trip circuit become~ operative At the ~De time, re~ct capacitor 51 is charged throuqh resistor 52, rendering the reset circuit operative The con~truction and operat$on of trip-coord$nate~
fault indicatorg 1B described ln u s Patent No 4,794,332 In a typical esbodiment intended for u~e with ~00 volt 60 hertz alternatlng current c~pac~tor S0 may have a value of 1 microfarad and capac~tor 67 may have a value of 01 microfarad Re~istor 73 may have a value of 50 megohms and zener diode 53 may have ~ threshold voltage of 50 volt~ The~e component v~lues result in trip capacitor 50 having a discharge time constant of approxi~ately 0 1 second Transistor 70 may comprise a type IR lZ3 enhanced FET, resi~tor 72 may have a value of 220 ohms, ~nd re~istor 71 may have a value of appro~ t~ly 50 ~egoh~-.
~ 17 ~L280~68 An alternate circuit for fault indicator 10 suitable for use with a dual-winding type flag indicator a88embly i6 shown in Figure 8. In this embodiment, two windings 74 and 75 are provided on the u-shaped magnetic pole piece. Reset capacitor 51 is connected to the juncture of the two windings, and through isolation resistor 52 to the output of rectifier network 43. Wlnding 74 is connected to SCR 53, which controls the discharge of trip capacitor 50 through the winding upon the occurrence of a fault, a8 previously described. Winding 74 is connected to SCR 60, which operates ~8 previously described to control the discharqe of reset captcitor 51 during the reset period. In accordance with one aspect of the invention, a differentiating network compri~ing a capacitor 75 and resistor 76 is provided in series-circuit relationship to the gate electrode of SCR 60 to improve its response time in activating the reset period upon the occurrence of a fault.
While the trip-inhibited fault indicator of the invention has been shown in conjunction with indicator assemblies of a conventional rotating indicator flag construction, it will be appreciated that the invention can be used with other types of indicators having other types of indicating elements. For example, the invention can be utilized in conjunction with a magnetic test point type 2S indicator such as that described in U.S. Patent 4,458,198 of the present inventor, or in conjunction with variou~ types of electronic readouts which are conditioned between re~et ~280~68 Applicant's U.S. Patent No. 4,794,329.
To provide ~n indie~tion of fault oeeurrenee, detector 120 includes on the front wall 128 of hou~lng 121 a pair of windows 130 through which an lndieator flag asse~bly 131 provides ~ visible lndie~tion of the oeeurrenet of a fault current A handling loop 132 h~vinq end~ anehored ~n the front w~ll extends fro~ hou~ng 121 to reeelve the hooked end of a lineman'~ tool (not ~hown) to f~eilitate lnstallation nd ~moval of the lnd$eato~ fro~ eabl- 122 m e variou- cireult eo~ponent- of the f~ult ~ndieator are Dountod on a e$reuit board 133 eontalned within hou-ing 121 A fir~t eleetro~tatie plek-up point between the deteetor eireuitry and the ~leetrie fi-ld surrounding eonductor 122 1~ provldbd by ~ fl~t l-etrieally Ls eonductive pl-te 13~ po-ltloned w~thin hou~ing 121 near re~r ~all 125 and eleetrically eonnected to the eireuitry b Conduetor 135 A eeond eleetrostatie pick-up point radially displ~eed from the first piek-up point rel~tive to conductor 12 i8 provided by ~n eleetr$e~11y eonduetive ~et~l ring }39 on the oppo~iee inside surfaee of housing 121 adjacent ~nd behind front w~ll 128 Thl~ hous$ng eonstruetion~ whieh advantageously provides suffieient excitation to the indic~tor eircuitry without tbe use of ~ external ground plane element~ dkaerib~d ln det411 1D
: ..
`~ 20 ~280~68 and f~ult identifying states by application of a momentary current.
An alternate embodi~ent of the inventlon suitable for mounting directly to a high voltage cable of a po~er S distribution system i8 æhown in Figures 9-17. As shown, this fault indicator 120 includes a generally cylindrical housing 121 formed of a hard electrically insulating weather-resistant material ~uch as LEXAN a trademark of GEneral Electric Company, of Schenectady, New York). The detector 120 is secured to a conventional high voltage cable 122 including an internal conductor 12 by mean~ of a pair of resilient inwardly-biased non-electrically condùctlve retaining arms 123 and 124. The retaining arms, which project rearwardly from hou~ing 121, include end portions 123a and 124a, respectively, which are inwardly formed ~o as to grasp and hold cable 122 in close proximity to the rear wall 125 ~Figure 9) of houslng 121. A pair of semi-resilient stiffening members 126 and 127 ~ay be provided in close association with member~ 123 and 124 to asæist in biasing the retaining memberæ against cable 122.
A~ shown to best advantage in Figure 9, upon insertion of cable 122 between the retaining member~, the ends of the retaining memberæ are forced apart. This allows houæing 121 to be pushed up against the cable, and as the cable abut~ the housing the end portions of the retaining memberæ push the cable into engagement. This cable attachment arrangement i8 de~crlbed and clalmed ln the .~ . s the afore~entloned u s Patent No. 4, 794 / 329 of the pre~ent lnventor ~ eferring to Figure 13, the cireuitry of f-ult ~ndic~tor 120 i8 seen to cowprise ~ fir-t reetifier net~orlc S comprising a pair of reetifier diodes 140 and 141 eonneeted to the capacitive pickup plate 134 through eonduetor 135 A
seeond reetifier network col~prising a pair of reetifier diode~ 142 and 143 are conneeted through a eonduetor 144 to the electrieally eonduetive eoating 139 providing eap eitive 10 eoupling to ground. Together, the two reetifier networlcs provide rectifieation of the altern~ting eurrent deriv-d fro~ the eleettic field Jurrounding eonduetor 12 to p~ ide energization of the trip, r~et and trlp ln~lblt eireult~ of the fault indie~tor.
me pul-~ting direet eurrent d~veloped ty diodes 140 and 141 during the presenee of voltage on eonduetor 12 i8 applied to a trip eapaeitor 1~5 and ~ trip inhibit e~paeitor 146 eonneeted aero~ the output t-r~$n~1- of the network. A zener diode 147 li~it~ the volt ge develop d across the eapaeltors to the thre~hold voltage of tbe zener diode, and a forward-biased diode ~48 eonneeted aeros~
eapacitor 1'16 limit~ the volt~ge aeross that device during the eharge eyele to the forward drop of the diode, typle~lly in the order of 0.7 volts.
The pulsating ditect eurrent developed by diodes 142 ~nd 143 is applied to a reset e~p~eitor 150 eonnected aeross the output of the second reetifier net~rorl~ to e~u~e il that capacitor to a1JO be charged during nor~al current flow.
To provide for periodic reset of the fault indicator, capacitor 150 is periodically discharged tbrough the series-connected winding~ 151 of flag indicator assembly 131. To this end, a silicon controlled rectifier (SCR) 152 i8 periodically conditioned into conduction by conduction through a zener diode 153 and bilateral diode 15~ in the gate circuit of the SCR upon tbe voltage across capacitor 150 exceeding a predeternined threshold level.
Following the discharge of reset capac~tor 150 through winding~ 151, the voltage across the capacltor drops and SCR 152 cea~es to conauct. Capacitor 150 then begins to recharge until the voltage acroQs reset capacitor 150 again reaches the threshold level of the zener and bilateral diode~, at which time conduction through SCR 152 is reestablished and another re~et cycle is accomplished.
Upon occurrence of a fault current in conductor 12, trip capacitor 1~5 i8 cau~ed after a predetermined time delay, in accordance with the inYention, to discharge in a rever~e direction through windings 151 through a second silicon controlled rectifier 155. This result~ from closure of reed switch contacts 156 positioned in close magnetic proximity to cable 122 and connected to the control ~25 electrode of SCR 155 through a delay circuit including a resistor 157 and a capacitor 158.
Trip capacitor 1~5 continue~ to dl wharge until the di~charge current is no longer sufficient to maintaln condwction through SCR 155. The magnetic pole pieoe 159 of flag indicator assembly 131 bowever remains biased in a magnetic polarity which maintain the indicator flag thereof S in a fault indicating position. Upon restoration of nor~al current in conductor 12, it remains for the reset circuit of reset capacitor 150 to remagnetize pole piece 159 to opposite magnetic polarities ~o as to reposition the indicator flag to a reset-indicating position.
To prevent false fault current indications as a result of inrush current associated with initial powerup of conductor 12, the fault indicator include~ the tr~p inbiblt capacitor 146 and s8sociated circuitry for discharging trip capacitor 145 upon 1088 of voltage on the conductor. In particular, the control electrodes of an enhanced ~ET~type 161 are connected across trip inhibit capacitor 146 througb a re~istor 162. Upon 1088 of excitation trip capacitor 145 is caused to partially discharge throuqh a resistor 163 into capacitor 146, causing the voltage across that dievice to reverse polarity and progressively increase in the reverse direction as the device is cbarged. Eventually the threshold voltage of transistor 161 is reached and the transistor i8 rendered conductive by the applied bia~ from capacitor 146, causing trip capacitor 145 to rapidly discharge through a resistor 164 and therefore be unavailable for providing trip current to windings 151.
Thus, the fault indicator i8 in~tially non-responslve to fault current oc~urring foll~ing the 1088 of volt~ge in conductor 12, and does not become operative for this purpose until capacitor 145 again beco~es charged.
Upon occurrence of a fault, reed switch 156 closes and an enabling current is applied to SCR 152 through a differen~iating network comprising a resistor 165 and capacitor 166, and a diode 167 to immediately di~charge reset capacitor }50 through ~inding~ 151, rendering the re~et circuit inoperative pending the recharging of capacitor 150 by diodes 142 and 1~3. A resistor 168 Day be connected across the capacitor to establish a mini-lun line voltage neces~ry for the capac~tor to att~in an operable charge level. SCR 155 i8 rendered conductive after a elay period e~tablished b~ reslstor 157 and capacitor 158, and a lS series-connected resistor 169 and bilateral diode 170.
The operation of flag indicator as~embly 131 i8 illustrated in Pigures 14-17. me indicator, which ~ay be identical in construction and operation to that described in U.S. Patent 4,495,489 of the present inventor, i~ seen to include an indicator flag 175 rotatably mounted on a shaft 176 within hou~ing 121. The indicator 1ag includes indicator ~egment~ on either side of the axis of rotation which preferably each extend less than 90 around the axi~
of rotation.
When aligned as ~hown in Figures 14a-14b the flag segment~ are masked and are not v~sible to the ob~erver through windows 130. ~owever, upon occurrence of a fault ~280168 current, the indicator flag rotates 90 such that the lndicator segments are positioned as shown in Yigures 16a-16b and are visible through ~indows 130. The indicator segments are preferably colored red, or another highly vieible color, to clearly indicate the occurrence of a fault current when viewed through the windows.
Actuation of flag menber 175 between re~et and fault indicating positions i~ accomplished by an annular flag actuator magnet 177 which is rotatably coupled to flag member 175 by shaft 176. The shaft is maintained in alignment with the axis of indicator housing 121 by means of a bearing surface ln a divider wall 178 (Fi~ure 10), which al~o prov~des a re~çt-indicat~ng 8urface vlewable througb windows 130 when the indicator flag is in its reset position. This surface i~ preferably colored white, or ~ome other color contrasting with the color of the indicator flag segments, to clearly indicate a re~et condition when viewed through the windows.
Actuator magnet 177, which may be formed of a magnetic material having a high coercive force, such a~
ceramic, i~ formed to provide four magnetic poles of opposite polarity, with opposite polaritie~ every 90 about the circumference of the magnet. Actuator magnet 177, and hence indicator flag 175, are bia~ed to the position shown in Figure~ 14a and 14b when the fault indicator 120 i8 in a non-trip or reset condition by Deans of the generally cross-shaped magnetic pole pieoe 159, which may be formea of :
!
1280~L68 a magnetic materlal having a relatively low coerci~e force, such a8 chrome steel. m e pole piece includes four magnetic poles in magnetic communication with flag actuator magnet 177. The pole piece 159 i8 mounted such that the four S magnetic poles extend to positions adjacent the magnetic poles of actuator magnet 177. A magnetic chield 185 (Figure~ 10 and 11) comprising a flat plate of magnetically conductive material i8 provided between the actuator assembly and conductor 12 to shield the actuator assembly from the magnetic field whicb acco~panies occurrence of a fault current in conductor 12.
Dur~ng normal circuit operation the pole~ of pole piece 159 are bia~ed to the magnetic polarities indicated in ~igures l~a and 14b. As a result, the opposite polarity pole~ of flag actuator magnet 177 are attracted to position the indicator flag 175 as shown, with the indicator segments thereof vertically aligned and out-of-view of windows 130.
Thus, all~that i~ seen is the ~hite reset-indicating surface of divider 178.
Upon 1086 of voltage in conductor 12, pole piece 159 is remagnetized to the magnetic polarities shown in Figures 15a-15b and 16a-16b by momentary energization of magnetic windings 151, which are located on the pole piece, as shown. As a result, the poles of flag actuator magnet 177 are repelled by adjacent like-polarity poles of the pole piece and the indicator flag i8 caused to rotate 90 to the indicating position shown in ~igure~ 16a-16b. I~ thi8 t' ~, 26 ~ ;
~280~68 positlon, the red indicator segments of the indicator flag 165 are visible through windows 130 and a lineman viewing the fault indicator is advi~ed that a fault current has occurred in conductor 12.
The indicator flag 175 remains in the fault-indicating position until the pole~ of pole piece 159 are subsequently remagnetized to the magnetic polarity shown in Figures 14a-14b by momentary application of a reset current to windings 151 as shown in ~igures 17a-17b. Thi8 causes flag actuator magnet 177 to again be repelled by the adjacent poles of pole piece 159 80 a8 to rotate indicator flag 175 to a vertical po~ltion, as shown in Pigure~
13a-13b.
The high input impedance provided by the embodiment of Figures 9-17 allows the fault indicator to be utilized on very high impedance test points, where coupling to a monitored conductor may range from 5 to only 1 picofarad, and on high voltage cables, where coupling to the conductor may be only 0.5 p~cofarad, without the need for external grounding connection~ or electrically conductive m~mbers projecting from the hou~ing.
The invention can al80 be incorporated in inductively couled fault indicators, as illustrated in Figure~ 18 and 19. In the fault indicator 180 shown, a winding 181 is magnetically coupled to the conductor 12 of a cable 122 by magnetic core a~sembly 182, which may be a8 described in U.8. Patent ~,~56,873 of the present ln~entor.
., ~ --A helical spring 183 may be provlded to hold the cable against a hou~ing 184 withln ~hich circuitry for controlling a remote indicator module 185 Day be contained. A
conventional magnetically actuated indicator flag a~se~bly 186, including a magnetic winding 187, a U-~haped pole piece 188, an actuator magnet 189 and a rotatable indicator flag 190, may be provided within eodule 185.
A voltage quadrupler comprising diode~ 191-194 and capacitors 195-199 is connected to winding 181 to develop operatinq power in a manner well known ~o the art. A
resistor 200 and zener diode 201 provide charging current to a tr~p capacitor 202 and a re~et capacitor 203, Capac~tor 202 i8 charged dlrectly through a diode 204, and capacitor 203 i charged through an isolation resistor 205.
Upon occurrence of a fault, a reed ~witch 206 close~ to apply enabling current througha diode 207, resistor 208, and bilateral diode 209 to the gate electrode of an SCR 210, which conducts to discharge reset capacitor 203 through winding 187.
In accordance with the invention, an SCR 211 i~
next enabled after a delay to discharge trip capacitor 202 through the winding to cause a fault indication. A network consisting of reistors 212 and 213, a capacitor 214 and a bilateral diode 215 provide the necessary delay. Resistor~
216 and 217 provide nece~sary ground returns for the gate electrodes.
Thu~, the reset circuit of fault indlcator 180 18 ~280168 tr~pped immediately upon occurrence of a fault, rendering it inoperative pending the completion of a subsequent charging cycle. ~hen, while the reset circuit is operative, the trip circuit i8 actuated to condition the indicator to a fault-indicating state. Since the reset circuit i8 inoperative when the fault circuit i8 actuated, the possibility of simultaneous actuation of the two circuits is eliminated.
In practice, the delay period utilized in actuating the trip circuit following a fault will depend on the duration of the reset period, which in turn wi}l depend on circuit parameters. In one successful embodlment of the invention, for example, a fault indicator havlng a ~16 millisecond reset period and a .4 millisecond trip period, may have a total trip delay of .28 milliseconds, which provides a space between the end of the reset pulse and tbe beginning of the trip pulse of .12 milliseconds, and a total reset and trip period of .68 ~illisecond~. ~owever, it will be understood that other pulse widths and delay periods ~ay be appropriate in other applications.
While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that change~ and modifications may be made therein without departing from the invention in its broader aspects, and, therefore, the aim in the appended claims is to cover all such changes and modifications a~
fall within the true spirit and scope of the invention.
Backqround of the Invention The present invention relates gener~lly to fault indicaeors for alternating current electrical distribution 5 systems, snd more particularly to ~elf-resetting fault indicators wherein upon occurrence of a fault the reset circuit of the indicator i8 actuated before the trip circuit thereof to preclude simultaneous actuation of the two circuits.
Fault indicators of various types have been con~tructed for detecting faults in electrical power distribution systems. Such indicators include cl~p-on type indicators, which clamp directly over cables in the system, and test point-type indicator~, which are mounted on te~t points provided on connector~ or component~ of the system.
Fault indicators of both types may be either of the manually reset type, wherein it i~ necessary that the indicator be phy ically reset following each fault, or of the automat$cally reset type, wherein a fault lndication is reset upon restoration of line current. Examples of such fault indicators are found in products manufactured by E. O.
Schweitzer Manufacturing Company of Mundelein, Illinois, and in U.S. Patent No~. 4,063,171, 4,234,847, 4,251,770, 4,236,550 4,438,403 and 4,458,198 of the present $nventor.
Self-re~etting fault indicaeors typically employ an indicator device, a trip circuit for conditioning the indicator device to indicate a fault upon occurrence of ~280i68 fault current in a monitored conductor, and a perlodically-actuated reset circuit powered by the monitored conductor for conditioning the indicator device to a reset state upon occurrence of normal current in the monitored conductor.
S Because the reset circuit i~ actuated at periodic intervals in the presence of current on the monitored conductor, there exists the possibility that the reset circuit will actuate at the same time the trip circuit actuates in response to a fault current, and the indicator will therefore fail to respond to the fault, providing the user with erroneous information that a fault did not occur.
Summarv of the InYention The invention is directed to a fault indicator for indicating the occurrence of a fault current in an electrical conductor of an alternating current po~er distribution system. The indicator includes status indicating means having reset-indicating and fault-indicating state6. Trip circuit means condition the ~tatus indicating means to the fault-indicating state in response to the occurrence of a fault current in the conductor.
Reset circuit means periodically condition the status indciating mean~ to the reset-indicating state in the presence of voltage on the conductor. The trip circuit means actuate the reset circuit means upon occurrence of a fault prior to conditioning tbe status indicator ~eans to the fault-indicating state to preclude simultaneous actuation of the reset and trip circuit means.
~280168 Briel DescriDtion of the Dra~in~
The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. The invention, together with the further S objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several figure~ of which like reference numeral~ identify like elements, and in which:
Figure 1 is a side elevational view, partially in section, illustrating an reset-coordinated ~elf-resettinq fault indicator constructed in accordance with the present invention mounted on the test-point terminal of a conventional elbow-type terminal connector.
Figure 2 is a fragmentary perspective view of the fault indicator of Figure 1 in a partially disa~sembled state.
Figure 3 is an electrical schematic diagram of the fault indicator illustrated in Figure6 1 and 2.
Figures 4a and 4b are diagrammatic views of principal indicator components of the fault indicator in a reset state.
Figures 5a and Sb are diagrammatic views similar to Figure 4a and 4b, respectively, showing the indicator components of the fault indicator in transition between a reset state and a tripped state.
Figure~ 6a and 6b are diagrammatic view8 simil~r i280168 to Figure 4a and 4b, re6pectively, showinq the indicator components of the fault indicator in a tripped state.
Figure 7 is an electrical schematic diagram of an alternate reset-coordinated circuit for use in the fault S indicator illustrated in Figure 1.
Fiqure 8 is an electrical scbematic diagram of an alternate two-winding reset coordinated circuit for use in the fault indicator illustrated in Figure 1.
Figure 9 is a per~pective view illustratinq a reset-coordinated fault indicator constructed in accordance with the present invention installed on a high voltage cable of a power distribution system.
Figure 10 is a cross-sectional view of the fault indicator taken along line 10-10 of Figure 9.
lS Figure 11 i8 a cross-sectional view taken along line 11-11 of Figure 10.
Figure 12 is a cross-sectional view taken along line 12-12 of Figure 10.
Figure 13 is an electrical schematic diagram of the fault indicator lllustr~ted in Figure 9.
Figures 14a and 14b are diagrammabic views of principal indicator components of the fault indicator illustrated in Figures 9 and 10 in a reset state.
Figures 15a and l5b are diagrammatic views similar to Figure~ 14a and 14b, respectively, showing the indicator components of the fault indicator in transition between a reset state and a tripped ~tate.
~Z80~68 Figures 16a and 16b are diagrammatic vie~6 similar to Figures l~a and 14b, respectively, showing the indicator components of the fault indicator in a tripped state.
Figures 17a and 17b are diagrammatic views similar to Figure~ 14a and 14b, respectively, showing the indicator components of the fault indicator in transition between a tripped state and a re~et state.
Figure 18 is a per~pective view of an indicatively coupled reset-coordinated ~elf-resetting fault indicator constructed in accordance with the invention.
Figure 19 i8 an electrical schematic diagram of the fault indicator illustrated in Figure 18.
DescriPtion of the Prfeferred embodiment Referring to the drawing~, and particularly to Figures 1 and 2, a trip-inhibited fault indicator 10 constructed in accordance wi~h the invention i8 shown inctalled on a plug-in elbow connector 11 of conventional construction for use in high voltage alternating current system for establishing a plug-in connection to a transformer (not sbown) or other device. As shown, the connector 11 includes generally an axial conductor 12 extending through an electrically insulating body portion 13 encased in an electrically-conductive sheath 14, the 6heath being grounded in accordance with conventional practice. An 25~ arcuate member 16 having ends anchored in ~heath 14 extends from the connector to receive the hooked end of a lineman's tool commonly used to remove plug-in connectors fro~ ~uch :
. ;- .
~280~L68 devices.
Elbow connector 11 includes a test point terminal 17 for receiving a circuit condition indicating device, in this case fault current indicator 10. The test point i8 formed by a portion of the insulating body layer 13, which projects radially through the conductive sheath 1~.
Embedded in the test point terninal 17 is an electrically conductive contact 18 which i8 exposed at its outer end to provide for an electrical connection to the contact, and which at its inner portion is positioned in proximity to conductor 12 to capacitively couple the contact to the conductor.
The housing of fault indicator 10 includes an electrically conductive semi-flexible rubber outer shell 20 which i6 open and dimensioned at one end for engaging test point 17. The shell 20 receives a corre~pondingly sized cylindrical plastic housing 21 in which the electrical components of the fault indicator device are contained. The cylindrical housing includes an integral partition 26 ~hich serve~ as a mask and spacing element, and a tran~parent end cap 27 which is sonically welded to the end of the housing.
At the closed end of ~hell 20, an apertured tab 29 is provided to facilitate installation and removal of the fault indicator with a conventional hooked lineman'~ tool.
Referring to Figure 2, a disc-shaped circuit board 31 i& positioned within housing 21 perpendicular to the axis of the housing at a location intermediate the ends thereof.
~280168 Ihe circuit board, which ~ay be secured in position by an eposy material 32, serves as mounting mean~ for the electrical components of the fault indicator. An electrical connection is established between this circuitry and test point contact 18 by means of a helical 6pring 33, the spring being connected at one end to a wire conductor extending from the circuit board, and being resilien~ly pressed at the other end against contact 18. An electrical ground connection is established to the circuit board by means of an additional electrical conductor 35 compressively wedged between housing 21 and the electrically conductive outer shell 20 grounded through sheath 14.
To provide an indication of the occurrence of a fault current in conductor 12, the fault indicator include~
within the lower end of housing 21 a disc-shaped target member 34 which is mounted for rotation on a pivot 6haft 36.
The face of the target disc ha~ a red ~egment 34a (Figures 4-6) and a white segment 34b, each comprising one-half of the target face, and only one of which is visible at a time through a window 37 provided in shell 20 and the end cap 27 of housing 21.
Secured ~o and pivotal with target 34 member i~ a disc-shaped target actuator maqnet 38, which is formed of a magnetic material having a high coercive force, sucb as ceramic, and which i6 magnetically polarized to form two magnetic poles of opposite magnetic polarity, as indicated in Figures ~-6. 5he actuator uagnet 38, and bence the ~280168 target member 34, are rotated between reset-indicating and fault-indicating positions by rotational force~ e~erted on the magnet by means of a stationary generally U-shaped magnetic pole piece 39, which is located within housing 21 with the projecting poles thereof diametrically opposed and adjacent the edge of the magnet.
When the fault indicator is in a reset-indicating state, pole piece 39, which i8 preferably formed of a magnetic material having a relatively low coercive force, such as a chrome steel, is magnetized at its projecting poles to the magnetic polarities ~ndicated in Figures 4a-4b.
As a result, the opposite polarity magnetic poles of the target magnet are attracted to position the target member 34 as shown. In this position the red ~egment 34a of the target disc is not visible through window 37, and only tbe white segment 34b is visible to indicate to an observer that the indicator i~ in thea re~et condition.
On the occurrence of a fault current in conductor 12, which current may, for e~mple, eYceed ~00 amperes, pole piece 39, and an adjacent au~iliary pole piece ~0 of similar construction, are remagnetized to the magnetic polarities æhown in Figures 5a-5b and 6a-6b by momentary energization of a magnetic winding 41 on the center section of pole piece 39. As a result, the poles of magnet 38 are repelled by the adjacent like-magnetic polarity poles of the pole pieces and the target disc iB caused to rotate 180 counter-clockwise to the tripped position shown in Figures 6a-6b. In tbi8 position, the red segment 34b of the target disc is visible through window 37 (Figure 2) and a lineman viewing the fault indicator i8 advised that a fault current has occurred in conductor 12.
Target di~c 34 remains in the fault indicating position until the poles of pole pieces 39 and 40 are ~ubsequently remaqnetized to tbe magnetic polarities shown in Fiqure~ 4a-4b by momentary energiation of winding 41 with a current in the opposite direction. As a reQult, the target magnet 38, and hence the target disc 34, are cauæed to rotate from the tripped position shown in P$gures 6a-6b to the reset position shown ln Fiqures 4a-4b, and the fault indicator is conditioned to respond to a subseguent fault current.
Energization of winding 41 in one direction upon occurrence of a fault current in conductor 12, and energization of winding 41 in the other direction upon re~toration of current in the conductor following a fault, is accomplished by means of e~ternally-powered circuitry contained within the fault indicator. Referring to the schematic diagram shown in Figure 3, operating power for energizing winding 41 i8 obtained by means of a bridge :rectifier network 43, con~isting of four diodes ~6-49. One input terminal of this networ~, formed at the juncture of the anode of diode 46 and the cathode of diode 47, is connected through the helical spring 33 to te~t point contact 18. The other ~nput terminal, formed at tbe anode of diode ~8 and the cathode of diode ~9, i~ connected to ground through the electrically conductive outer shell 20 of the faul~ indicator housing. With this arrangement. high voltage alternating current carried in conductor 12 is capacitively coupled to the bridge rectifier network, resulting in the production of a pul~ating unidirectional current at the output terminals of the network.
The positive polarity output terminal of the bridge rectifier network i6 formed at the cathodes of diodes ~6 and 48, and the negative polarity output terminal of the rectifier network is formed at the juncture of the anodes of diodes 47 and 49. To provide the trip and re~et functions of the fault indicator, a trip capacitor 50 and a reset capacitor ~1 are connected to the output terminals to receive a charge current from the rectifier network. Trip capacitor 50 is directly connected, and reset capacitor 51 i8 connected through winding ~1, and an isolation resistor 52. A zener diode 42 i8 connected across the network output terminals to limit rectifier output voltage.
To provide for energization of winding 41 in one direction upon occurrence of a fault current in conductor 12, the winding ig connected to receive discharge current from trip capacitor 50 through a gilicon controlled rectifier (SCR) 53 connected in series with the winding and the capacitor. Upon occurrence of a fault current, a reed switch 54, positioned within housing 21 in close proximity to conductor 12 80 a~ to close ln response to the magnetic ~280~68 field produced by a fault-level current, cause~ an enabling current to be applied from rectifier network ~3 through a resistor 55 and bilateral d~ode 56 to the gate electrode of SCR 53 to initiate conduction through the SCR. A capacitor 57 and re~istor 58 in the SCR gate circuit provide a predetermined ti~e delay to the trip function following closure of switch 54. A resi~tor 59 provides a drain circuit to qround for the gate electrode.
To maintain fault indicator 10 in a reset condition in the absence of a fault current, reset capacitor 51 i~ periodically discharged into winding 41 in a reverse direction to the discharge current of trlp capacitor 50 in the presence of voltage on conductor 12. To this end, winding 41 i8 connected through a s~licon controlled rectifier (SCR) 60 to re~et capacitor 51. Periodic conduction through SCR 60 i~ obtained ffl connecting the gate electrode of that device to tbe positive polarity output terminal of bridge rectifier U through a resi~tor 61 and a pair of series connected bilateral diodes 62 and 63. A
resistor 64 provides a ground return for the gate electrode.
~nder normal current flow condition~, a~ trip capacitor 50 i8 charged by the pulsating direct current output of bridge rectifier network, reset capacitor 51 i~ charged through winding 41 and resistor 52. Ihe voltage developed across the capacitor~ progressively increases with time, until the threshold voltage of the bilateral diode~ i8 reached, at which time conduction i8 initiated through 8CR 60 and ,~
~280168 c~pacitor 51 discharges througb winding 41. Resistor 52 prevents trip capacitor 50 from being discharged with reset capacitor 51, leaving this capacitor available for powering the trip circuit. Following the discharge, SCR 60 i8 rendered non-conductive until tbe voltage level acros~
capacitor S2 increa~e~ to the threshold voltage level of the bilateral diodes, at which time another reset cycle occur~.
With the periodic energization of winding 41 in the manner magnetic pole assembly 39 ic magnetized as shown in Figures 4a-4b with the presence of voltage on conductor 12, and flag indicator 34 i8 positioned as shown to indicate a reset mode.
In practice, the breakdown voltage of bilateral diodes 62 and 63 may be in order of 34 volts, and the time required for capacitor 51 to reach this threshold level with a typical voltage level of 4,400 volts on conductor 12 may be approxiamtely 2 minutes or less. Ihe voltage level within conductor 12 i8 not critical to the operation of the reset circuit, and has only the effect of changing the repetition rate of the reset cycle.
Upon occurrence of a fault current in conductor 12 trip capacitor 50 is discharged through SCR 53 and trip winding 41. The resulting magnetic flux in pole piece 39 reverces the magnetic polarities of the pole piece and causes rotation of indicator flag 34 to a trip-indicating position as previously described. In particular, the ~agnetic polarities of pole piece 39 are reversed as shown ~280~68 in Figures Sa-5b, causing the magnetic poles of the pole piece to repel the like pole~ of magnet 38 and induce a 180 rotation of the indicator flag. The auxiliary pole piece ~0 a~ists in this rotation.
S To preclude the possibility of ~imultaneou~
actuation of the trip and reset circuits and consequent failure of flag indicator 34 to regi~ter a fault, a reset coordination feature i8 provided in accordance with the invention to actuate and thus disable the reset circuit for a predetermined period of time following the fault, and to delay the actuation of the trip circuit until ~fter actuation and disablement of the reset circuit. To this end, switch 54 iQ connected through a diode 65 and resistor 66 to the juncture of bilateral diodes 62 and 63. ~pon lS closure of switch 54, an enabling signal i8 applied to the gate electrode of SCR 60, resi~tor 66 serving to l~mit current flow and diode 65 ser~ing to prevent actuation of SCR 53 with application of normal reset signals to SC~ 60 through bilateral diode 62. Since the enabling signal will ordinarily exceed the threshold of diode 63, tbe result i8 immediate conduction through SCR 60 and discharge of reset capacitor Sl through winding ~1. Resistor 52 prevents any appreciable discharge of trip capacitor 50 at this time.
Capacitor 51 continues to discharge through ~ winding 41 in a direction whicb resets the indicator flaq for a finite reset period until the voltage across the ~280168 capacitor falls to a level where SCR 60 ceases to conduct.
The cluration of this reset period is dependent on a nu~ber of circuit components and circuit parameters, including capacitor 51, windin~ 41 and tbe voltage developed by S rectifier network 43 across capacitor 51, and in practice may typically be in the order of .16 millisecond.
Following the reset period the reset circuit is inoperative, and doe~ not again become operative until capacitor 51 is charged sufficiently to exceed the voltage thre~hold of bilateral diodes 62 and 63. As previously developed, this recovery period may be in the order of two minutes or more.
During the recovery period of the reset circuit SCR 53 i8 rendered conductive to cause trip capacitor 50 to discharge through winding 41 in a direction which conditions indicator flag 54 to a fault-indicating state. mi8 is accomplished by connecting switch 54 to the gate electrode of SCR 53 through an R-C network comprising resi~tors 55 and 58, capacitor 57, and bilater~l diode 56, which introduce~ a predetermined delay period to the trip signal greater than the duration of the reset cycle. By reason of re6istor 55 being connected between the gate and switch 54 the network is prevented from having a delaying effect on the ~ignal applied to the gate electrode of SCR 60.
Thus, upon occurrence of a fault and closure of ~witch 54, the reset circuit i~ immediately actuated, and the trip circuit i~ only actuated after a predetermined 1~
1280~68 delay period which i8 greater than the operating period of the re~et circuit.
An alternate circuit for use in a trip-coordinated fault indicator constructed in accordance with the invention S is shown in Figure 7. In ~uch trip-coordinated fault indicators the trip circuit is inhibited upon re~toration of power on the monitored conductor to prevent initial surge current~ from cau~ing a fault indication. To this end, the circuit includes an additional trip inhibit capac~tor 67 in series with trip capacitor. A diode 57 is connected acros~
capacitor 54 in a direction forward-bia~ed to the charging current produced by rectifier network 43.
The ~uncture of capacitors S3 and 54 is connected to one principal electrode of an enhanced ~ET-type transistor 60. The remaining principal electrode of transistor 60 i~ connected through a resistor 61 to the positive polarity output terminal of rectifier network 43.
The gate electrode of transistor 6~ is connected through a resistor 62 to the negative polarity output ter~inal of the ~20 network.
In operation, in the presence of voltage on conductor 12 the voltage developed across trip inhibit capacitor 67 by the pulsating charge current developed by bridge rectifier network 43 is limited to the forward voltage drop of diode 68. By reason of re~istor 71, thi~
limited voltage appear~ as a reverse bias on the gate ~Z80168 electrode of transistor 70, causing that device to be conditioned to a non-conductive state. Consequently, the transistor and resistor 72 have no effect on the charge contained on trip capacitor 50.
S ~owever, upon 1088 of voltage on conductor 12, and the consequent absence of output from bridge rectifier network 43, a portion of the charge contained in trip capacitor 50 is transferred tbrough resistor 73 to trip inhibit capacitor 67, causing that capacitor to be rapidly charged in a reverse direction. A~ the capacitor receive~
the charge the voltage across the capacitor reverses polarity, and progressively increases in a rever6e direction which tends to bias FET transi~tor 70 into conduction.
Eventually the threshold level required for conduction in transistor 70 i8 reached, and that device i8 rendered conductive. This causes capacitor 50 to be discharged through resistor 72, rendering the trip circuit inoperative.
Since the charge tran~fer bet~een capacitor S0 and capacitor 67 takes place relatively quic~ly, typically in the order of 0.1 second, and resistor 72 bas a relatively low resistance, trip capacitor S0 is discharged almo~t immediately following a voltage loss in the monitored conductor. Trip inhibit capacitor 67 i8 eventually also discharged through re~istor 72.
The absence of charge in capacitor 50 precludes operation of the trip circuit, since it is this charge that i8 supplied to winding ~1. Consequently, the fault 1~80168 ind$cator iB de~irably rendcred lnoperatlve for the detection and ~nd$cation of f-ult currents follo~lng -volt~ge 1088 in conductor 12 ~pon regtorat~on of voltage in the conductor, capacitors 50 and 67 ~re again ch~rged by the pulsating unidirectional currcnt from bridge rcctif$er network 43 Since transistor 70 is rendered non-conductive at this time by the reverse-bias forward voltage drop of diode 68 appearing acros~ trip inhibit capacitor 67 ~nd applied to the tr~n6istor control clectrodes, tr$p capacitor 50 is quickly recharged to its qulescent charge state and the trip circuit become~ operative At the ~De time, re~ct capacitor 51 is charged throuqh resistor 52, rendering the reset circuit operative The con~truction and operat$on of trip-coord$nate~
fault indicatorg 1B described ln u s Patent No 4,794,332 In a typical esbodiment intended for u~e with ~00 volt 60 hertz alternatlng current c~pac~tor S0 may have a value of 1 microfarad and capac~tor 67 may have a value of 01 microfarad Re~istor 73 may have a value of 50 megohms and zener diode 53 may have ~ threshold voltage of 50 volt~ The~e component v~lues result in trip capacitor 50 having a discharge time constant of approxi~ately 0 1 second Transistor 70 may comprise a type IR lZ3 enhanced FET, resi~tor 72 may have a value of 220 ohms, ~nd re~istor 71 may have a value of appro~ t~ly 50 ~egoh~-.
~ 17 ~L280~68 An alternate circuit for fault indicator 10 suitable for use with a dual-winding type flag indicator a88embly i6 shown in Figure 8. In this embodiment, two windings 74 and 75 are provided on the u-shaped magnetic pole piece. Reset capacitor 51 is connected to the juncture of the two windings, and through isolation resistor 52 to the output of rectifier network 43. Wlnding 74 is connected to SCR 53, which controls the discharge of trip capacitor 50 through the winding upon the occurrence of a fault, a8 previously described. Winding 74 is connected to SCR 60, which operates ~8 previously described to control the discharqe of reset captcitor 51 during the reset period. In accordance with one aspect of the invention, a differentiating network compri~ing a capacitor 75 and resistor 76 is provided in series-circuit relationship to the gate electrode of SCR 60 to improve its response time in activating the reset period upon the occurrence of a fault.
While the trip-inhibited fault indicator of the invention has been shown in conjunction with indicator assemblies of a conventional rotating indicator flag construction, it will be appreciated that the invention can be used with other types of indicators having other types of indicating elements. For example, the invention can be utilized in conjunction with a magnetic test point type 2S indicator such as that described in U.S. Patent 4,458,198 of the present inventor, or in conjunction with variou~ types of electronic readouts which are conditioned between re~et ~280~68 Applicant's U.S. Patent No. 4,794,329.
To provide ~n indie~tion of fault oeeurrenee, detector 120 includes on the front wall 128 of hou~lng 121 a pair of windows 130 through which an lndieator flag asse~bly 131 provides ~ visible lndie~tion of the oeeurrenet of a fault current A handling loop 132 h~vinq end~ anehored ~n the front w~ll extends fro~ hou~ng 121 to reeelve the hooked end of a lineman'~ tool (not ~hown) to f~eilitate lnstallation nd ~moval of the lnd$eato~ fro~ eabl- 122 m e variou- cireult eo~ponent- of the f~ult ~ndieator are Dountod on a e$reuit board 133 eontalned within hou-ing 121 A fir~t eleetro~tatie plek-up point between the deteetor eireuitry and the ~leetrie fi-ld surrounding eonductor 122 1~ provldbd by ~ fl~t l-etrieally Ls eonductive pl-te 13~ po-ltloned w~thin hou~ing 121 near re~r ~all 125 and eleetrically eonnected to the eireuitry b Conduetor 135 A eeond eleetrostatie pick-up point radially displ~eed from the first piek-up point rel~tive to conductor 12 i8 provided by ~n eleetr$e~11y eonduetive ~et~l ring }39 on the oppo~iee inside surfaee of housing 121 adjacent ~nd behind front w~ll 128 Thl~ hous$ng eonstruetion~ whieh advantageously provides suffieient excitation to the indic~tor eircuitry without tbe use of ~ external ground plane element~ dkaerib~d ln det411 1D
: ..
`~ 20 ~280~68 and f~ult identifying states by application of a momentary current.
An alternate embodi~ent of the inventlon suitable for mounting directly to a high voltage cable of a po~er S distribution system i8 æhown in Figures 9-17. As shown, this fault indicator 120 includes a generally cylindrical housing 121 formed of a hard electrically insulating weather-resistant material ~uch as LEXAN a trademark of GEneral Electric Company, of Schenectady, New York). The detector 120 is secured to a conventional high voltage cable 122 including an internal conductor 12 by mean~ of a pair of resilient inwardly-biased non-electrically condùctlve retaining arms 123 and 124. The retaining arms, which project rearwardly from hou~ing 121, include end portions 123a and 124a, respectively, which are inwardly formed ~o as to grasp and hold cable 122 in close proximity to the rear wall 125 ~Figure 9) of houslng 121. A pair of semi-resilient stiffening members 126 and 127 ~ay be provided in close association with member~ 123 and 124 to asæist in biasing the retaining memberæ against cable 122.
A~ shown to best advantage in Figure 9, upon insertion of cable 122 between the retaining member~, the ends of the retaining memberæ are forced apart. This allows houæing 121 to be pushed up against the cable, and as the cable abut~ the housing the end portions of the retaining memberæ push the cable into engagement. This cable attachment arrangement i8 de~crlbed and clalmed ln the .~ . s the afore~entloned u s Patent No. 4, 794 / 329 of the pre~ent lnventor ~ eferring to Figure 13, the cireuitry of f-ult ~ndic~tor 120 i8 seen to cowprise ~ fir-t reetifier net~orlc S comprising a pair of reetifier diodes 140 and 141 eonneeted to the capacitive pickup plate 134 through eonduetor 135 A
seeond reetifier network col~prising a pair of reetifier diode~ 142 and 143 are conneeted through a eonduetor 144 to the electrieally eonduetive eoating 139 providing eap eitive 10 eoupling to ground. Together, the two reetifier networlcs provide rectifieation of the altern~ting eurrent deriv-d fro~ the eleettic field Jurrounding eonduetor 12 to p~ ide energization of the trip, r~et and trlp ln~lblt eireult~ of the fault indie~tor.
me pul-~ting direet eurrent d~veloped ty diodes 140 and 141 during the presenee of voltage on eonduetor 12 i8 applied to a trip eapaeitor 1~5 and ~ trip inhibit e~paeitor 146 eonneeted aero~ the output t-r~$n~1- of the network. A zener diode 147 li~it~ the volt ge develop d across the eapaeltors to the thre~hold voltage of tbe zener diode, and a forward-biased diode ~48 eonneeted aeros~
eapacitor 1'16 limit~ the volt~ge aeross that device during the eharge eyele to the forward drop of the diode, typle~lly in the order of 0.7 volts.
The pulsating ditect eurrent developed by diodes 142 ~nd 143 is applied to a reset e~p~eitor 150 eonnected aeross the output of the second reetifier net~rorl~ to e~u~e il that capacitor to a1JO be charged during nor~al current flow.
To provide for periodic reset of the fault indicator, capacitor 150 is periodically discharged tbrough the series-connected winding~ 151 of flag indicator assembly 131. To this end, a silicon controlled rectifier (SCR) 152 i8 periodically conditioned into conduction by conduction through a zener diode 153 and bilateral diode 15~ in the gate circuit of the SCR upon tbe voltage across capacitor 150 exceeding a predeternined threshold level.
Following the discharge of reset capac~tor 150 through winding~ 151, the voltage across the capacltor drops and SCR 152 cea~es to conauct. Capacitor 150 then begins to recharge until the voltage acroQs reset capacitor 150 again reaches the threshold level of the zener and bilateral diode~, at which time conduction through SCR 152 is reestablished and another re~et cycle is accomplished.
Upon occurrence of a fault current in conductor 12, trip capacitor 1~5 i8 cau~ed after a predetermined time delay, in accordance with the inYention, to discharge in a rever~e direction through windings 151 through a second silicon controlled rectifier 155. This result~ from closure of reed switch contacts 156 positioned in close magnetic proximity to cable 122 and connected to the control ~25 electrode of SCR 155 through a delay circuit including a resistor 157 and a capacitor 158.
Trip capacitor 1~5 continue~ to dl wharge until the di~charge current is no longer sufficient to maintaln condwction through SCR 155. The magnetic pole pieoe 159 of flag indicator assembly 131 bowever remains biased in a magnetic polarity which maintain the indicator flag thereof S in a fault indicating position. Upon restoration of nor~al current in conductor 12, it remains for the reset circuit of reset capacitor 150 to remagnetize pole piece 159 to opposite magnetic polarities ~o as to reposition the indicator flag to a reset-indicating position.
To prevent false fault current indications as a result of inrush current associated with initial powerup of conductor 12, the fault indicator include~ the tr~p inbiblt capacitor 146 and s8sociated circuitry for discharging trip capacitor 145 upon 1088 of voltage on the conductor. In particular, the control electrodes of an enhanced ~ET~type 161 are connected across trip inhibit capacitor 146 througb a re~istor 162. Upon 1088 of excitation trip capacitor 145 is caused to partially discharge throuqh a resistor 163 into capacitor 146, causing the voltage across that dievice to reverse polarity and progressively increase in the reverse direction as the device is cbarged. Eventually the threshold voltage of transistor 161 is reached and the transistor i8 rendered conductive by the applied bia~ from capacitor 146, causing trip capacitor 145 to rapidly discharge through a resistor 164 and therefore be unavailable for providing trip current to windings 151.
Thus, the fault indicator i8 in~tially non-responslve to fault current oc~urring foll~ing the 1088 of volt~ge in conductor 12, and does not become operative for this purpose until capacitor 145 again beco~es charged.
Upon occurrence of a fault, reed switch 156 closes and an enabling current is applied to SCR 152 through a differen~iating network comprising a resistor 165 and capacitor 166, and a diode 167 to immediately di~charge reset capacitor }50 through ~inding~ 151, rendering the re~et circuit inoperative pending the recharging of capacitor 150 by diodes 142 and 1~3. A resistor 168 Day be connected across the capacitor to establish a mini-lun line voltage neces~ry for the capac~tor to att~in an operable charge level. SCR 155 i8 rendered conductive after a elay period e~tablished b~ reslstor 157 and capacitor 158, and a lS series-connected resistor 169 and bilateral diode 170.
The operation of flag indicator as~embly 131 i8 illustrated in Pigures 14-17. me indicator, which ~ay be identical in construction and operation to that described in U.S. Patent 4,495,489 of the present inventor, i~ seen to include an indicator flag 175 rotatably mounted on a shaft 176 within hou~ing 121. The indicator 1ag includes indicator ~egment~ on either side of the axis of rotation which preferably each extend less than 90 around the axi~
of rotation.
When aligned as ~hown in Figures 14a-14b the flag segment~ are masked and are not v~sible to the ob~erver through windows 130. ~owever, upon occurrence of a fault ~280168 current, the indicator flag rotates 90 such that the lndicator segments are positioned as shown in Yigures 16a-16b and are visible through ~indows 130. The indicator segments are preferably colored red, or another highly vieible color, to clearly indicate the occurrence of a fault current when viewed through the windows.
Actuation of flag menber 175 between re~et and fault indicating positions i~ accomplished by an annular flag actuator magnet 177 which is rotatably coupled to flag member 175 by shaft 176. The shaft is maintained in alignment with the axis of indicator housing 121 by means of a bearing surface ln a divider wall 178 (Fi~ure 10), which al~o prov~des a re~çt-indicat~ng 8urface vlewable througb windows 130 when the indicator flag is in its reset position. This surface i~ preferably colored white, or ~ome other color contrasting with the color of the indicator flag segments, to clearly indicate a re~et condition when viewed through the windows.
Actuator magnet 177, which may be formed of a magnetic material having a high coercive force, such a~
ceramic, i~ formed to provide four magnetic poles of opposite polarity, with opposite polaritie~ every 90 about the circumference of the magnet. Actuator magnet 177, and hence indicator flag 175, are bia~ed to the position shown in Figure~ 14a and 14b when the fault indicator 120 i8 in a non-trip or reset condition by Deans of the generally cross-shaped magnetic pole pieoe 159, which may be formea of :
!
1280~L68 a magnetic materlal having a relatively low coerci~e force, such a8 chrome steel. m e pole piece includes four magnetic poles in magnetic communication with flag actuator magnet 177. The pole piece 159 i8 mounted such that the four S magnetic poles extend to positions adjacent the magnetic poles of actuator magnet 177. A magnetic chield 185 (Figure~ 10 and 11) comprising a flat plate of magnetically conductive material i8 provided between the actuator assembly and conductor 12 to shield the actuator assembly from the magnetic field whicb acco~panies occurrence of a fault current in conductor 12.
Dur~ng normal circuit operation the pole~ of pole piece 159 are bia~ed to the magnetic polarities indicated in ~igures l~a and 14b. As a result, the opposite polarity pole~ of flag actuator magnet 177 are attracted to position the indicator flag 175 as shown, with the indicator segments thereof vertically aligned and out-of-view of windows 130.
Thus, all~that i~ seen is the ~hite reset-indicating surface of divider 178.
Upon 1086 of voltage in conductor 12, pole piece 159 is remagnetized to the magnetic polarities shown in Figures 15a-15b and 16a-16b by momentary energization of magnetic windings 151, which are located on the pole piece, as shown. As a result, the poles of flag actuator magnet 177 are repelled by adjacent like-polarity poles of the pole piece and the indicator flag i8 caused to rotate 90 to the indicating position shown in ~igure~ 16a-16b. I~ thi8 t' ~, 26 ~ ;
~280~68 positlon, the red indicator segments of the indicator flag 165 are visible through windows 130 and a lineman viewing the fault indicator is advi~ed that a fault current has occurred in conductor 12.
The indicator flag 175 remains in the fault-indicating position until the pole~ of pole piece 159 are subsequently remagnetized to the magnetic polarity shown in Figures 14a-14b by momentary application of a reset current to windings 151 as shown in ~igures 17a-17b. Thi8 causes flag actuator magnet 177 to again be repelled by the adjacent poles of pole piece 159 80 a8 to rotate indicator flag 175 to a vertical po~ltion, as shown in Pigure~
13a-13b.
The high input impedance provided by the embodiment of Figures 9-17 allows the fault indicator to be utilized on very high impedance test points, where coupling to a monitored conductor may range from 5 to only 1 picofarad, and on high voltage cables, where coupling to the conductor may be only 0.5 p~cofarad, without the need for external grounding connection~ or electrically conductive m~mbers projecting from the hou~ing.
The invention can al80 be incorporated in inductively couled fault indicators, as illustrated in Figure~ 18 and 19. In the fault indicator 180 shown, a winding 181 is magnetically coupled to the conductor 12 of a cable 122 by magnetic core a~sembly 182, which may be a8 described in U.8. Patent ~,~56,873 of the present ln~entor.
., ~ --A helical spring 183 may be provlded to hold the cable against a hou~ing 184 withln ~hich circuitry for controlling a remote indicator module 185 Day be contained. A
conventional magnetically actuated indicator flag a~se~bly 186, including a magnetic winding 187, a U-~haped pole piece 188, an actuator magnet 189 and a rotatable indicator flag 190, may be provided within eodule 185.
A voltage quadrupler comprising diode~ 191-194 and capacitors 195-199 is connected to winding 181 to develop operatinq power in a manner well known ~o the art. A
resistor 200 and zener diode 201 provide charging current to a tr~p capacitor 202 and a re~et capacitor 203, Capac~tor 202 i8 charged dlrectly through a diode 204, and capacitor 203 i charged through an isolation resistor 205.
Upon occurrence of a fault, a reed ~witch 206 close~ to apply enabling current througha diode 207, resistor 208, and bilateral diode 209 to the gate electrode of an SCR 210, which conducts to discharge reset capacitor 203 through winding 187.
In accordance with the invention, an SCR 211 i~
next enabled after a delay to discharge trip capacitor 202 through the winding to cause a fault indication. A network consisting of reistors 212 and 213, a capacitor 214 and a bilateral diode 215 provide the necessary delay. Resistor~
216 and 217 provide nece~sary ground returns for the gate electrodes.
Thu~, the reset circuit of fault indlcator 180 18 ~280168 tr~pped immediately upon occurrence of a fault, rendering it inoperative pending the completion of a subsequent charging cycle. ~hen, while the reset circuit is operative, the trip circuit i8 actuated to condition the indicator to a fault-indicating state. Since the reset circuit i8 inoperative when the fault circuit i8 actuated, the possibility of simultaneous actuation of the two circuits is eliminated.
In practice, the delay period utilized in actuating the trip circuit following a fault will depend on the duration of the reset period, which in turn wi}l depend on circuit parameters. In one successful embodlment of the invention, for example, a fault indicator havlng a ~16 millisecond reset period and a .4 millisecond trip period, may have a total trip delay of .28 milliseconds, which provides a space between the end of the reset pulse and tbe beginning of the trip pulse of .12 milliseconds, and a total reset and trip period of .68 ~illisecond~. ~owever, it will be understood that other pulse widths and delay periods ~ay be appropriate in other applications.
While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that change~ and modifications may be made therein without departing from the invention in its broader aspects, and, therefore, the aim in the appended claims is to cover all such changes and modifications a~
fall within the true spirit and scope of the invention.
2~
Claims (19)
1. A fault indicator for indicating the occurrence of a fault current in a monitored electrical conductor of an alternating current power distribution system, comprising:
status indicating means having a reset-indicating state and a fault-indicating state;
trip circuit means for conditioning said status indicating means to said fault-indicating state in response to the occurrence of a fault current in the conductor;
reset circuit means periodically operable for a predetermined reset period for conditioning said status indicating means to said reset-indicating state, and inoperable for a predetermined recovery period following each such reset period; and said trip circuit means rendering said reset circuit means initially operable upon occurrence of a fault, and conditioning said status indicating means to said fault-indicating state during said recovery period following a trip delay per greater than said predetermined reset period to preclude simultaneous operation of said trip and reset circuits.
status indicating means having a reset-indicating state and a fault-indicating state;
trip circuit means for conditioning said status indicating means to said fault-indicating state in response to the occurrence of a fault current in the conductor;
reset circuit means periodically operable for a predetermined reset period for conditioning said status indicating means to said reset-indicating state, and inoperable for a predetermined recovery period following each such reset period; and said trip circuit means rendering said reset circuit means initially operable upon occurrence of a fault, and conditioning said status indicating means to said fault-indicating state during said recovery period following a trip delay per greater than said predetermined reset period to preclude simultaneous operation of said trip and reset circuits.
2. A fault indicator as defined in claim 1 wherein said reset circuit means include a reset capacitor for supplying operating current thereto, and a discharge circuit operable in conjunction with said reset capacitor for establishing said predetermined reset period.
3. A fault indicator as defined in claim 2 wherein said reset capacitor is capacitively coupled to the monitored electrical conductor.
4. A fault indicator as defined in claim 3 wherein said trip circuit means include switch means responsive to the occurrence of a fault in the monitored conductor, and said reset circuit means are responsive to the closure of said switch means for initiating said reset period.
5. A fault indicator as defined in claim 4 wherein said switch means comprise a reed switch in magnetic communication with the monitored conductor.
6. A fault indicator as defined in claim 2 wherein said reset circuit means include a charging circuit for said reset capacitor, said charging circuit forming in conjunction with said reset capacitor an RC timing circuit for establishing said recovery period.
7. A fault indicator as defined in claim 6 wherein said recovery period is substantially greater than said reset period.
8. A fault indicator as defined in claim 1 including a trip coordination circuit for inhibiting said trip circuit for a predetermined coordination period following initial power-up of the monitored conductor.
9. A fault indicator as defined as claim 8 wherein the operation of said coordination circuit is substantially independent of the operation of said reset circuit.
10. A fault indicator as defined in claim 1 wherein said trip circuit means include a trip capacitor for powering said trip circuit, and an RC timing circuit operative in conjunction with said trip capacitor for establishing said trip delay period.
11. A fault indicator as defined in claim 10 wherein said trip capacitor is capacitively coupled to the monitored electrical conductor.
12. A fault indicator for indicating the occurrence of a fault current in a monitored electrical conductor or an alternating current power distribution system, comprising:
status indicating means having a reset-indicating state and a fault-indicating state;
reset circuit means periodically operable for a predetermined reset period for conditioning said status indicating means to said reset-indicating state, and inoperative for a predetermined recovery period following each such reset period, said reset circuit means including a reset capacitor for supplying operating current thereto, a discharge circuit operable in conjunction with said reset capacitor for establishing said reset period, and a charging circuit operable in conjunction with said reset capacitor for establishing said recovery period; and trip circuit means for rendering said reset circuit operable, and including a trip capacitor and an associated RC time constant circuit for conditioning said status indicating means to said fault-indicating state during said recovery period after a predetermined trip delay period greater than said reset period, in response to the occurrence of a fault current in the monitored conductor, whereby simultaneous conditioning of said indicating means by said reset and trip circuit means is prevented.
status indicating means having a reset-indicating state and a fault-indicating state;
reset circuit means periodically operable for a predetermined reset period for conditioning said status indicating means to said reset-indicating state, and inoperative for a predetermined recovery period following each such reset period, said reset circuit means including a reset capacitor for supplying operating current thereto, a discharge circuit operable in conjunction with said reset capacitor for establishing said reset period, and a charging circuit operable in conjunction with said reset capacitor for establishing said recovery period; and trip circuit means for rendering said reset circuit operable, and including a trip capacitor and an associated RC time constant circuit for conditioning said status indicating means to said fault-indicating state during said recovery period after a predetermined trip delay period greater than said reset period, in response to the occurrence of a fault current in the monitored conductor, whereby simultaneous conditioning of said indicating means by said reset and trip circuit means is prevented.
13. A fault indicator as defined in claim 12 wherein said reset and trip capacitors are capacitively coupled to the monitored electrical conductor.
14. A fault indicator as defined in claim 12 wherein said recovery period is substantially greater than said reset period.
15. A fault indicator as defined in claim 12 wherein said trip circuit means include switch means responsive to the occurrence of a fault in the monitored conductor, and said reset circuit means are responsive to the closure of said switch means for initiating said reset period.
16. A fault indicator as defined in claim 15 wherein said switch means comprise a reed switch in magnetic communication with the monitored conductor.
17. A fault indicator as defined in claim 12 including a trip coordination circuit for inhibiting said trip circuit for a predetermined coordination period following initial power-up of the monitored conductor.
18. A fault indicator as defined in claim 17 wherein the operation of said coordination circuit is substantially independent of the operation of said reset circuit.
19. A fault indicator as defined in claim 12 wherein said recovery period is substantially greater than said reset period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000556530A CA1280168C (en) | 1987-04-24 | 1988-01-14 | Fault indicator having delayed trip circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US042,282 | 1987-04-24 | ||
| CA000556530A CA1280168C (en) | 1987-04-24 | 1988-01-14 | Fault indicator having delayed trip circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1280168C true CA1280168C (en) | 1991-02-12 |
Family
ID=4137258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000556530A Expired - Lifetime CA1280168C (en) | 1987-04-24 | 1988-01-14 | Fault indicator having delayed trip circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1280168C (en) |
-
1988
- 1988-01-14 CA CA000556530A patent/CA1280168C/en not_active Expired - Lifetime
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