CA1278391C - Enhanced density modified isoplanar process - Google Patents

Abstract

Attorney Docket Number 53.1057 ENHANCED DENSITY MODIFIED ISOPLANAR PROCESS
Abstract An improved process for fabricating modified isoplanar integrated circuits with enhanced density incorporates a number of interactive and co-acting process steps. First, oxide isolation of epitaxial islands is effected in a two step process, forming a thin thermally grown oxide layer over the surfaces of shallow trenches and then filling the shallow trenches with deposited low temperature oxide.
Second, an enhanced single polycrystalline or polysilicon layer process uses a blanket implant, eliminates certain masking and etching steps, and defines the polycrystalline layer for greater and more efficient use in resistor, transistor, and related circuit interconnects and elements of the integrated circuit structure. Third, a new method and structure is provided for dielectrically isolating and separating contact locations on different surface levels of the integrated circuit structure adjacent to step locations between the surface levels. Spacer shoulders of dielectric material are formed at the step locations separating contact locations on the lower surface level of the monosilicon epitaxial layer from contact locations on the upper surface level of the polysilicon layer by anisotropic etching of a blanket conformal spacer layer of dielectric material.
Finally, a new method constitutes all of the electrical contact locations for the elements of the integrated circuit structure at the same substantially isoplanar level. This is accomplished by bridging from contact locations on the lower surface level of the monosilicon epitaxial layer to transfer contact locations on the polysilicon layer.
Polycrystalline islands provide the transfer contact locations and the spacer shoulders at the polycrystalline islands provide sites for bridges or strips of titanium or other refractory metal used in siliciding the contact locations.

Description

A~torney Docket Number 53.1057c EN~ANCED DENSITY MODIFIED LSOPLANAR PROCESS
Technlcal_Field Thi8 invention rela~es to new methods for f~brlcating bipolar modified isoplanar integrated circuit s~ructure~ to minimize geometry and enhance den~lty for very large scale integration. In particular the invention provides new methods for: oxide isolation of epitaxial islands, limiting encroachment of isolation oxide regions into the epitaxial lQ islands or mesas, thereby permitting smaller epi~axi21 island or mesa dimensions; enhanced and more efficient use of a single polycrystalline layer in forming higher density transistor, resistor and related circui~ elements of the integrated circuit structure; electrical isolation and separation of electrical contact locations on different levels of an integrated circuit structure with minimum spacing be~ween contact locations, and in par~icular isolation of contact locations on the monosilicon e?itaxial layer from contact locations on the overlying pol,~silicon layer; and transfer o electrical contact locations on different levels of the integrated circuit s~ructure to the same substantially isoplanar level.
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The clas~ical isoplanar proces6 for fabrica~ion of integrated circu~ts is described, for example ln the Peltzer-U.S. Pa~ent ~umber 3,648,125. An epita~ial l~yer of semiconductor material of one conductlvity type is deposited over a -~ubstrate of ~emiconductor material of opposite conductivity type forming an isolation junction or inter~ace extending laterally through the structure. The epitaxial layer is aubdivided into a plurality of epi~a~ial lslands, pedestals or mesa~ ~eparated by i801ation oxide regions.
The actlve and passive integrated circuit elements arc then formed in the epitaxial lslands by a complex sequence of masking, etchlng and difiusion steps.
The lsoplan~r proce~s for fabrication of integrated circuit structure~ h~ been the subJect of contlnuing evolution and improvement. The How~ll et al. U.S. Patent 7 ~ 3~
Number 4,498,227 d~scribes ~n improved i~oplanar process which fully ln~egrate~ ion implant methods into the isoplanar process and fully substi~u~e~ ion implant methods for diffuslon methods. The use of passivatlng and 5 protective oxide and nitrlde layers over the epit~xial layer throughout ~he fabrication process is al80 described.
Development~ have also continued in the arrangement of other structUres and elements including, for example, the buried collector layer regions and channel stop regions of the 10 substrate, etc.
Further improvements in the isoplanar process include ~he incorporation of one or more polycrystalline semiconductor material layers or polysllicon layers in the fabrication process for constituting the active and passive 15 elements of the integrated circuit structure. For example in the single layer polysilicon emitter bipolar process a polysilicon layer is formed over the monosilicon epitaxial layer for establishing the emi~ter region of transistors and related elements of the integrated circuit structure t 20 including electrical contact locations. In the "single poly" emitter technologies all electrical contacts to elements of the integrated circuit structure are mad~
; through the poly~ilicon layer at the same lev~l requiring ~` extra masking and implanting steps.
A nu~ber of problem8 can be identified in the improved isoplanar processes for example during isolation of the epitaxial islands with i601ation oxide region~. In conventional lsolation processes, a substantial portion of the silicon of the epi~axial islands may be con~umed during 30 growth of thermal oxide from the 8ilicon in regions between the epitaxial islands. The 1088 of sil~con from the epitaxial island~ duri~g thermal growth of isolation oxide can amount ~o for example 2~ around the sides of the islands or me~a~. During earlier years in the of 35 development of the i60planar process with epitaxial island siæes in the range of 20~, this loss was acceptable. As epitaxial lsland or me8a sizes have decreased wlth large scale integratlon from 20 ~ to 6 ~ wide and ~maller, the ~!, ~7~3~

loss by encroachment into the epitaxial islands can arnount to as great as 40 to 60% o~ ~he islands. The ~otal encroachment includes not only the losses from isolation oxidation but also from photolithography and etching.
One method seeking to eliminate encroachment into the epitaxial islands in large scale integration, currently under development, is "trench technology" or "groove technology". According to the trench technology, the epitaxial islands are first separated by etching unidirectionally through the layers of the integrated circuit structure including the epitaxial monosilicon layer ~; and any buried collector layer region into the subs~rate of semiconductor material. The trenches are etched using an anisotropic plasma etch through all layers for examp~e to a depth of 4 with no encroachment into the epitaxial islands. A difficulty with growing thermal isolation oxide in the ~renches however is that the thermal oxidation produces stresses and defects at corners of the trenches which propagate into the epitaxial islands. As a result, the trenches are instead filled with oxide deposits such as low temperature oxide or plasma enhanced chemical vapor deposition to avoid stresses and defects. However, deposition of oxide or other dièlectric into the trenches instead of the thermal growth of oxide introduces contaminants such as sodium with consequen~ parasitic MOS
effects between the islands. Moreover, it is difficult to obtain good ohmic contact for the ground substrate contacts.
The trench or groove technology is not yet suitable for bipolar technologies.
A disadvantage of the conventional polycrystalline layer procedures for defining and completing the integrated circuit elements is that additional maskin~, etching and implanting steps are required during wafer fabrication.
Typically separate masking, etching and implant sequences are required for N- implants for resistors, N+ implants for ëmitter, collector sink and resistor contact locations, and P+ implants for base contact locations and ground contact locations. Furthermore ull advantage is not taken of the ~.~i7~

properties of the polysilicon layer, either low resistance or high resistance, in constituting the final struc~ure of the integrated circuits.
To avoid the additional masking steps accompan~ing introduction of a polycr~stall:~ne silicon layer or polysilicon layer in addition to the monocrystalline silicon or monosilicon epitaxial layer, electrical contact locations for the integrated circuit elements may result at two different levels across the surface of the integrated circuit. For example the contact locations for circuit elements of semiconductor material of first conductivity type such as P type silicon ground contac~s and transistor base contacts may be formed in the monosilicon epitaxial layer at a first level or lower surface level while emitter, collector sink, and resistor contacts of semiconductor material of second conductivity type such as N type silicon contacts may be formed in the polycrystalline layer at a second level or upper surface level.
This departure from the true isoplanar process with ~lectrical contact locations of integrated circuit elements on two surface levels with step locations between the surface levels makes it difficult to achieve effective electrical isolation of contacts in the vicinity of step locations under the constraints of spacing and size required by very large scale integration.
Furthermore, subsequent masking, etching and deposition steps Eor example for the final metal contact masking must be carried out at two levels.
Disclosure of the Invention In order to avoid these problems the present invention provides an enhanced polycrystalline layer process for fa~ricating a bipolar modified isoplanar integrated circuit structure which may include resistor and transistor elements.
The component elements are formed with contact locations on a lower surface level semiconductor material epitaxial layer and contact locations on an upper surface level semiconductor material polycrystalline layer. The structure is characterized by step locations bet~een the upper and lower surface levels.
The enhanced poly layer process of the invention provides a new method for transferring contact locations from the lower surface level to the upper surface level ~ forming polycrystalline islands during ~abrication o the integrated circuit structure adjacent to contact locations on the lower surface level, exposing adjacent contact locations on the lower and upper surace levels, and forming a refractory metal reactive with the semiconductor material over the lower and upper surface levels.
Further steps according to the invention include sintering and reacting the layer of refractory metal with the semiconductor material at the contact locations thereby forming a low resistance layer over the contact locations on the lower and upper surface levels, and selectively masking and stripping the Eormed metal layer of refractory metal. The layer of refractory metal is selectively masked and stripped for removing unreacted refractory metal between contact locations to be isolated and separated and leaving conductive metal strips or bridges between contact locations on the lower surface level and transfer contact locations on the upper surface level provided by adjacent polycrystalline islands. The method thereby constitutes contact locations for elements of the inte~rated circuit structure from different levels on substantially the same upper surface level of the poly layer.
The preferred example embodiment of the process incorporates the further step o forming dielectric material spacer shoulders between adjacent contact locations at step locations between lower and upper surface levels and leaving the conductive strips or bridges between contact locations on the lower sur~ace level and transfer contact locations on the upper surface level over the spacer shoulders.
The enhanced polylayer process produces a new product in the form of a modi~ied isoplanar integrated circuit structure with polycrystalline islands ormed adjacent to contact locations on the lower surface level for providing transfer contact locations on the upper surface level. The s~ructure is ~urther characteriæed by spacer shoulders of dielectric material at step locations between the polycrystalline islands and contact locations at the lower surface level. A low resistance layer overlies the contact locations. ~efractory metal s~rips or ~ridges overlie the spacer shoulders between contact locations on the lower surface level and transfer contact locations on the upper surface level of adjacent poly islands. All contact locations for the modified isoplanar integrated circuit structure are therefore constituted on substantially the same upper surface level of the poly layer.
Without limitation to the generality and scope o~ the foregoing process and product of the invention, ~urther features, aspects and details of the invention are summarized as follows.
The epitaxial layer of semiconductor material of first conductivity type formed over the substrate of the integrated circuit structure is divided into a plurality of epitaxial islands, pedestals or mesas. The epitaxial islands are isolated relative to each other with isolation oxide regions. Collector sink regions of semiconductox material of second conductivity type are implanted in the epitaxial islands. Base regions of semiconductor material of irst conductivity type are implanted in the epitaxial islands spaced from the collector sink regions.
Thereafter a polycrystalllne layer of semiconductor material is deposited over the substantially isoplanar epitaxial islands and isolation oxide regions.
According to the enhanced single polysilicon layer process of the invention, the polycrystalline layer is blanket implanted with dopant material orming a uniform polycrystalline resistor layer of semiconductor material across the integrated circuit structure. Typically a uniform N- or P- polysilicon layer is established by the blanket resistor implant across -the surace of the integrated circuit structure. A blanket polycrystalline oxide, polysilicon oxide, or polyoxide layer is then grown over -!
the polycrys~alline layer. The invention then contemplates defining regions for emitter, collector, and resistor contact locations by masking and etching the polyo~ide layer to form an emitter, collector, and resistor contacts implant mas~.
De~inition of these regions for contact locations is f~llowed by implanting through the mask formed by the polyoxide la~ler into the polycrystalline layer with ~opant material forming regions of semiconductor material of low resistance second conductivity type for emitter collector, and resistor contact locations. T~pically low resistance N+ polysilicon regions provide the emitter, collector, and resistor contact locations. The polycrystalline layer is then capped with a dielectric barrier layer which ma~ be followed by an emitter anneal step for driving N+ dopant material into the P- base ~egion to form the emitter region.
Therea~ter the invention contemplates de~ining areas of the polycrystalline layer to be retained and to ~e removed by masking and etching the dielectric barrier layer there~y forming a poly-definition mask. Exposed portions of the polycrystalline layer are etched away through the poly definition mask leaving resistor regions of high resistance, for example N- polysilicon resistor regions, and emitter, collector, and resistor contact locations of low resistance second conductivity type, for example ~+
polysilicon contact locations.
~ feature and advanta~e of the enhanced polysilicon steps according to the present invention is that a masking sequence is eliminated in the preparation of the polycrystalline layer by the blanket resistor implant which avoids an N- or P- masking and etching step. Furthermore, full advantage is taken of the polycrystalline layer during the N~ implanting, maskin~, and etching steps in utilizing either the low resistance or high resistance characteristics of the polycrystalline layer for integrated circuit elements. For example in addition to emitter, collector, and resistor contact locations of polycrystalline semiconductor material of low resistance second conductivity type, N+ interconnects or runs are also defined pro~iding ~2~7~3~

effectively an addltional conductive layer assuming some of the functions of subsequent metal layers. On the other hand the regions o-E high resistance, typically N- type regions, are used for defining resistors with N+ contact locations at each end of the resistor providing good metal contacts.
The enhanced single layer polysilicon process of the invention also eliminates a subsQ~uent maskin~, etching and implant se~uence for forming semiconductor material of first conductivity type in the polysilicon layer over base regions and ground regions. conventionally, P type polysilicon regions are implanted in the polysilicon layer ~or base contact locations and ground su~strate contact locations at the sur~ace level of the polysilicon layer. According to the present invention the polysilicon layer is selectively defined and etched to expose the P- ground subst~ate and base contact locations at the surface level o~ the monosilicon epitaxial layer and the P type mask, etch and implant sequence in the polysilicon layer is elirninated.
The result of incorporating the polycrystalline or polysilicon layer in the fabrication process for integrated circuit structures according to the invention is that resistor, transistor and circuit Plements are formed having contact locations at least at two different surface levels with step locations between the surface levels. Contact locations at one sur~ace level are electrically isolated and separated from contact locations at the other surface level while minimizing the spacing requirements. An etch stop layer is formed over semiconductor material contact locations on the different surface levels namely the lower surface level of the monosilicon epitaxial layer and the upper surface level of the polysilicon layer. A blanket conformal spacer layer of dielectric material of substantially uniform thickness is deposited over the integrated circuit structure including the different surface levels and step locations between the levels.
The spacer layer is then anisotropically etched in the direction orthogonal to the surface levels of the integrated 3~

i~ircuit structure using a blanket uni~irectional anisotropic plasma etch. The spacer layer is e~ched to the etch stop layer over the semiconductor material contact locations on the different surface levels, leaving spacer shoulders of dielectric material from the spacer layer at the step loc,ations between levels. A feature and advantage of this arrangement is that the contact locations on different surface levels adjacent to the step locations are dielectrically isolated and separated with minimum spacing between the contac~ locations. The maskless anisotropic etch of the present invention avoids the greater spacing requirements of a mask etch and the registration problems of photolithograph~ thereby reducing transistor size.
Typically the blanket spacex layer comprises a nitride layer formed by plasma enhanced chemical vapor deposition while the etch stop layer is an etch stop oxide layer. Alternatively the blanket spacer layer may comprise low temperature oxide with an etch stop layer of different material such as for e~ample an etch stop nitride layer. Typically the lower surface level is a monosilicon layer namely the monosilicon epitaxial layer while the upper surface level is provided by the polysilicon layer.
The spacer shoulders isolate and separate base contact locations on the lower surface level monosilicon layer, typically P-silicon regions, from emitter contact locations on the upper surface level polysilicon layer, typically N+ silicon regions.
Ground contact locations on the lower swrface level mo~osilicon layer may be isolated for example from resistor contact locations on the upper surface level polysilicon layer.
After establishing the spacer shoulders, good metal contacts surfaces may be established at the contact locations by forming a low resistance silicide layer or other sintered layer over the semiconductor material of the contact locations. To this end the invention provides the steps of removing the etch stop layer thereby exposing the contact locations at the different levels and sputtering or otherwise depositing a layer of refractory metal reactive with the semiconductor material over the different ^~' ?

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surface levels. The layer of refractory metal is then sin~ered and reacted with the semiconduc~or material forming a low resistance silicide layer or other sintered layer over the contact locations on the dif~erent levels. The refractory metal remains unreacted over the dielectric surfaces and is stripped from the spacer shoulders between contact locations to be isolated and separate~ thereby leaving isolated and separated low resistance contact locations with minimum spacing requirements.
In the preferred embodiment the reastive and refractory metal is titanium sputtered over all of the surfaces of the integra~ed circuit structure.
The invention also provides a new method for resolving the problems presented by electrical contact locations at different levels of an integrated circuit structure. Thus, in the enhanced polycrystalline layer process or single polysilicon layer process for fabricating bipolar modified isoplanar integrated circuits according to the invention, transistor element contact locations and in particular the base contact locations, typically P or P-type silicon are formed and exposed on the monosilicon epitaxial layer. The monosilicon layer rorms a lower surface level in the integrated circuit structure. On the other hand the emitter, collector sink, and resistor contact locations, typically N~ type silicon are formed in the polycrystalline layer or polysilicon layer overlying the monosilicon epitaxial layer. The polycrystalline layer forms a second upper surface le~el of ~he integrated circuit structure. Step locations between the lower and upper surface levels separate contact locations on the two levels. This departure from a thorough going isoplanar process requires masking, etching and depositing metal contacts at two different levels in finishing the integrated circuit structure.
According to the present in~ention the departuxe from isoplanar arrangements of the electrical contacts may be resolved by forming polycrystalline contact islands during fabrication of the integrated circuit structure adjacent to contact locations on the lower surface level of the monosilicon layer. The !

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polycrystalline or polysilicon contact islands provide transfer contact locations at the upper surface level for electrical transfer from contact locations on the lower surface level~ The contact locations on the lower and upper surface levels are exposed and a layer of refractory metal reactive with the silicon is formed over the lower and upper surface levels for example by sputtering. The invention provides the steps of sin~ering or reacting the layer of refractory metal with the monosilicon and polysilicon at the contact locations forming a low resistance silicide layer over the contact locations on the lower and upper surface levels.
The layer of refractory metal is selectively masked and etched from the surface levels r~moving unreacted refractory metal between contact locations to be isolated and separated while leaving conductive metal strips or bridges between the silicide layers over contact locations on the lower surface level and transfer contact locations on the upper surface level provided by adjacent polysilicon islands. Alternatively, the sputtered or deposited metal layer is selectively masked and stripped prior to sintering or reacting to leave the desired pattern. A eature and advantage of this "bridging" arrangement is that all of the contact locations for elements of the integrated circuit structure are constituted on the same upper surface level of the polycrystalline layer substantially restoring an isoplanar arrangement of contact locations for subseguent processing according to isoplanar methods.
In order to accomplish this result the step of defining the areas of the polycrystalline layer to be retained and to be removed includes defining polycrystalline or polysilicon islands to be retained for transfer contact locations. Advantageously the polycrystalline or polysilicon islands are constructed and arranged adjacent to contact locations of the lower surface level on the monosilicon epitaxial layer. Thus the polycrystalline islands are included in the poly-definition mask. The step of etching away exposed portions o~ the polycrystalline or 3~

polysilicon laycr leaves the pol~crystalline islands for electrically transferring contact locations from the lower surface level epitaxial layer to the upper surface level polycrystalline layer. Typically, the transfer contact loca~ions of the polysilicon islands are of semiconductor ma~erial of low resistance second conductivity -t~lpe, for example N-~ t~ype polysilicon. The transfer contact locations on the polysilicon islands are N+ implanted during ~he previous emitter, collector sink, and resistor contacts N~ implant sequence in the polysilicon layer.
The method of developing spacer shoulders of dielectric material at the step locations between surface levels particularly lends itself to the new me~hod for transferring and constituting all of the contact locations to the upper surface level polycrystalline layer. While the dielectric material spacer shoulders isolate and separate contact locations on the two surface levels adjacent to the step locations, the spacer shoulders also provide dielectric surfaces for unreacted refractory metal deposited over tha upper and lower surface levels. Multiple use of the dielectric material spacer shoulders may be implemented after sintering and reacting the layer of refractory metal with the exposed semiconductor material at contact locations.
Thereafter the invention contemplates selectively masking and etching or stripping the refractory metal layer removing unreacted refractory metal from spacer shoulders between contact locations to he isolated and separated. On the other hand the selective masking and etching of the titanium layer or other refractory metal layer is constructed and arranged to leave conductive metal strips or bridges cver spacer shoulders at the polysilicon islands adjacent to contact locatlons on the lower surface level. Thus, con~uctive metal strips or bridges are left over the polysilicon island shoulders of dielectric material between contact locations on the lower surface lavel of the monosilicon layer and transfer contact locations on the upper ?

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l3 surface level or the polysilicon islands.
In the absence of the spacer shoulders of dielectric material, the sputtered or deposited refractory metal la~er must be selectively masked ~nd etched to leave the desired pattern prior to sintering or reacting the metal. ~ feature and advantage of the d:Lelectric spacer shoulders is that the ~etal remains unreacted over the dielectric surface of the spacer shoulders during sintering.
In summary, the present invention provides an improved and enhanced process for fabricating modified isoplanar integrated circuits incorporating a number of interactive and co-actin~
process steps to minimize geometry, reduce dimensions, and enhance density for very large scale integration. The invention enhances use of the single polycrystalline or polysilicon layer using a blanket implant, eliminates mas~ing and etching steps, and defines the polycrystalline layer for greater and more efficient use for resistor, transistor, interconnect, and related circuit elements of the integrat~d circuit structure. Spacer shoulders of dielectric material are formed at the step locations separating contact locations on the lower surEace level o~ the monosilicon epitaxial layer from contact locations on the upper surface level of the polycrystalline or polysilicon layer using a blanket layer and an anisotropic etch.
Finally the invention provides a new method and a new modified isoplanar IC structure for constituting all of the electrical contact locations for the elements of the integrated circuit structure at the same substantially isoplanar level.
This is accomplished by bridging from contact locations on the lower surface level of the monosilicon epitaxial layer to transfer contact locations on the polysilicon layer.
Polycrystalline islands provide the transfer contact locations and are included in the definition of the polycrystalline layer.
The spacer shoulders at step locations of the polycrystalline islands provi~e sites for leaving bridges or strips of refractory metal between the contact locations at the lower surface level ~ ~27~

and the transfer contact locations on the upper surface levels of the poly islands~
Other objects, featur~s and advantages of the inv~ntion are apparent in the following specification and accompanying drawings.
Brief Description of the Drawings Figure 1 is a fragmentary diagr~mmatic cross-section of a portion of an integrated circuit structure showing epitaxial islands or mesas separated by shallow trenches according to the invention. The etched sloping boundaries of the shallow trenches or shallow "V" grooves follow the 54 inclined plane of the silicon crystal. In subse~uent figures this etched boundary between the isolation oxide and active epitaxial layer elements is shown diagrammatically as vertical for simplicity and clarity of the drawings.
Figure 2 is a fragmentary diagrammatic cross-section of the same portion of the integrated circuit structure showing isolation oxide regions formed according to the two step oxide isolation process of the invention. The isolation oxide is shown in two parts, the thin layer of thermally grown isolation oxide and overlying deposited low /~
temperature oxide. Isolatlon oxide/epit~xial layer boundaries are shown to be vertical for simplicity.
Figure 3 is a composite fragmentary diagrammatic cross~section of the same portion of the integrated circuit 5 structure showing the N+ implant of the col.].ector sink region and P- implant of the base region and ground contact region. In this and subsequent drawings, the thermal isola~ion oxide thin layer and deposi.ted low temperature oxide are shown for simplicity as the single merged lOisolation oxide region.
Figure 4 is a fragmentary diagrammatic cross-section of the same portion of the integrated circuit structure showing the deposition of the polysilicon layer, blanket N- implant of the polysilicon layer and polyoxide layer according to lSthe invention.
Figure S is a fragmentary diagrammatic cross~section of the same portion of the integrated circuit structure showing .the N+ implant mask and N+ implant into the polysilicon layer.
Figure 6 is a composite fragmentary diagrammatic side cross-section of the same portion of the integrated circuit structure showing the etched polysilicon layer and the ;, overlying spacer layer of clielectric material according to the present invention.
Figure 7 i~ a fragmentary diagrammatic cross-section of the same portion of the integrated circuit structure showing the dielec~ric spacer dielectric shoulders resulting from the anisotropic etch.
Figure 8 is 8 fragmentary diagramma~ic cross section of 30tlle same portion of the integrated circuit structure showing the silicidation of exposed contact locations and the conducting bridges or transfer strips formed over the spacer shoulders be~ween contac~ locations on the two different levels according ~o the invention.
Figure 9 is a fragmentary diagrammatic cross-section of the same portion of the integrated circuit structure showing a metal contact mask in place over the integrated circuit structure with ~11 cont~ct locations at the same upper 7~,~3~

levels, while Figure 9A is a schematic equivalent circuit diagram of the structure of Figure 9.
Figure 10 is a fragmen~ary diagrammatic plan view of the layout of integrated circuit elements showing the polysilicon island according to ~he invention with a refractory metal strip or bridge over the polysilicon island spacer shoulder for transferring the contact location from the lower surface level monosilicon base contact to the upper surface level polysilicon island, while ~igure lOA is 10 a diagrammatic cross-section of the same structure in the direction of the arrows on line A-A of Figure 10.
Detailed Description of Preferred Example Embodiments and Best Mode of the Invention The steps in fabricating a new bipolar modified 15 isoplanar integrated circuit structure according ~o the invention are illustrated in Figures 1-9. Figure 1 shows in diagrammatic cross section a fragmentary portion of a substrate 10 of, for example, P type silicon semiconductor material. The N~ silicon buried collector layer or subcollector layer 12 is formed in the conventional manner by mask, etch, and implant steps. Thus, an initial oxide layer is grown uniformly across the substrate 10, a $ photoresist material is spun on the oxide layer, the photoresist is exposed through a light mask with openings 25 defining the buried collector regions, and the exposed portions of the photoresist layer are washed away with developer leaving the photoresist material as an etching mask. The underlying oxide layer is etched to expose the substrate 10 at the surface locations of buried collector 30 layer regions 12 and N type impurities such as arsenic or phosphorous are introduced into the buried collector layer regions by ion field implant methods or diffusion, followed by anneal, to an N+ concentration which affords low resis~ance or high conduc~ivity semiconduc~or material in 35 the buried collector layer regions 12.
The channel stop regions 14, 15, and 16 are similarly formed in the substrate 10 by conventional mask, etch, and implant steps. P type impurities such as boron are ~3 introduced into the channel stop regions by implant or diffusion to P~ concentration levels for low resistance or high conductivity. The channel stop regions 14, 15, and 16 a~sure the reliability of the integrated circui~ structure by substantially eliminating the problem of parasitic MOS
FET transistor effects between adjacent epitaxial islands.
The initial oxide layer is stripped and epitaxial layer 18 is then deposited or precipitated onto the substrate 10 in the form of a single crystal layer by, for example, an 10 epitaxial chemical vapor deposition process. The epitaxial silicon is lightly doped with arsenic so that the epitaxial layer is formed with N- concentration for high resistance or low conductivity. The surface of epitaxial layer 18 is oxidized to form a thin epitaxial oxide layer or epioxide 15 layer 20 of silicon dioxide (SiO2). Epitaxial oxide layer 18 forms an isoplanar oxide layer and provides stress relief for the nitride layer or cap 22. The nitride layer 22 is deposited over the epitaxial oxide buffer layer 20 by, for example, chemical vapor deposition. The silicon nitride 20 layer 22 is of the chemical form SiXNyOz comprising, for example, Si3N4.
According to the invention epitaxial islands 25 are ~" formed by defining isolation oxide regions 30 between the epitaxial islands using the dielectric layers 20 and 22 as 25 the isolation oxide mask. This is accomplished by photomasking and etching the nitride layer 22 and epioxide layer 20 in the pattern of the isolation oxide regions.
In contrast to the conventional etching of the silicon epitaxial layer 18 at the locations of the isolation oxide 30 regions 30, the present invention uses a timed anisotropic plasma etch through the major portion of the epitaxial layer 18. By timing control the etch through the major portion o epitaxial layer 18 is limited to a level above the interface 26 between the epitaxial layer 18 and substrate 10 leaving a 35 thin layer 27 of epitaxial semiconductor material at the base of a shallow groove in the epitaxial layer 18.
As shown in Figure 1, the timed or time controlled plasma etch produces a shallow trench in the vicinity of the /y isolation oxide regions 30 terminating just above the interface 26. The silicon is preferably etched along the crystal planes resulting in shallow trenches or grooves with sloping walls 28 along, for example, the 54 crystal axis of the epitaxial silicon. The epitaxial layer 18, typically 1 micron (~) in thickness, is etched for exampl~ to a depth of 9,000 angstrom units (A) leaving a thin epitaxial layer 27 of for example 1,000 ~ lining ~he base of the shallow groove or trench.
As shown in Figure 2, the isolation oxide regions 30 are filled with oxide according to the invention in a two-step process by first growing a thin thermal isolation oxide layer 32 at elevated temperatures from the thin layer 27 of epitaxial semiconductor material lining the surfaces 15 of the shallow trenches or grooves shown in Figure 1. The thin thermal oxide layer grown in the etched grooves or trenches of the isolation oxide regions 30 is in contrast to ~ .
conventional isolation oxide procedures in which a substan~ial portion of the epitaxial islands are consumed in 20 the thermal oxide of the isolation oxide regions. In conventional isolation oxide processes, approximately half of the epitaxial layer 18 may be consumed in growing thermal isolation oxide. According to the present invention, only a thin layer of epita~ial silicon in the order of, for 25 example, 1,000 A or .1~ is consumed with only very limited encroachment into the walls of the epitaxial islands.
The thin thermal oxide layer 32 is typically grown in a furnace at, for example, 960-1,000 C in dry oxygen for a reaction time of approximately an hour or in steam for 30 approximately a half hour. Growth of the thin thermal oxide layer 32 may also be accelerated in a pressure vessel at, for example, 25 atmospheres of steam for a reaction time of approximately ten minutes at 950 C.
The preferred thickness of the thin thermal oxide layer 35 32 lining the isolation oxide regions 30 is in the range of approximately 1,500 A - 3,000 A. At the thinner end of the range a thermal oxide layer of 1,500 A is sufficient to prevent any substantial amounts of impurities from passing 3~

through the thin thermal oxide layer 32 into the epitaxial layer. At thicknesses greater than 3,000 A there is substantial encroachment into the epitaxial islands and stresses are produced at corners and defects in the epitaxial layer along the surface of the shallow trench or groove. In order to achieve the preferred range of thickness for the thin thermal oxide layer 32 of 1,500 A -3,000 A, the anisotropic plasma etch through ~he epitaxial layer is timed to leave a ~hin layer 27 of epitaxial silicon 10 lining the trench or groove in the range of 600 A - 1,200 A.
The oxide growth ratio of silicon to silicon dioxide (Si/SiO2) is approximately 1/2.5 thereby establishing the ! preferred range for ~he thin epitaxial layer 27.
In the second step of the isolation oxide process the 15 shallow trenches or shallow V grooves lined with the thin thermal oxide layer 32 are filled by depositing low temperature isolation oxide 34 in the shallow trenches.
Filling of the isolation oxide regions 30 over the thin thermal oxide layer 32 may be accomplished by either a low 20 temperature oxide (LTO) deposit, a plasma enhanced chemical vapor deposition (PECVD), a low pressure chemical vapor deposition (LPCVD), etc. The low temperature or vapor P, deposition of silicon dioxide fills the isolation oxide regions 30 without the stresses associated with growing high 25 temperature thermal oxide and without the encroachment into epitaxial islands. The present invention is therefore suitable, for example, for large-scale integration with enhanced density and epitaxial islands 6 ~ in width and even 3 ~ - 6 ~ in width. Encroachment of thermal oxide into the 30 sides of the LSI epitaxial islands is therefore limited to acceptable levels. Upon completion of the two-step isolation oxide process, according to the invention, the epitaxial islands and isolation oxide regions are planarized according to standard procedures.
In forming the shallow trenches or grooves in - preparation for establishing ~he isolation oxide regions, the epitaxial silicon is preferably etched along the crystal planes~ for example the 54 crystal planes or axes. Etching Z7B3~1 fi~
~ 7 across the crystal planes or axes leaves an electrically active layer of active bonds lining the trench or groove.
Such active sites may cause defects in the epitaxial crystal layer which propagate into the epitaxial islands during growth of the thermal oxide. The active sites along the walls or sides of the epitaxial islands may also produce dead regions in the epitaxial islands. According to the present invention these difficulties are avoided by preferentially etching along the crystal planes or axes.
10 The thin thermal oxide layer may also help to passivate any active sites on the walls of the V trenches or grooves.
While the sloping sides or walls 28 of the shallow grooves or V trenches are shown in the diagrarmnatic view of Figure l, the walls or sides of the isolation oxide regions 15 30 are simplified and shown diagrammatically as vertical sides or walls in the subsequent Figures 2 through 9. This simplification or diagrammatic presentation is intended only for clarity of the illustrations keeping in mind the preferred plasma etch orientation along the crystal planes 20 or axes in establishing the isolation oxide regions.
Furthermore as shown in Figure 2 the isolation oxide region is comprised of two structural elements established . in a two step process namely the thin thermal oxide layer 32 grown from the thin layer 27 of epitaxial silicon and the 25 filler of deposited oxide 34 for example LTO or PECVD. In the subsequen~ Figures 3 through 9 however the isolation oxide region 30 is simplified and shown diagrammatically as a merged structure. In Figures 3 through 9 therefore the isolation oxide regions are designated by the single 30 reference numeral 30.
As shown in Figure 2, during the growth of the thin ther~al oxide layer 32 at high temperatures there is some up diffusion of the P+ region 14 and the N+ buried collector layer region 12 into the r~maining semiconductor material of 35 the epitaxial layer 18~ The P+ region 14 may be used for ' example to provide a ground contact location or ground substrate tap as hereafter described. On the other hand the P+ channel stop regions 15 and 16 encounter the thin thermal ~ J ~ ~7~3~
,.~/
oxide layer 32. ~s a result the thin thermal oxide layer 32 and P+ channel stop regions 15 and 16 meet substantially at the interfAce between ~he epitaxial layer 18 and substrate 10. During thermal growth of the thin oxide layer 32 the boron in the P~ channel stop region 14 updiffuses so that the ground substra~e taps become more conductive.
Updiffusion from the buried collector layer 12 into the active region of epitaxial island 25 is limited to acceptable levels.
Upon planarization of the epitaxial islands and isolation oxide regions using standard planarization methods such as plasma etch back of a photoresist layer, spaced apart collector sink regions and base regions are implanted in the active epitaxial islands 25. The collector sink 15 contact 35 is formed by an N+ implant, for example of arsenic ions, through the collector sink mask 36, using standard mask, etch and implant steps followed by an anneal step to drive the N~ dopant material of the collector sink contact 35 into the buried collector layer 12. As a result 20 the collector of a transistor to be formed on epitaxial island 25 includes of continuous low resistance or high conductivity semiconductor material. During the anneal step a thin oxide layer or screen oxidation layer may be grown over the exposed epi~axial layer silicon.
The base region 38 is formed by a P- implant through the base mask 40 using a standard photoresist mask, etch and implant sequence. The base region 38 is implanted through the thin oxide layer. At the same time the base mask 40 is formed with openings for implanting the ground substrate 30 taps or contacts 42 with a P- implant. Thus, the base mask 40 provides a P- concentration implant of boron wherever contacts to the substrate are to be made, in addition to base regions for transistors on active epitaxial islands 25.
During the sink implant, anneal, and base implant steps, 35 boron in the P+ channel stop region 14 diffuses upward in ` the ground contact or substrate tap region. The P~ up diffusion compensates for the high resistance N- epitaxial silicon and merges with the P- implant to form a ground , ~4 contact region of P+ to P low resistivity silicon shown as the continuous region between the P+ channel stop region 14 and the merged P ground tap or contact 42.
Following implant of the collector sink, base and S ground taps, a single polycrystalline or polysilicon layer 45 is formed over the integrated circuit structure of epitaxial islands and isolation oxide regions. The polysilicon is deposited at a temperature in the range of for example 600C forming small crystals randomly oriented.
10 The polycrystalline, polysilicon or poly layer 45 is deposited to a depth of approximately ~ ~ or 4,000-5,000 A
units. According to the invention the polysilicon layer 45 is then implanted with a blanket N- implant forming an N-polylayer and eliminating a subsequent masking step. A
15 blanket thermal oxide layer is then grown over the polysilicon layer 45 forming the protective polyoxide layer 46.
The blanket N- implant of the polysilicon layer 45 results in a high resistance layer to be used in subsequent 20 resistor components or elements of the integrated circuit structure as hereafter described. The blanket N- implant is therefore also referred to as a resistor implant.
Furthermore the blanket implant of the polysilicon layer 45 may alternatively be a P- implant, also providing a blanl~et 25 high resistance or resistor implant for use subsequently in resistor components and elements. For some applications of the blanket implant, which according to the invention avoids a conventional masking step the P- resistor implant is actually preferable to the N- implant. The blanket resistor 30 implant of polysilicon layer 45 is intended to provide a sheet resistance in the range of for example 750 ohms per square to 1,200 ohms per square. The subsequent polyoxide layer 46 is grown to a thickness sufficient to protect the resistor regions from later processing, a thickness in the 35 range of for example 1,500-2,500A units and typically 2,000A
units. - ~~
An N+ mask, etch and implant sequence forms low resistance high conductivity N+ regions in the polysilicon 7~3~3 layer 45 for defining collector contacts, emitter contacts, resistor contacts and low resistance interconnects or runs between contacts on the upper surface level polysilicon layer. The results of the N+ photoresist mask, oxide etch 5 and N~ implant sequence is shown in Figure 5. Following ~he N+ implant sequence ~ thermal oxide layer or cap 46 i9 gro~m over the polysilicon layer 45 followed by an anneal step.
While the N~ cap or dielectric layer 46 is typically an oxide grown over the polysilicon layer 45, a deposited oxide lOor nitride layer may also be used. After the polycrystalline layer is capped with a dielectric barrier layer, an emitter anneal step may be used for driving N~
dopant material into the P- base region 38 to form the N~
emitter region 48.
Portions of the polysilicon layer 45 to be retained and to be removed by masking and etching are defined by a polydefinition mask using the dielectric barrier layer or ` cap 46. By means of a mask and etch sequence the oxide layer 46 or other dielectric cap is etched over areas where 20the polycrystalline silicon material is to be removed. The patterned and etched oxide cap or other dielectric layer 46 provides the polydefinition mask and exposed portions of the polycrystalline layer are etched away. The portions of polysilicon layer 45 retained include the N- high resistance 25resistor region 50, N+ low resistance resistor contacts 52 and 54, N+ low resistance collector contact 56, low resistance interconnect 55 interconnecting the resistor contect 54 and collector contact 56, N~ low resistance emitter contact 58, and N+ low resistance polycrystalline 30islands 60 and 62. As hereafter described, the polycrystalline islands 60 and 62 provide N~ low resistance transfer contact locations on the upper level polycrystalline layer for transfer of the contacts for the base region 38 and ground substrate 14 to the upper surface 35level.
The polydefinition mask and etch sequence exposes on the lower surface level of the epitaxial layer 18 contact locations for the base region 38 of the transistor in active epitaxial island 25 and a ground contact for the ground substrate tap 14. Thus as shown in Figure 6 the exposed contacts for the ground substrate tap 14 and base region 38 are on the lower surface level monosilicon epitaxial layer 18 whil the collector, emitter, resistor and interconnect contacts are on the upper surface level polycrystalline l~yer 45. Furthermore, the polycrystalline islands 60 and 62 and the transfer contact locations provided by the poly islands 60 and 62 are also on the upper surface level. ThP
10 polydefinition mask and etch sequence further establishes step locations between contact sites or locations on the two levels all as shown in Figure 6. The polycrystalline islands 60 and 62 and the upper surface level transfer contact locations of polycrystalline islands 60 and 62 are 15 strategically defined and positioned adjacent to the lower surface level contact sites or contact locations for the base re~ion 38 and ground substrate tap 14 for subsequent transfer of these contact locations from the lower surface level to the upper surface level over the intermediate and 20 adjacent step locations all as hereafter described.
Following the polydefinition etch, the oxide cap or layer 46 is supplemented ~ith oxide layers 64 providing an ~, etch stop layer over all of the exposed silicon. The etch stop oxide layers 46 and 64 are selected to be of different 25 material from the blanket conformal spacer layer 65. This spacer layer 65 is then deposited with substantially uniform thickness over the entire integrated circuit structure including the different surface levels of the monosilicon epitaxial layer 18, the polycrystalline layer 45, and the 30 step locations between the levels.
The blanket conformal spacer layer 65 is typically a nitride layer deposited for example by plasma enhanced chemical vapor deposition while ~he etch stop layer 46 and 64 is an oxide layer. Alternatively, the blanket spacer 35 layer 65 may comprise low temperature oxide deposited over the integrated circuit structure with an etch stop layer 46, 64 of different ma~erial such as for example an etch stop nitride layer. In the preferred example of an etch stop ,~
oxide layer 46, 64 and a PECVD blanket spacer layer, the etch stop oxide layer 46, 64 may be a thin layer of low temperature oxide or a light ~hermal oxide layer. A light thermal oxide layer covers all the exposed polysilicon and 5 monosilicon areas, both contact areas on the top and side walls. The light thermal oxide layer is grown to a thickness of for example 750A units over the exposed monosilicon layer contacts forming the etch stop layer 64 while the previously formed oxide cap or layer 46 is lOenhanced also forming an etch stop oxide layer.
The blanket PECVD nitride layer 65 having a spacer layer thickness of for example 4,000-5,000A units is then etched using an anisotropic unidirectional plasma etch in the downward direction to the etch stop oxide layer 46, 64 15and the isolation oxide regions 30. The maskless unidirectional etch leaves portions of the dielectric blanket spacer layer 65 in the configuration of shoulders 66 ` at the step locations between the retained portions of the polysilicon layer 45 and the epitaxial monosilicon layer 18.
20As a result the adjacent contact locations on the polysilicon upper level and monosilicon lower level are dielectrically isolated and separated with minimum spacing ~,. between the contact locations.
The width of the shoulders 66 is typically for 25example 4,000-5,000A units. The width of the shoulders 66 may be controlled by the thickness of the spacer layer 65 affording a wide range of available spacings for example for the base to emitter spacing of the emitter contact 58 and the contact to the base region 38.
The etch stop layer 46, 64 is removed in an etch stop dip leaving the exposed monosilicon and polysilicon contacts on the lower level epitaxial monosilicon layer 18 and upper level polysilicon layer 45 as shown in Figure 7. The bare or exposed dielectric nitride shoulders 66 separate and 35isolate the exposed contacts at the two levels and avoid the much greater spacing requirements and registration problems of marking and photolithography. The transistor size and base resistance are reduced enhancing the density of the integrated circuit structure.
A feature and advantage of the present invention and process over conventional advanced single polysilicon layer 5 emitter couple technology is that not all contacts must be made through the polysilicon layer 45. As a result the number of mask, etch, and implant sequences is reduced.
Accordin~ to the standard advanced single poly emitter contact technology, no electrical contact locations are lOallowed at the lower level epitaxial monosilicon layer and all contacts must be made through the polysilicon layer to the first metal layer. According to the present invention the contacts for elements or components of the integrated circuit structure are exposed at both the upper level lSpolysilicon layer 45 and the lower level epitaxial monosilicon layer 18 separated by the dielectric spacer shoulders 66 of the present invention. As hereafter described, the shoulders 66 afford a new method and arrangement for constituting all electrical contact 20locations at the upper level or polysilicon layer.
A refractory metal such as titanium is then applied by sputtering over the entire surface of the integrated circuit structure including the exposed poly contac~s on the upper surface level polysilicon layer and the exposed monosilicon 25contacts on the lower level epitaxial layer 18. The titanium or other refractory metal then reacts with the exposed silicon both the polysilicon and monosilicon, in a rapid thermal anneal based sintering process. The sintering reaction is accomplished in a small chamber for example with 30a ocused heat source which heats the wafer to approximately a thousand degrees in seconds for a short reaction time.
The titanium sinters or reacts with the silicon to form a silicide (TiSi2) conductive layer over the contact locations as shown in Figure 8.
For further processing with contact locations at the two separate levels the unreacted titanium over the dielectric surfaces is stripped leaving the isolated and separated low resistance contact locations with minimum ; ` G~ 3~ ¢JI~

2~
spacing requirements. As ~hown in Figure 8, the contact locations include the resistor contact locations 5Z and 5~, the collector contact location 56 and the interconnect 55 electrically coupling the resistor contact 54 and collector contact 56. The upper level contact locations also include the emitter contact location 58. The lower contact locations include the base contact location 68 and the ground contact location 70. All of the contact locations are covered with the low resis~ance silicide layer 10 designated in Figure 8 by the heavier lines TiSi2.
According to the present invention however all contact b~ locations are constituted on the upper surface level for further processing. Unlike the conventional advanced single poly layer emitter coupled technology, electrical contact to 15 the lower surface level monosilicon layer 18 is not made through the polysilicon layer 45. Rather all electrical contacts are constituted on the upper surface level by the novel process and structure illustrated in Figures 8 and 9.
According to the invention polysilicon islands 60 and 62 are 20 retained from the polysilicon layer 45 as heretofor described and the layer of titanium or other refractory metal is sintered on the upper surface to provide transfer contact locations 72 and 74 adjacent to the lower surface level base contact location 68 and ground contact location 25 70. In further accordance with the invention the remaining unreacted titanium is selectively masked and stripped from the surfaces of the integrated circuit structure removing unreac~ed refractory metal be~ween contact locations to be isolated and separated such as the emitter contact location 30 58 and the base contact location 68. On the other hand the refractory metal such as titanium is retained by the mask between contact locations on the lower surface level and transfer contact locations on the upper surface level provided by adjacent polysilicon islands.
Thus referring to Figure 8, an unreacted refractory : metal strip or bridge such as titanium strip or bridge 75 i5 retained over the spacer shoulder 66 between the base contact location 68 on the lower surface level epitaxial ~ a monosilicon layer 18 and the transfer contact location 72 on polysilicon island 60 of the upper level polysilicon layer 45. Re~erence is also made to Figures 10 and 10A ~or a detailed plan view and side cross sectior. of t~liS
5 frag~entary portion of Figu-re 8. Similarly an unreacted refractory metal strip or bridge and in particular titanium strip or bridge 76 is re~ai~ed on shoulder 66 at the step location ~etween ground contact 70 on the lower level monosilicon epitaxial layer 18 and the transfer contact 10 location 74 on polysilicon island 62 of the upper level polycrystalline layer 45. As a result, all silicon contact locations of the integrated circuit structure are transferred or constituted on the upper surface or upper level polycrystalline silicon layer 45 for subsequent 15 processing according to isoplanar methods. The titanium strips 75 and 76 are designated in Figures 8 and 9 ~y the intermediate weight lines Ti.
According to the invention a bridge mask or refractory metal mask is used to retain conductive metal strips or 20 bridges over the spacer shoulders 66 at step locations between monosilicon contact locations and polysilicon transfer contact locations bringing all contacts up to the same level for final metal contact masking. The titanium bridges, straps or strips are only required for transfer 25 from lower surface level monosilicon contacts to adjacent transfer contact locations on the polycrystalline islands.
Once the electrical contacts are transferred or constituted on the poly level, the silicide layer over the polycrystalline interconnects may be used for conductors 30 between elements or components of the upper level polycrystalline layer. Thus poly interconnects are previously laid out an~ retained during the poly definition mask such as for example the poly interconnect 55 interconnecting the resistor contact 54 o~ collector resistor 50 with the collector contact 56 of transistor collector 35, part of the active epitaxial island 25 and epitaxial layer 18. As shown in Figure 10, the titanium runs or bridges 75 are relatively short and wide within the ~q space constraints and depending upon the current to the carried to minimize resistance. Other refractory metals may also be used for the conductive bridges, strips or straps such as molybdenum or tungsten.
Finally a planarized dielectric layer 80 is formed over the entire integrated circuit structure followed by a mask and etch for electrical contacts to be made at the collector C, emitter E, base B, and ground GND connections as shown in Figure 9. An equivalent circuit of this portion of the 10 final integrated circuit structure of Figure 9 is illustrated in Figure 9A with corresponding elements designated by the same reference numerals and letters. The Schottky diode 82 between the base region 38 and collector region 35 results from the intermediate N- silicon region 82 15 as shown in Figure 9. The ground contact substrate tap of Figure 9 separate from the active epitaxial island 26 is not shown in the equivalent circuit diagram of Figure 9A.
` While the invention has been described with reference with particular example embodiments it is intended to cover 20 all variations and equivalence within the scope of the following claims.

Claims (11)

1. An enhanced density single polycrystalline layer semiconductor process for fabricating a bipolar modified isoplanar integrated circuit structure having a substrate of semiconductor material of first conductivity type, an epitaxial layer of semiconductor material of second conductivity type deposited over the substrate, said epitaxial layer being subdivided into a plurality of epitaxial islands, pedestals, or mesas, with isolation oxide regions surrounding and isolating the epitaxial islands, said isolation oxide regions being substantially coplanar with the epitaxial islands, base regions of semiconductor material of first conductivity type formed in the epitaxial islands spaced from the collector sink regions, and a polycrystalline layer of semiconductor material deposited over the substantially isoplanar epitaxial islands and isolation oxide regions, the method for defining and completing transistor and resistor elements in the integrated circuit structure comprising:
blanket implanting the polycrystalline layer with dopant material forming polycrystalline layer of semiconductor material of high resistance across the integrated circuit structure;
growing a blanket polyoxide layer over the polycrystalline layer;
defining emitter, collector, and resistor contact locations by masking and etching the polyoxide layer thereby forming an emitter, collector, and resistor contacts implant mask;
implanting through the emitter, collector, and resistor contacts mask formed by the polyoxide layer into the polycrystalline layer with dopant material forming emitter, collector, and resistor contact locations of semiconductor material of low resistance in the polycrystalline layer;
capping the polycrystalline layer with a dielectric barrier layer;

defining areas of the polycrystalline layer to be retained and to be removed, by masking and etching the dielectric barrier layer thereby forming a poly-definition mask;
etching away exposed portions of the polycrystalline layer through the poly-definition mask leaving polycrystalline layer resistor regions of high resistance and polycrystalline layer emitter, collector, and resistor contact locations of low resistance while exposing base region contact locations and ground contact locations on the epitaxial layer, said epitaxial layer forming a first or lower surface level of electrical contact locations including base region contact locations and ground contact locations, said polycrystalline layer forming a second or upper surface level of electrical contact locations including the emitter, collector, and resistor region contact locations, with step locations between the lower and upper surface levels;
forming an etch stop layer over exposed contact locations on the lower and upper surface levels;
depositing a blanket conformal spacer layer of dielectrical material of substantially uniform thickness over the integrated circuit structure including the lower and upper surface levels and the step locations between the levels; and anisotropically etching the spacer layer in the direction orthogonal to the surface levels of the integrated circuit structure using a blanket unidirectional anisotropic etch, etching to the etch stop layer over the contact locations on the lower and upper surface levels, and leaving spacer shoulders of dielectric material from the spacer layer at the step locations between surface levels thereby dielectrically isolating and separating contact locations on the two surface levels adjacent to the step locations.

2. The process of Claim 1 further comprising the step of annealing after implanting through the emitter, collector, and resistor contacts implant mask and after capping the polycrystalline layer with a dielectric barrier layer thereby driving dopant material and forming emitter regions in the base regions of the epitaxial islands.

3. The process of Claim 1 wherein the step of forming an emitter, collector, and resistor contacts implant mask includes defining interconnects for interconnecting elements with runs of low resistance semiconductor material; wherein the step of implanting through the implant mask includes forming interconnect regions of polycrystalline semiconductor material of low resistance; and wherein the steps of forming the poly-definition mask and etching away portions of the polycrystalline layer leave low resistance polycrystalline semiconductor material interconnects in the polycrystalline layer.

4. A method for fabricating a bipolar modified isoplanar integrated circuit structure including a substrate of semiconductor material of first conductivity type, an epitaxial layer of semiconductor material of second conductivity type deposited over the substrate and buffer or protective dielectric layers formed overlying the epitaxial layer, comprising:
defining the isolation oxide regions by masking and etching the overlying dielectric layers forming an isolation oxide mask;
etching the epitaxial layer through the isolation oxide mask to a level above the interface between the epitaxial layer and substrate leaving a thin layer of epitaxial semiconductor material lining the isolation oxide regions between epitaxial islands;
filling the isolation oxide regions in a two step process by growing a thin thermal isolation oxide layer at elevated temperatures from the thin layer of epitaxial semiconductor material thereby limiting encroachment of thermal isolation oxide into the epitaxial islands, and depositing low temperautre isolation oxide over the thin thermal isolation oxide layer;

forming collector sink regions of semiconductor material of second conductivity type in the epitaxial islands;
forming base regions of semiconductor material of semiconductor material of first conductivity type in the epitaxial islands spaced from the collector sink regions;
depositing a polycrystalline layer of semiconductor material over the substantially isoplanar epitaxial islands and isolation oxide regions;
blanket implanting the polycrystalline layer with a dopant material forming polycrystalline layer of semiconductor material of high resistance across the integrated circuit structure;
growing a blanket polyoxide layer over the polycrystalline layer;
defining emitter, collector, and resistor contact locations by masking and etching the polyoxide layer thereby forming an emitter, collector, and resistor contacts implant mask;
implanting through the emitter, collector, and resistor contacts implant mask formed by the polyoxide layer into the polycrystalline layer with dopant material forming emitter, collector, and resistor contact locations of semiconductor material of low resistance in the polycrystalline layer;
capping the polycrystalline layer with a dielectric barrier layer;
defining areas of the polycrystalline layer to be retained and to be removed by masking and etching the dielectric barrier layer thereby forming a poly-definition mask;
etching away exposed portions of the polycrystalline layer through the poly-definition mask leaving resistor regions of high resistance and emitter, collector, and resistor contact locations of low resistance, said etching away of exposed portions of the polycrystalline layer exposing base region contact locations and ground contact locations on a lower surface level formed by the epitaxial layer, with said emitter, collector, and resistor contact locations being on an upper surface level formed by the polycrystalline layer;
forming an etch stop layer over exposed semiconductor material contact locations on the lower and upper surface levels;
depositing a blanket conformal spacer layer of dielectric material of substantially uniform thickness over the integrated circuit structure including the lower and upper surface levels, and step locations between the levels;
anisotropically etching the spacer layer in the direction orthogonal to the surface levels of the integrated circuit structure using a blanket unidirectional anisotropic etch, etching to the etch stop layer over the semiconductor material contact locations at the lower and upper surface levels, and leaving spacer shoulders of dielectric material from the spacer layer at the step locations between surface levels thereby dielectrically isolating and separating contact locations on the two levels adjacent to the step locations with minimum spacing between the contact locations.

5. The method of Claim 4 further comprising the steps of:
removing the etch stop layer thereby exposing the contact locations at the lower and upper surface levels;
sputtering a layer of refractory metal reactive with the semiconductor material of the contact locations over the lower and upper surface levels;
sintering and reacting the layer of refractory metal with the semiconductor material forming a low resistance silicide layer over the contact locations on the lower and upper surface levels; and stripping unreacted refractory metal from spacer shoulders between contact locations to be isolated and separated thereby leaving isolated and separated low resistance contact locations.

6. The method of Claim 4 wherein the step of defining areas of the polycrystalline layer to be retained and to be removed includes defining polycrystalline islands to be retained for transfer contact locations adjacent to contact locations on the lower surface level, wherein the step of etching away exposed portions of the polycrystalline layer further leaves polycrystalline islands providing transfer contact locations at the upper surface level for electrical transfer of contact locations from the lower surface level epitaxial layer, the further steps after anisotropically etching the spacer layer comprising:
removing the etch stop layer thereby exposing the contact locations at the lower and upper surface levels;
forming a layer of refractory metal reactive with the semiconductor material of the contact locations over the lower and upper surface levels;
sintering and reacting the layer of refractory metal with the semiconductor material, forming a conductive silicide layer over the contact locations on the lower and upper surface levels; and selectively masking and etching the formed layer of refractory metal, removing unreacted refractory metal from spacer shoulders between contact locations to be isolated and separated and leaving conductive refractory metal strips or bridges between the silicide layer of contact locations on the lower surface level and transfer contact locations on the upper surface level provided by adjacent polycrystalline islands thereby constituting all contact locations for elements of the integrated surface structure on substantially the same upper surface level provided by the polycrystalline layer.

7. An enhanced density single polycrystalline layer semiconductor process for fabricating a bipolar modified isoplanar integrated circuit structure having a substrate of semiconductor material of first conductivity type, an epitaxial layer of semiconductor material of second conductivity type deposited over the substrate, said epitaxial layer being subdivided into a plurality of epitaxial islands, pedestals, or mesas, isolation oxide regions surrounding and isolating the epitaxial islands, said isolation oxide regions being substantially isoplanar with the epitaxial islands, collector sink regions of semiconductor material of second conductivity type formed in the epitaxial islands, base regions of semiconductor material of first conductivity type formed in the epitaxial islands spaced from the collector sink regions, and a polycrystalline layer or semiconductor material deposited over the substantially isoplanar epitaxial islands and isolation oxide regions, said polycrystalline layer being implanted to provide semiconductor material regions of high resistance and low resistance in the polycrystalline layer said polycrystalline layer being capped with a dielectric barrier layer, the method for defining and completing transistor, resistor and related circuit elements in the integrated circuit structure comprising:
defining areas of the polycrystalline layer to be retained and to be removed by masking and etching the dielectric barrier layer thereby forming a poly-definition mask;
etching away exposed portions of the polycrystalline layer through the poly-definition mask leaving polycrystalline layer resistor regions of semiconductor material of high resistance, polycrystalline islands, and emitter, collector, and resistor contact locations of semiconductor material of low resistance, said step of etching away exposed portions of the polycrystalline layer exposing base region contact locations and ground contact locations on a lower surface level formed by the epitaxial layer, said emitter, collector, and resistor contact locations comprising contact locations on the upper surface level formed by the polycrystalline layer, said polycrystalline islands providing transfer contact locations at the upper surface level for transferring contact locations from the lower surface level epitaxial layer;
forming an etch stop layer over exposed semiconductor material contact locations on the lower and upper levels;

depositing a blanket conformal spacer layer of dielectric material of substantially uniform thickness over the integrated circuit structure including the lower and upper surface levels, and the step locations between the levels;
anisotropically etching the spacer layer in the direction orthogonal to the surface levels of the integrated circuit structure using a blanket unidirectional anisotropic etch, etching to the etch stop layer over the semiconductor material contact locations of the lower and upper surface levels, and leaving spacer shoulders of dielectric material from the spacer layer at the step locations between surface levels thereby dielectrically isolating and separating contact locations on the two surface levels adjacent to the step locations with minimum spacing between the contact locations;
removing the etch stop layer thereby exposing the contact locations at the two surface levels;
forming a layer of refractory metal reactive with the semiconductor material over the lower and upper surface levels;
sintering and reacting the layer of refractory metal with exposed semiconductor material forming a low resistance layer over the exposed semiconductor material contact locations on the lower and upper levels, and a layer of unreacted refractory metal over dielectric surfaces; and selectively masking and stripping the sputtered layer of refractory metal, removing unreacted refractory metal from spacer shoulders between contact locations to be isolated and separated and leaving conductive metal strips or bridges over spacer shoulders between contact locations on the lower surface level and transfer contact locations on the upper surface level provided by adjacent polycrystalline islands thereby constituting all contact locations for elements of the integrated circuit structure on substantially the same upper surface level of the polycrystalline layer.

8. The method of Claim 7 further comprising the steps of forming a metal contact mask dielectric layer over the integrated surface structure and masking and etching said dielectric layer to form a metal contact mask for establishing metal layer contacts at the contact locations constituted on the upper surface level of the polycrystalline layer.

9. An enhanced density polycrystalline layer process for fabricating a bipolar modified isoplanar integrated circuit structure including resistor and transistor elements having contact locations on a lower surface level semiconductor material epitaxial layer, and contact locations on an upper surface level semiconductor material polycrystalline layer, with step locations between the upper and lower surface levels, the method for transferring contact locations from the lower surface level to the upper surface level comprising:
forming polycrystalline islands during fabrication of the integrated circuit structure adjacent to contact locations on the lower surface level;
exposing the contact locations on the lower and upper surface levels;
forming a layer of refractory metal reactive with the semiconductor material over the lower and upper surface levels;
sintering and reacting the layer of refractory metal with the semiconductor material at the contact locations forming a low resistance layer over the contact locations on the lower and upper surface levels; and selectively masking and stripping the formed layer of refractory metal removing unreacted refractory metal between contact locations to be isolated and separated and leaving conductive metal strips or bridges between contact locations on the lower surface level and transfer contact locations on the upper surface level provided by adjacent polycrystalline islands thereby constituting contact locations for elements of the integrated circuit structure from different levels on substantially the same upper surface level of the polycrystalline layer.

10. The process of Claim 9 comprising the further step of forming dielectric material spacer shoulders between adjacent contact locations at the step locations between lower and upper surface levels and leaving the conductive metal strips or bridges between contact locations on the lower surface level and transfer contact locations on the upper surface level over said spacer shoulders.

11. An enhanced density single polycrystalline layer bipolar modified isoplanar integrated circuit structure including resistor and transistor elements having contact locations on a lower surface level semiconductor material epitaxial layer, and contact locations on an upper surface level semiconductor material polycrystalline layer, with step locations between the lower and upper surface levels, the structural elements for transferring contact locations from the lower surface level to the upper surface level comprising:
polycrystalline islands formed adjacent to contact locations on the lower surface level for providing transfer contact locations on the upper surface level;
a low resistance layer formed over the lower and upper surface level contact locations;
spacer shoulders of dielectric material at step locations between the polycrystalline islands and contact locations of the lower surface level, and refractory metal strips or bridges over the spacer shoulders between the contact locations on the lower surface level and transfer contact locations on the upper surface level of adjacent polycrystalline islands whereby all contact locations for elements of the integrated circuit structure are constituted on substantially the same upper surface level of the polycrystalline layer.