CA1275700C - Method and apparatus for transceiving cryptographically encoded digital data - Google Patents

Abstract

METHOD AND APPARATUS FOR TRANSCEIVING
CRYPTOGRAPHICALLY ENCODED DIGITAL DATA

ABSTRACT OF THE DISCLOSURE

Method and apparatus are disclosed for transceiving digital control and cryptographically encoded data signals in a unique format. The format includes frame synchronization, cryptographic synchronization and selective signalling (addressing) information both in a preamble portion to an entire message and recurrently at regular intervals throughout a message of encrypted digital voice signals. This arrangement permits successful late entry and/or synchronization recovery (both frame and cryptographic synchronization recovery) in an addressable selective signalling type of private radio communication system even if such synchronization is never acquired from the preamble (e.g. because of a long radio transmission channel fade or the like) or in the event such synchronization is temporarily lost after the preamble has already occurred.

Description

~X~7~i7(~

45~R 466A

METHOD AND APPARATUS FOR TRANSCEIVING
CRYPTOGRAPHICALLY ENCODED DIGITAL DATA

This application is a divisiGn of Canadian Application Serial Mo. 494,791, filed November 7, 1985.
This in~ention relates to method and apparatus for tra~scei~ing digital signals. Although generally u able in any transmlssion media (e.g. wire li~es using modems), it finds especially ad~antageous application over a radio com~unication channel. I~ particular, it is re~ates to systems in which di~itized cryptographically encoded voice ~or other~ data signals as well as suita~le digital synchronization and/or other digital control signals are transmit~ed on the same communication channel with the digitized and encrypted voice data si~nals.
This application is related to other commonly a~signed Canadian applications claiming other in~entions contemplated for combined use in the comm~rcial embodiment of this invention: Canadian Application Serial No. 498,346, filed December 20, 1985, Szczutkowski et al, entitled "Cryptographic Digital Signal Transceiver L~ethod and Apparatus"; Canadian Application Serial No. 494,7 a 9, filed Novemher 7, 1985, Zlnser, entitled "Rybrid Subband Coder/Decoder Method and Apparatus"; and Canadian Application Serial No. 494,790, filed November 7, 1~85, Szczutkowski, entitle "~ethod and Apparatus for Efficient Digital Tim~ Delay Compensation in Compressed Bandwidth Signal Processing".
Transceiving digital control and message data signals over radio communication channels is already ~' well known in the art. For example, reference may be had to commonly-assigned U.S. Patent No. 4,02?,243, issued May 31, 1977 to Stackhousa et al which describes a form of digital message generator for a digitally controlled radio transmitter and receiver in a radio communication system. Provisions are made for acquiring bit synchronization as well as word synchronization (including the multiple transmission of address information .
in complemented and uncomplemented form) in each of a steady succession of digital command messages transmi~ted between radio station sites. A modem circuit capable of detecting a 2 out of 3 voted Barker code sync word for frame synchronization is included in the Stackhouse et al system.
Cryptographic encoding of digitized speech signals is also well known in the prior art. For example, the Data Encryption Standard (3ES) utilized in the presently preferred e~emplary embodiment of this invention is itself well known and more fully described in detail in the following printed publications:
"Federal Information Processing Standards"
Publication ~o. 46, Data Encryption Standard, U.S. Department of Commerce, NTIS, 5285 Port Royal Road, Springfield, Virginia 22161;
"Federal Standard 1027 GSA, TelecommunicatiOns, General Security Requirements for Equipment Using DES" available Erom NTIS or the U.S. Government Printlng Office; and "Federal Infor~ation Processing Standards Publication No. 81, DES Modes of Operation"
(the "output feedback mode" is utilized in the presently preferred embodiment of this invention), also available from NTIS or the U.S. Government Printing Office.

7~3V

_ 3 _ ~

Typically, as in ~ES, encoded digital voice signals are transmitted in blocks or "frames" of fixed size along with a progressively changing encryption "vector" which, when combined with appropriate secret "key" digital data, may be used to encode or decode digitized voice data (or any other type of digital data).
I~ is also known to provide automatic selective 5 ignalling within radio communiCatiOn networks of various types. Sometimes a separate "control5' channel is utilized for achieving the desired selective signalling functions (e.g. selection of available communication channels and selection of a desired subset of message recipients within the system).
However, for various reasons, in prior voice privacy systems utilizing digitized and cryptographically encoded voice data signals, truly automatic selective signalling capability is not believed to have been previously available. Nevertheless, it is highly desirable in many radio communication environments to have such selective signalling capability. For example, it may be very useful to selectively address one of plural repeaters that may be within range of a given transceiver which is generatin~ or relaying such an encrypted digital voice message.
It is also believed highly desirable to permit late entry and/or synchronization recovery tboth word and cryptographic synchronization recovery) in the context of a digital voice privacy radio communication system having true selective signalling capability.
As explained in Stackhouse et al, above-mentioned U.S~ Patent 4,027,243, a radio frequency communication channel is a relatively noisy and sometimes unreliable environment. Impulse noise, multipath interference and signal fadin~ are typical of the expected problems that must be successfully overcome.
The present invention utilizes a unique format ~ 7~7~ 45MR 466A
- 4 ~ ~

of conlrol and encoded voice digital signals which provides the above set forth desired features especially well in the contex~ of a radio frequency communication c~annel. I~ follows, of course, that the same unique format is also advantageous for any other less onerous type of communication channel such as~ for example, conventional telephone channels or wire lines (perhaps also using added conventional modems on each end of the channel).
Thes~ as well as other objects and advantages of this invention will be more completely understood and appreciated by reading the following detailed description of the presently preferred exemplary em~odiment of this invention in conjunction with the accompanying drawings, of which:
FIGURE 1 is a schematic block diagram of an exemplary microprocessor controlled radio transceiver in accordance with this invention;
FIGURE 2 is a schematic/graphic depiction of an exemplary preferred format or time sequence of the transmitted and/or received stream of digital signals in the exemplary embodiment of FIGURE l; and FIGURES 3-5 are simplified general flow bloc~
diaqrams of exemplary computer pro~rams that are embodied in the control program memory devices of the exemplary PIGURE 1 system embodiment for the purposes of sync maintenance, acquisition and late entry.
The transceiver of FIGURE 1 includes the usual radio frequency transmitter 10 and radio requency receiver 12 (or any other communication channel transmitter and receiver such as, for example, the transmit lines and receive lines of a conventional wire line modem). As indicated in FIGURE 1, the transceiver may be in communication with one or more repeaters or transceivers or base station(s) over a radio frequency or other form of communication channel. The clear~private 1~ ~57~ 45MR 466A

switches S1, s2 (typically realized as conventional solid state controlled MUX switches used to switch analog signals under control of digital switch signals) may be provided so that the transceiver can operate in a conven-tional "clear" mode or alternatively, in the cryptographicor "private" mode. For example, when the switches are in the "clear" mode as shown in FIGURE 1, the audio input coming from a microphone and to be transmitted is simply directly connected to transmitter 10 while the output of receiver 12 is directly connected to the usual receiver audio output circuit.
However, when switches Sl, S2 are moved to the "private" mode position, then the microprocessor controlled remainder of the FIGURE 1 clrcuitry is switched into operation between the usual receiver audio input~output circuits and the usual radio frequency transmitter/receiver circuits 10, 12. In particular, the micrnprocessor controlled circuitry will take conventional audio input signals (e.g. from a microphone or audio amplifier or the like) and convert those to a stream of cryptographically encoded digital signals input at switch Sl to the modulator of transmitter 10. On the receiving side, a stream of digital signals arrives via the detector outpu~ of receiver 12 and is ultimately decoded and con~erted into analog audio signals at the lower contact of switch S2 before being passed onto the usual receiver audio output circuits (e.g. audio amplifiers, loudspeakers, etcetera).
In the preferred embodiment, the detector output of receiver 12 is constantly connected to the "private" digital decoding circuits (as shown in FIGURE 1) so that the received signal can constantly be monitored. If a switch from "clear" to "private"
mode is unexpectedly effected at the transmitter (e.g.
initially or in the middle of an ongoing message), then the receiver "private" circuit will automatically begin ~ ~57~3 45MR 466A
- 6 ~ ~

the requisite decoding process an~ have decoded audio signals switched to the receiver audio output circuits automa~ically. This arrange~ent also make~ it possible for the receiving set to automatically switch itsel~ i~to t~e "private~' mode wherever incoming digital signals are succesæfully decoded and in fact, ~h~s is contemplated for the preferred embodiment.
me overall architecture of the microprocessor control circui~s sho~n in FIGURE 1 is generally conventional. In particular, the heart of the system is a control microprocessor 14 (e.g. an IntelT~ 8031 integrated circuit chip). co~munication with the remainder of the digital circuitry is via the usuaL data bus 16 and control bus 18. The usual push-to-talk (PTT~
switch 20 may ~e considered as one wire in the control bus 18 if desired. A manual clear/private mode switch used for selecting the mode of transmitted voice may also be one wire in the control bus 18 if desired. As should bs appreciated, there is no need for a manual receive clear/private mode switch when automatic receive mod~
switching is performed a~ explained above. The system may include a conventional codec 22 ~e.g. an IntelTM 2916 integrated circuit chip) and conven~ional speech coding circuits 24 in the form of a suitably pro~rammed Digital Signal Pracessor (DSP) (e.g. an NEC 7720 integrated circuit chip) for converting audio signals to/from digital-analog form in accordance with known speech digitization and processing algorithms.
In the preferred exemplary embodiment, a hybrid subband coding technique ig employed in accordance with the invention claimed in the relate~ aforementioned Canadian application of Zi~ser. There the audio frequency band 180-2900 ~z is split into four octaves with the highest frequency band 1450-2gO0 Hz being subject to conventional block companded pulse code modulation (BCPCM) and the lower three subbands ~eing subject ~o conventional ~ 757~0 45MR 466A

adaptive pulse code modulation ~APC~) digital bandwidth compression techni~ues. This plus the novel time delay com~ensation technique o~ ezczut~owski permit the speech coding to ~e carried ou~ using but a single DSP chip 24.
~owever, as should be understood, ~he use of such speech codi~g techni~ues is optional insofar as the presently claLmed in~e~tio~ is concerned. The no~el me~sage formst-ti~g employed in the present invention may be utilized with any desired type of digital speech encoding algoritk~
or with any type of digital data (e.g. A5CII, etc.).
The Data Encryption Standard is implemented via conventional DES circ~its 26 (e.g. an MC 6859 integrated circuit chipj ar.d a co~Yentional DFS key memory 28 (e.~.
64 byte~ of ~A~)~ Suitable conventional RO~ circuits 30 (e.g. 4 kilobytes) are also provided to physically embody the program control structure perti~ent to the ~r~sent inve~tion as indicated in FIGU~E l.
The tra~smit~receiYe interface circuits 32 are somet m~s referred to as "modem" circuLts and may also be of con~entional design. They preferably incLude bit restoration circuits of the type descriked in commDnly assi~ned U.S. Patent No. 4,382,2g8, issued ~ay 3, 1983 to ~vans. Although conYentional clock reco~ery and up~down counter circuits can be employed with this in~ention, it is pre~ently preferred to use the cloc~ reco~ery circuits described in the Canadian Application Serial No. 468,504, filed No~ember 23, 1984, Evans, and the up/down counter circuits descri~ed in the com~only assigned EYans U.S. Patent No. 4,611,337, issued Septem~er 9, 1~6. Reference may also be had to the aorementioned Stackhouse et al U.S. Patent No. 4,027,243 for digital transmit~recei~e mod~m interface circuits suitable for use with radio frequenCY
transmitters and recei~ers such as transmitter lO and recei~er 12 and for a hardwired Barker code sync w~rd detector. In the ereferred exemplary embodiment, the ~ ~5 7~ 45MR 466A

interface 32 may be placed in a "sync search" mode whereupon such a Bar~er code sync word detector is activated and which thereupon outputs a priority interrupt signal to control microprocessor l~ whenever such a sync word is detected.
A conYentional Gaussian Minim~m Shift Key (G~S~) filter 34 (e.g. a fourth order low pa~s Bessel filter havinq an about 7 kilohertz cut-off measured at the 3 dB pointsl is pre~erably included to procass the stream of digital output signals before they are pa~sed onto the modulator of transmit~er 10 as should be appreciated by those in the art.
The output of receiver 12 (e.g. from an fm discriminator~ ic also preferably passed through a conventional limiter circuit 36 to eliminate d.c. bias effects that otherwise might be present in the output of the receiver discriminator. For example, the limlter 36 may utilize a simple comparator to compare the instantaneous incoming signal from receiver 12 with a running averaged value over some previous relatively short inter~al as should also be appreciated by those in the art.
The transmit/receive interface 32 may, for example, on the transmit side comprise a con~entional parallel-to-serial shift register for generating a serial stream of digital binary signals to be transmitted.
On the receive side, the transmit/receive interface 32 may typically utilize a digital phase locked loop for achievinq bit synchronization and a hardwired correlator for recognizing a predetermined Bar~er Code which may be used for achieving word synchronization.
The preferred time sequence of digital signals being transmitted by transmitter 10 o~ received via receiver 12 is schematically depicted in FIGU~E 2.
This format or time sequence of digital signals is generated for transmission under program control of the ~7S7~0 _ g ~

microprocessor 14 and, in t~e receive mode, the control microprocessor 14 is also programmed (e.g. via ROM 30) so as to properly detect and decode the same time sequence or format of digital signals. This unique format permits initial and ongoing frame synchronization, repeater address-ing, cryptographic synchronization and selective signalling. All four types of information are repetitively transmit~ed in a relati~ely lon~ preamble portion for fade protection (e.g. the usual Raleigh fading which may be expected on radio frequency communication channels) and, in addition, all four types of inrormatiOn are repeatedly retransmitted at regular intervals within the encrypted voice data stream. Fade protecting the preamble by multiple repeats and/or other techniques provides a very high probability of correct initial synchronization and addressing functions. Repeating all four types of information within the voice data stream permits late entry (in the event that the preamblë is missed or unsuccessfully decoded) and/or permits recovery of synchronization (in the event that synchronization initi~lly acquired from the preamble is subsequently lost before the end of a given message occurs).
When the transceiver of FIGURE 1 is in the "private" mode and the PTT switch is activated, the 2S preamble portion of the format shown ir, FIGURE 2 is first transmitted so as to establish bit synchronization, word or frame synchronization, cryptographic synchronization and addressing (e.g. repeater and~or other selective signalling). Fade protection for deep fading (e.g. up to 45 milliseconds) is preferably provided by multiple repeats of a synchronization sequence as well as the initialization vector (IV) and selective signalling (SS) signals.
The initial "dotting" se~uence is merely an alternating 1,0 pattern of digital signals (e.g. 10101010...~ and is continued for a "transmitter 1~ 757~ 45MR 466A
-- 10 -- `
wake-up time" (e.g. 25 milliseconds~. During this initia}
~Idotting~ time, the receiver circuits can quickly obtaln bit synchronization. For example, con~entional hard~ired bit synchronization circuits might ~e utilized in the transmit~receive inter~ace 32 as previously descri~ed so as to automatically obtain and remain in bit synchroniza~ion with the inco~ing serial stream of digital signals. Those skilled in the art will appreciate th~t logic l's and 0Is may ba interchanged throughout this discussion since they refer only to two binary level~ and not to a rigid ~oltage polarity or magnitude.
The synchronization sequence next occurs for a time duration equal to the sum o~: (a~ the maximum expected fade duration, (b) the bit duration required to ensure 99% synchronization acquisition, and (c) the typical time required for repeater turn-on to occur. T~
exemplary synchronization seque~ce includes 12 repeats of 48 bit synchronization groups, each of which groups include~ a 16 bit synchronization word S (an 11 bit Barker code such as 11100010010 and 5 bits of fill or dotting), an 8 bit "outside address" (OA) repeated once in complemented form (which may alternatively comprise other internal data configurations such as a 5 bit repeater address repeated twice plus flller) to complete a second 16 bit field and a 5 bit sync num~er (SN) repeated three t~mes (with the second repeat being in complemented form) plus 1 final bit of odd parity code so as to complete the third 16 bit field in a given 48 ~it group. At 9600 baud, it requires approximately 60 mill~seconds ((4B x 12)/9600) to transmit all 576 bits of thQ synchronization saqu~nce in the preamble of FIGURE 2.
once a correct synchronization word S is decoded, the following OA and SN fields may be recognized ~y requiring that all the vec~ors within each field (2 in 3S the OA field and 3 in the SN field) match (i.e. taking into account the complemented form of adjacent repeated ..D ~ o r ~
1~ 7~ ~ 00 4 5MR 4 6 6A
-- 11 ~ `

vectors) to ensure proper frame synchronizatLon and/or that sufficlently error free reception is being enjoyed.
(Late ent~I is diiferentia~ed from preamble entry by th~
format of the OA fi~ld). T~e proper synchronization num~er S~ is reconstructed by voting 2 or 3 on the three 5 bit vector fields. Th~ synchronization number data 5N not only helps establish the current or instantaneous position within the synchronization sequence, it also helps ensure that the correc~ boundary is identified between the sync lQ sequence and the following IV and SS signal sequence as shown in FIGURE 2.
The IV and SS fields follow the synchronizat~on sequence in the preamble of FIGURE 2. This second control data sequence includes a 64 bit guard band (GB~, a 64 bit initialization vector (IV) and a 16 bit selecti~e signalling address (SS) repeated 9 times in the overall IV and SS
sequence of 1296 bits depicted in FIGURE 2. The 64 bit guard band GB pro~ides fade protection while the 64 bit field is used to establish cryptographic synchronization i~
accordance with the conventional D~S. Tha 16 bit selecti~e slqnalliny field SS provides group and individual selective signalling capability within a radio communication networ~.
The IV and SS sequence subsists for a time 2~ duration eallal to the sum of: (a) the time required for transmitting the initiali~ation vector IV, (b) the time required for selective signalling transmissions SS, and ~c) the degree of fade protection desired for the SS~I~
control data fields. In the exemplary embodLment, approximately 45 milliseconds of fade margin is provided in the I~ and SS sequence of 1296 bits.
The selective signalling vector SS may be used for selective calling of individuals or groups using the same DES cryptographic ~ey. Accordingly, truly selecti~e signalling capability is provided within a crypto-graphic communication network. The 16 bit SS field may 1~ 7 57~ 45MR 466A
-- 1 2 ~

represent~ for example, a user group with individual addresse5 therewithin so that users with the same cryptographic key nevertheless ha~e the ability to further subdi~ide their calls to subsets or individual transcei~ers S within their particular networ~. For example, the SS
field may also be enorypted to facilitate seleoti~e signalli~g within a group of users having ~he same DES key while providing no informa~ion to a user with a dif~erent key (or an evesdropper).
The guard band GB may be used for additional message or signalling capabilities if desired but, in the present exemplary em~odiment, it is merely filled with a do~ting pattern. 64 bits or dotting was chosen so as to pro~ide a fade margin of approximately 45 milliseconds.
The DE5 initialization vector IV conventionally contains 64 bits and is a pseudo-ra~domly generated initlalization vector used by the con~entional DES
encryption algorithm to initialize the cipher-stream generation.
A "five-of-nine" vote is utilized for analy2ing the 9 times repeated IV~SS data sequence. For example, at the recei~er each of the nine se~uential GB/IV/SS
data fields is voted bit-~y-bit on an at least fi~e-out-of-nine basis. The voted results are stored as used as the correct IV~SS vectors for cryptographic synchroni-ization and selectiYe signalling purposes.
The pream~le format of FIGURE 2 is chosen so as to provide a 99% probability of correct reception in a radio frequencY communication channel experiencing up to about 3% bit error rate (BER)~ In this analysis, fading is treated as a separate process and dealt with by inter-leavinq redundant data (or left "open" by using all li 5 or all 0's, any ar~itrary pattern or simply dotted guard bands~ along with repeated critical synchronizatiOn data as shown in FIGURE 2. For example, the FIGURE 2 format is designed so as to protect agains~ data losses ~ 757~0 45MR 466A

even thou~h up to a~out 45 miLliseconds of fading may occur on the radio fre~uency communication channel. The probability or correct reception for the required information is the~ the product o~ the pro~a~ilities of the S individual fields.
Thus if Pch is the pro~ability of the correct preamble reception, then Pch = (Pcs ~ Pcoa * Pcsn) *Pcss *Pciv ~Equation l]
where, Pcs is the probability of correct sync S
reception;
Pcoa is the pro~ability of correct OA receptio~:
Pcsn is ~he probability o~ correct sync number SN reception;
Pcss is the probability of correct seLective signalling SS address reception; and ~civ is the probability of correct initialization vector I~ reception.
Assumin~ a 3~ BER and the FIGURE 2 format:
(a~ for a repeater receiver or a mobile receiver;
Pcs * Pcoa * Pcsn = O.98964 [Equation 2 (b) for a mo~ile receiver (the repeater may not require IV and SS);
Pcss * Pciv = 0.99978 ~Equation 3]
(c) for the repeater, proba~ility o~ correct ac~uisition is Pcra - 0.98964 tEquation 4]
(d) for a mabile, probability of correct reception of the preamble is Pcma = 0.98964 * 0.99978 ~Equation 5]
Pcma = O.98845 [Equation 6l The format of FIGURE 2 typically provides;
- Initial entry time of about 250 msecS, - Rentry (in case of temporary sync loss), - Late entry capability 1.~ 7 57U0 4 5~ 4 6 6A

- Proba~ility of correct d~tection of he~e:r ~ 99% at a Ch21~rlSlQl BB o~ 3%, - Protae:tion a~ f ad~ of up to about SO m:squ::~ duration, - Fals~ rate of le~2~ th2~ about o~
p~r w~c~
TI~Q outp~t fe~db~c~ modq~ of op~ration Or t~ DES
algorithm rQ~ir~ t~.t a 64-bi~ v~ctor ~c~ t~anE~mi~ ~t l~t once p~ T aC~iYa~ion. I~ tha pre~rred 10 e~o~liment, ~Q 64 bit ~ç~ctor is t~tt2d onc~ p~
fr~ma to allo~ for re-entry or late entry. T~is ~r~stor is dif~erene for each trans~ission there~y cans~ituti~g 1 ou~
o~ 264 po~ible vectors. The vector is ca~led an i~itia~ization vector or I~.
The reconstruct ~ SS and rv v~ters are thæ
result of vot ~g at le~o~ 5-of-~ on t~ aYailabl~ gxo~p of 9 vectors as p~e~iously d~scribed. T~e proce~s o~ vot~g at least 5-out-of-9 o~ th~ inco~ing data stream haE th~
Q~ect of improving the ef~ect~Y~ bit error rate ( B 3 o~
~he chnnnel. For a gi~en channQl ersor rate Pe, th~
pro~ability of correct reception where the p~o~abil~ty of correct IV and SS reception Pci~*Pcss can be calculat~d aQ
Pcss*Pciv = ~ pe)k (l-Pe)9~~ ] 80 k~S
2S For Pe = .03 (3~ BER), t~en Pci~*Pcss wo~k- out aa .9~978 or 99.9B% pro~abili~y o~ co~rect reception.
CorrQct sync S (11 bit Barker code) re¢option is ensured ~y rep~ating th~ 11 bits of thQ ~arker cod with a 5 ~it fill co~tinuou~ly ovar a finite p~riod. Tnl~ ti~R
wa~ chosen as the su~ o~ thR worst casQ (expected~ fadQ
dura~ion and the time taken to repeat the sync patt~rn so that th~ probability of correct reception is at le~Bt g9%
at a 3% BER.

1~ 757~ 45MR 466A
15--`

The proba~ility that 2~ bits will ~e correct at a 3~ sER, is simply (1-0.03) or .439, i.e. the proba~ility that the sync is corrupted is (1~0.439) or .56 Thus the probability that the s~nc is corrupted n times in a row is ~0.561)n or the probability of correct sync under these conditions is 1-(0.561)n. This is required to ~e at least 0.99 in the exemplary em~odiment. The value of n satisfying the ahove equation is at least 8 (12 is used in the exemplary embodiment and is thus more than ample~. The prsbability or correct sync S and OA
is 0.~9902.
The probability of correct preamble reception under these conaitions is Pch = Pcs ~ Pcsiv = 0.99902 *
O.99~0.99978 = O.9~99 = ~_O.99.
Followinq the preamble shown in.FIGURE 2 are successive data frames, each of which includes a 112 bit header portion and 2040 ~its o f encrypted voice data.
The header includes a single repeat of the.sync word 5, the outside address OA, the initialization vector IV and the selective signalling address SS. No sync count number S~
is provided nor are multiple xepeats provided in an attempt to keep the overall data fr3me le~qth as low as possible (e.g. on the order of 225 milliseconds) and~or to keep the re~uired data processing overhead to a minimum during the time it is necessary to also decode and otherwise process the incoming encrypted voice data Nevertheless, by inserting such a header into each data frame, enou~h informatian is regularly provided so as to allow for late entry into an ongoing megsaqe or conversation and~or so as to reestablish lost frame or cryptographic synchronization (e.g. as might occur from temporary loss of signal or multiple transmitting conditions or the like on a typical radio frequency communication channel). A synchronization maintenance control function in the receiver may thus monitor the ongoing received data frame header. It may permit a 1~ 757~0 45MR 466A

certain amoun~ of "free wheeling" even i a bad header is sometimes detec~ed since the critical crypto~raphic initialization vec~or I~ can be predicted from the previously received (corre~t) IV. Once cryptographic synchxonization has been completely 105t, the pre~erred e~emplary embodLment requires two valid received IV's (in consecuti~e data frames) to be dete~ted ~eore proper cryptographic synchronizatio~ is resumed.
As also depicted in FIGURE 2, an end of message (EOM) signal is transmitted at the end of a message transmission ~.g. upon release of the P~ switch 20).
The EO~ signal is continued for abou~ 50 milliseconds in the e~emplary emnodiment so as to allow for relatively long fades in the received signal while still ensuring that the EOM is properly decoded.
In the format of ~IGU~E 2, the syn~ word S
should preferably preceed the other associated fields te.~. OA, IV, SS) so as to permit fxame sync acquisition before the other fields are to be detected. ~owever, the exact order of the remaining OA, IV, SS fields ls ~ssentially a matter of choice.
Those skilled in the art should be able to readily devise transmission control programs for the microprocessor 14 re~uired to assemble and transmit data streams in accordance with the time sequences depicted in FIGURE Z. ~owever, since the reception processinq control is somewhat more involved, an exemplary embodiment of suitable computer proyram subroutines is presented in FIGURES 3-5 for causing the micro-processor control system of FIGURE 1 to properly receiveand decode the time sequence of digital signals depictea in FIGURE 2.
The receive control functions required by the digital siqnal format of FIGURE 2 may be divided into two major functional computer program subroutines: (a) a synchronization acquisition subroutine as shown in ~ 7S70~ 45MR 466A

FIGU~E 3, an~ (b) a synchronization maintenance suhrout~e as shown in FIGURE 4. A lower leveL "late entry" subroutL~e shown in FIGURE S is ut~lized in conjun~tion with the other pro~rams of FIGU~ES 3 and 4 so as to permit successful late entry into an ongoing co~ersation.
A repeated hard~wired tes~ is made for presenc~
o~ the 11 bit Barker code synchroniz~tion word S in the transmit~receive in~erface 32 irrespecti~e of the private/
clear mode status thus enabling automatlc reception of either DE5 enco~ed digi~al voice or normal analoy voice tr nsmissions. Then, whenever decoded voice is present, the control microprocessor 14 itself auto~atlcally switches 52 into a "private" receive mode. A suitable visual or other indicator o~ this automatically deri~ed "pri~ate" mode may also be acti~ated by the control microprocessor. (If de~ired, the transmit portion of switches S2, S2 may also be autamatically switched to the "pri~ate" mode in readiness for any return transmission.) A will be recalled, the transmit/recei~e interface 32 o~
PIGU~E 1 is preferably hardwired so as to automatically recognize the appropriate Bar~er code word and to generate an appropriate priority interrupt signal for the microprocessor 14 which then abruptly switches con~rol to entry point 100 of the s~nc acquisition subrout~ne.
Alternati~ely, the transmlt/receive interface 32 may pro~ide a sLmple m?~lti-bit register throug~ which the incoming bit stream passes and which is periodically sampled hy mioroprocessor 14 at block 102. I~ the proper Barker code word is not yet received, then the incoming bit stream may be advanced by one or more bits in the interface buffer at 104 and another test made for the proper Barker code at 102. In the preferred exemplary em~odiment, the te~t at 102 should always simply confirm that a proper ~arker code sync word is present --since that is the condition upon which control is passed to ~'75~

entry point 100. If not, then the interface 32 is replaced in its sync search mode and control of microprocessor 14 is passed back to higher level programs until the next priority interrupt is produc~d by interface 32 signifying that another proper sync word S has been detected. As should be appreciated, the interface 32 is prefQrably wired to inhibit generation of any subsequent priority interrup until it is again placed in a sync search mode. Oth~rwise, a priority interrupt would always be generated whenever an incoming S word occurs. It should also be recalled that bit synchronization is typically handled by conventional fixed hardware in the transmit~receive interface 32.
When a correct Barker Code synchronization word S
has been detected at 102, control passes to 106 where a check is made for a proper outside address OA. In other words, is the OA correct for the particular transceiver site in question? If not, then control is passed to wait loop block 108 where microprocessor 14 now waits for the next sync word S which is tested against at 102.
If both a valid synchronization word S and valid outside address OA are detected at bloc~cs 102 and 106, then a test is made at 110 to determine whether the S and OA
data just received comes from the preamble of FIGURE 2 or from a data frame header which, in the latter case, would indicate that a late entry is being attempted to an ongoing message. As explained earlier, the OA field includes two 8-bit vectors. In the preamblel the second vector is the logical complement of the first vector. However, in the data frame header the second vector i5 merely a straight forward repeat of the first vector.
Accordingly, a test may be made at bloc]c 110 to see whether the second vector in the just received OA
field is inverted. If it is, then exit is made to the late entry subroutine of FIGURE 5 as indicated. If not, then a normal sync acquisition from the preamble is ~;~75~

- 19 - 45M~ 466A

indicated and control is passed onto block 112 where a test is made to determine if the synchronization number SN
is a valid number (e.g. do the three 5-bit ~ectors and odd parity cod~ bit check out with respect to one another and, if so, is the indicated sync number less than or equal to 12?). If the sync number SN is not valid, then exit is taker. via wait loop 114 back to block 102 to wait for the next valid Barker code synchronization word S.
However, if a valid synchronization number SN is detected at 112, then control is passed to block 116 where the data field boundaries within the preamble are now established (e.g. because one now knows which one is the 12 repeated S/OA/SN fields has just been successfully detected and where it is located in the interface buffer register). The nine repeated GB/IV/SS fields in the IV
and SS seq~ence of the preamble are then received and a vote is taken among the nine repeats of the IV and SS data fields. In the exemplary embodiment, a simple majority vote (e.g. at least 5 out of 9) is taken on a bit-by-bit basis to determine the final IV and SS field values for later usage by microprocessor 14.
Aft~er the voted SS field is available, control is next passed to block 118 where the SS field is tested to make sure that it is correct for this particular transceiver/site. If not, then exit may e taken via block 120 where the receiving modem in interface 32 is again placed in the sync search mode where a search is undertaken for the next correct Barker code word.
Finally, if the entire sync acquisition subroutine of FIGURE 3 has been successfully completed, then exit from block 118 will be made to begin actually decoding the data frames which follow so as to drive the receiver audio output circuits. However, since the first portion of each data frame in the exemplary embodiment is a header portion which repeats the S/OA/IV/SS fields, exit from the FIGURE 3 subroutine may, if desired, simply 57()0 be taken to the synchronization maintenance subroutine of FIGURE 4 where control of the microprocessor 14 normally resides anyway during the ongoing receipt of a succession of data frames.
Upon entry to the sync maintenance subrou~ine of FIG~RE 4 at block 200, control is passed to block 202 where the IV and SS fields from the currently received data frame header are read in~o a buf~er register and the just received cryptographic initialization vector IV is compared to the predicted next IVo As will be appreciated by those in the art, the conventional DES algorithm permits one to predict the next I~ based upon the previous IV. For the very first data ~rame, the IV in the header should be the same as the IV already received and voted upon from the preamble. Thus, so as to accommodate the first data frame, an initial housekeeping operation might be performed (e.g. back in the sync acquisition subroutine so as to initially set the predic~ed next IV to be equal to the voted upon preamble IV).
Additionally, block 202 may include a test for the end of message character EOM since this would be a con~enient place to make such detection. If detected, then the interface 32 may again be placed in the sync search mode ant~ control of microprocessor 14 passed back to higher level programs.
The actual comparison of the currently received IV with the predicted next IV is depicted at block 204 in FIGURE 4. If the two do not match, then an IV loss is indicated and control is passed to block 206 where a test is made to see if a late entry flag has previously been set (by the late entry subroutine of FIGURE 5 to be discussed later). If the late entry flag was set, then exit is taken to block 20~ whEre the current received IV
is used to derive a predicted next IV and control is passed back to block 202.
on the other hand, if the late entry flag was 75~

not set, then control is passed from block 206 to block 210 where a "loss of IV" counter is incremented. The counter contents is then tested at 212 to see if it is less than or equ~l to some desired maximum. In the exemplary embodiment, the maximum may be set at a value up to 10. If the "loss of IV" counter has not yet exceeded the maximum permitted contents, then exit is made to block 214 where the currently received encrypted voice data field is decoded using conventional DE5 algorithms. The decoded results are then conventionally also passed on to codec 22 which drives the analog receiver audio output circuits as should now be appreciated by those in the art and control is passed back to block 202 of the sync maintenance subroutine for processing the next data frame of the incoming message.
If the "loss of IV" counter exceeds the maximum permitted value as tested at block 212, then this indicates a loss of sync and, as a result, the interface 32 is again placed in its sync search mode and control is passed back to higher level programs as indicated by block 216.
Under normal circumstances, when there is no IV
loss as tested at block 204, then control is passed to block 218 where a test is made on the late entry flag. If the late entry flag has not been set, then control is passed directly to block 220 ~here the "loss of IV"
counter is cleared (just in case it might have previously accumulated some content) and control is passed onto block 214 where the encrypted voice data field is decoded, etc.
as previously described. On the other hand, if the late entry flag was set as tested at block 218, then the late entry flag is reset at block 222 so as to indicate a good late entry sync acquisition. ~s should now be appreciated, during normal message reception times, control of microprocessor 14 repeatedly passes about the 35 loop comprising blocks 202, 204, 21~, 220 and 214.
If exit is made to the late entry subroutine 570C) from block 110 of FIGURE 3, then co~trol is passed to block 300 of FIGURE S where the I~ and SS fields are decoded and stored from the currently received data frame header. A
test is made at 302 to see if the SS field is correct for this particular ~ransceiver/suite. If not, then the interface 32 is again placed in its sync search mode and control is passed back to higher level programs as indicated by block 304.
On the other hand, if the SS field is detected as beiny correct at block 302, then the late entry flag is set at block 306 and the next initialization vector IV will then be iteratively predicted at block 308 in accordance with conventional DES algorithms and a wait loop maintained until the ne~t data frame time whereupon a return is made to the entry of the sync maintenance subroutine in FIGURE 4.
To summarize the control algorithm represented by the flowcharts of FIGURES 3-5, initial sync acquisition involves acquisition of the ll-bit Barker code to establish word synchronization. The hardwired interface circuits 32 detect the Bar~er code word and priority interrupt the microprocessor 14 whereupon control passes to the sync acquisition subroutine of FIGURE 3. The repeater address or outside address field OA and the other following fields are then subsequently acquired and temporarily held in a suitable ~uffer storage. The information thus held in the buffer will have a unique characteristic identifying it as having come from the preamble or from the header of a regular data rame.
In the exemplary embodiment, such differentiation is provided by causing the second or repeated vector in the outside address OA field to be inverted in the preamble but not inverted in the header of a regular data field.
Thus, a test can be made at block 110 of FIGURE 3 to determine whether the lncoming S and OA fields originated from a preamble or from the header of a data frame.

~X7~7(~V
- 23 ~ 45MR 466A

If sync acquisition is madedurin~ the preamble (as should normally occur), the next occurring 16-bit - SN field is grouped into three 5-bit ~ields and a single odd parity bit field. In the exemplary embodiment, the second 5-bit vector is in~erted but otherwise the three 5-bit vectors should match if correctly received and the value of the 5-bit vector identifies which one of the 12 repeated synchronLzation packets (i.e. S/OA~SN) has just been successfully received. This permits the correct boundary to be established between the 576-bit sync sequence and the 1296-bit IV~SS sequence of the preamble. Once this boundary has been established, then the 9-way redundant GB/IV/SS data stream may be properly framed, received and a majority vote process performed so as to provide a degree of error correction in the resultant initially received IV and SS data fields. The error corrected SS address is then checked for proper identification and, if correct, then the error corrected IV may ~e used for DES decr~ption of the encrypted voice data field.
On the other hand, if successful sync acquisition is not made during receipt of a preamble to a message, then a "late entry" situation is indicated.
This may occur, for example, because the receiver was somehow "late" in acquiring synchronization either by missing the preamble altogether or by having temporarily lost sufficient RF signal due to a long fade situation in a RF communication channel. In such case, the fields following the OA of the data frame header are the IV and SS fields. If the SS field correctly checks out (i.e. indicating that the message is indeed intended for this particular receiver), then a late entry flag is set and the incom.ing IV data from the data frame header is stored. This first received IV from a data frame header is not used immediately for voice data decryption but, rather, is used only to predict the IV for the next ~5~

frame. Thus, a wait is made for the next frame where entry to the sync maintenance su~routine provides the - IV received from the next data frame.
If the late entry flag is set, and the predictPd and currently received IV's do no~ match, then the current IV is merely used as the "seed" for the next predicted IV to be used in the sync maintenance subroutine while continuing to inhibit the audio output. Accordingly, in the case of a late entry, two successive correctly received IV's are required before audio output is permitted to occur.
During sync maintenance (for either type of sync acquisition) the just received incoming IV stream is compared to the predicted new IV internally generated lS in accordance with the DES algorithm. If the late entry flag was set and a good IV comparison is made, then the sync loss counter is cleared and the correct IV may be used to generate a DES decryption vector (e.g. using the DES key from emory 28) in accordance with conventional 2a DES algorithms.
During steady state, the receiver continues to decrypt the encrypted voice stream. Furthermore, if during steady state operation the predicted IV does not properly compare with the currently received IV, a sync loss counter is incremented and when the value exceeds a maximum (e.g. 10), the receiver is assumed to have dropped out of synchronization and attempts are then made to resynchronize the receiver with the incoming date stream. Accordingly, in the exemplary embodiment, once a steady state operation has been achieved, the receiver can "coast" for about data frames (e.g. about 2.25 seconds) before synchronization is considered to have been completely lost.
While only one exemplary embodiment of this invention has been described in detail, those skilled ~7~7~V

in the art will appreciate that many modifications and variations may be made in the exemplary embodiment while yet retaining many of the novel advantages and features of this invention. Accordingly, all such variations and modifications are intended to be included within the scope of the appended claims.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
1. A method of transmitting signals over a communication channel subject to fading phenomena comprising the steps of:
(1) transmitting a synchronization sequence including a plurality of redundant fields of digital frame and addressing synchronization signals for a duration in excess of a predetermined maximum expected fade duration;
(2) subsequent to said transmitting step (1), sequentially transmitting a guard band field and a further field of digital encryption synchronization signals each for a duration selected to obtain a desired degree of fade protection; and (3) repeating said sequentially transmitting step (2) of a plurality of times to obtain a sequence of interleaved transmitted guard band fields and encryption synchronization signal fields.
2. A method of receiving signals present on a communication channel subject to fading phenomena comprising the steps of:
(1) receiving a synchronization sequence including a plurality of redundant fields of digital frame and addressing synchronization signals for a duration in excess of a predetermined maximum expected fade duration;
(2) voting on said received redundant frame Claim 2 continued:
and addressing synchronization signal fields to select the received version of said frame and addressing synchron-ization signal field with the highest frequency of receipt;
(3) subsequent to said receiving step (1), receiving a sequence of fields including a guard band field and a further field of digital encryption synchronization signals each having a duration selected to obtain a desired degree of fade protection;
(4) repeating said receiving step (3) a plurality of times to obtain a sequence of redundant, interleaved received guard band fields and encryption synchron-ization signal fields; and (5) voting on said received redundant encryption synchronization signal fields to select the received version of said encryption synchronization signal field within the highest frequency of receipt.