CA1274319A - Contention switcher - Google Patents

Abstract

ABSTRACT

An electronic switching system for making logical connections between at least one computer and a plurality of computer terminal devices, the connection being soft instead of being a metallic path. If service is unavailable, the user requesting service is automatically queued for service and will be connected automatically when a port becomes available.

Description

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The present invention relates to an electronic switching system, and more particularly, a system for making logical connections between at least one computer in a plurali-ty of computer terminal devices.
Contention switching relates to the ability to switch any terminal requesting service into any available port of a "~IOST"
computer system. A "many-to-few" relationshlp, much like a rotary telephone system: i.e. fifteen terminals into eight ports. This invention relates to a "logical" switcher as opposed to a "physical switcher". The connection is soft instead of being a metallic path~
According to the present invention there is provided an electronic switching system for making logical connections between a plurality of computers and a plurality of computer terminal devices, the system including a plurality of asynchronous receiver-transmitters (ART) for converting serial binary data to and from parallel binary data, one ART for each said plurality of computers, respectively, and each of the plurality of computer terminal devices, respectively, and means for connecting each respective computer terminal device and computer to an ART, respectively. A microprocessor is provided with memory means controlled by the microprocessor for storing the identity of each of the plurality of computer terminal ; devices and each of the plurality of computers and the respective art to which they are connected and a connection table for current logical connections between pairs of the ARTs. A
sequencer logical means is controlled by the microprocessor and the data stored in the memory means including the table of current logical connections, for receiving connection request signals from one of the terminals for connection to a specific one of the plurality of computers and sequentially establishing a logical nonmetallic connection between the ART to which said one of the terminals is connected and the art to which the specific computer is connected so that the connection and da-ta transfer is transparent and a maximum utilization of each of the plurality of computers is achieved.
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If service is unavailable, -the user requesting service is automatically queued for service and will be connected automatically when a port becomes available. (Instead of "falling off the end").
Since operating systems for micro-based systems know nothing about switchers, contention switchers incorporating the invention to monitor all traffic across every port to de-termine when it may disconnect and give the port to another user. Contention switcher incorporating the Invention may accommodate up to sixteen operating systems simultaneously; watching for trigger messages, and/or "idle" timeouts, and sending appropriate termination sequences. All are user-definable.
All of the above may be extended to as many as sixteen "HOSTS" or "GROUPS". While "HOST" generally refers to ports associated with a specific host computer, it is synonymous with - la -- - ~ ' ', . ~ ' ' :
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"GROUP", which may include groups of modems or terminals. A
further feature of the invention is that any terminal may be designated as a member o~ a "GROUP", and for each group there is a master. With a few keystrokes, the master may at any time override his group's individual activities, causing their keyboards to be locked and his display to be replicated onto theirs, without their jobs being terminated. Once released by the master, they may resume at the same place.
This capability i5 particularly useful in a teaching environ-ment, and for demonstrations to groups larger than can gatheraround a single terminal.
Different computer systems have different standards as to data bits, stop bits, and parity. (i.e. ALTOS brand computers require 8 data, 1 stop and no parity, while NC~
-~ brand computers require 7 data, 1 stop and even parity.) Terminals connected directly or through a physical switcher would normally require reconfiguration to move from one system to another. A further ~eature of the invention is that the connection and data transfer is transp~rent because it is not a mekallic path and each port stands alone.
Different peripheral devices operate at different speeds of data transfer. (i.e., terminals normally operate at 960~
baud, while modems typically operate at 1200 baud.) This invention allows devices of differing speeds to be logically switched and connected with total transparency. (i.e. the 1200-baud modem can be connected to the 9600-baud terminal and the invention provides buffering and speed translation, within

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lirnits. j Cc,r,ter,tic,rl switcrlers irlcoroc.rat1rlr~ t,~e ir;ver~ic~n are fI~l1 1Y caPaole ,-,f aet fc,rrnir,g clata trar,sfer tcl/ft c~rn 1~5 ! irni~ ,~f 1.-'~ p,_,rls, ar,r~ ,_,f tne ab~-~ve ~Ilrlcr. 1"r:s, ~i ~n -erc, ~e~radat 1c,r t~o lts llsers. I=ile trar,sfers are easi'y arld efficier,tly acc,-,rnol isneC thrc~ur,~ tne l~se ,_,f the C;h trn r~acka~e lOt' e~ 1iva 1 erlt;~
This ir,ver,t ic~n car, accc,r,lPl isn al l clf the fl.lrlct i,_,r,s . r a Lccal ;irea Netwclrk (Lf~l~l) with ~erc~ ~egradat icln at either terrnir,al c~r prc.cessc,r l eve l .
T~e ~asic systern c,_,r,sists ,-~f thirty-twc~ ) I.lser pclrts ar~d twc. systern o,~rts ~cc~r,sclle arld l,_,gr~irlq Prir,ter). ~ c~edicated cc,r,sc,le device is r~c,t re~ ired.
f~ featl~re nf the irlventi~-~n is the systern is expar~da~le t,-, a 1 Z~ user pc,rt g i r, i r,crer,lerlt s c~ f 3;~ pc~rt s ~ a 1 1 f i e 1 d--i rls t a 1 1 ab 1 e by c~lstc,rner persc,rlr,el. ~I,owever, it wi 11 be aaoreciat2c) that the pr1r,ciPles ar,a feat~res ,-,f the irlver~ti~-ln are r"-,t lirllir.ed t._l trlis r,~rnc~er ,-,f oc,rts.
Cc,rlter,t ic~r swltcners ir,cc~r~c,rat irlg the ir,ver.t i.-,r. are cc,rnrnar~r~ ariver,. ever, tn._,llgn the resll1t ir,rj act i,-.,r, rnay be ar, 1nteractive rlisalay. .~lc,t~r,la1 I.lse req~lires as little as a ,irlgle ~.eystr--.~.e ~1.e. ";-") tc, realle~;t tl~e r.e>~t o,-,r~v .-,r, a sDecific hc,i2t systern, o-.l~ c,tner c,-.rnrnar,r~s are:
- ~ETUF~ T~:RI~lIhlf~L CGN~ECl STI~l US hGSl- DISGl~ tl~ T
F~O ~ r GROUP T i c~, E
D IAGNOS T IC
~iil sYs~er,l c~_-r~fia~.lra~lc~tl ;s accc~rnDi:Lshed 1,hrc-l.lrl~ a very ;. _ ; _ .~. \

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set-frier,dly rl~ ccreen ir,teractive r~isplay. ~ffet1tlr~
soft-set~r~ of eacn pararnetet or pcltt atttiDutz. ~very 3._1rt is ir,aiviaual1y cnr~figura~1e to any forrnat, speed, llse, gr_ll.lp desir~natic,n, ~rivacy restticticln ar,a n~-lst-connect testrictiorl.
~ tu1i-scteer, a1sD1ay rnay be reauested at any 1;irlle to sn,-~w curter,t ~_~oeraeinr, cclnrigl.ltctticlrl anc~ cclt-lrlecti~rls~ 1r,c1~ldinr~
time-,~f-day cc~nnected. etc. The cc~ntention switchet systern i r,c ludes battery bach~ D wn i cn w i 1 1~ after a ~clwer fai1~lre, provide at least sixty-(6~ hc~urs of tetentillrll~lf key infcrmatior~.
~ ccc~rdirlg to the inverlticlrll extensive and exnaustive diagnclstic prc~grarlls are held in PROi~1 mernc~ry at all tirnesl and r~n both ~.n-1ine and off-line tcl verify inter;rity of ,~peratior, ~r tc~ Doint directly tn the source l~f the ptclblern.
; Everl thc,ugn thete rnay be as rnany as twelve events ccurrinq simultar,el_,lls1y. al1 are execllted thr,-,l.~gh Larae-~ca1e-Irlteqration ~LsI or VLSI) circuitry and thete ~re r"-, - rnc~ving parts except fot fans.
F~ower fa11ure is autc,r,laeica11y ser~se~ (,_,r rnay be reauested by ~ressitng the lc,qic Dc,wer switch) ar~d shutd~,wr, har,dled by the ir,ver,tic,rl. Wnen powet is ayairl avai1ab1e~ the systern is autc~matica11y ~r~-,ugh~ bac~ ur~. The Systems ~drnir,istrat.-,t rnay ass1gn tc. each terrnina1 r~ott the ab1lity to cc,r,fiqute and furthet trl execute diagr,ostirs ft,_lm that pclrta ~1so~ tre 3clrt ar~d its cattacned terrllirla1 may be a11clwed -lr deniec' access to speeific h,_lsts ,-~r 9rclups~

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BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, advantages and features of the invention will become more apparent when considered with the following speciEication and accompanying drawings representing an exemplary embodiment of a contention switching system incorporating the invention wherein:
Fig. 1 is a schematic block diagram of a contention - switching system in accordance with the present invention, Fig. 2 is a schematic block diagram of the central processing unit (CP~) incorporating the invention, Fig. 3 is a schematic block diagram of the polling assist hardware components incorporated in the invention, Fig. 4 is a schematic block diagram of one of the inputtoutput tO/I) boards incorporated in the invention, Figs. 5a, b and c are flow charts illustrating the system initialization sequence according to the invent;on, ! 20 Figs. 6a and b are flow charts illustrating the system connect and disconnect sequence according to the invention, Figs. 7a, b, c, d, e, f, g and h are flow charts illustrating the various interrupts of the system.

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GLOSSARY CONTENTION SWITCHER
The following list defines vari OU5 terms related to the contention switoher whlch are used throughout this specilication.
~UD ~TE - The unit of signaling speed indicating the number of signal transitions per second that occur over a data comm~lnications channel.
CO~ND CONSOLE - ~ data terminal through which the contention switcher is controlled.
- CONFIGU~TION - The complete speoification of all of the necessary parameters required to operate the contention switcher in a specific operating environment~
CONNECTION S~QUENCE - The dialogue entered at a terminal port which c~uses a logical connection to be made to a ho5t port.
CONNECTION TQBLE - an internal list of the c~lrrent logical connections.
CONTENTION S~ITCHER (CTSW) - ~ single piece of equipme~t designed to replace the function of many pieces of data communication equipment by creating logical connection paths internally between any two of its external ports. The contentlon 5Wi tcher may be connected to other data communication equipment only if the interconnecting cab~e has certain signal lines crossed.
CONT~OL REGISTER - ~ special latch used by the microproce~sor t~ control control specific hardware on the ~PU board, s~ch as the status indicators and~or the Watchdog Timer.
CPU ~OA~D - ~rinted circuit card containing the microprocessor, ; system memory, time of day clock~ programmable timer~
seq~encer logic, and console/error logger interface.
D~T~ C0~ iU~IC~TION CHQNNEL - The entire communications interface~
including but not limited to a piece of data terminal eq~lipment connected to d~ta communic~tion equipment which i5 in turn connected to another piPce of data communication equipment and finally terminating at another peice of data terminal equipment.
D~T~ CC~UNIC~TION EQUIPMENT (VCE) - A devic~ for the conversion of a serial binary data str~am to and from signals sui~able for transmission over long distances~ spec-ifically telephone lines. ~lso refered to as a MOD~.
The El~ Standard RS-232-C specifies that a fem~le connector i 5 to be assooiated with DCE.

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, ` . . . ` ~ ` ~ ~ " , DAT~ TER~INQL EQUIF~MENT (DTE) - ~ny device used for the display and transmission o~ serial data. ~ computer (being capable of displaying ~nd transmitting serial data) may al~o be refered to as Data Terminal Equipment.
The EI~ St~ndard RS ~-C specifies that a male connector i5 to be associated with DTE, although this convention i5 4requently not adhered to.
DI~GNOSTICS - Special commands which are entered at the command console which e;:ercise various portions o-f the CTSW
in order to detect and identify hardware failures.
DISCON~ECT TIMEOUT - ~ period of time after which, if no data activity is detected, ~ Logical connection is brolcen~
DU~L ~SYNCHROUNOUS F;ECEIVER-TRQNSMITTEF~ (DU~RT) - A single integrated circuit chip containing all of the digital logic necessary to perform the conversion o~ serial binary d~ta to and from parallel binary data ~ar two ports.
The DU~T ~lsed in the Q~X~D~nt is the MC6868~.
EI~ - Electronic Industries Association ~ 1 Eye Street,N.W.~ Washington~D.C. 20006 FIFO - ~ self addressed memory chip that remembers the order that data is stored into it, such that the first data written into it is automatically the ~ir~t data to be read aut of i~. (First In, First Out~
GROUP - A collection of one or more ports which are handled - as a unit. Groups are defined by the GR0UP comm~nd.
HOST FORT - any one of the d~ta comm~nication channels which is connected to a external computer port. The connection may be directly to the computer or thro~lgh a MO~EM.
- I/O ~O~RD - Printed circuit card containing sixteen DU~RTs and ; the necessary interface logic required to access those ~U~RTs from the CFU board. This board also contains the signal drivers and receivers that go to the inter4ace connectors on the back of the contention switcher~
INTERF'UPT - ~n electrical signal generated in order to notify the ~icroprocessor of an ex~ternal condition that requlre~
the attention of the centra} processing unit.
INTERRUPT RRIORITY LEVEL (IPL~ - The relative importance assigned to e~ch interrupt which indicates to the micropr~cessor which interrupt to handle first if more than one external dev~ce requires it s ~ttention at the same time.
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LOGIC~L CONNECTION - ~ connection bet~een two ports of the CTSW. Once a logical connection is made, the two ports behave as if they are physically connected to each othe~q although there is a 51 i qht delay introduced by the CTSW of less than one character transmission time plus one millisecond.
~AST~R TERMIN~L - ~ data terminal that is connected to a port which is configured to control one or more slave terminal ports.
MEGAHERTZ - One million cycles per seeond ~ODEM (~Odulator/~EModulator) - See DQTA COM~UNIC~TION EQUI~MENT.
MIC~OPROCESSO~ - The central processing unit used to maintain control over all of the internal functions of the contention switcher. The microprocessor used is the ~C~8010.
NO~AL/SERVICE SWITC~ - ~ two position switch located on the CPU board which is used to lockout certain commands which if inadvertently entered co~lld destroy the config~lratlon.
O~E~TION~L ~ODE - The normal mode of operation for the CTSW. Certain diagnostic commands which could interfere with normal operating of the CTSW are not allowed to be entered.
The opp~site of operational mode i 5 shutdown mode~
POLLING - the regular e>:amination by the seq-lencer of the DU~RT
ports used to transfer data between the ports.
PORT - an electrical passageway into or out o~ a computer or a computer related piece of equipment used for data ~ communication. ~lso used to refer to one ~f the two --- data communication channels in a DU~T.
F~OGR~M~LE - an integrated circuit chip used-to generate precisely TIMER timed interrupts. The timer used is -the MC~840.
- ~F~L TI~E CLOCK - an integrated circuit chip used to ~eep tr~ck of the time of day and the current date. ~lso refered to as "Time of Day Clock".
~5-232~ n EI~ standard de~inin~ an "Interf~ce ~etween Data Terminal Equipment and Data Co~munication Equipment employing 5erial ~inary ~ata Interchange"
SL~vE TER~IN~L - a terminal configured to be under the control of a master terminal. When the master terminal enters the override com~and, the charaters entered at the slave terminal port are ignored, and à copy of the data received from the host port connected t~ the master terminal port is trans~itted to the slave terminal.

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SHUTDOWN MODE - The mode of operation that the CTSW i5 required to be in order to run diagnostics. No new connections are allowed to be made at any of the terminal ports.
TERMINQL - See DQT~ TE~IN~L EQUIPMENT.
TERMIN~L F'ORT - any one of the contention switcher ports which is connected to data terminal equipment. The connec-tion ! may be directly to a terminal or through a MODEM~
TIME OF D~Y CLOCK - 5ee RE~L TIME CLOC~.
TRIGGER ~ESS~GE - ~ one to sixteen character string, which when received by the CT5W from a host port~ initiates a disconnect timeout sequence.
W~TC~DO~ TIMER - a special programmable timer which~ i~ n~t regularly attended to by the microprocessor, assumes that the CPU has failed and causes a system reset to occur.

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DETf~ I L~ SC R I . ~T I O~ OF l H~: I NV~ r 1 o.~

Referr1nq tcl Fig. 1~ a MicroDrc~cess-~r cc~fltrl_llled cc,r,ter,ti,-,n switcner 1~ incc,rpot atit-lr~ the inverlti,~ln1 r.as a pll~rality of p,_,rts 11 (typically Ei~--Star,dard RS23;~ for har~aling lcl ical c,-,r,necticlrls aet~een .-~r,e ,_lr mc~re cc,~ utet s 12, 1~. 14. . .Cn (ss,rne tirnes aes1gnated h~-~st~ ar~d muitiplY ~oeripheral aevices SUCh as termirlals l~ , 171 18... In. f~ecc~rr~irlr~ to ~he 1nvent lC~t~ if a uset of any of the terrninal aevices wis~es tcl bre cc,r,nected to a partic~lar cornDI~tet ~ a t~eql~est i5 en~ered c~r, his terminal. The c,-,ntentiorl sw~tcher 1~ ~etermines if ar:y of trle pc,rts of tne uset selected hcst cc,rnpl~er are availa~le and, if ;~- available. achieves a lclgical cc~rlnect1~rl (as r,ppl:,sed t,-, a pnysical switcned metal 1 ic path ot cclnrlect iclr,) l~e~ween the reauest itlg tet minal anri the selected complltet . If al l Cl1- the pc.rts c,f the selected c.:lrnp~ter are beir,g used ~ it beirlg 2,DDreciated that the h-st cc~m~ ter car" ifl s,:,r,le cases~ only have or,e Dort ) the reql.~est ir,q l~ser ~i l l be adv~sed -,f halw rnclr,y at e .: wai~ir,g~ if they wish t,-, wait àrld he que~ed fut servlc~ by the selected cc~rnr~utet l if tnat uset sc, ~esires. Or,ce the l,-~ical - c._,rlnect 1c,n patn c,~ a terminal nas ~eer, rnaCe t,-, a selecte~ host cc,rnpl~ter, tne corter~ic~n swl~cher rn,:,r,lt,-,t s all aata traffic acrc~ss every ~c~rt.

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IN1RODUCTION TO SYSTM DESCRIP~ION
This specification describes the hardware and software used to implement one embodiment of a contention switcher (CTSW) incorporating the invention. The CTS~ is capable of handling up to 64 logical connections between a ma~imum of 128 EIA Standard RS-232-C devices, at data rates up to 9600 baud.
In the embodiment disclosed herein, the CTSW includes one CPU board (Fig. 2) and from one to four I/O boards (Fig. 4). The CPU used is the ~C68010 16-bit microprocessor which is run at 8 megahertz. Each I/O board contains sixteen MC68681 Dual Asynchronous Receiver/Transmitter (DUART) chips. Each DUART is capable of handling two RS-232 ports, for a total of 32 ports per ItO board. Each port is connected to a terminal (Terminal Port) or to a selected host computer port (~ost Port). Both the CPU
board and the l/O boards contain special hardware used to assist the microprocessor in handling the intense data rates required.
The CPU board contains the system memory, including up to 8K
bytes of battery backed up RAM used to maintain the system configuration when power is removed from the CTSW. A Time of Day Clock is also maintained by the battery backup system. A
programmable timer PT is used to generate the regular interrupts needed to keep data moving in a timely manner. One DUART 51 on the CPU board handles two RS-232 ports which are not part of the - 12~ switched ports. These two ports are used to communicate directly with the processor in order to update the system con~iguration, log connection information, and run diagnostlcs in - the case of a system failure.
There are two basic modes that the processor operates in to - handle DUART I/O. Initially, all ports are handled on a 100%
~ 30 interrupt driven basis. As logical connections are made between -~ ports, they are mapped into a connection table. Periodically, all DUART ports entered into this table are polled in order to do any necessary character data transfers between them. This defines an asymmetrical operation, both interrupt driven and polled, so that initially the CPU can deal with a greater number ot interrupts. ~s more connections are made, less time is .
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~7~L3~9 available for handling the interrupts, but less time is needed.
The worst case polling loop would consume approximately 50% of the CPU time, leaving approximately 50% for handling interrupts.
The best case would be 0% polling time and 100% interrupt handling. The polling loop overhead is totally dependent upon the number of logical connections at any given time.

SYSTEM INTERRUPTS DESCRIPTION
The system processor 20 can be interrupted from any of a number of external events. The following descriptions are ordered from the highest priority event to the lowest. All interrupts (except System Reset~ are initially disabled from interrupting the processor until the Interrupt Enable bit is set in the CPU Control Register.
System Reset - is generated upon initial power-up of the system or by the RESET push button on the CPU
board. A reset is also Eorced if the watchdog timer enable bit it set in the CPU Control Register and the progra~nable watchdog timer is allowed to count down to zero.
20 System Abort - is generated by the Abort push bu-tton on the IPL _ 7 CPU board. This interrupt is also caused by a power fail indication from the p~wer supply or a FIFO Full condition from the CPU board interrupt handling circuitry.
- PTM Interrupt - is generated by the Programmable Timer and is IPL = 6 used to initiate polling of the l/O board DUARTS on a regular basis.
RTC Interrupt - is generated by the Time of Day Clock once each IPL = S second. It is used to maintain the system 30clock and to timeout idle system ports.
CPU Board DUART - This Interrupt is generated by the DUART 51 on IPL = 4 the CPU board.
I/O FIFO Full - is generated if one of the FlFOs on any of I/O
IPL = 3 boards reaches it's maximum capacity of sixteen . .
interrupting DUARTS. This interrupt is used as .
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a load balancing mechanism, giving I/O board(s) that have an excess number of pending interrup-ts priority over I/O boards that are less busy.
1/0 Board DUART - This interrupt is generated when any of the 1/0 IPL _ 2 Board Duarts 30 requires attention. These interrupts are presented to the microprocessor in a round-robin fashion by the hardware.
Shutdown Switch - This interrupt indicates that the front panel IPL - 1 Startup/Shutdown switch is requesting that the system should be shutdown.

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CO~FREHE~ISIVE ADDRESS ~QF
________+________________________+_________________________,,____~ __ _ $FFFFFF ' , $FFFFFE
~ I/O ~0~1~D DUQRT QDDkESSING AREQ
$F(:)t:)C)(~:) ' ' *F(:)t:)l~:)t ________+_______ _ ______________+._________________ _______+________ *EFFFFE I I $EFFFFF
I SE~.UEN5Ek RQM DIF:ECT QDDRESSING RRER
` ~Et.)~ (:)t ________+________________________+_________________________+________ $DFFFFE I I $DFFFFF
' CFU ~O~RD I/O DEVICE QDDRESSING AkEA
$~:)()(-)()(-) , ' $DI:)(:)(:)~:ll ________+________________________+____ ____________________+________ *CFFFFF ' I ~CFFFFF
~ CPU ~ORkD CONTROL REGISTER RF'EA
$C(~ (:)(-)t) , , $C~
________+_______ ________________+___ _____________________+________ : UhlUSED QDDRESS SF'QCE
________~.________________________~________________ ________+________ *1~FFFF ' kE5E~VED FOR QDDITIOhlAl_ ' $1~.FFFF
$1~CC)t)l) ~ WRITRBLE kD~ ~UR TO l~8~::) ' *12CC)(:)I-) ________+________________________+_____ ___________________+________ FFE . ' $1~BFFF
I W~IT~LE kO~ (4S~l~ t *1~C)~ , . *** DIAGhlDSTIC ~ODE ONLY *** I $1 ?OOC) 1 ________+________________________,._________________________+________ :~11FFFE ' ~E5EkVED FOF; ADDITIQNAL I -~11FFFF
.~1C)C(-)(-)t1 ' SYSTE~ kO~ (U~ TO 1~9k~ 1C)CC)(:)1 ________+________________________+_________________________+_~______ ~1OBFFE I ~ ~1t:)BFFF
- I SYSTE~ ROM ~4~
________~________________~___ ___+_________________________.,.________ : UhlUSED QDDRESS SPQCE
_________t_________________________+_________________________+________ ~t:)-.FFFE . RESEF;VED FOR ~DDITIONRL I *C)~.FFFF
$C).~ )t-) '~ATTERY BACt~ED-UP kR~ ~UF TO 64~::) . . $t:)~t-)t:)1 .._______._+_______ ________________~________________ ________,________ $t:)~.1FFE '' *t:)~lFFF
IE~QTTEkY BACk::ED-~F RA~ (Sk;) *(:)~t:)t:)t:)c) ' ` ' $t:)~.t-)t)t:)l ________+___ _______________._____, __.___________ __. _______+____ __ .~.t.)~FFFE ' RESERVED FOk AD~ITIONAL I $0~FFFF
$C)()5(:)~ ) ' SYSTE~ kQ~ ~UF TO 1~ :) l *t:)t-)5t:1t:)1 ____ __~________________________+_________________________~________ $Cio4FFE ' I -$CI(:)4FFF
ISYSTE~ kRM ~lq~.) I
. *()(~(-)4t:lCl l~ $t:~C~ t:~1 ________,._____.__________________+__~______________________~________ ~t:~t:~C).~FE ' SYSTE~ INTEF~RUFT ~ :$(~ t-~FF
~C~ OC~C)(:) ' VECTOF'S ~1k~ ~ *(-~C~o(~)01 _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ .._ _ ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ._ ~ _ _ _ _ _ _ _ _ , :
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FOR~AT OF OFF ~OARD DU~F;T REC I STER AccEss WO~D

+~ -ADDRESS LOOF~ACt ENA~LE ~IT
~ - DU~RT I NTE~UPT ACt~NO~LEDCE
A17 A1~ ~15 Ai4 A1~ A1~ A11 ~1: As AS A7 A~ A~ A4 ~l A~ A1 A
~ _ _ _ + _ _ _ f __ _ _ _ _ _ _ _ _ __ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ + ,_ _ _ _ _ _ _ _ _ _ _ + _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ + _ _ _ + _ _ _ +
~AL~ ACt~lSS41SS7.1SS~ SS1 ' RS.~. I RS? I RS l I ~S~ I BS~ I ~S l, CS4 . CS~U CS~ I CS l PS4 xxx - FOLL ING SEQUENCE SELECT
RECISTER SELECT ~ G
~OARD SELECT ~ ~ 1 ----------------------+ o CHI p SELECT 4 .~ ~ 1 ---------------------~-------------~ E
REG I STER SELECT 4 -----------------------------------------------+
NOTES:
1) ~IT O DEFINES EVEN OR ODD ~YTE hDDRESSES. DUARTS ~AY ~E
ACCESSED AT E I THER EVEN W~F;D OF; ODD ~YTE ADDRESSES.

) THE FOLLING SEQUENCE sELEc-r IS DECODED AS FOLLOWS
t-~ O - A~.SOLUTE DUAF~T AcEsss -~ol~ 1 - POLL I I~G SE~.UENCE STEF 1 . POLLING SE~.UENCE .~
POLLIN~ SE~.UENCE s-rEl~ 7 ~ :) - DUART I NTERRUFT A~.NOWLEDGE-~READ ONLY ) O1C)Ot~ - FIFO F ULL INTERRUPT RESET
- lC~ l - DIAGNOSTIC SE~UENCr STEP 1 ...... D I AGN05T I C sE~uENcE ~

ADDRESS LOOPE~AC~ ENA~LE IS ONLY V~LID FOF: DIAGNOSTIC STERS
REFER TO POLLING SEQUENCE STEP DEFINITION FOR MURE DETALL
~) THE FOLLOWIN~ TA~LE DEFINES THE UTILIZATION OF THE DU~RT
INPUT AND OUTPUT PORT pINs OPO = CTS A ** I F (:~ rs A *~
OF~ = DsR A IF- = I~TR
OP~. - DSR ~ I F.~ DTR -~
I F ~ -- DCI:) A **
** = MODEM FORTS ONLY Ips = RI ~ *~

3~
SPECIAL PURPOS~ CPU BOARD RAM MAP

~D~E55 1 UFFER D~TA ~YTE LOWEh DAT~ ~YTE
+_________________________+___ _____________________~
~EO4IFE I I EXP~NDED CO~F~E ~ I $EO41FF
*EO410l~ t , ~ OFTION ~1~8 ~Y ~ ~ITS) : $EO4l01 *_________________________~_______.___.________ _____.,.
*EI:~40FE I ~ HQRDWQRE COMP~RE RQM *E040FF
*E~4C~C~8 ~Y 8 ~ITS) ' ~EC~40C~1 ~_________________________*_________________________~
*EC)~OFE .~ H~RDW~RE POINTER ~M I ~E020FF
*E~OOI) I ~8 ~Y 8 ~ITS~ I *E1~2001 $E~ FE ~ H~ J~E M~PPI~G ~ *E~ F
$EI~ f~ (1~8 ~Y 8 ~lTS3 ' *E~
~________________________ ~_________ _______________~
.

NOTES:
1) The Hardware Compare RAM (Fig. 3) contains up to 8 short messages. Each message can be up to 16 characters in length. Only the low 7 bits are used for the compare operation. The MSB (bit 7) of the character from the Compare RAM indicates the last character of the message. If set, and the final character matches the received character, then Bit 7 of the status byte written into the Pointer RAM
is set indicating a complete match. Bit 2 of the Status byte will be cleared, in order to determine if any characters are received after the match occurs.

2) The Hardware Pointer RAM is addressed by bits A7 - Al of the DUART Register address/command word. During a polling sequence, the Hardware Pointing RAM is used to address the Hardware Compare RAM. If the character read from the Compare ~AM matches the character read from the DUAE~T then the low 4 bits of the pointer are incremented to point to the net character. Otherwise the low 4 bits of the pointer are reset to point to the beginning of the short message.

. - ~ . .. . :
: . :..... . -.

- .' ~ - : ' ' : ' :
.

~2~L3~

ON BO~PD I/O DEVICE ~DDPESS ~AP
ADDriESS I UFPEF~ DATQ BYTE LOWEk D~T~ BYTE
+_________________________+--------------------------------------------------1-~ MC684t) ~ PFiOGF;~M~ElLE TIMEk I *DCC)FFF
$Dc,:)c)~jE I I ~Ir~ TI~EF; 3/F;D LSE~ BUF t $DCt:)Cl~:)F
*DC~ l':)C I l WFi~ ~ISB BUF/kD ~IMEF; 3 1 *DCl~l:)l:)D
$DCl')-)OA I I WF; TIMEk ~/kD LSB E~UF I *DCl:)C)l:)B
*DCl;';':~8 1 I Wk MSB BUF/kD TIMEP 2 1 *DCl:)~:)9 *DCl:~C)S I l WF; TIMER 1/F;D LSB BUF I *DCI:)~ 7 ~DCl:)l:)C14 1 I WF; MSB BUF/kD TIMEP 1 1 *DCC)C)1:)5 *DCC~I WP CF~EG 2/F~EAD SrATUS I $DCt.)C~:)3 $DCC)':Il:3':) 1 I WkITE CONTROL F~EG 1X3 1 *DCI~l:)t.)1 +_________________________+_________________________+
I ~C146818 ID~TE / TIME CLOC~ I *D8~:1FFF
~D8C)C)7E'1 IHIGHEST F;~M BYTE t *D8~ 7F
*D8C)C)1C I ~LOWEST kAM BYTE I *D8001D
*D81:)l:)1A I I ~ISC hEGISTEF; D I *D8C)l:)1B
*D8t~C)18 1 ~ ~MISC kEGISTEr~ C I *D8C)l:)1q *D80l~16 1 1 ~lISC F;EGI5TEh~ B I *D80C)17 $D8l')C)14 1 ~ MISC kEGISTEF; Q I *D8C)l'.)15 $DsliC~l? I ~ YEAR kEGISTEF; I *D8l:)l:)13 *~8C)C)~ MONTH F~EGISTEF; I *D8C)1:)11 *D8qO':~E I I DQY OF ~ONTH F;EG I $D8C~l:)l:)F
*D8C)~P:~C I ~ D~Y OF WEE~ PEG I ~D80~ D
*D8C)~ A I I HOURS hL~kM F;EC I *D81~l:)C)B
*D8l:)gl:)8 I HOUPiS FtEGISTEF; I $D8ljC)1:)9 *D81:)00b 1 ' ~ MINUTES ~LARM PEG I *D8bOlj7 ~D8gC)C)4 1 1' ~IINUTES F;EGISTEP I $D8l~C)):)5 *D8'~ 2 1 I SECONDS ~L~F;M F;EG I $D84~
$D8C)~C~q ~ ~ SECONDS F;EGISTEk I $D8bC)C)i +____~____________________+_________________________+
I ~'IC68~81 I CPU BO~F~D DU~F;T~S) I $DC)-IFFf *DC)I~Eb2 1 I STOP CTk/OP BIT F;ESET I *D':)~El~3 ~D':U:)CO2 1 I STF;T CTPi/OP BIT SET I *D'~':)Cl~
*DC)':)A02 1 1 INPUT FORT / OF'CF; F;EG I *D-.ibA~j3 *DC)C)8~2 ~ I INTEF;F;UFT VECTOr~ F;EG l $Dl:)~'.)8l:)3 *D~ I I PCVF;/XMIT'rEk BUFFEF; B I *Dljl~6l~3 $DC)C)4lj2 1 I CO~MQND F~EGISTEk B I ~DC)-.)40 $DC)~ I STATUS / CL~::-SEL kEG Ei I ~D~jl:)2C
$DOI')Ol:)2 1 I MODE 1X2 fiEGISTEF; B I *DC)C)~
$DC)gE~ CTP ~ TIMEF~ LOWEk FEG I *DC)OE''.1 *DC)C)Cg~:) I I CTF; X TIl1EF; UFFEP F;EQ I *DC)C)C01 $D~ C)C) ~ I INT STATUS / MAS~C F~EG I $D~:~gAl~1 *DI:)C)agC) I I IP CHANGE/~UX CTL F~EQ I $DClg8C)1 *DC)06Cff:) I I kCVk/XMITTEP BUFFEF; ~ I *DOl:)601 $Dl'~C)4~C) I ~ CO~ A~D F;EGISTEk ~ I *D':)':)4 *DCICI201:) l I STATUS / CLh-SEL F;EG f~ l *DOO~
*DOgC)gl:) I I t101;E 1/2 FEGISTEF; `h ' *DC)C)g~:)i + _ ~

` . : . ' . .

,.' ~r~ ~

CFU ~OAhD I/O REGISTER ~D3PESS ~P
DDRESS I UPFER DATA ~YTE LOWE~ DAT~ RYTE
~_________________________+________._________________+
CCQC10l~ ~ ' INT DIAG REGISTE~ ~W/O) ' *CCO~
C8C~ ST~TUS REGISTEF~ ~/0) ~ ~C8C)~-.)01 C4~)C)O~ I I CQNTF;OL kEGISTEh ~R/W) I $C4~)C~
+___________________ _____+_________________________~
15 ~ 8 7 6 5 4 3 ? 1 ~) CONTROL +-----~ ----+---- ~ ----+---~----+---+---+
RE5ISTER NOT USED ILE41LE~ILE ILE1~JREIWPE~WDTlINT~ ~RE~D/WRITE) +__________+__ +___~___+___+___+___+___+_ _~
LEl THRU LE4 ~ CFU ~OQF;D LED 1 THRU LED 4~ ~) = EXTINGUISH~ 1 = ILLUMINATE
WRE ~ WfiITA~LE R~M ENQ~LE/DISA~LE CONTROL~ C~ = DISA~LE~ 1 - ENA~LE
WFE ~ WRITE FF~OTECT ENA~LE/DISA~LE CONTROL~ 1.1 = DIS~LEl 1 = ENA~LE
WDT ~ WATCH DOG TIMER ENA~LE/DIS~LE CONTROL, 11 ~ DIS~LE~ 1 = EN~LE
INT ~ MASTER INTE~RUFT ENA~LE/DISABLE CONTROL~ ~1 = DISA~LE~ 1 = ENA~LE
15 - 8 7 ~ 5 4 ~. 2 1 ~
STQTUS +~~~~~~~~~-+~~~+~~-~---+~~~~---+-~~~~~~+~~~+
REGISTE~ . I NOT USED IN/S~CFIC111CJI~lWREIWPTIWDT~INTl ~READ ONLY) + + + --~------+------~___~___~
WF;E~WPT9WDT~INT ~ IDENTIC~L. TO CONTROL REGISTER ~ITS
N/S ~ NORMAL/SE~VICE ~ODE SWITCH~ C) = NOPM~L~ 1 ~ SE~VICE
~CF ~ A/C POWE~ FAILURE DETECTION~ 1~ = NOT F~ILED~ 1 = F~ILED
- CJ1 ~ND CJ~.) CONFIGURATION JUMFE~S~ C~ = INSTALLED~ 1 = kEMOVED
- THE CJ~-CJ1 JUMPEFS WILL ~E INTERFRETED AS FOLLOWS:
- ~OTH JUMFE~S INST~LLED = q6C)CI E~UD CONSOLE POPT
CJl a~iLY INST~LLED = 1?~0 ~UD CONSOLE FOkT
CJ~.~ JU~PER INSTQLLED = ~f~ UD CONSOLE FORT
~OTH JUMFERS kEMOVED ~ llCl ~UD CONSOLE PORT
15 ~ 8 7 6 5 4 3 ?
~ INTEkRUPT + ~~~~~~~~~+~~~+~~~+~~~+~~~+~~~+~~~~~~~+~~~+
: DI~GNOSTIC I NOT USED ~FF~.IFF?IFF11FFC)IIF-31IF-21IFilIF~ W~ITE ONLY) REGI5TE~ +~--~------~---+---1---~---~---~----~---+---+
FF3 THF:;U FF~:~ ~ SIMlJLf~TE FIFO FUl L~ ~ = INTERRUPT~ 1 = NO INTERRUFT
IP:~i THF;U IPt:) -- SIMULQTE INTERRUPT PENDINGl ~:) = INTERRlJPT~ 1 = NO Il~lJPr ,, ' ~ ' '.
~ ` ~ 17 -~ .
- . . . . . ..

- ~ , . . . . .
,. . , . - -. ~ ' . ' ' . . ~ ~ ' ', .
,: . :

~2~74~

PROGRAM~A~LE QRF~AY LOGIC ~FAL) ~OOLEAN SPECIFICATION
The Following specific~tion is used to program the FAL
that decodes the memory address into sever~l general categories of ~ccess (IOEN,HDRA~,LOCIO,MCSF;G,LOC~. This PAL also indic~tes an interrupt ackno~Jledge c~fcle ~INTRC) or non-interrupt tFCHI) cy~le. It gener~tes th~ signal ERREN* if ~ user mode ac~ess i5 attempted with the F~OTect bit set in the CFU Control Pegister.
=====_.=============================-_===a==================================
PALl~L8 FAL ~ESIGN SPECIFICATION
FATTERN Q2-4t:)3~FU1 4~1~84 SUMCHEC~ = 4~48 CATEGORY DECODER FUSES ~LOWN =
A23 Q2~ A21 ~?O FCC) /OE /IOEN /FCHI /LOCIO /LOCt~
/CRGS /HDkAM /INTAC~ /ERREN VCC
IF IOE) IOEN = f~2~ * f~2? * A21 ~ A?O * FC2 * FCHI
IF (OE~ FCHI = /FC2 ~ /FC1 ~ /FCO
IF (OE) LOCID = A23 * A2~ * /A?l * A~Q * FCHI
IF (OE) LOC~ = /A2~ * /f~Z * /A~1 * FCHI
IF (OE) CRGS = A23 * A22 * /A~1 * /A2C) * FCHI
IF ~OE) HDPA~ ,a A~3 * A22 * A?1 * /A20 * FCHI
IF (OE) INT~Ch~ a FC2 * FC1 * FCQ * ~ASl IF ~OE) EFF;EN = /FC~ * PROT

.

. ~ ' . ' : , ' ~27~

FF;OGR~MM~8LE ARP~Y LOGIC tF~L) ~OOLE~N SPECIFICQTION
The following speci~ication is Ltsed to program the FAL
that decodes the general catagory oF access into several specific enable~clock.i~g si~nals ~DUSEL,RTCSEL7PTMSEL,MCF;WR,MSRRD,IDRWR)~
It also generates Valid Peripheral ~ddre~s (VPQ~ back to the microprocessor, and an error sig~al (ERF~EN) if an in~alid acc~s~
is attemRted.
=======,=====._=====================~=--===========,,=======--===~==~=,==,=,=, P~Ll~L8 ~ FAL DESIGN SFECIFIC~TION
P~TTEF;N C~4-4C~8PU4 7~15~84 SUMCHEC~ = 8~.08 SELECT DECODER FUSES ~LOWN = 1017 Alq- Ai8 ~ERF;EN ~VMA ~INTACh~
WRITE FC~ /LOCIO /CRGS GND
DAS1 /IOERF~ ~DUSEL fRTCSEL ~PTMSEL
MCRWk ~MSRF~D IDRWR /VPA VCC
IFtVCC) IOERR = D~S1 * ERfiEN * LOCIO
~ D~S1 * LOCIO * ~lq * ~18 + VM~ * ~FC2 ~ CRGS
+ VM~ ~ CRGS * ~iq * ~18 + VMA * WRITE * CRGS * ~lq * ~A18 + VMA * ~WRITE * CPGS * Ai9 * ~18 IFtVCC) DUSEL = DAS1 * ~ERF;EN * LOCIO * ~19 * /Q18 IFtVCC) RTCSEL = DAS1 * ~EF;REN * LOCIO * A19 * ~18 IF(VCC) FTMSEL = DAS1 * ~ERREN * LOCIO * ~19 * A18 : IF~VCC) ~MCF~WR = ~FC~ + ~VMA + ~CF;G5 * Alq ~ ~A18 ~ ~WRITE
: IFtVCC) MSRRD = FC2 . * VMA * CRGS * ~lq * A18 -~ ~W~ITE
FC~ * VMA * CRGS * A19 * ~A18 * ~WFiITE
IFtVCC~ ~IDF;WR = ~FC~ + /VMA + /CF~GS + /Alq + /A18 + /WF;ITE
IFtVCC) VP~ = D~S1 * CRGS
: + DAS1 * INTACK
+ DAS1 * LOCIO * ~19 * ~A18 .
` "i ":

.
.
- : :
:'' ` ' ' `
.
- . : . ` - ' ' , ~Z7~31~
OVERVIEW OF OFFBOARD DUART l/O HANDLI~G
When a successful connection sequence is entered at a terminal port Tl, T2...TN, the selected host port and the terminal port are logically connected by entering their l/O
addresses into a RAM 35 (Mapping RAM) on the CPU board (~ig. ~).
One bit of these I/O addresses is used to define an op-tional master/slave relationship between a configurable ~roup of termlnals. The master terminal may enter a command which will cause all slave terminals to be driven with the characters received from the master terminal's host port. ~dditionalIy, while these terminals are slaved, no data will be transferred to their respective host ports.
Once a pair of DUART ports have been logically connected, a regularly timed polling sequence conditionally transfers data between them. ~irst, the status of the two ports is latched on the CPU board. If the status latched indicates that the receiver is ready in the source DUART and that the transmitter is ready in the destination DUART then (except for a slaved terminal port) a MOVE instruction will transfer the data from the source DUART
receiver to the destination DUART transmitter. If any required condition is not met, then the l/O Enable signal to the VERSABUS
will not be asserted (as well as other signals associated with the message compare logic described below) and the MOVE
instruction will have no effect on the DUARTs addressed. The MOVE instruction is executed, irregardless of the latched status.
Therefore, the M~VE is a hardware conditional, rather than a CPU
internal test.
As each character is received from a selected host port, it is compared to one of 8 short messages contained in a R~M
(Compare RAM) on the CPU board. As each character of the message is matched, a pointer in another R~M (Pointer RAM) is incremented. If the MSB of the character read from the Compare RAM is set, and that character matches the character bein~
received, a bit is set in a status byte which is written into the pointer ~AM, indicating that the message has been completely matched. This status byte is periodically checked by the .

-, ~ . ..
.
- - : ' . - ', ~'., ' . ' ':
. .
: : ' ' , . , -: ,'' ~ ', ~;7~3~
processor, and if no characters are received from -the -terminal por-t within a configurable timeout period, the connection will be terminated.
Abnormal DUART conditions (Overrun Error, Framing Error, Received Break, Input Change) are always processed by the DUART
interrupt handler. I/O board DUART interrupts are queued in a "FIFO" on the ljO board, so that they can be processed on a first come, first serve basis. In order to handle multiple DUART
interrupts in an efficient manner, the DUART interrupt handler uses a special address/command word to acknowledge DUART
interrupts. After entering the DUART interrupt handler, this address/command word is read to determine the address of interrupting DUART. After handling the interrupt, this address is read again to determine the address of the next DUART to handle. If the address byte read is ZERO, then no more DUART
interrupts are pending and the interrupt handler is exited.

POLLING LOOP TIMING
An interrupt from the MC6840 programmable timer PT initiates a polling loop once every 900 microseconds. The polling loop initializes seven address registers with the address/commands used to poll each pair of logically connected DUART ports. Then the following sequence of five instructions is executed for each logical connection:

TST.W (AO)+ LATCH TERMINAL PORT DUART ADDRESS
TST.W (Al)+ LATC~ TERMINAL STATUS + HOST DUART ADDRESS
TST.W (A2)+ LATCH HOST STATUS + COMPARE RAM ADDRESS
~OY~.W (A3)+, tA4)+ MOVE DATA (HOST TO TE~) + CHECK MESSAGE
MOVE.~ (A5)+, (A6)+ MOVE DATA (TERM TO HOST) + STORE STATUS

Word access is used so that at the end of each polling - 30 sequence each address/command has been incremented by two. The next polling sequence will then address the next connection pair.
The following table shows the expected execution time ` necessary to process one complete pollin~ loop for the 8 ~ .

.
- :

~27~3~'9 Megahert~ CPU:

FUNCTION UNIT # OF CYCLES CYCLES uSECS
Interrupting the Processor 44 44 5~5 Saving Register Contents 20 ~ 8 x 8 Registers 84 10.5 Setup for Polling Loop 20 + 8 x 8 Registers 84 10.5 Entering the Polling Loop 14 -r 6 20 2.5 Poll each Logical Connection 48 x 64 POLLS MAX3072 384.0 ~OOP instructlon Overhead4 + 10 per 8 POLLS 84 10.5 Restoring Register Contents2G + 8 x 8 Registers 84 10.5 10 Exiting from the Interrupt 24 24 3.0 -TOTAL MAXIMUM EXECUTION TIME 3496 469.0 - 21a -- :
.
.
.
: .. . . ~, ', .. . . . . . .

FOLLING LOOP SE6!UENCE DEFINITION
The following table show~ the utili~ation of the latches used to impiement the hardware assisted polling sequence. Rn "X" is placed at each step in the sequence where data is either clocked into a specific latch or a 3pecific l~tch's OUtp-lt i5 enabled.for a particular use. fieference the EtLOCI~; DIAGRAM QF
POLLING ASSIST HAkDWARE sht~ in Fig. 3 for the location of each latch.

TEFiMS LAT LAT LhT LAT LAT LAT LRT LAT LhT LAT LAT LAT LAT
---- 1 1 2 . 2 3 4 5 6 ~ 7 7 8 ~ SEQ
STEFS ---- CL~ ENA CLIC ENA CLK CL~C CLK CLt~ ENA CLK ENA CL~ ENA #
+___*___+___*___~___+___*___*___+___*___*___*___~___+___*
TST ~A~)+ ~ X I
TST tA1)+ 1 I X : X Z l X I I I 1 1 1 l l I 2 1 TST ~h2)* 1 1 I I X I I X I X I
MQVE (A~)~, 1 1 1 I X I I I I X I t I I X I 1 4 1 (A4)* 1 l X I I I I I I I X , I I I X 1 5 1 MOVE (h5)*, 1 I X I I l I I I I I X I I I I b l tA~)* I I I I X I I I I I I I X I I 1 7 1 *___*___*___*___~___~__ .,.___*___.,~.___*___~___.~___*___.i.___*
LATCH 1 - Holds the address of the Terminal Port and SlaYed E~it LQTCH ~ - Holds the address of the Host Fort and Master ~it LATCH 3 - Holds the st~tus register from the Terminal Fort DURPT
LATCH 4 - Holds the status register from the Host Port DUART
LATCH S - Holds the pointer used to address the Compare RAM
LRTCH ~ ~ Used to update the Compare RhM address pointer LATCH 7 - Used to ~Ipdate the Hardware Sequencer Status Ftyte LATCH ~ - Holds a character to be output to SlaYed Terminal Ports ;- NOTE: The outputs of latches ~, 4, and 5 ~re enabled during the - entire poling sequence.
The following table ~hows the utili~ation o~ the fiAMs used ta implement the hardware assisted polling sequence. An "X" is pl~ced at each step in the sEquence ~here data is either read into a specific F~AM or a speific ~AM's output is - enabled for a particular use. keference the ~L~Ch DlAGkAM OF
POLLING ASSIST HRPDWA~E for the location of eah kAM.
---- TEF;MS FOINTEF; COMPAF~E MAFPING MEMOF;Y SEQUENCE EiITS
- F;AM fiAM RAM A5CE5S
STEPS ---- ENAEILE ENA~LE ENhE~LE CYCLE 14 13 1~ 11 ~ ~ *_______+_ _____.,. _______+_______ .,.____________ __*
TST ~RC1~* I I : X I kEhD I ~ D
TST ~Ri)~ I I I X I F:EAD l ~:~ O 1 O t TST (R?~* I X I I l fiEhD I O C~
MOVE ~A3)*, I X : X ~ I F;EAD l Cl 1 O ,O
~R4~+ t X I l I lJFiITE I : 1 C~ 1 1 MOVE ~R5~+, I X : I I kERD I ~t 1~ 1 O
~R6)~ I X : I I WFiITE l t:~ 1 1 1 1 + * +--_____________~

.~

~27~

FFOGkAM~A~LE AFk~Y LOGIC ~PAL) ~OOLEAN SPECIFICATION
The following speci-Fi~tion is ~Ised to program ~he PAL
tha~ en~bles the kAMs and ~he bu~fers used to dire~tly access those kAMs th~t ~re a p~rt of the polling assist h~rdl~are.
This PAL ~150 generates the DU~kT a~knowledge ~DUACI~) and the FIFO Interrupt Fieset (FFF~ST) si~nals.

F~116L8 FAL DESIGN SPECIFICATION
PQTTEF~N 06-6(:)1FFU6 7/15/84 SUMCHEC~ = 5216 SEQUENCE DECODER 1 ~LO~IN FUSES = 6~$.2 ~15 A14 Al~s. A12 /IOEN
/WkITE /HDRAM DA5 ~16 GND
DAS~ XMAPEN~ /PTkEN~ /CMPENA /~4EN~
/~s`ENA t~lENA tFFkST ~DUACh VCC
IF~VCC) ~4ENQ = DAS2 * HD~AM * tA15 * X~14 * /Ai3 ;ADDR :~EI:'OXXX
IF~VCC) MRFENA = DAS * HDkAM * /~15 * /~i4 * /~ ADDk *EOOXXX
+ DQS2 * IOEN * /A14 * /A1~ * A12 ;Sl~D1 + DAS2 * IOEN * /A14 * A1~ * /A12 ;S2~D~
IF~VCC) ~lEN~ = DAS2 * HDkQM * /A15 * /A14 * Als. j~DDP $EO~XXX
IF(VCC) PTkENA = DAS * HDkAM * /A15 * t~14 * ~1~ jADDF ~EC)2XXX
+ DAS2 * IQEN * tA14 * ~ * Al? jS~D~
tWPITE * DA52 * IOEN * ~14 ;S4-S7~D4-D7 ~ WklTE * DAS * IOEN * A14 jS4-S7~D4-D7 IF~VCC) ~ENA = DQS~ * HDkQM * /A15 * A14 * tA1~ . jADDk *E04XXX
:~ IF~VCC) C~PENA = DAS * HDkAM * tAlS * A14 * tA1~ jADDk *E04XXX
+ D~S2 * IOEN * hl4 * t~ tA12 ;54-D4 IF~VCC) FFkST = D~S * IOEN * /A16 * ~15 * /A14 * t~ * t~12 ;SEQ 8 IF~VCC) DUACh = tW~ITE * IOEN * A16 * ~15 * tQ14 * tAls. * tA12 ;SEQ 8 '' .
~===~=--================================Q==a=========cc==========--=========

., . . .. : , : .
: . . .: .
.

FROGRA~A~LE AF;F~AY LOGIC ~FAL) ~OOLEAN SPECIFICATION
The foll~wing speci-fi~atiQn is ~sed t~ pr~ram the FAL
that enable~ the l~tches th~t s~lpplv variO-ls d~t~ during the hardware ~ssisted polling sequen~
This PAL also generates the enable~ for th~ b~lffers used to drive address (~5ENA) and dat~ (B6ENA) oLlt on the VE~SA~US, as well as the signal which enables the I!O boards (IOEC).
===============,==_=================~=========__=== ====
F~L16L8 FAL DESIEN SF~ECIFICATION
FATTE~N 07-7:)2FPU7 7/15/84 SU~CHECK = 6E72 SEQUENCE DECODE~ 2 FUSES ~LOWN = 84~
AlS A14 A13. A12 ~IOEN
~lRITE Ll~IT7 TE~MRDY HOSTRDY GND
DAS2 /IOEC /LlENA /L2ENA /L6ENA
/L7ENA /L8ENA /B5ENA /~6ENA VCC
IF(VCC) IOEC = IOEN * /Ai5 * ~Q14 ;DIRECT,S1,52,53 ~ IOEN * JLl~IT7 * HOST~DY * ~AlS * Al4 * ~A13 ;S4,S5 * IOEN * Ll~IT7 * HOST~DY * /A15 * A14 * ~A13 * A12 ;55 IOEN * ~Ll~IT7 * TE~MRDY * ~A15 * ~14 .* A1-~ ;S6,S7 + lOEN * ~15 * /A14 * fA13 * /A12 ;FF~ST,DUACK
IF(VCC) LiENA = IOEN * A1~ * /Q12 ;S2,D2,S~,D6 -~ IOEN * A14 * /Ql3 * A12 ;S55DS
IF~VCC) L2ENA = IOEN * A1~ * A12 ;S3,D3,S7,D7 * IOEN * A14 * /A1~ * /A12 ;54,D4 IF~VCC) L6ENA = DAS2 * IOEN * ~J~ITE * A14 * /A1.~ * A12 ;55,D5 IF~VCC) L7ENA = DAS2 * IOEN * WRITE * A14 * A13 * Ai2 ;S7,D7 IF~VCC) L8ENA = DAS2 * IOEN * LlBIT7 * IJRITE * /A15 * A14 * /A13 * A12 ;55 DAS2 * IOEN * LlBIT7 * /WRITE ~ Q15 * A14 * /Ai~ * A12 ;D5 . ~ DAS2 * IOEN * /W~ITE * A15 ~ /A14 * /Ai3 * Q12 ~D1 : * DAS2 * IOEN * /~I~ITE * AlS * A14 * /A13 ~ ~A12 jD4 i * DQS2 * IOEN * /WF;ITE * A15 * A13 ;D2,D~.,D6,D7 - IF~VCC) ~5EN~ = IOEN * ~A14 * ~A1~ * /~12 jDIRECT,FF~ST,DUACh IF~VCC) ~6ENA = DQS2 * IOEN * ~A14 ;DI~ECT,DUAC~,FFfiST,S1-S-,D1-D3 * DQS2 * IQEN * Q14 ~ ~A13 * /Q12 ;S4,D4 * DA52 * IQEN * /Ll~IT7 * A14 * /A1-~ * Q1~ jS5,D5 - * DQS~ * IOEN * Ll~IT7 ~ /WRITE * A14 ~ ~Q13 * A12 ;SS,D5 * DQS2 ~ IOEN * Q14 * Q13 jS6-S7,D6-D7 ~ 24 -, - ` ' ~ ' ~ ~ ' ' F~OG~A~MA~LE A~hAY LOGIC (FAL) ~OOLEAN 5PECIFICATION
The fallowing specifi~tion is used to p~ogr~m the FAL
th~t clocks da-ta into the l~t~hes useci to hol~ vario~ls data d~lring the h~rw~re ~ss`isted polling seqLlence.
This PAL also gener~tes the siyn~l CT~CLh~* used to ~lo~k the 4-bit counter that increments the Comp~re ~AM address pointer.

PATTE~N 08-8CI~FPU8 5/1~84 SOMCHEC~ -- 429_ SE~UENCE DECODE~ 7. ~LOWN FUSES - 519 ~15 A14 A13 Al~ /IOEN
/W~ITE Ll~rT7 L2~IT7 HOSTF~DY GND
DAS ~LlCL~; /L23CL~; /L4CL~ /LSCL~
/L6CL~; /L7CL~ /L8CLK /CTRCLh~ VCC
IF(VCC) LlCL~ = DQS * IOEN * /~14 ~ /~13 * A12 ;Sl,Dl IF~VCC) L?3CL~ = DAS * IOEN * /A14 * Al7 ~ /A12 ;S2,D2 IF~VCC) L4CL~ = DA5 * IOEN * /Ll~IT7 * /A14 * A13 * Ql~ ;S39D3 IF(VCC) L5CL~ = D~S * IOEN * /~14 * ~13 * Al~ jS3,D7 IF(VCC) L6CL~C = DAS * IOEN * A14 * /A13 * /A12 ;S4,D4 IF(VCC) L7CLI~ = DAS * IOEN * ~14 * A13 * /A12 ;S~,D~
IF~VCC) L8CL~ = DAS * IOEN * L2~IT7 * HOST~DY * A14 * /A13 * /A12 jS4,D4 - + DAS * IOEN * W~ITE * A15 * A14 * ~13 * /Al~ ;D6 ONLY
IF~VCC) CT~CLh~ = DAS * IOEN * /A14 ~ ~13 * Al_ ;53,D3 + DAS * IOEN * /LlE(IT7 ~ HOST~DY * A14 * /Al7 * /A12 jS4,D4 ============_========================================

:

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,, - `, .

~;~7~3~

PROG~ AEILE ARRAY LOGIC (~L) EOOLE~N SPECIFICATION
The following spe~ification is ~lsed to program the PAL
that defines v~rio~ts control signals on the I~O board.

PALl6LB PAL DESIGN SFECIFICATION
PATTERN 09-914FPU9 ~/lSt84 SU~CHECK~C ~E2 I/O E10APD DECODER FUSES ~LOWN = 4~2 RESET /DAS /FFRST /O~VER /IOEC
~DA52 ~DUACt; ~ACt;:IN /E~DENA GND
INTV ~CSENA ~DAT~ENA /FFSRST /QCI;ST
~ACKOUT /DTACKST tDISCON NC VCC

IFtVCC) CSENA = ACKIN * E~DENA * ~DISCON * DAS * IOEC * ~DUACK * ~FF~ST
IF~VCC) DATAENA = ACK~IN * E~DENA * ~DISCON * DAS? * IOEC * ~DU~C~ * ~FFRST
I ACKIN * E~DENA * ~DISCON * DA52 * IOEC * DUACK * ~FF~ST
OE~VER * INTV
IF(VCC) FFSRST = ACKIN * E~DENA * ~DISCON * DAS * IOEC * ~DUACK * FFRST
~ RESET
-~ IF(VCC) AC~CST - ACICIN * E~DENA * /DISCON * D~S ~ IOEC * DUACK * /FFRST
IF~VCC) ACKOUT = ACK.IN * ~E~DENA ~ IOEC
~ ACK~IN * DISCON
- IF(VCC) DTACKST = ACKIN * E~DENA * ~DISCON ~ DAS * IOEC

~.
:- ` ` .

. : . - . . . : .
- ' ' . . , , :
:-~i~7~

INTRO~CTION TO COM~D DESCRIPTIO~S
The Contention Switcher (CTSW) has many various commands whlcn are used to control the system s operation. The oper~tion of these commands is affe~ted by many different things.
These things include from which port the command is entered1 which mode of operation the CTSW i5 currently in~ and/or the connection status of any particular port. The commands are intended to be fle~ible, funtional~ and ~onsistently structured. ~ost of the commands can be conveniently abbreviated for ease of use. Options are available for obtaining command syntax information directly from the system.
The Contention Switcher operates in several different modes~
depending upon commands entered, battery backup status~ and a Normal/Service mode switch located on the front edge of the CPU
board. Thi~ switch i5 provided as an extra safe~uard against inadvertently destroying any configuration inFormation maintained in the battery bac~ed up portion of the system s memory. ~esides the SER~ICE mode that this switch defines, the system may be in either the SHUTDOWN or the NOR~L mode of operation. One other mode of operation that is halfw~y between these two mades is the S~UTDOWN IN P~OGRESS mode. When the CTSW i 5 commanded to shutdown either by command, or by the front panel p-tshb-ttton~ a delay occurs to allow users o~ the system enough time to cleanly terminate their connections.
Once the system enters the NO~MAL mode of operation, a llmited set of comm~nds are available to any terminal that ls eonnected to a contention 5wi t~her port. These commands allow a terminal to be able to connec~ to or disconnect from any one of the other ports in the system according to system configuration information. In the case af a port designated in the oonfiguration as the master over one or more slave terminals, a command is available that will cause the slaved terminals to receive a copy of the data being received received by the master terminal.
Commands are entered in response to th~ ~ ~ prompt. The prompt is displayed at any terminal after the tem i~ init~ally started and any character is typed at the terminal. In the case of a port that has already established a connection7 ~
prompt is obtained by entering an attention sequenc2. The sequ2nce consists of holding the break key down longer than the configured break timeout period, or by entering the number of breaks configured as the minimum break count required for attention before the end of the configured break timeou~ period. The prompt is also displayed when a configurable TRIGGER message is received by a connected port.

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:. :
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DESCRI PT ~ ON OF COM~ND SYNT~X

Commands are entered in response to the " >" prampt.
The following notation is used for describing the syntax of commands. ~11 other symbols are entered exactly as shown.
> The angular brackets enclose a symbol that i5 replaced ~y one of a class of symbols that it represents.
The vertical bar indicates that a choice is to be made.
Only one of the symbols separated by this delimiter is allowed to be entered.
{ ? Curly braces enclose syntax that is optional.
{ ~... Curly braces followed hy an ellipsis enelose syntax that is optional and may be repeated one or more times.
The general format of a command is~
C~cmd>} C ~<vname~-<val~l<val?}... ~ <val>C,<val~}... ~ /<opt> ~L
where~
<cmd> is the name of the command to be executed. If this field i~ omitted, is is assumed to be a CONNECT command.
<vname> is the name of a pa~ameter with one or more associated values.
val~ is a numeric or symbolic value associated with a parameter~
~opt> is the name of a parameter without an associated value.
~lphabetical character~ may be entered in upper and/or lower case.
~11 commands will be converted to uppercase before interpretation~
Each command, ~ption, and/or value name may be abbreviat2d to its least amblguous~farm.
Values may be entered with or without their preceding value names, n however, if the value names are omitted the values must be entered in the exact ofder shown in each command desc~iption. If a command is entered followed by a "/?" (slash~question mark), all available option and/or v~lue names for that command will be displayed.

- , . - . .
. : . : .

INDEX TO CO~ND DESCRIPTIONS

The following commands are only available at the command console, and only if the Normal/Service switch on the CPU board is in the Service position.
DEPOSIT - ~lter a memory location EX~MINE - E~amine memory loc~tion 5 MEMTEST - Exercise memory locations INITI~LI~E - Initiali~e battery bac~up memory The following commands are only available at the command console, and only 1~ the sy~tem is in the shutdown mode.
~QWNLOQD Receive configur~tion information from a host port.
DU~RTTEST - Execute Duart Diagnostic te~t RESET - Perform a System ~eset SEQUENCER - Execute Sequencer Diagnostic ~est ST~TUP - ~egin NO~MAL operational mode UPLO~D - Transmit configuration in~ormation to a hQst port.

The following commands are available in both shutdown and~or operatiqnal mode at the command console only.
GROUP - Establish a name for a collection of ports.
LOGGER - Start/Stop loqging activity for specified ports.
~ESS~GE - Establish a symbol name for a string of text.
OVERRIDE - Cause s}aved terminals to copy master terminal.
SETUP - Alter configuration parameters of system port~.
SHOW - Display configuration parameters of system ports.
SHUTDOWN - End operational mode.
ST~TUS - Displays the operational status of system ports.
TIME ~isplay or set Time of Day clock.
.

The following commands are available at any port only when the CTSW is in the NO~M~ operational mode.
OONNECT - establish a port to port connection DISCnNNECT - break a port to port connection OVER~IDE - override slaved terminal'~ connec~ions ~ .

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' . . . . `' ., - : .
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,: . .. . :
.. . , , ~ ., ~ ... . .. ' :
:
~ ' , . ,: . .

C~NNECT CCNNECT PORT CO~MAND CONNECT

CONNECT ~ ~TO= } <group> C /F~OM= } <term~ ~/W~IT=} <nwait>
wheres ~group~ identifies the port or group of ports to connect to~
<term~ identifies the port to be connected. Thi 5 option may only be specified from a privileged part.
<nwait~ is the gueuing threshhold indicator. If the number of other connection requests already waiting for a port from the desired group exceeds this number, then the connection request will not be queued. The default queuing threshold i5 three connection requestsS

The CONNECT ~ommand establishes a connection to another port.
- If the command is entered without specifying any parameters; the port will be connected to one of the def~ult connection por~s, if any. If a connection was temporarily suspended as the result of break attention ~equence or a T~IG~E~ match, the connection will be resumed instead.
When the CONNECT commands specifie~ connection to a group of ports, the first available port in that group with a config~ration compatible with the port to connect ~ill be used a~ the port to connect to. If all of the available ports in the group are already connected to other ports, then the connection request is placed in a queue, provided that the number of connection requests already queued for thi~ group is less than the threshhold s4ecified by th~
/W~IT parameter.
- If there are no ports in the specified group that have a compatible config~lration (baud rate, bits per character, ~t~.) with the port to be connected9 then ~n appropriate error me~sage will be displayed.
1~ a GROUP name i5 entered in response to the " -- ~" prompt, it will be interpreted as if the group name had been specified un the "/TO" option of the CONNECT command.

. .

~ 30 -... . ..

~ - . . ' - ' ' ~ ; .

.

DEPOSIT DEPOSIT ~E~ORY CO~AND DEPOSIT

DEPOSIT { /ST~RT= } ~addr~ { /DAT~s ~ <data>
~ /INTERV~L= ~ Cintv~ EPE~T- } <rept>
{ /BYTE t /WO~D , /LONG }
where~
<a~dr~ i5 Up to six he~ digits defining the 5y5tem memory address to modify.
<data> is the data to stnre at the specified address~ ~n error message is displayed if the data will not fit into the memory entity type selected~ ~ mcmory entity i5 either a byte~ a word~ or a long~ord of memory.
<intv~ is the interval between entities of memory to modify, If specified as ~ero~ the same memory location i5 repeatedly modified. If 5pecified as one~ seq~ential addresses are modified. If specified to be two every other memory entity will be modified. Et cetera~ et ceteran <rept~ is the number of times to repeat the command. If ~ero is specified, or no value follows the /~EPE~T option~ the command i5 repeated indefinitely~ or until a break is typed at the console.
~BYTE causes one byte of memory to be modified~
This i5 the default system memory display format~
~WORD causes one word of memory to be modified.
Only even addresse~ may be modified in this mode~
/LONG causes one longword of memory to be modified.
Only even addresses may be displayed ln this mode.
: ' The DEPOSIT Command modifies a system memory location. This command may only be used if the Narmal~SerYice 5Wi tch on the CPU
board is in the Service position. The modified memory location i5 displayed in hexidecimal after the memory location i5 changed.

. ' ' ' ~` :

DISCONNECT DISCONNECT PO~T COMM~ND DX5CONNECT

DISCONNEOT ~ ~PORT= } ~pname~ -where:
~pname~ identifies the port to be discDnnected.

The DISCONNECT command break~ a connection between portsO
When thi~ command is entered on the command console, it requlres the name of a port to disconnect. If the specified port i5 not connected, an error will be disp~ayed~
. When this command is entered at a terminal port~ that port is defined as the port ta disconnect and the /PORT option i5 not allowed.

; . .
`
, , DU~RTTEST TEST DU~TS CO~M~ND DU~TTEST

DUA~TTEST ~ /~O~D= } ~bo~rd> ~ fCHIF~ ~ <chip~
~ /TESTS= } <tnum>~,Ctnum>} C ~REPE~T- } <passes~
{ /~NT~RV~L= } ~intv> { /W~IT= ~ ~wait> { /LOOP
where:
~board~ defines which board to exercise~ Board ~ero refers to the CPU board. ~/0 boardc are numbered from one to four.
~11 o~ the I/O ~oards are tested if the ~O~Rg option i5 not spec i ~ i ed .
Cchip~ identifies a specific ~U~T chip to ëxërcise. ~ll DU~Ts on the selected board are e~ercised if this option i5 not specified.
~tnum~ identifies a specific desired DU~RT test to execute.
- If this option i5 not specified, then all of the DU~RT
tests will be exec~ted.
~passes~ is the n~lmber of times to repeat the test r If ~ero is specified, or no value follows the /R~PE~T opti~n, the command is repeated indefinitely, or until a break i~
typed at the terminal.
<intv~ specifies the interval between pass completion messages.
~f specified as .ero, e~ch test identifies itself on a separate line along with a P~SS/F~IL indicationO If the INTERV~L is specified as a non-~ero value9 then the test identification will not be produced, Inless a test fails.
If all of the tests specified pass 7 then the message that ~- indicates the number of sucessfully completed passes is output at the specified interval between p~ss messages.
<wait~ specifies a w~it count. ~ delay of approximately l.~S
microseconds per count is added at varlous points during the test i n order to visually identify ertain specific events by observing the ~EDs on the boards. ~ wait co~nt of ~ero indicates that the test should run ~t full speed.
/LOOP causes the test to loop on any condition that generates an error. This allows visual display of signals on an oscilloscope.

The DU~RTTEST Command exercises one or more DU~rs~
The test is divided into three major parts~ The first part of-the DU~RT tests exercises one DU~RT at a time. The second part of the test exercises one I/O board at a time, and the third par~ of the test exercises all of the I/O boards at the same time~ a~ wel~ a~
the interrupt handling circuitry on the CPU Board.
The 4irst part of the DU~T test is divided into sevzn test~.
Test ero writes and reads back all 2~6 pos~ible 8-blt data patterns to and ~rom the D~QRT interrupt vector register. Test one ~rites and reads back the same data pattern~ from both mode registers of DU~RT
channel f),. Test two c:heck:s the mode regi sters of DU~RT channel El~
.

:

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. . :," . .

lZ~7~3~
DU~RTTEST TEST ~U~RTS CO~ND (continued~ DUA~TrEST

The DUQRT i5 then initiali~ed and both DUART channels are setup into the data loopbac~ mode. Test three sends all of the a-bit data patterns to the channel Q transmitter and chec~s them when they are received at the channel ~ receiver. Test four tests channel B of the DU~RT in a similar fashion.
Finally~ test five enables DU~RT interr~lpts for Channel Q and commands the channel ~ transmitter to ST~RT ~RE~. When the interrupt is received from the channel A receiver, it is chec~ed in order to verify that it came from the correct DU~RT. The channel ~ receiver buf~er i5 checked for the correct break indicator character and the channel ~ transmitter i5 commanded to STOP ~RE~K. When the next CHANGE IN ~RE~K interr~lpt is received and verified~ or if the interrupt is not received within a fixed timeout period, further interrupts fro~ channel A of the ~U~RT are disabled. Test six i5 a similar test for channel ~ of the same DU~RT.
The second part of the DU~T test begins with test seven, which is executed only after all si~teen DU~RTS on an I/a board have been tested. Initially, ~11 normal DUART interrupts are prevented from interrupting the CPU by writing to the CPU statu~ register. Then all sixteen DU~RTs on the selected I/O board are eaused to interr~pt.
This generates a FIFO FULL condition on the I~Q board ~hich causes a FIFO FULL interrupt at the CPU which, after being accounted for~
will allow the processor to resume normal DUART interrupt handling.
The test will fail if all of the expected interrupts are not received within a fixe~ timeout period.
The third part of the DU~T test begins with test eight~ which executed only after the first two parts of the test are successfully completed on all of the selected I~O boards. Thi 5 portion oF the test simulates the complete operating environment of the contention switcher including the seq~encer. The mapping R~M is setup to send the characters received by PORT A of the first DU~RT t~ the transmitter of FORT ~. The characters laoped back fro~ PORT B are then moved by the sequencer to the PORT ~ transmitter of the next ~U~RT being tested. ~11 of the DU~RTs under test are similarly chained together except that the characters received at PORT ~ of the last DUART in the ch~in are not moved by the sequPncer. The Compare R~M is initiali~ed with 8 strin~s of 1~ decending values~
The Pointer R~ pointer for each DU~RT under test i5 initialized to point to on of the 8 compare strings. The sequencer status byte for each DUART ~lnder test is cleared. A simulated polling sequence is started at regular intervals and the test begins.
~ 56 character patterns are pushed into the PO~T A transmitter of the first DUQRT and each character is checked ~5 it is received at PORT ~ ~f the last DU~RT. I`f ~11 of the characters match~
and the sequencer status byte for each DU~RT indicates that the compare string matched, the test reports successful completion.

.: -: '......... . , ~

7~

EXAMINE EX~INE ME~ORY CO~AND EXA~1INE

EXA~INE ~ /S-rA~T= } <addr> ~ /COUNT= ~ ~count>
~ /INTERVQL= . ~intv~ C /~EPEAT= ~ ~rept~
C /BYTE I /WO~D ' /LO~G }
where:
<addr~ i5 the first system memory address to examine and display.
The value entered is assumed to be in he~idecimal unless otherwi~e indicated.
~count~ is the total number of memory entitys ~o examineO ~ me~,ory entity is either a byte, a word, or a lonqword of memory~
The value entered is ass~med to be in decimal unless otherwise indicated.
<intv~ is the interval between displayed entities of memory.
If specified as 2ero, the same memory location is repeatedly accessed. If specified a~ one, sequential accesses are made. If specified to be two every other memory entity will be acessed. Et cetera~ et cetera.
The value entered is assumed to be in decimal unless otherwise indicated.
~rept~ is the number of times to repeat the command. If 2ero i5 - specified, or na value follo~s the /REPE~T opti~n, the command i5 repeated indefinitely, or ~ntil a break i5 typed at the console. The value entered is assumed to be decimal unless otherwise indicatedl /~YTE ca~ses the memory display to be formatted in bytes.
This i5 the default system memory display format.
- /WORD ca-lses the ~emory display to be formatted in word~.
Only even addresses may be displayed in this mode.
/LONG causes the memory display to be formatted in longwords.
Cnly even addresses may be displayed in this mode.

The EXA~INE Command examines a block of 5y5tem memory. This command may only be used if the Normal/Ser~ice switch on the CPU
board is in the Service position. Up to sixteen by~es of memory are displayed on each line, in hexidecimal numbers formatted appropriately for the selected memory entity type. Each di 5pI ayed ~- line has the ~SCII character representation for th~ data on that line appended to the end of the line. If a byte o~ data ha~ no corresponding ASCII representation, a period (.) is display.ed.

- - 35 ~

: ' ,, r ,, , . , , ~ .
. .' . :
- .
.
, ., ~ ' ' ' , ' :
' ~

.

G~OUP DEFINE G~UP OF ~ORTS CO~MRND GROUP

G~OUP { /N~ME= } <group~ { /QD~= } ~port~ C ,<port>
{ ~DELETE ~ C ~REMOVE= } <port~ C ,<port~ }
~ /REN~E= } <rname~ ~ /DELETE }
where:
<group> identifies the group to be displayed~ modified or renamed.
<port~ identifies a port or group o4 ports to be added to or removed from the group /DELETE indi~ates that the group is to be dissolved ~11 ports ~re removed from the group and the group name and the memory space alloc~ted for the group i5 released.
~rname~ is a ne~ identification for the same grDup. ~ny references to the old group name continue to refer to the new group~

The GROUP command establishes a collection of ports If a group name is specified with no other options, then a list of the port~
belonging to that group is displayed Ports may be added to a new group or an already existing group Ports may only be removed from already e~isting groups.
- I4 no options are specified on the G~OUP command, a list of all of the e~isting groups are displayed ~ ma~imum of (???) groups may be established at any one time Port groups have many useful p-lrposes in the ~ommand structure The mast important use of a group is to identify the ports that the CONNECT command will use to satisfy a connection request~ Other uses - include identi4ying ports to be logged ~LOGGER command), ports to be slaved to other terminals (OVE~IDE c~mm~nd), and ports to change the configuration of ~STUP comm~nd).

': ' ' ', ' " , ' ~ . ~ ' ' ' . ' ' ~. ' ~. . . ...................... . :
:, :

INITIhLIZE INITI~LIZE CONFIGUR~TIO~ ME~O~Y INITI~LIZE

INITIALIZE ~ ~ALL I /CO~FIG ~ ~SYM~OLS }
where:

/QLL causes all battery backed-up data structures to be initia~ized~
~CO~FIG ca~ses onl y con~iguration information to be 1 ni ti al i zed.

~SY~OLS causes only symbol information to be initialized.

The INITI~LIZE comm~nd initiali~es data structures contained in the battery backup memory. ~ny previously entered configuratiQn information and~or symbol definitions t groups 9 messages, ett...~
are destroyed. This command may be executed only from the console and only if the normal/service switch on the CPU board is in th~
SERVICE positi on .

~ESET SYSTEM ~ESET CO~ND ~HUT W WN

RESET

- This command performs the equivalent ~unction ~f a ~ystem reset. ~ system reset can be caused by system power up~ watchdog timeout9 or by pushing th~ reset button on the front edge o~ the CPU board. System reset is the only point in time that th~
SERVICE mode of operation may be entered. ~f th~ put into normal operation ~ith the STARTUP command, the SERVIC~ mode will be ~- terminated9 and another system reset is required in order to get hack into service mode. The ~ESET command may only be e~ecuted when the system in in the SHUTDOWN mode.

. . .
''' ' ~'' . ~ ' , .

LOGGER LOGGER PORT CONTROL COM~QND LOGGER

LOGGER ~ /PORT= ~ <pname~ ~ /ST~RT I /STOP
where:
<pname> identifies the port or group o~ ports to be logged.
~ST~RT indicates that logging i5 to begin~
/ST~P indicates that logging is to be terminated The LOGGER command causes ~11 activity of a port or group o4 ports to be logged at the logger port. ~ctivity logged includes conn~ctions ta the port, disconnections of the port and any failures related to the port.
If the LOGGER comma~d i 5 entered without either the /START
or the /STOP option~ then the logging statLIs of each affected te~minal will be toggled to be opposite to its previou~ state.

.: ` ' ' , ' . . .- ' .- ~ ' -, ~ ~r~

MEMTEST TEST l lEMORY COMM~qND i~lEMTEST

ME~TEST { /START= ~ <addr~ ~ /COUNT- } <count>
C /INTERV~L= ~ <intv> C /REPEAT= } <rept>
{ /~YTE ~ ~WORD : /LON~ }
where n <addr> i5 Up to six hex digitc defining the fir~t system memory address to e~ecise.
<count~ is the total number of memory entitys to test. ~ memory entity i5 either a byte~ a word7 or a longword of memory.
<intv? is the interval between tested entities o~ memory.
If specified as ~ero, the same memory location i~
repeatedly tested. If specified as one~ sequential acce~ses are made. ~f specified to be tw~ every other memory entity will be tested. Et cetera~ et cetera.
~rept~ is the number of times to repeat the commandO I~ zero is specified~ or no value follows the ~REPEAT option, the command i 5 repeated indefinitely, or until a break is typed at the console.
~YTE causes the memory display to be formatted in bytes.
This is the default sy~tem memory display forma ~WORD causes the memory di 5pl ay to be formatted in words.
Only even addresses may be displayed in this mode.
~LONG causes the memory display to be formatted in longwords.
Only even addresses may be displayed in this mode.

The ~EMTE5T Command exercises a block of system memory. This command may only be used if the Normal~Service switch on the CPU
board is in the Service position. The test is divided into three parts.
The first test exercises memory one byte at a time. Various data patterns are writ~en to and read back from each byte of ~em~ry in the speci~ied area~ If the data read b~ck from a memory location does not ~erify9 the memory address, expected data~ and actual data read back ar~ output to the command consol e.
The second test i5 similar to the first except that the memory is tested one word at a time instead of one byte at a time. If the ~tart address of the memory area to test is odd, this portion o~
the memory test will not be run. This allows testing of memory areas that are byte-addressable only.
The third test writes a test pattern to each byte of memory in the specif~ed area and then ch~cks other locations wlthin the specified area to insure that they have not been modifiedv If a loca~ion that should not have been modified is chang~d~ the memory address, the modified mæmory addre~s, and the actual data read back are output to thæ ~om~and c~ns~le.
_ 3~ _ - . . . . .. .
.
- , . - - . ' ...... . . ' . - , .. .. .
, ~ .' ' ~--MESS~GE DEFINE MESS~GE COMM~ND ~ESS~GE

~ESS~GE ~ /NQME= } <name> ~ ~EXIT= } <char> ~ /REN~E3 } <rname~
~ /QSSOCI~TE- } <aname> ~ /DELETE ~ C /TRIGGER
where:
Sname~ identifies the message to be displayed, modified or copied.
<char> indentifies the character which will identify the end o~
the message text. The default message te~t termin~tQr i5 a carriage-return character. This option must be used if a multiple line message is to be entered.
<rname~ is a new name for the same message. ~ny reference~
to the old message name continue to refer to thc same message text~
~aname~ identifies the name of a trigger message to associate thl~
message ~ith. When ~ port th~t use5 the associated trlgg~r is disconnected froml this message is transmitted to that port. The specified message should cause the host computer attached to that port to logoff any user logged in at that port, and/or any other desired actions upan disconnect.
/DELETE indicates that the message is no longer required. Any text associated with the message name as well as the memory space allocated for the message name itself is released~
If there are ~ny references to the message name to delete~
an error message will be displayed and the mess~ge will not be dele~ed~
/TRIGGER indieates that this i5 a disconnect trigger ne5~age.
The me~sage text may not exceed 16 character~.
A question mark in the message text will rnatch any character in that position.

~ The MESS~GE command establishes a named text string. Thi~ teKt i5 then referenced by oth2r commands. The total number of characters defined by all of the message strings may not exceed ~???~
If the /T~IG~ER optio~ is specified on the ~E55AGE command, then the text associated with the messaqe name 1~ used to trigger a disconnect timeout. If no characters are received from the terminal port within the specified timeout period, after the tr~gger string has been recei ved f rom the host port, then the connection b~tween the two ports wl 11 be termi nat~d. If there is a message ass~ciated this trigger it will be transmitted to the host port as p~rt of the disconnect sequence.
~ max~imum of eight (8) trig~ r messages may e~i~t at any one time. ~ny question mark characters specified in the trigger text will match any single ~haracter receiv~d fro~ the ~05t port in that character positlon. The trigger message cannot be longer than a maximum of sixteen (16) chara~ters.

~ 40 -.. . . .
- , . ........... .~ ~ ' - - .

OVERRIDE OVERRIDE S-~VE PORTS COMMAND OVE~RIDE

OVERRIDE { ~PORT= ~ <pname~ ~ /SET ' /CLEAR }
wheres ~pname? identifies the port or group of port3 to be overridden.
/SET indicates that override i5 to be established /CLE~R indicates that override is to be terminated The OVERRIDE command causes a port or group of ports to tempararily receive a copy of all data received at the terminal port that is configured as the master for the selected ports.
Th~ 5 command may be entered from any terminàl, however it will only affect ports which are configured with /M~STER set to the port that the command is entered fro~.
If the OVERRIDE command i 5 entered without either the /SET
or the ~CLE~R option, then the override status of each affect2d terminal will be toggled to be opposite to its previous state.
If no ports are pecified on the OVERRIDE command then all ports which are configured with ~M~STER set to the pnrt that the command i5 entered from are a~fected. If the command is entered from the command console~ al 1 ports that have ~M~ST~R set to any port other than NONE will be affected.

.

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.

S~QU~NCER TEST DU~RT SEQUENCE~ COMMA~D SE~UENC~R

SEQUENCER C ~ST~RT- } <start~ { /END= } ~end~
C /TESTS-`} ~tnum~C,~tnum~ ~ /kEPE~T~ ~ ~passe~
{ ~INTER~L= ~ Crept> t ~WAIT~ } ~wait~ ~ ~LOOP
where:

~tnum~ identi~ies a specific desired DUART test to execut~.
If this option i5 not specified, then all of the DUART
tests will bE ~ecuted.
<pa55e5> is the number of times to repeat the test. If ~ero is specified, or no v~lue follows the /RFPEAT option, the command i5 repeated indefinitely~ or until a break is typed at the terminal.
<intv> specifies the interval between pass completion me~sages.
If specified as ~ero, each test identifies itself on a separate line along with a PASS/FAIL indicaticn. lf the INTERV~L is specified a5 a non-zero value, then the test identification will not be produced, unless a te~t ~ail5.
If all of the tests specified pass7 then the message that indicates the n~(mber of sucessfully completed p~se~ i~
output at the speclfied interval between pas~ m~ssages.
<wait~ specifies a wait count. A delay sf approximately 1.2~
microseconds per count i5 added at various points during the test in order to visually identi~y certain speclfic events by observing the LEDs on the boards. A wait ~unt of zero indicates that the test should run at full speed.
/LOOP causes the test to loop on any ~ondition that generates an error. This allows visual display of ~ignals on an oscilloscope.

The SEQUENC~R Command exercise~ the sequencer logic on the CPU board. The test is divided into several steps. The first three steps run memory t2st routines on the Compare, Mapping and Pointer RA~s. The fourth step writes all 256 po~sibl~ characters and reads back from the latch used to hold the character~ copied to slaved terminals. The f~fth and sixt~ step tests all 128 posslble DU~RT
addresses that can be latched into the two DUART addre~ latche~.
Th~ seventh step writes all 256 posible statu~ value~ to both DUART port status byte latches and checks the sequencer status byte for correct settings. The eigth step checks all 256 character patterns against 25~ different character patterns stored in the Compare R~ by using the sequencer comparator and checking the sequencer ~tatus byte for correct setti ng of the message match bi t .
The ninth step tests that the pointer that is used to addres~ the Compare RA~ can be incremented thru all compare R~ addresses and that it resets to the beginning of the messag2 when a character does not match.

, ~ ` ' '` ' `, -~z~

SETUP SETUP PORT CONFIGUF~TION CO~M~ND SETUP

SETUP ~ /PORTS= } ~LL ' <pname~ pname?}
UD= } 9~00 1 7~0~ ' 4800 1 7400 t ~QOO I 1800 ~12~ 00 ~ 300 ~ 150 ) 134.5 ~ 110 1 7S
~ /BITS_PER_CH~R= ~ S t b ~ 7 ' 8 { /STDP ~ITSs ~ 1~0 1 1.5 . 2.0 C /PARITY- ~ EVEN ~ OD~ 1 ~ARK ~ SP~C~ I NON~
/TIMEOUT= ~ ~tmo> ~ /TRIGGER~ ~ ~trmsg~ O NONE
{ /W~LCOME- } <wmsg~ ~ NONE { /CONNECT- ~ Crname>
/M~STER= ~ ~mport~ : NONE ~ /RESTRICT- } <rname~ ~ NONE
C /PRI~ILEGE= } CONFIG I DIAG I INFO I OPER
{ /DIS~BLED : /ENA~LED } { /~ODE~ O~ODFM
~ ~STARTED } C /LOC~ED
where:
<pname> i5 a port identifier or group name identifying the port or group of ports to be configured.
<baud> specifies the baud rate of the specifiDd port or ports.
Initially, all baud rates are set to 9~00 baud.
/~ITS specifies the number of bits per character for the port or group of ports specified. Initially, all ports are are set to send and receive 8 bits per character.
/STOP specifies the length of the stop bit used ~or the port or group of ports specified. Initlally, all ports are are set to send and receive 1 stop bit per character.
/PA~ITY sp~cifies the parity type of the specified port or port~.
Initially, all ports are set to /PA~ITY-NONE.
<tmo~ speci~ies the number of minutes of inactivity before - an ~LEX> prompt is automatically issued~ I~ the prompt - is not responded to within i5 seconds a disconnect will occur.
<trig> specifies one of the logoff trigger messages. If connected to a port that has a trigger specified, when the trigger message is received from that port, an ~ prompt i~
automatically issued.
~wmsg~ specif ie5 a welcome message. This message is sent to the port when the port is first issued an ~ ~ prompt.
<connect~ i5 a port identifier or group n~me identifylng the port or ports this port is connected to by default~ Refer to the /ST~RT option and/or the CONNECT command for detail.
<master> is a port identifier or group nam~ identifying the port or ports which may s~erride this port s connection.
Initia}ly all ports ~re ~ASTER = NONE.
<rstrct> i5 a port identifier or group name identifying the port or group o~ ports that are allowed tu connect with thi~
port. Initially, there are no restriction~ on any ports.
- ~3 -' ' .: . :
. .

~7~3~

SETUP SETUP PORT CONFIGUR~TION CO~ND ~continued) SETUP

/PRIVILEGE indicates which kind of -~ commands are to be allowed to be e~ecuted at the port ar ports bei ng configuredO
/DISA~L~ mark~ the port or group of ports as unavailable.
/ENA~LE marks the port or group of ports as availa~le.
~11 responding port~ are initially enabled.
/MODEM identifies the port or group of ports ~5 being connected through a modem. This setting i5 only valid for the - first ou~ of e~ch four ports.
~NO~ODEM identifies the port or group of ports as being directly connected. This i5 the initial setting f~r ~11 ports.
/STARTED identifies the port or group of ports to be automa~ically connected upon system startup. The port will be connected to one of the ports defined by the /CONNECT option.
/LOC~ED identifies the port or group of ports as being permanently connected. Prompts, timeouts and triggers are disabled for each port with the /LOCKED attribut~.

The SETUP command is used to alter or display the configuration parameters of one or more ports. If the SETUP command ~s entered with no other sptions, the configuration o4 all of the ~ort~ is displayed. If the name of a port or group of ports is the only supplied parameter, then the configuratien p~r~meters are displayed for those ports only.
~ ltera~ion of the configurable par~meters for a port will only affect the port upon reinitialization of that port~ ~11 ports are reinitiali~ed when the system-is initially started.
When a port i 5 disabled, no new connections are allowed to be made to or from that port. ~ny existing connectlon remains valld until terminat2d in the normal f~shion. Connections may be forced fro~ any privileged portO
I~ a trigger mPssage i5 specified for a port~ then during any connection to that port, the data stream received from that port is continuously monitared for the specified me~sag~. Whenever the specified message is received from the triggered port, a timeout sequence is started for that connectionO If no characters are sent to the triggered port before the end of the speclfied timeout perlod, the connection will be terminated.

. .

: . - , . . ~ - .
- . .

- , :
-': . ~ . . :: .
.

SHOW SHOW PORT ~ONFIGURATION COM~ND SHOW

SHOW { /GROUP= } ~LL ' ~group>{,<group>~
~8~UD- ~ q6~ ' 7~0 4~00 ~ ~400 ' ?000 ~ 1~00 ~1~00 ~ 600 ~ ~00 t 1~0 ~ 134.5 1 110 1 7S
/8ITS_PER_CH~R= } 5 ~ ~ 1 7 1 /STOP_BITS- } 1.0 ~ 1.5 1 2.0 C /PARI~Y= } EVEN ~ O~D ~ ~RK I SP~C~ ~ NONE
{ /TI~EOUT~ } ~tmo> t /TRIGGER- ~ ~trmsg> ~ NONE
C /WELCOME~ } ~wmsg~ I NONE C ~CONNE~T~ } <cname~
C /M~STER= } <mport~ : NONE { /~ESTRICT= ~ ~rname> ' NONE
~PRIVILEGE= } CONFI~ I DI~G ' INFO ' OPER
/DIS~LE~ ' /ENA~LED ~ ~ /MODEM ~ /NOMODEM
{ /ST~RTE~ ~ C /LOCKED } C /ZPRIV }
where:
~group> is a port identifier or group mame id~nti~ying the port or group of ports to show the configuration of.
~ba~ld> restricts the command to display only those ports which are configured with the specified baud rate.
~ITS restricts the command to display only those ports which ar~ configured with the specif ied number of ~ITS pcr character.
/STOP restricts the command to display only those ports which are configured with the specified stop bit length~
/P~RITY restricts the command to display only those ports which are configured with the specified /P~RI~Y setting.
<tmo> restricts the command to display only those port~ which are configured with th~ specified TIMEOUT period.
<trig> restricts the command to display only those port~ whi~h ~re conflgured with the specified TRIGGER message~
<wmsg~ restricts the comm~nd to display only those ports which are configured with the specified WELCOME message.
-- <master~ restricts the command to display only those ports which are config~red with the specified master port~.
<rstrct> restricts the command to display only those ports which have the specified connection restrictions.
/PRIVILEGE restricts the command to display only those ports which hav~ the specified set of privileges.

.
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~7~

SHO~ SHOW P~T CONFIGURATI~N COM~ND 5HOW

/ENA~LE restricts the command to display only those ports which are enabled.
/iIS~BLE restricts the command to display only those ports which are disabled.
~MODEM restricts the command to display only those ports which are configured as being connected to a MQDE~. ' ~NOMODEM restricts the command to display only tho~e pQrts which are configured as not being connected to a ~ODE~.
/STARTED restr$cts the command to display only those ports which are configured to be connected upon system startup.
/LOCKED restricts the command to display only those ports which are configured such that their connections are LOCKED.

The SHO~ command i5 used to display the configuration parameters of one or more ports. If the SHOW command is enter~d without parameters9 the configuration of the port that the command was entered from 1~ displayed.
Specification o~ any of th~ configurable parameters will restrict the display to only those ports that are configured as p~r the parameters specified.

-' ' ' , .. ~ , :

STARTUP ST~RT ~PER~TION~L MODE COM~AND ST~TUP

ST~RTUP

The ST~RTUP command causes th~ contention switcher to enter the oper~tion~l mode~ Diagnostic commands are disabled, permanent anJ/~r t~mporary connection~ defined in th~ con~iguration tabl~s are established 9 and all other enabled terminal ports are allowed mak~ connections. This command may only be entered at the command consol~.

SHUT W WN END GPER~TIONAL MODE COM~AND SHUTDUWN

SHUTDOWN { /WAIT- } <wait~ { /MESSAGE= } <mess~
wheres <wait~ i5 the number of minute~ to wait before shutting down.
The default shutdown delay i 5 5 minutes.
<mess> specifies a messctge which will be broadcast to ~11 connected ter~inal ports, indlcating the reason for shutdown or other appropriate message.

.
- The SHUTDOWN command causes the contention switcher to exit the operational mode. Initially, all terminal ports are di~abled from establishing new connections. After the specified waiting period, all logical connections are broken and the CTSW entPr~
the shutdown mode.

~ ..
..

~: :

~L27~; 1~
ST.qTUS D I SPLF~Y F~OF~T ST~TU5 COIvlMF~NO ST~TUS

ST~TUS C /G~OUP= } ~LL ' <~roup~C ,~group~}
C /QUEUFS } ` { /SYM~aLS }
where:
~group> displays information about the current state of the selected port or group a~ ports.
/QUEUES displays information about the current ~tate of the variDus system queues.
/SY~OLS displays in~ormation ~bout the system symbol table.
;

The ST~TUS command i5 used to display in~ormation about the operating state of the syste~. If the ST~TUS oo~mand i~ entered without specifying any parameters, all available statu~ infor~ation is displayed~

' ., : - . . ~: : , .. . . . :
~.. .. . ..
. , , , .: ` ' ~ . :`
: `

TIME DISPL~Y/5ET TI~E OF D~Y CD~ND TI~E

TIME C /5ET }
where~
~SET indicates that time and date are to be set.

The TI~E command displays the system date and time. This command may be entered from any terminal port.
If the TI~E command i5 entered with the /SET option then the the current date and time is prompted for~ The /SET op~ion is only allo~ed from the command console port.

. ~ ' ' ' ' - - . - ,. : : :, . .

,' ': ~. ' . , ' ' - . :

Claims (5)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. Electronic switching system for making logical connections between a plurality of computers and a plurality of computer terminal devices comprising, a plurality of asynchronous receiver-transmitters (ART) for converting serial binary data to and from parallel binary data, one ART for each said plurality of computers, respectively, and each of said plurality of computer terminal devices, respectively, and means for connecting each respective said computer terminal devices and computer to an ART, respectively, a microprocessor, memory means controlled by said microprocessor for storing the identity of each of said plurality of computer terminal devices and each of said plurality of computers and the respective ART to which they are connected and a connection table of current logical connections between pairs of said ARTs, sequencer logic means, controlled by said microprocessor and the data stored in said memory means including said table of current logical connections, for receiving connection request signals from one of said terminals for connection to a specific one of said plurality of computers and sequentially establishing a logical non-metallic connection between the ART to which said one of said terminals is connected and the ART to which said specific computer is connected so that the connection and data transfer is transparent and a maximum utilization of each of said plurality of computers is achieved.

2. Electronic switching system as defined in claim 1 wherein there are a plurality of ports on said selected ones of one or more computers, each of said ports being connected to one of said ARTs, respectively, and means for selecting a port of a computer for a requesting terminal to connect thereto.

3. Electronic switching system as defined in claim 1 including means electrically connected to said microprocessor for monitoring and comparing information data exchanged between logically connected ART pairs to detect any hiatus in data transfer for a predetermined period of time, and generating a disconnect signal for said logically connected ART pairs.

4. Electronic switching system as defined in claim 3 including self-addressed memory means controlled by said microprocessor for storing requests from terminals for connection to selected ARTs, respectively.

5. Electronic switching system as defined in claim 1 including at least one further ART connected solely to said microprocessor, and a command console for entering and retrieving data from said microprocessor.