CA1267201A - Inductance systems - Google Patents
Inductance systemsInfo
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- CA1267201A CA1267201A CA000485408A CA485408A CA1267201A CA 1267201 A CA1267201 A CA 1267201A CA 000485408 A CA000485408 A CA 000485408A CA 485408 A CA485408 A CA 485408A CA 1267201 A CA1267201 A CA 1267201A
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Abstract
Abstract A transducer having an inner inductive coil and a relatively movable reluctance device surrounding the coil according to changes in a dynamic parameter; a signal generator including a variable inductor and an inverter, comparator or operational amplifier; a pro-cessor for processing signals from the signal generator according to a count of the cycles in the output signal Or the signal generator and a predetermined pulse train value; and a digital to analog converter for inte-grating digital signals to yield analog signals of a non-unitary slope whose length is reflective of the duration of the digital signals.
Description
Inductance Systems Bac kground The present invention concerns apparatus and methods employing inductance devices having a variable reluctance in their magnetic rields ~or convertlng a parameter, such as relative motion, force~ or pressure, into an electrical signal for measurement. The inven-tion rurther i~volves the generation o~ signals of varying frequency according to some parameter, and to the processing Or such signals ~or some use~ul purpose.
Transducers employing variable reluctance~ and inductances for detecting motion are known. These are referred to by such terms as proximity sensors and magneto sensors, and examples o~ these devices include the linear varlable differential trans~ormer (1'LVDT");
eddy current killed oscillator ("ECKO") and eddy cur-rent oscillator level detector ("ECOLD"). One such transducer uses a magnetic diaphragm positioned between two coils having magnetic cores. A change ln diaphragm position in response to a force applied to it changes the gaps between the cores and the dlaphragm resulting in changes in the lnductances of the coils. The ratio of the changes in the inductances Or the coils is mea-sured through an alternating current brldge. In order to obtain a direct current indication Or the diaphragm motlon, the alternatlng current bridge signal must be demodulated. These known transducers are generally ~expensive, are usually physically large and the cir-cuitry ls susceptible to mechanical shock because of 30lts bulk. U.S. Patent No. 4,406,9gg discloses an in-ductlve sensor having an outer coil J a rerromagnetic core and a conductive sleeve movable between the coil and core, wherein displacement Or the sleeve is re-flected in changes in inductance Or the device. U.S.
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Transducers employing variable reluctance~ and inductances for detecting motion are known. These are referred to by such terms as proximity sensors and magneto sensors, and examples o~ these devices include the linear varlable differential trans~ormer (1'LVDT");
eddy current killed oscillator ("ECKO") and eddy cur-rent oscillator level detector ("ECOLD"). One such transducer uses a magnetic diaphragm positioned between two coils having magnetic cores. A change ln diaphragm position in response to a force applied to it changes the gaps between the cores and the dlaphragm resulting in changes in the lnductances of the coils. The ratio of the changes in the inductances Or the coils is mea-sured through an alternating current brldge. In order to obtain a direct current indication Or the diaphragm motlon, the alternatlng current bridge signal must be demodulated. These known transducers are generally ~expensive, are usually physically large and the cir-cuitry ls susceptible to mechanical shock because of 30lts bulk. U.S. Patent No. 4,406,9gg discloses an in-ductlve sensor having an outer coil J a rerromagnetic core and a conductive sleeve movable between the coil and core, wherein displacement Or the sleeve is re-flected in changes in inductance Or the device. U.S.
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Patent No. ll,310,807 dlscloses a reluctance proximity sensor having a reactive sensing unlt in an L/C tunlng circuit of an oscillator, which is connected ahead Or an operational amplifier. ~ shortcoming of the latter sensor is the requirement Or a separate squaring cir-cuit for generating a square wave frequency response.
Variable frequency oscillators are known which can be used with variable capacitive transducers to generate output signals whose ~requencies are a func-tion Or the parameter being sensed by the transducer.
For example, see V.S. Patent No. ~,310~806 datedJanuary 12, 19~2.
'~hese known devices are characterized by any Or various shortcomings. They tend to be expensive, bulky, delicate, complex in structure and in the way they must be connected to other circuit components, operational only at high'power levels and at high volt-- ages, an~ to be excitable only by AC voltage inputs.
Summary of the Invention It is a general object Or the present inven-tion to measure a dynamic, physical parameter in an erfic1ent and effective manner.
Another object is to provide an inexpensive yet effective system for measuring a dynamic, physical parameter.
It is a more particular ob~ect of the inven-tion to provide a transducer for assuming electrical characteristics re~lective o~ the value o~ a dynamic, physical parameter, which can be constructed as a rugged~ accurate, ineY.pensive and small device. A
related obJect is to provide such a transducer which is stable under various temperature conditions, easy to use with other circuit components, and which is gener-ally rree Or the shortcomings o~ known transducers.
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Patent No. ll,310,807 dlscloses a reluctance proximity sensor having a reactive sensing unlt in an L/C tunlng circuit of an oscillator, which is connected ahead Or an operational amplifier. ~ shortcoming of the latter sensor is the requirement Or a separate squaring cir-cuit for generating a square wave frequency response.
Variable frequency oscillators are known which can be used with variable capacitive transducers to generate output signals whose ~requencies are a func-tion Or the parameter being sensed by the transducer.
For example, see V.S. Patent No. ~,310~806 datedJanuary 12, 19~2.
'~hese known devices are characterized by any Or various shortcomings. They tend to be expensive, bulky, delicate, complex in structure and in the way they must be connected to other circuit components, operational only at high'power levels and at high volt-- ages, an~ to be excitable only by AC voltage inputs.
Summary of the Invention It is a general object Or the present inven-tion to measure a dynamic, physical parameter in an erfic1ent and effective manner.
Another object is to provide an inexpensive yet effective system for measuring a dynamic, physical parameter.
It is a more particular ob~ect of the inven-tion to provide a transducer for assuming electrical characteristics re~lective o~ the value o~ a dynamic, physical parameter, which can be constructed as a rugged~ accurate, ineY.pensive and small device. A
related obJect is to provide such a transducer which is stable under various temperature conditions, easy to use with other circuit components, and which is gener-ally rree Or the shortcomings o~ known transducers.
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Still another ob~ect of the present inventionis the provision of an oscillator for generating sig-nals whose frequencies vary according to characteris-tics Or a transducer in the oscillator network, wherein the oscillator is effective and efficient and relative-ly free of the shortcomings of the prior art as dis-cussed previously.
A further object of the inventlon ls the pro-~ision o~ an erfective and efficient processor ror processing signals rrom the signal generators which generate variable frequency signals~ such as those described above, to produce intelligible or otherwise usable output signals. Such a processor can be con-structed to be compact and rugged, and capable of avoiding shortcomings o~ the prior art as discussed above Another obJect is to provide an efficient digital to analog converter.
The invention in preferred forms provides a small, rugged, inexpensive variable reluctance trans-; ducer used in con~unction with an electronic circult that operates solely with direct current excitation.
Accordlng to an aspect of the invention, an inductor having a variable reluctance that affects its magnetic field may form part o~ a sel~-excited oscillator gen-erating an analog or digital alternating current slgnal having an inductance-dependent frequency. The result-ing inductance i9 varied by changing the reluctance in the magnetic rield created by the inductor. Changes in inductance and, therefore, the magnitude o~ the move-ment of the transducer components because o~ the applied force or pressure are conveniently determined by measuring the change in the ~requency of the oscil-lator ~gnal.
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In the preferred transducer, a reluctance means for varying the reluctance of the magnetlc field of the inductor may be a shield recelving khe inductor or a solid body proximate to, and movable relative to, the inductor. The reluctance means is made of a mate-rial that modifies the magnetic field by providing a reluctance different from that of air. Either the reluctance means or the inductor may be mounted on a movable base such as a diaphragm that can be displaced in response to a force applied to it. A change in the nature of the magnetic path of the inductor leads to a change in inductance and indicates the relative motion Or the reluctance means with respect to the lnductor.
Thus, eddy currents can be responsible for changes in errective inductance by providing a variable obstacle to the fleld. An oscillator according to the inven-tion produces a signal wlth an inductance-sensitive frequency, according to changes in a transducer in-cluded in the oscillator network, and when a transducer as described above is so employed, relative motion of the transducer elements results in changes in frequen-cy. Both the direction and magnitude of frequency changes may be conveniently measured in novel digital processor circuitry readily adapted to integrated cir-cuitry. That novel clrcultry measures the time re-quired by an oscillator having an inductance-sensitive frequency to generate a fixed number of cycles in com-~parison to time required to generate that number of cycles when no stimulus ls applied to the transducer.
A digital to analog converter according to an embodi-ment of the invention receives digital signals like theroregoing, and integrates them to produce output sig-nals having non-unitary slopes and lengths which vary according to the duration Or the digital signals.
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- : ., -5~ 2 Brlef Description of Ihe Drawlngs Flgure 1 is a side view of an embodiment of a reluctance transducer according to the inventlon.
Figure 2 is a graph o~ the electrical response of an embodiment Or the invention built according to Figure 1.
Figure 3 is a graph Or the electrical response of an embodlment of the invention built according to Figure 1.
Figure 4 is a graph of the electrical response o~ another embodiment of the invention built according to Flgure 1.
Figure 5 is a perspective view o~ an embodi-rnent Or a reluctance transducer according to the lnven-tion.
Figure 6 is a perspective view of still an-other embodiment o~ a reluctance transducer according to the invention.
Figure 7 is a side view of a fourth embodiment of a reluctance transducer according to the invention.
Figures 8-13 are schematic diagrams of embodi-ments of signal generators according to the lnvention.
Figure 14 is a schematic diagram of signal processing circuitry according to the invention for process~ng a signal generated in a variable inductance signal generatorO~
Figure 15 is a timing diagram illustratlng the o~eratlon o~ the circuitry shown in Figure 14.
; 30 Figure 16 is a schematic diagram of other ~ ~ signal processing circuitry according to the invention ;~ ror processing a signal generated in a variable induc-tance signal generator.
Figure 17 is a timing diagram illustrating the operatlon Or the circuitry shown in Figure 16.
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Detailed Description of Pre~erred Embodiments In Figure 1 an embodlment Or a transducer according to the invention is shown in slde view.
Transducer 1 includes a core 3, about which a coil 5 is wound. Preferably core 3 and coil 5 are rigidly mounted with respect to a flexible diaphragm 7 on which a hollow cylinder 9 Is securely mounted. Core 3 is preferably made Or a ferromagnetic material to increase the inductance of coil 5. Hollow cylinder 9 can be a non-ferrous metallic or ferromagnetic material whose relative position will variably alter the magnetic field around the coil, allowing for either an eddy current or altered magnetization ef*ect. As shown in Figure 13 core 3 and coil 5 protrude partially into hollow cylinder 9. In response to ~orces applied to the diaphragm (in the horizontal direction according to the drawing of Figure 1) 3 diaphragm 7 flexes with the result that the coil is inserted ~urther into or with-drawn from cylinder 9. When current flows through coil 5,~a corresponding magnetic rield is created around the ~ coil. Part Or that field is intercepted by cylinder 9 and is modi~ied by the cylinder. As diaphragm 7 flexes, more or less of the magnetic field of coil 5 is intercepted, resulting in a change with respect to time ; ~ o~ the current flowing through coil 5. This time rate 30 ~ Or change of current and its corresponding rield and inductive characteristics therein, serves to modify the lnherent inductance o~ coil 5. The inductance change is measured by sensing the change in the current flow-ing through coil 5. That is, cylinder 9 provldes a ::: :::~ ::
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variable reluctance means for changing the reluctance to the magnetic field in the region about coil 5.
As in all the embodiments of the transducers illustrated ln the figures, the shape of coil 5 in Figure 1 is merely schematic. The coil need not be helical and could even be planar. Various coll config-urations and the choice of core and shield materials affect the basic inductance achievable and the magni-tude of the changes in inductance, i~e. the dynamic range and sensitivity of the transducer resulting from the relative motion of the elements Or the transducer.
However, so long as the movement Or the dlaphragm is linear with respect to the applied force and the reluc-tance means principally intercepts relatively straight magnetic lines, the response of the transducer is lin-ear.
A number of exarnples of the embodiment of Figure 1 have been constructed and thelr electrical characteristics measured. Core 3 was formed from a ferromagnetic material and coil 5 wound around it. In these examples, cylinder 9 has a close fit over coil 5 but is relatively free from physical contact in order to reduce the rriction between them to a minimum. A
plastic sleeve was placed over the coil to protect it against damage and to reduce that friction. In gener-al, a closer fit between the cylinder and coil yields a greater dynamic range but a greater risk of friction; a looser fit yields a smaller dynamic range and a lower risk of friction. It was desired to construct a small, low cost, lightweight transducer so cylinder 9 was constructed of aluminum in the measured examples. In order to obtain linear operation in any embodiment, it is preferable to have the edge of cylinder 9 intercept only the magnetic lines created by coil 5 that are nearly parallel to the longitudinal axis of core 3. In .
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terms of the dirnensions o~ the measured examples~ the edge Or cyllnder 9 should extend over and cover a por-tion of the coll beyond the end of core 3 during opera-tion to assure operation in the linear range. In the measured examples~ diaphragm 7 was initially a convo-luted rubber diaphragm having a central planar sur~ace with concentric corrugations between it and the outer support structure. ~owever~ this type Or diaphragm was found subJect to drift, i.e. gradual position changes or "creep" under the influence Or a steady state pres-sure or ~orce. The drift erfect is greatly reduced if a soft spiral spring is used in con~unction with the diaphragm. The spring provides increased resistance to its movement; however, this technique could increase cost and assembly time. A di~ferent diaphragm was constructed with a circular piece o~ rlat or "sheet"
rubber stretched over an open ended cylinder. This arrangement provided the necessary stability without the use Or the enhancement spring mentioned above.
In Figure 2, the measured change in frequency of an oscillator Or the type shown in Flgure 9 de-scribed below and includlng a reluctance transducer as shown ln Figure 1 is plotted as a function Or the de-rlection or relative movement Or the cylinder and coil of the transducer. 'Ihe cylinder had an inside diameter of 4.2 mm and an outside diameter of 6.25 mm~ meaning its wall thickness was approximately 1 mm. A large linear range of frequency change as a runction of de-flection was measure~d; e.g. the linear fre~uency re-sponse over a de~lection range of about 3 mm was over 300 kHz.
In Figure 3, the measured change in rrequency as a function of~de~lection ~s plotted ror five more ; examples of oscillators Or the type shown in Figure 9 3~5 and lncluding reluctance transducers built according to :
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the embodiment of Figure 1. The curves show decreasing sensitivity as the cylinder's inner diameter becomes greater and the wall's thickness becomes thinner. This lS the expected result because the thinner wall thickness means a smaller cross section and volume of reluctance varying metal is present to intercept the magnetic field of the coil Likewise, the same wall thic~ness effects are shown in the graph illustrated in Figure 4, which plots the measured output response for four other oscillators similar to the foregoing but where the wall is quite thin, being constructed of layers of foil. Making the cylinder of a ferromagnetic material would increase the sensitivity and dynamic range of these transducers substantially, but at a significant increase in the cost of the unit.
Another embodiment 11 of a rel~ctance trans-ducer is shown in Figure 5. There a coil 13 is wound around a tub~lar structure 15 which has an air inner core 17. The reluctance shield includes a tubular portion 19 which is concentric to a rod 21. While these elements are shown separated in Figure 5 for clarity, in use core 15 is received by tubular shield 19 and rod 21 is received by air core 17. Both tube 19 and rod 21 are mounted on a fle~ible diaphragm 23 to which the forces to be measured are applied. In com-parison to the embodiment of Figure 1, this embodiment yields a lower inductance because of air core 17, but a greater dynamic range because a large portion of the total magnetic field produced by coil 13 is influenced by the incremental movement of the shield and tube over and into the coil. A very useful alternative to the simultaneous movement of tube 19 and rod 21 over and into the coil, is to securely mount tube 19 around the outer portion of coil 13. As a stationary shield, tube 19 will protect the coil against outside disturbances such as magnetic or electro-magnetic fields or the ~';' ~.... .
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motion`oE other metallic parts in the vicinity of the measurement. In this case, only the inner tube 21 will move into or out of the core section of the coil, i.e.
a reversal of the rneans shown in Figure 1. Shield 19 can be a ferromagnetic material for best results in ,his approach.
Still another embodiment 31 of a reluctance transducer is shown in Figure 6. As in the other em-bodiments, a coil 33 is wound about a core 35. }low-ever, in place of a shield, a magnet 37 having a con-cave face 39 opposite coil 33 is mounted on a flexiblediaphragm 41. In this embodiment, a large dynamic range is achieved because of the large magnetic field produced by magnet 37. It is not necessary that face 39 be concave, but that shape extends the linear re-sponse range of this embodiment because the concaveface 39 is conformal to the magnetic lines of force leaving the top of core 35.
~ n embodiment 51 of a transducer shown in Figure 7 permits measurement of a force regardless of its direction. The force is applied to a deflectable beam 53 on one end of which a magnet 55 is mounted. As in Figure 6, magnet 55 is disposed opposite a coil 57 wound around a core 59. Any oCf-axis motion between coil 57 and rnagnet 55 results in a disturbance of the coil's magnetic field which may be measured as a change in the time dependent current flowing through the coil, i.e., a change in inductance. By strategically select-; ing the cross sectional shape of beam 53 as suggested by the cross cut sections 54~ 61 and 63, the amount of deflection in response to a given force in any direc-tion can be controlled. For example, for one unit of force in the x-direction, the bearn could be made to move four units of distance, while the same one unit of ~ force in the y-direction could be made to move the beam :; :
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o ~ `~v~lw only one unit of dlstance. Any number Or force-distance combinations could be implemented for any number o~ beams alone or in combination (parallel, for example), could be made.
Networks have been devised for generating variable ~requency signals according to changes in inductance, and these can be used for measuring the changes in inductance in a reluctance transducer.
Figure 8 schematically depicts a simple circuit in which changes in inductance are converted into changes in frequency that may be sensed to determine the force or pressure applied to, i.e. the relative movement of, the transducer elements. In Figure 8, a coil 71, which may be the coil of a reluctance transducer~ ls con-nected between the input and output terminals of aninverter 73. Inverter 73 may be an integrated circuit Schmitt trigger such as a CD 40106. The input terminal of inverter 73 is connected to ground through a vari-able resistor 75. When the signal at the input termi-2~ nal of inverter 73 is in its low state, the signal at the output terminal ls in its high state, causing an increas~ng current to flow through inductor 71 and the magnetic ~ield about the inductor to grow. The rate of growth o~ the f~eld is determined by the time constant Or the inductance divided by resistance of the induc-tive network 71 and 75. As the coil approaches saturation, i.e. a constant value of current, the volt-age drop across inductor 71 declines, causing a voltage rise at the input terminal of inverter 73. Once the ; 30 switching threshold voltage of inverter 73 is exceeded at its input terminal, the voltage at the inverter's output terminal switches to its low state causing a reverse flow of current through inductor 71 as the magnetic field of inductor 71 collapses at a rate -~ r ~ J~ limlted by the time constant o~ the inductive network.
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When the current falls low enough, the voltage at the input terrninal of lnverter 73 drops below the in-verter's switching threshold causing the voltage at the output terminal Or inverter 73 to swltch back to its high state. This process is repetitive and generates a pulse train as shown in Figure 8. The frequency or pulse repetition rate and pulse width of the pulse train are determined in large measure by the character-istics of inductor 71. A higher inductance decreases frequency and current consumption. ~hile lower fre-quencies are less susceptible to interference, higher frequencies provide be-tter resolution of the measure-ment. Resistance 75 allows adJustment of the base, i.e. quiescent, frequency of the oscillator by changing the resistance component of the time constant. Changes in the inductance of inductor 71 resulting from dis-turbance of its normal magnetic field, as by the shield of a reluctance transducer, disturb the oscillation process Just described, resulting in an alteration of ~ the frequency, i.e. the repetition rate, of the pulse train stgnal generated In Figure 9 a rnodification Or the embodiment of Figure 8 is schematically shown. The signal gen-erated by the embodiment of Figure 9 still has a fre-quency related to the~ magnitude of the inductance~ butincludes circuitry for improvin~ its ~tability. The output terminal of an inverter 81 is connected to the input terlninal of an inverter 83 and to one terminal of an inductor 85. The other terminal of inductor 85 is connected through a reslstance 87 to the input terminal of inverter 81 and through a variable resistance 89 to the output terminal of inverter 83. Inductor 85 may be the coil of a reluctance transducer. In this embodi-ment, resistance 87 provides a measure of stability ~ ,, .
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against temperature and power supply voltage varia-tions. As in the embodiment Or Figure 8, variable resistor 89 ad~usts the ~requency of the output signal by ad~usting the inductive time constant of the net-work. Common, low power consumption, CMOS integratedcircuit Schmitt trigger inverters such as the CD 40106 may be used in the sensing means embodiments shown in Figures 8 and 9.
A difrerent embodiment of a signal generator is shown in Figure 10, where a clrcuit element 101 may be either a comparator to produce a pulse train signal as shown or an operational amplirier to produce an analog, sinusoidal signal which is also shown. me positive sense input terminal 103 of circuit 101 is used to establish a switching threshold. A voltage source 105, connected through the wiping contact Or a potentiorneter 107 to input terminal 103, is used to establish that threshold. As be~ore, an inductor 109, which may be a coil in a reluctance transducer, is connected from the output terminal of circuit 101 to its negative sense input terminal 111. As in Figures 8 and 9, a variable resistance 113 connected between ground and terminal 111 permits adJustment o~ the time related input voltage characteristics to circuit 101.
~5 ~en circuit 101 is a comparator, it acts like the inverter described above, switching the signal at its output terminal between high and low output states in response to voltage changes applied at negative sense input terminal 111 that cross the threshold es-tablished at positive sense input terminal 103. The resulting output signal is a pulse train, i.e., a digi-tal signal. When circuit 101 is an operational ampli-rier, it responds to incremental changes in the input slgnal. As a result, the output signal is sinusoidal.
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, frequency and in the latter, it has its greateæt effect in varying the initial conditlon amplitude Or the sinu-soidal signal.
Another signiricant dif~erence results depend-ing upon whether clrcuit 101 is a comparator or opera-tional amplifler. For a comparator, the frequency of the pulse train generated varles when the inductance of inductor 109 changes. For an operational amplifier, the greatest variation is seen ln the amplltude of the output signal that varies ln response to the changes in inductance While these changes may be detected by different circuitry, each of these sensing means em-bodiments generates a signal havlng a characteristic that varies in response to variations in the inductive time constant of feedback elements 109 and 113.
In many applications it is desirable to reduce power consumption to a minimum, for example where a battery is used. Power consumption may be reduced by operatlng transducer circuitry only part of the time, substantially reducing average power requirements. In order not to lose "detail" in measurements, a time-control means must turn the transducer clrcultry on and ~: O~r at rate that is raster than the most si~nificant varlation in the varlable being measured.
Figure ll illustrates circuitry analogous to that of Figure 8, except NAND gate 121 is substltuted for inverter 73 as both a control means and ~requency generatlng means. One input terminal of NAND gate 121 recelves a control signal as schematically illustrated in Figure ll. The other input terminal and the output terminal of NAND are connected with the circuit ele-ments as described in Figure 8 to rorm a variable-frequency oscillator. Only when the control signal is in its high state can the depicted circuitry operate to produce an oscillation signal at its output terminal.
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' ' ,~ ~"' ' Thus a power savings is achieved by repeatedly pulsing gate 121 to operate the oscillator only intermittent-ly. me output rrequency of this network is rar more sensitive to supply voltage variations than that of Figure 12 described below; therefore, it can be used as a "battery condition indicator" by making perlodic checks on the oscillator frequency and comparing it against the initial condition value. Gate 121 may be a type CD 4093 quad Schmitt Trigger CMOS NAND gate.
In Figure 12, a circuit analogous to that of Figure 9 is shown. Inverter 81 is replaced by a NAND
gate 131, and an electronic switch 141 is connected in series with inductor 85 which together act as the control means described for Figure 11. The output level of gate 131 is always high in the OFF mode of operation; thus, the OFF state of the inverter is always low which serves to avoid any uncertainty in the logic levels to be expected during intersnittant opera-tlon. Switch 141 rnay be a type CD 4066 and its opening and closing in response to the application of the con-trol signal assures the absence o~ oscillation during the OFF cycle.
Circuitry analogous to that Or Figure 10 is illustrated in Figure 13. In the circuit of Figure 13, an electronic switch 151, which may be a type CD 4066 is again connected in series with inductor 109 o~
Figure 10 as a control means. A control signal opening ;and closing the switch is applied to switch 151. An open switch 151 prevents oscillation, a closed switch 15] permits oscillation. By thus removing the lnductor ~rom, and returning it to the network, the circuitry is essentially turned on and off to limit power consump-tion.
Figure 14 shows a schematic ernbodisnent Or circuitry ~or detecting variations in the frequency, .
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i.e. repetition rate, of a pulse traln. The operation of the circuitry of Figure 14 is best underskood in reference to the timing diagram of Figure 15.
A frequency generator supplies the signal in s which ~requency variation is to be detected. For simplicity and not as a limitation~ the circuitry of Figure 9 is repeated as an embodiment of a frequency generator with inverters 201 and 203 connected in series 3 an inductor 205 connected between the common connection o~ the inverters and through a resistor 207 to the input terminal Or inverter 201. A variable resistance 209 is connected between the output terminal of inverter 203 and through lnductor 205 to the input terminal o~ inverter 203. The output termlnal of in-verter 203 ~s designated as point A and the signal present at that point is designated as signal A for convenience of reference. It is understood that the variable frequency oscillator shown in Figure 14 as generating signal A can be replaced by any of the 20 oscillator embodiments shown in Figures 8, 10, 11, 12 or 13 or any another variable frequency osclllator embodirnent.
A timing oscillator is constructed similarly, including inverters 211 and 213 connected in serles.
The ~ixed terminals of a potentiometer 215 are respec-tively connected between the common connection of in-verters 211 and 213 and (a) in series through a re sistor 217 to the input of inverter 211 and (b) through a capacitor 219 to the output terminal Or inverter 213.
The wiping contact Or potentiometer 215 is connected to the terminal of capacitor 219 that is not connected to the output terminal of inverter 213. For purposes o~
explaining operation Or the embodiment, the signal observed at the output termlnal of inverter 213 is designated as signal B.
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~17- ~6~7 A pulse train generakor identical to the timing osclllator ~ust described is provided~ but its components can be of dif~erent values to produce di~-ferent pulse widths and repetition rates. That gen-erator includes inverters 221 and 223, a potentiometer 225, a reedback resistor 227 and a capacitor 229. The output signal at the output o~ inverter 223 is desig-nated as signal C to aid description of the operation of the circuit.
The output of the rrequency generator, signal A, is transmitted through a line connected to a count-ing means. In the embodlment shown, the counting means comprises two ~our bit counters, 231 and 233, connected in series to ~orm an eight bit counter. The counters could each be one half of a CD 4520 binary type cir-~cuit. Each four bit counter has a count input terminal C, an enable input terminal E, a reset terminal R and ~our output blt lines. Signal A is transmitted to terminal C of counter 231. The highest count bit line of counter 231 is connected to the E terminal of counter 233. The R terrninals of each counter go to a reset line, RSl. The C terminal of counter 233 is grounded and its highest count bit llne serves as an output terminal QN~ The output signal B of the timing oscillator including inverters 211 and 213 is connected to enable terminal E of counter 231. When that enable terminal receives a high signal, counter 231 begins countlng the pulses in signal~A. When that count reaches the sixteenth pulse, meaning 16 pulses have been received, a high to low transition occurs at the highest bit line and so is transmitted to the enable terminal of counter 233 which, serving as a negative edge trigger, will count one unit. The process is repeated untiI a count o~ 12B pulses is reached where-upon~the slgnal at terrninal QN goes high.
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The QN terminal Or counter 233 is connected to an 8 bit counter driver, includlng two 4 bit counters 235 and 237 connected to each other as counters 231 and 233 are. The enable terminal Or counter 235 iS
connected to the QN terminal of counter 233 and the C
terminal of counter 235 receives the signal designated as C and generated by the pulse train generator in-cluding inverters 221 and 223. Counters 235 and 237 coul~ each be half of a CD 4518 BCD (Binary coded decimal) type clrcuit. A reset line RS2 iS connected to the reset terminals of counters 235 and 237. The output bit lines Or each of counters 235 and 237 are connected, respectively, to display drivers 239 and 241 which convert the BCD information into the form neces-sary to drive a two digit visual display 243. Drivers 239 and 241 each have a store terminal S, both o~ which are connected to a store line ST, and seven output terminals connected to display 243. Drivers 239 and 241 may each be a CD 4056 type circuit~
Figure 14 also includes in phantom lines a D-rlip flop 245 having its C terminal connected to termi-nal QN Or counter 233 ~which in this option is not connected to counter 235). A type CD 4013 flip flop is suitable rOr this applicatlon. The QNN output term ~ al of flip flop 245 is connected to the enable ter~inal of counter 235. Reset terminal R Or ~lip flop 245 is connected to reset line RSl. As more fully explained below,~the purpose of f`lip ~lop 245 is to hold or ~reeze a high signal generated at the ~N terminal of ~30~ counter 233, since that signal could assume its low state in the émbodiment after 256 pulses of Signal A;
this would disable the 235, 237 counters causing an lncorrect reading to occur.
The operation of the circuit Or Figure 14 is more clearly understood by rererence to t~he timing : ' : "
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diagram o~ Figure 15 where the top three time scales show the A and B signals and that at terminal QN when no stlmulus is applied, i.e. when the ~requency Or the frequency generator is in its initial condition state.
I~ a reluctance transducer is present in the frequency generator A, that state would be a quiescent one when no force or pressure is being applied to the transducer elements. The middle three time scales show the A and C signals and signal at terminal QN when a positive sense stimulus is applied. The lower three time scales show the tirning of the reset and store signals, RSl, RS2 and ST, respectively.
At the start of an interval, the timing means switches signal B to its high condition activating the cycle counter 231, 232 to count the transitions in the pulses generated by the frequency generating means 201, 203. The timing means is designed to switch slgnal B
to its low state, end1ng the interval, on the positive transition Or the 128th pulse, i.e. precisely when the QN signal goes high, if the ~requency generating signal, signal A, is Or the constant, quiescent frequency~ These conditions are shown in the top three time scales of Figure 15. The end of timing Cycle B
generates reset pulse RS1 to clear the counters to zero in preparation of the ne~t measurement interval.
Pulses ST and RS2 follow. If a positive sense stimulus is applied causing the frequency of the signal A to increase, the QN output goes high before the B signal goes low to disable the cycle counter and end the interval. This condition is illustrated in the middle three time scales of Figure 15. In this situation~
when the 128th pulse is reached and QN goes high, the display driver counter 235, 237 is activated and begins counting the pulses in signal C. This counting con-tinues until the end o~ the interval when the B slgnal ~ ' - ::
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goes low. The number of pulses Or slgnal C counted is proportional to the increase in the frequency of signal A and~ there~ore, in the case of a llnearly operating reluctance transducer, proportional to the force or pressure applied. As before, the end of timing signal B generates reset pulse RSl which clears the reluctance counters and with QN low disables the dlsplay counters 235 and 237. The store pulse ST then latches the pulse count of signal C into the display drivers 239, 241 and the information is displayed on digital display ~43 as a measure of the magnitude of the stimulus, e.g. the force or pressure applied. Following the ST pulse and the reset slgnal RS2 the next interval of measurement can begin immediately i~ desired.
The circuitry of Fieure 14 visually dlsplays the change in frequency above the base rrequency. Each successive dlsplay interval shows a value proportionate to the difference in frequency above the base value, but there is no ability to show changes in frequency having a negative sense, i.e. changes reducing the frequency below the base or quiescent value. The cir-cuitry of Figure 16 provides this feature where needed.
In Figure 16 another embodiment of a detecting means for detecting changes in the rrequency of a digi-tal slgnal is provided. This embod~ment is similar tothat shown in Figure 14~ but has the ability to measure both positive and negative sense stimuli. Because this circuitry is similar to that o~ Figure 14, the same elements in both are given the same reference numerals as are the same signals. The operation of the circuit-ry of Figure 16 is better understood by reference to the timing diagrams of Figure 17~
In Figure 16, a ~requency generator, just like that in Figure 14 generates a pu]se train, signal A.
The generator receives a stimulus that changes the :
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rrequency Or the pulses and that stimulus may be the changing inductance of a reluctance transducer respond-ing to an applied force. Signal A is applied to an 8 bit counter, cornprising two 4 bit counters connected in series just as in Figure 14. The output signal of the 8 bit counter at terminal QN of counter 233 is con-nected to the input terminal of D-flip flop 245, the element that was noted as optional in Figure 14. In Figure 16 the output signal at the primary terminal, 10 QNN of flip flop 245 is connected to the first of two input terminals of an AND gate ?47 The output at the complernentar,y terminal ~NN is connected to the first of two input terminals of an AND gate 249. Otherwise, flip flop 245 is connected in Figure 16 as it was in Figure 14. A timing oscillator, Just as in Figure 14, generates signal B, a very long pulse in comparison to the pulse wldths of signal A. Signal B is applied not only to the enable input terminal of counter 231 but also to the second of the two input terminals of AND
20 gate 247 and to an inverter 251. The signal at the output of AND gate 247~ signal D, is connected to the C
terminal of a second D-flip ~lop ~53. Flip flop 253 also receives rese~ signal RSl at its reset terminal.
The output signal from the primary terminal Q+ of flip 25 flop 253 is connected to a setting circuit 255 for establishing the sign of visual display 243 according : to the direction of the change of the frequency of signal A. The output terminal of inverter 251 at which the complement of signal B, ~, appears is connected 30 to the second input terrninal of AND gate 249. The output signal o~ AND gate 249, slgnal E, is likewise connected to an input terrninal of a third D-~lip flop 257, having the same reset connection to RS1. The output slgnal at the primary output terminal Q_ of flip 35 flop 257 is connected to a second setting circuit 259 ~., .
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-2,-for establi~hing the sign of digital visual display 243 according to the direction of change of the frequency of signal A. Signals D and E, respectively, are connected to the two input terminals of an OR gate 261.
The output terminal of OR gate 261 is connected to the enable terminal E of the driver counter means, including counters 235 and 237 as in Figure 14. The AN~ and OR
gates, together with flip flop 245, com?rise a decision means receiving the first enabling signal appearing at terminal QN of counter 233 when, as before, 128 pulses have been counted. A first timing signal, the low-high transition of signal B, is generated to begin an interval and a second timing signal, the high-low transition of signal B is generated during the interval, to determine whether the frequency of signal A is increasing or decreasing. The decision means also receives these timing signals and determines whe-ther the oscillator frequency is increasing or decreasing. The result of that determination is the generation oE a-t least one direction signal, such as signals D and E, and the slgnals supplied to the setting circuits 255 and Operation of the circuitry of Figure 16 is further understood by reference to the timing diagrams of Figure 17. The top five time scales in Figure 17 illustrate operation of the circuitry when the frequen-cy source is quiescent, i.e. when it is operating at its base frequency. This si-tuation may include a re-~luctance transducer with no force applied to it. Sig-nal A is constant in frequency over the entire inter-val. Signal B starts the interval with its low to high transition and later during the interval, preferably at its midpoint, generates as a second tir,ling signal by undergoing a high low transition. At the beginning of the interval, signal B goes high, but the signals at : ~
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terminals QN and QNN are low because the RSl and RS2 signals had already reset the network in preparatlon for -the new intervals. As a result, signals D and E, and those at Q+ and Q terminals of flip flops 253 and 257, are low. When 128 pulses have been counted, the ~ignals at QN and QNN g high, but in thls quiescent state, signal B drops to its low state at the same time. As a result, signal D remains low because of the transition in signal B and signal E remains low since the signal at terminal ~NN drops to its low state in the B signal transition. The driver counter 235, 237 is not enabled, no dlrection signal is generated and the ST pulse causes display 243 to register the ~ero signal at the output of counters 235~ 237.
The sixth through ninth timing scales o~
Figure 17 illustrate the operation of the circuit when a positive stimulus, a stimulus causing an increase in frequency, is applied to the source of signal A. The increased frequency Or signal A means that 128 pulses will be counted during the high level of signal B, and the signals at terminals QN and QNN will go high during the early part of an interval, i.e. before the high-low transition o~ signal B. In response, signal D goes hi~h, until the high~low transition in signal B, and display counter 235, 237 is enabled through OR gate 261. When signal D ~oes high~ a direction signal.
appears at the Q+ terminal of ~lip rlop 253 so that setting circuit 255 establishes the sign on display 243 as positive. The display counters 235, 237 then count the puIses in signal C until the high-low transition in signal B, which switches signal D to its low state. At that point, the output of flip flop 245 has already latched with QNN terminal signal high and QNN termi-nal signal low, so that signal E remains in its low state. The output signal of OR gate 261 goes low, ;; ' ,: ' ':" '':,, :
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disabling display counter 235, 237. The display counter generates a frequency change slgnal that i8 transmitted to display 243 by the ST pulse and which displays a value proportional to the number o~ pulses of signal C that were counted, a nwnber that is propor-tional to the lncrease in frequency of signal A over the base frequency.
When the stimulus is in the opposite sense causing the rrequency of signal A to decrease, the situation shown in the last ~our time scales of Figure 17 results. In this case~ from the time the interval begins when the rirst timing signal is given, i.e., when signal B goes from low to high, until the second timing signal is generated, i.e., at the high-low transition of signal B, fewer than 128 pulses are counted by cycle counter 231, 233. Therefore~ the signals at terminals QN and QNN remain low during the first portion of the interval. With the high-low transition of signal B, the ~ signal at the output of inverter 251 goes high and since the signal at ~NN
has remained high, signal E goes high enabling driver counter 235, 237 through OR gate 261. That is, the driver counter begins counting the pulses Or signal C
when signal B switches from high to low. Of course, when 128 pulses have been counted, the signals at ter-minals QN and QNN still go high, meaning the signal atQNN goes low, switching signal E to its low state.
Signal D never goes high in this situation, Display counter 235, 237 is then stopped and the rrequency change signal indicating the n~nber Or pulses counted is transmitted by pulse ST and appears on display 243 indicating the amount of the decrease in frequency, or, orce or pressure according to the scaling. When sig-nal E goes high, a direction signal is produced as a high level signal at the Q terminal Or rlip ~lop 257 ,, :.~
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-25~ 7~ ~1 activating setting circuit 259 to set the sign Or dis-play 243 as negative.
No matter what scenario takes place during the interval, l.e. between the low-high transitions in signal BJ at the end Or each interval, reset signals RSl and RS2 are generated in a conventional way to reset the cycle counter and display counter. Signal ST
is also generated to save the value in the counter and display it on display 243. Another interval may begin immediately thereafter or there may be a "dead" time between intervals.
Obviously, the measwrement interval in any of the circuits should be much shorter than the minimum duration of variations in the ~requency being detected.
This same performance criteria applies whether measurements are made constantly or the circuitry is intermittently operated as described above to reduce power consumption. It is also important to realize that the digital displays 243 o~ Figures 14 and 16 may be replaced with other types of displays and, as dis-cussed in Figure 18 below~ their drive signals can be used for other runctions 3 digital or analog. The cir-cuitry of Figures 14 and 16 is particularly useful because it may be conveniently constructed 3 except ~or visual displays~ on a single totally digital integrated circuit chip.
As suggested above~ the drive signals (D and E) that are developed from the interrogatioM o~ the applied ~orce or pressure can be used ror other userul functions. For example, a plus and minus digital to analog converter can be made by integrating the length Or either or both of the D and E intervals to produce an analog signal level indicative Or the parameter being measured. This type Or circuitry will be useful .
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gate 270. Switch 272 is connected to a resistor 276, and a grounded resistor 278 is connected to the line interconnecting switch 272 and resistor 276. A signal VADp(l~ is applied to resistor 276. The output of resistor 276 is connected to each of a switch 280, a capacitor 282 and to the negative input of an amplifier 15 284. Switch 274 is connected to a resistor 286, and a grounded resistor 288 is connected to the line inter-connecting switch 274 and 286. A signal VADp( 2) is applied to resistor 286. The output of resistor 286 is connected to the positive input of amplifier 284~ to a 20 capacitor 289 and to a switch 290. The latter switch is connected across capacitor 289, and the capacitor is connected to ground. A RESET signal can be applied to ~ each of switche~s 280 and 290. The output signal of ; amplifier 284 is designated VO~ and the output line of 25 amplirier 284 is connected to switch 280, to capacitor ` 282, and optionally to a switch 292 whose output is designated VOS. In the operation of the foregoing circuit 3 amplif1er 284 of the network will respond to the E interval,through OR gate 270 and by closin~
30 sw1tch 272 when E is high. In this case, a fixed volt-age appears at the input of resistor 276 connected to the inverting port of amplifier 284 resulting in the output of amplifier 284 having a negative moving ramp with a fixed slope, the length of which is dictated by ~the length of E. Resistor 278 references the inverting ~ ' :~ ~
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input to ground uhen switch 272 is open. In a simllar manner, ampllrier 284 responds to the D interval through OR gate 270 and by closing switch 274 to place a ~ixed voltage on the input of resistor 286 which is connected to the non-inverting port o~ amplirier 284;
the output of amplifier 284 generates a positive moving ramp with a fixed slope, the length of which is dic-tated by the length of the D interval. As before, resistor 288 references the non-lnverting input to ground when switch 274 is open. In this way, a series Or short ramps, all of equal positive or negative non-unitary slopes (i.e. having values other whole numbers) and each having a length (and therefore a final ampli-tude) wh~ch is directly related to the length of time the signal appears. If nelther E or D appears during a measurement interval, the output of amplifier 284 re-mains unchanged which is indicative of the ract that the measured parameter is the same as the reference and no correction is needed. In this case, OR gate 270 remains inactive until the next occurrence o~ either the D or E lnterval. In essence, the system integrates intermittent and variable intervals o~ time over the continuous progression o~ time, a unique and difrerent concept in the art o~ control system theory. It should be noted that the integration time constants for the positive or negative corrections do not have to be equaI; this would be especially useful i~ the correc-tlon in one direction requires a greater weight than that o~ the opposite direction. Further, the slope, or correction could~also be adaptive by allowing the adapting input signal to autornatlcally change the inte-gration time constant in response to certain pre-selected and properly weighted system parameters. This is suggested by the VADp signals to the now variable input resistors 276 and 286.
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Fln~lly, capacitors 282 and 2a9 are the reac-tive portion Or the inte~ratlon Slme const~nt, and since they represent the storage elements in the con-trol network, switches 280 and 290 along with the reset pulse shown are used to either lnitialize the system or to clear it as requlrements dictate.
As an alternatlve to the output slgnal dls-cussed above, sample and hold function 292 (shown in phantom) could be added to the output. In this case, each and every measurement interval for the generation of the D or E signals would result in a brand new out-put signal VO whose absolute value ls a direct repre-sentation of the measured parameter rather than a cor-rection of the old VO as previously described. The new value would then be stored in capacitor 294 by virtue Or the momentary closure Or switch 292 when the sample pulse occurs.
The inventlon has been described with refer-ence to certain preferred embodiments. Various substi-tutlons and modificatlons wlthout departlng from thespirlt Or the lnvention will occur to those Or sklll in the art. Accordingly, the scope Or the inventlon is limited solely by the following claim~.
.
Still another ob~ect of the present inventionis the provision of an oscillator for generating sig-nals whose frequencies vary according to characteris-tics Or a transducer in the oscillator network, wherein the oscillator is effective and efficient and relative-ly free of the shortcomings of the prior art as dis-cussed previously.
A further object of the inventlon ls the pro-~ision o~ an erfective and efficient processor ror processing signals rrom the signal generators which generate variable frequency signals~ such as those described above, to produce intelligible or otherwise usable output signals. Such a processor can be con-structed to be compact and rugged, and capable of avoiding shortcomings o~ the prior art as discussed above Another obJect is to provide an efficient digital to analog converter.
The invention in preferred forms provides a small, rugged, inexpensive variable reluctance trans-; ducer used in con~unction with an electronic circult that operates solely with direct current excitation.
Accordlng to an aspect of the invention, an inductor having a variable reluctance that affects its magnetic field may form part o~ a sel~-excited oscillator gen-erating an analog or digital alternating current slgnal having an inductance-dependent frequency. The result-ing inductance i9 varied by changing the reluctance in the magnetic rield created by the inductor. Changes in inductance and, therefore, the magnitude o~ the move-ment of the transducer components because o~ the applied force or pressure are conveniently determined by measuring the change in the ~requency of the oscil-lator ~gnal.
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In the preferred transducer, a reluctance means for varying the reluctance of the magnetlc field of the inductor may be a shield recelving khe inductor or a solid body proximate to, and movable relative to, the inductor. The reluctance means is made of a mate-rial that modifies the magnetic field by providing a reluctance different from that of air. Either the reluctance means or the inductor may be mounted on a movable base such as a diaphragm that can be displaced in response to a force applied to it. A change in the nature of the magnetic path of the inductor leads to a change in inductance and indicates the relative motion Or the reluctance means with respect to the lnductor.
Thus, eddy currents can be responsible for changes in errective inductance by providing a variable obstacle to the fleld. An oscillator according to the inven-tion produces a signal wlth an inductance-sensitive frequency, according to changes in a transducer in-cluded in the oscillator network, and when a transducer as described above is so employed, relative motion of the transducer elements results in changes in frequen-cy. Both the direction and magnitude of frequency changes may be conveniently measured in novel digital processor circuitry readily adapted to integrated cir-cuitry. That novel clrcultry measures the time re-quired by an oscillator having an inductance-sensitive frequency to generate a fixed number of cycles in com-~parison to time required to generate that number of cycles when no stimulus ls applied to the transducer.
A digital to analog converter according to an embodi-ment of the invention receives digital signals like theroregoing, and integrates them to produce output sig-nals having non-unitary slopes and lengths which vary according to the duration Or the digital signals.
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- : ., -5~ 2 Brlef Description of Ihe Drawlngs Flgure 1 is a side view of an embodiment of a reluctance transducer according to the inventlon.
Figure 2 is a graph o~ the electrical response of an embodiment Or the invention built according to Figure 1.
Figure 3 is a graph Or the electrical response of an embodlment of the invention built according to Figure 1.
Figure 4 is a graph of the electrical response o~ another embodiment of the invention built according to Flgure 1.
Figure 5 is a perspective view o~ an embodi-rnent Or a reluctance transducer according to the lnven-tion.
Figure 6 is a perspective view of still an-other embodiment o~ a reluctance transducer according to the invention.
Figure 7 is a side view of a fourth embodiment of a reluctance transducer according to the invention.
Figures 8-13 are schematic diagrams of embodi-ments of signal generators according to the lnvention.
Figure 14 is a schematic diagram of signal processing circuitry according to the invention for process~ng a signal generated in a variable inductance signal generatorO~
Figure 15 is a timing diagram illustratlng the o~eratlon o~ the circuitry shown in Figure 14.
; 30 Figure 16 is a schematic diagram of other ~ ~ signal processing circuitry according to the invention ;~ ror processing a signal generated in a variable induc-tance signal generator.
Figure 17 is a timing diagram illustrating the operatlon Or the circuitry shown in Figure 16.
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Detailed Description of Pre~erred Embodiments In Figure 1 an embodlment Or a transducer according to the invention is shown in slde view.
Transducer 1 includes a core 3, about which a coil 5 is wound. Preferably core 3 and coil 5 are rigidly mounted with respect to a flexible diaphragm 7 on which a hollow cylinder 9 Is securely mounted. Core 3 is preferably made Or a ferromagnetic material to increase the inductance of coil 5. Hollow cylinder 9 can be a non-ferrous metallic or ferromagnetic material whose relative position will variably alter the magnetic field around the coil, allowing for either an eddy current or altered magnetization ef*ect. As shown in Figure 13 core 3 and coil 5 protrude partially into hollow cylinder 9. In response to ~orces applied to the diaphragm (in the horizontal direction according to the drawing of Figure 1) 3 diaphragm 7 flexes with the result that the coil is inserted ~urther into or with-drawn from cylinder 9. When current flows through coil 5,~a corresponding magnetic rield is created around the ~ coil. Part Or that field is intercepted by cylinder 9 and is modi~ied by the cylinder. As diaphragm 7 flexes, more or less of the magnetic field of coil 5 is intercepted, resulting in a change with respect to time ; ~ o~ the current flowing through coil 5. This time rate 30 ~ Or change of current and its corresponding rield and inductive characteristics therein, serves to modify the lnherent inductance o~ coil 5. The inductance change is measured by sensing the change in the current flow-ing through coil 5. That is, cylinder 9 provldes a ::: :::~ ::
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variable reluctance means for changing the reluctance to the magnetic field in the region about coil 5.
As in all the embodiments of the transducers illustrated ln the figures, the shape of coil 5 in Figure 1 is merely schematic. The coil need not be helical and could even be planar. Various coll config-urations and the choice of core and shield materials affect the basic inductance achievable and the magni-tude of the changes in inductance, i~e. the dynamic range and sensitivity of the transducer resulting from the relative motion of the elements Or the transducer.
However, so long as the movement Or the dlaphragm is linear with respect to the applied force and the reluc-tance means principally intercepts relatively straight magnetic lines, the response of the transducer is lin-ear.
A number of exarnples of the embodiment of Figure 1 have been constructed and thelr electrical characteristics measured. Core 3 was formed from a ferromagnetic material and coil 5 wound around it. In these examples, cylinder 9 has a close fit over coil 5 but is relatively free from physical contact in order to reduce the rriction between them to a minimum. A
plastic sleeve was placed over the coil to protect it against damage and to reduce that friction. In gener-al, a closer fit between the cylinder and coil yields a greater dynamic range but a greater risk of friction; a looser fit yields a smaller dynamic range and a lower risk of friction. It was desired to construct a small, low cost, lightweight transducer so cylinder 9 was constructed of aluminum in the measured examples. In order to obtain linear operation in any embodiment, it is preferable to have the edge of cylinder 9 intercept only the magnetic lines created by coil 5 that are nearly parallel to the longitudinal axis of core 3. In .
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terms of the dirnensions o~ the measured examples~ the edge Or cyllnder 9 should extend over and cover a por-tion of the coll beyond the end of core 3 during opera-tion to assure operation in the linear range. In the measured examples~ diaphragm 7 was initially a convo-luted rubber diaphragm having a central planar sur~ace with concentric corrugations between it and the outer support structure. ~owever~ this type Or diaphragm was found subJect to drift, i.e. gradual position changes or "creep" under the influence Or a steady state pres-sure or ~orce. The drift erfect is greatly reduced if a soft spiral spring is used in con~unction with the diaphragm. The spring provides increased resistance to its movement; however, this technique could increase cost and assembly time. A di~ferent diaphragm was constructed with a circular piece o~ rlat or "sheet"
rubber stretched over an open ended cylinder. This arrangement provided the necessary stability without the use Or the enhancement spring mentioned above.
In Figure 2, the measured change in frequency of an oscillator Or the type shown in Flgure 9 de-scribed below and includlng a reluctance transducer as shown ln Figure 1 is plotted as a function Or the de-rlection or relative movement Or the cylinder and coil of the transducer. 'Ihe cylinder had an inside diameter of 4.2 mm and an outside diameter of 6.25 mm~ meaning its wall thickness was approximately 1 mm. A large linear range of frequency change as a runction of de-flection was measure~d; e.g. the linear fre~uency re-sponse over a de~lection range of about 3 mm was over 300 kHz.
In Figure 3, the measured change in rrequency as a function of~de~lection ~s plotted ror five more ; examples of oscillators Or the type shown in Figure 9 3~5 and lncluding reluctance transducers built according to :
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the embodiment of Figure 1. The curves show decreasing sensitivity as the cylinder's inner diameter becomes greater and the wall's thickness becomes thinner. This lS the expected result because the thinner wall thickness means a smaller cross section and volume of reluctance varying metal is present to intercept the magnetic field of the coil Likewise, the same wall thic~ness effects are shown in the graph illustrated in Figure 4, which plots the measured output response for four other oscillators similar to the foregoing but where the wall is quite thin, being constructed of layers of foil. Making the cylinder of a ferromagnetic material would increase the sensitivity and dynamic range of these transducers substantially, but at a significant increase in the cost of the unit.
Another embodiment 11 of a rel~ctance trans-ducer is shown in Figure 5. There a coil 13 is wound around a tub~lar structure 15 which has an air inner core 17. The reluctance shield includes a tubular portion 19 which is concentric to a rod 21. While these elements are shown separated in Figure 5 for clarity, in use core 15 is received by tubular shield 19 and rod 21 is received by air core 17. Both tube 19 and rod 21 are mounted on a fle~ible diaphragm 23 to which the forces to be measured are applied. In com-parison to the embodiment of Figure 1, this embodiment yields a lower inductance because of air core 17, but a greater dynamic range because a large portion of the total magnetic field produced by coil 13 is influenced by the incremental movement of the shield and tube over and into the coil. A very useful alternative to the simultaneous movement of tube 19 and rod 21 over and into the coil, is to securely mount tube 19 around the outer portion of coil 13. As a stationary shield, tube 19 will protect the coil against outside disturbances such as magnetic or electro-magnetic fields or the ~';' ~.... .
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motion`oE other metallic parts in the vicinity of the measurement. In this case, only the inner tube 21 will move into or out of the core section of the coil, i.e.
a reversal of the rneans shown in Figure 1. Shield 19 can be a ferromagnetic material for best results in ,his approach.
Still another embodiment 31 of a reluctance transducer is shown in Figure 6. As in the other em-bodiments, a coil 33 is wound about a core 35. }low-ever, in place of a shield, a magnet 37 having a con-cave face 39 opposite coil 33 is mounted on a flexiblediaphragm 41. In this embodiment, a large dynamic range is achieved because of the large magnetic field produced by magnet 37. It is not necessary that face 39 be concave, but that shape extends the linear re-sponse range of this embodiment because the concaveface 39 is conformal to the magnetic lines of force leaving the top of core 35.
~ n embodiment 51 of a transducer shown in Figure 7 permits measurement of a force regardless of its direction. The force is applied to a deflectable beam 53 on one end of which a magnet 55 is mounted. As in Figure 6, magnet 55 is disposed opposite a coil 57 wound around a core 59. Any oCf-axis motion between coil 57 and rnagnet 55 results in a disturbance of the coil's magnetic field which may be measured as a change in the time dependent current flowing through the coil, i.e., a change in inductance. By strategically select-; ing the cross sectional shape of beam 53 as suggested by the cross cut sections 54~ 61 and 63, the amount of deflection in response to a given force in any direc-tion can be controlled. For example, for one unit of force in the x-direction, the bearn could be made to move four units of distance, while the same one unit of ~ force in the y-direction could be made to move the beam :; :
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o ~ `~v~lw only one unit of dlstance. Any number Or force-distance combinations could be implemented for any number o~ beams alone or in combination (parallel, for example), could be made.
Networks have been devised for generating variable ~requency signals according to changes in inductance, and these can be used for measuring the changes in inductance in a reluctance transducer.
Figure 8 schematically depicts a simple circuit in which changes in inductance are converted into changes in frequency that may be sensed to determine the force or pressure applied to, i.e. the relative movement of, the transducer elements. In Figure 8, a coil 71, which may be the coil of a reluctance transducer~ ls con-nected between the input and output terminals of aninverter 73. Inverter 73 may be an integrated circuit Schmitt trigger such as a CD 40106. The input terminal of inverter 73 is connected to ground through a vari-able resistor 75. When the signal at the input termi-2~ nal of inverter 73 is in its low state, the signal at the output terminal ls in its high state, causing an increas~ng current to flow through inductor 71 and the magnetic ~ield about the inductor to grow. The rate of growth o~ the f~eld is determined by the time constant Or the inductance divided by resistance of the induc-tive network 71 and 75. As the coil approaches saturation, i.e. a constant value of current, the volt-age drop across inductor 71 declines, causing a voltage rise at the input terminal of inverter 73. Once the ; 30 switching threshold voltage of inverter 73 is exceeded at its input terminal, the voltage at the inverter's output terminal switches to its low state causing a reverse flow of current through inductor 71 as the magnetic field of inductor 71 collapses at a rate -~ r ~ J~ limlted by the time constant o~ the inductive network.
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When the current falls low enough, the voltage at the input terrninal of lnverter 73 drops below the in-verter's switching threshold causing the voltage at the output terminal Or inverter 73 to swltch back to its high state. This process is repetitive and generates a pulse train as shown in Figure 8. The frequency or pulse repetition rate and pulse width of the pulse train are determined in large measure by the character-istics of inductor 71. A higher inductance decreases frequency and current consumption. ~hile lower fre-quencies are less susceptible to interference, higher frequencies provide be-tter resolution of the measure-ment. Resistance 75 allows adJustment of the base, i.e. quiescent, frequency of the oscillator by changing the resistance component of the time constant. Changes in the inductance of inductor 71 resulting from dis-turbance of its normal magnetic field, as by the shield of a reluctance transducer, disturb the oscillation process Just described, resulting in an alteration of ~ the frequency, i.e. the repetition rate, of the pulse train stgnal generated In Figure 9 a rnodification Or the embodiment of Figure 8 is schematically shown. The signal gen-erated by the embodiment of Figure 9 still has a fre-quency related to the~ magnitude of the inductance~ butincludes circuitry for improvin~ its ~tability. The output terminal of an inverter 81 is connected to the input terlninal of an inverter 83 and to one terminal of an inductor 85. The other terminal of inductor 85 is connected through a reslstance 87 to the input terminal of inverter 81 and through a variable resistance 89 to the output terminal of inverter 83. Inductor 85 may be the coil of a reluctance transducer. In this embodi-ment, resistance 87 provides a measure of stability ~ ,, .
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against temperature and power supply voltage varia-tions. As in the embodiment Or Figure 8, variable resistor 89 ad~usts the ~requency of the output signal by ad~usting the inductive time constant of the net-work. Common, low power consumption, CMOS integratedcircuit Schmitt trigger inverters such as the CD 40106 may be used in the sensing means embodiments shown in Figures 8 and 9.
A difrerent embodiment of a signal generator is shown in Figure 10, where a clrcuit element 101 may be either a comparator to produce a pulse train signal as shown or an operational amplirier to produce an analog, sinusoidal signal which is also shown. me positive sense input terminal 103 of circuit 101 is used to establish a switching threshold. A voltage source 105, connected through the wiping contact Or a potentiorneter 107 to input terminal 103, is used to establish that threshold. As be~ore, an inductor 109, which may be a coil in a reluctance transducer, is connected from the output terminal of circuit 101 to its negative sense input terminal 111. As in Figures 8 and 9, a variable resistance 113 connected between ground and terminal 111 permits adJustment o~ the time related input voltage characteristics to circuit 101.
~5 ~en circuit 101 is a comparator, it acts like the inverter described above, switching the signal at its output terminal between high and low output states in response to voltage changes applied at negative sense input terminal 111 that cross the threshold es-tablished at positive sense input terminal 103. The resulting output signal is a pulse train, i.e., a digi-tal signal. When circuit 101 is an operational ampli-rier, it responds to incremental changes in the input slgnal. As a result, the output signal is sinusoidal.
3S In the former case, resistance 113 varies the base . ,, -: .
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, frequency and in the latter, it has its greateæt effect in varying the initial conditlon amplitude Or the sinu-soidal signal.
Another signiricant dif~erence results depend-ing upon whether clrcuit 101 is a comparator or opera-tional amplifler. For a comparator, the frequency of the pulse train generated varles when the inductance of inductor 109 changes. For an operational amplifier, the greatest variation is seen ln the amplltude of the output signal that varies ln response to the changes in inductance While these changes may be detected by different circuitry, each of these sensing means em-bodiments generates a signal havlng a characteristic that varies in response to variations in the inductive time constant of feedback elements 109 and 113.
In many applications it is desirable to reduce power consumption to a minimum, for example where a battery is used. Power consumption may be reduced by operatlng transducer circuitry only part of the time, substantially reducing average power requirements. In order not to lose "detail" in measurements, a time-control means must turn the transducer clrcultry on and ~: O~r at rate that is raster than the most si~nificant varlation in the varlable being measured.
Figure ll illustrates circuitry analogous to that of Figure 8, except NAND gate 121 is substltuted for inverter 73 as both a control means and ~requency generatlng means. One input terminal of NAND gate 121 recelves a control signal as schematically illustrated in Figure ll. The other input terminal and the output terminal of NAND are connected with the circuit ele-ments as described in Figure 8 to rorm a variable-frequency oscillator. Only when the control signal is in its high state can the depicted circuitry operate to produce an oscillation signal at its output terminal.
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' ' ,~ ~"' ' Thus a power savings is achieved by repeatedly pulsing gate 121 to operate the oscillator only intermittent-ly. me output rrequency of this network is rar more sensitive to supply voltage variations than that of Figure 12 described below; therefore, it can be used as a "battery condition indicator" by making perlodic checks on the oscillator frequency and comparing it against the initial condition value. Gate 121 may be a type CD 4093 quad Schmitt Trigger CMOS NAND gate.
In Figure 12, a circuit analogous to that of Figure 9 is shown. Inverter 81 is replaced by a NAND
gate 131, and an electronic switch 141 is connected in series with inductor 85 which together act as the control means described for Figure 11. The output level of gate 131 is always high in the OFF mode of operation; thus, the OFF state of the inverter is always low which serves to avoid any uncertainty in the logic levels to be expected during intersnittant opera-tlon. Switch 141 rnay be a type CD 4066 and its opening and closing in response to the application of the con-trol signal assures the absence o~ oscillation during the OFF cycle.
Circuitry analogous to that Or Figure 10 is illustrated in Figure 13. In the circuit of Figure 13, an electronic switch 151, which may be a type CD 4066 is again connected in series with inductor 109 o~
Figure 10 as a control means. A control signal opening ;and closing the switch is applied to switch 151. An open switch 151 prevents oscillation, a closed switch 15] permits oscillation. By thus removing the lnductor ~rom, and returning it to the network, the circuitry is essentially turned on and off to limit power consump-tion.
Figure 14 shows a schematic ernbodisnent Or circuitry ~or detecting variations in the frequency, .
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i.e. repetition rate, of a pulse traln. The operation of the circuitry of Figure 14 is best underskood in reference to the timing diagram of Figure 15.
A frequency generator supplies the signal in s which ~requency variation is to be detected. For simplicity and not as a limitation~ the circuitry of Figure 9 is repeated as an embodiment of a frequency generator with inverters 201 and 203 connected in series 3 an inductor 205 connected between the common connection o~ the inverters and through a resistor 207 to the input terminal Or inverter 201. A variable resistance 209 is connected between the output terminal of inverter 203 and through lnductor 205 to the input terminal o~ inverter 203. The output termlnal of in-verter 203 ~s designated as point A and the signal present at that point is designated as signal A for convenience of reference. It is understood that the variable frequency oscillator shown in Figure 14 as generating signal A can be replaced by any of the 20 oscillator embodiments shown in Figures 8, 10, 11, 12 or 13 or any another variable frequency osclllator embodirnent.
A timing oscillator is constructed similarly, including inverters 211 and 213 connected in serles.
The ~ixed terminals of a potentiometer 215 are respec-tively connected between the common connection of in-verters 211 and 213 and (a) in series through a re sistor 217 to the input of inverter 211 and (b) through a capacitor 219 to the output terminal Or inverter 213.
The wiping contact Or potentiometer 215 is connected to the terminal of capacitor 219 that is not connected to the output terminal of inverter 213. For purposes o~
explaining operation Or the embodiment, the signal observed at the output termlnal of inverter 213 is designated as signal B.
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~17- ~6~7 A pulse train generakor identical to the timing osclllator ~ust described is provided~ but its components can be of dif~erent values to produce di~-ferent pulse widths and repetition rates. That gen-erator includes inverters 221 and 223, a potentiometer 225, a reedback resistor 227 and a capacitor 229. The output signal at the output o~ inverter 223 is desig-nated as signal C to aid description of the operation of the circuit.
The output of the rrequency generator, signal A, is transmitted through a line connected to a count-ing means. In the embodlment shown, the counting means comprises two ~our bit counters, 231 and 233, connected in series to ~orm an eight bit counter. The counters could each be one half of a CD 4520 binary type cir-~cuit. Each four bit counter has a count input terminal C, an enable input terminal E, a reset terminal R and ~our output blt lines. Signal A is transmitted to terminal C of counter 231. The highest count bit line of counter 231 is connected to the E terminal of counter 233. The R terrninals of each counter go to a reset line, RSl. The C terminal of counter 233 is grounded and its highest count bit llne serves as an output terminal QN~ The output signal B of the timing oscillator including inverters 211 and 213 is connected to enable terminal E of counter 231. When that enable terminal receives a high signal, counter 231 begins countlng the pulses in signal~A. When that count reaches the sixteenth pulse, meaning 16 pulses have been received, a high to low transition occurs at the highest bit line and so is transmitted to the enable terminal of counter 233 which, serving as a negative edge trigger, will count one unit. The process is repeated untiI a count o~ 12B pulses is reached where-upon~the slgnal at terrninal QN goes high.
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The QN terminal Or counter 233 is connected to an 8 bit counter driver, includlng two 4 bit counters 235 and 237 connected to each other as counters 231 and 233 are. The enable terminal Or counter 235 iS
connected to the QN terminal of counter 233 and the C
terminal of counter 235 receives the signal designated as C and generated by the pulse train generator in-cluding inverters 221 and 223. Counters 235 and 237 coul~ each be half of a CD 4518 BCD (Binary coded decimal) type clrcuit. A reset line RS2 iS connected to the reset terminals of counters 235 and 237. The output bit lines Or each of counters 235 and 237 are connected, respectively, to display drivers 239 and 241 which convert the BCD information into the form neces-sary to drive a two digit visual display 243. Drivers 239 and 241 each have a store terminal S, both o~ which are connected to a store line ST, and seven output terminals connected to display 243. Drivers 239 and 241 may each be a CD 4056 type circuit~
Figure 14 also includes in phantom lines a D-rlip flop 245 having its C terminal connected to termi-nal QN Or counter 233 ~which in this option is not connected to counter 235). A type CD 4013 flip flop is suitable rOr this applicatlon. The QNN output term ~ al of flip flop 245 is connected to the enable ter~inal of counter 235. Reset terminal R Or ~lip flop 245 is connected to reset line RSl. As more fully explained below,~the purpose of f`lip ~lop 245 is to hold or ~reeze a high signal generated at the ~N terminal of ~30~ counter 233, since that signal could assume its low state in the émbodiment after 256 pulses of Signal A;
this would disable the 235, 237 counters causing an lncorrect reading to occur.
The operation of the circuit Or Figure 14 is more clearly understood by rererence to t~he timing : ' : "
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diagram o~ Figure 15 where the top three time scales show the A and B signals and that at terminal QN when no stlmulus is applied, i.e. when the ~requency Or the frequency generator is in its initial condition state.
I~ a reluctance transducer is present in the frequency generator A, that state would be a quiescent one when no force or pressure is being applied to the transducer elements. The middle three time scales show the A and C signals and signal at terminal QN when a positive sense stimulus is applied. The lower three time scales show the tirning of the reset and store signals, RSl, RS2 and ST, respectively.
At the start of an interval, the timing means switches signal B to its high condition activating the cycle counter 231, 232 to count the transitions in the pulses generated by the frequency generating means 201, 203. The timing means is designed to switch slgnal B
to its low state, end1ng the interval, on the positive transition Or the 128th pulse, i.e. precisely when the QN signal goes high, if the ~requency generating signal, signal A, is Or the constant, quiescent frequency~ These conditions are shown in the top three time scales of Figure 15. The end of timing Cycle B
generates reset pulse RS1 to clear the counters to zero in preparation of the ne~t measurement interval.
Pulses ST and RS2 follow. If a positive sense stimulus is applied causing the frequency of the signal A to increase, the QN output goes high before the B signal goes low to disable the cycle counter and end the interval. This condition is illustrated in the middle three time scales of Figure 15. In this situation~
when the 128th pulse is reached and QN goes high, the display driver counter 235, 237 is activated and begins counting the pulses in signal C. This counting con-tinues until the end o~ the interval when the B slgnal ~ ' - ::
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goes low. The number of pulses Or slgnal C counted is proportional to the increase in the frequency of signal A and~ there~ore, in the case of a llnearly operating reluctance transducer, proportional to the force or pressure applied. As before, the end of timing signal B generates reset pulse RSl which clears the reluctance counters and with QN low disables the dlsplay counters 235 and 237. The store pulse ST then latches the pulse count of signal C into the display drivers 239, 241 and the information is displayed on digital display ~43 as a measure of the magnitude of the stimulus, e.g. the force or pressure applied. Following the ST pulse and the reset slgnal RS2 the next interval of measurement can begin immediately i~ desired.
The circuitry of Fieure 14 visually dlsplays the change in frequency above the base rrequency. Each successive dlsplay interval shows a value proportionate to the difference in frequency above the base value, but there is no ability to show changes in frequency having a negative sense, i.e. changes reducing the frequency below the base or quiescent value. The cir-cuitry of Figure 16 provides this feature where needed.
In Figure 16 another embodiment of a detecting means for detecting changes in the rrequency of a digi-tal slgnal is provided. This embod~ment is similar tothat shown in Figure 14~ but has the ability to measure both positive and negative sense stimuli. Because this circuitry is similar to that o~ Figure 14, the same elements in both are given the same reference numerals as are the same signals. The operation of the circuit-ry of Figure 16 is better understood by reference to the timing diagrams of Figure 17~
In Figure 16, a ~requency generator, just like that in Figure 14 generates a pu]se train, signal A.
The generator receives a stimulus that changes the :
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rrequency Or the pulses and that stimulus may be the changing inductance of a reluctance transducer respond-ing to an applied force. Signal A is applied to an 8 bit counter, cornprising two 4 bit counters connected in series just as in Figure 14. The output signal of the 8 bit counter at terminal QN of counter 233 is con-nected to the input terminal of D-flip flop 245, the element that was noted as optional in Figure 14. In Figure 16 the output signal at the primary terminal, 10 QNN of flip flop 245 is connected to the first of two input terminals of an AND gate ?47 The output at the complernentar,y terminal ~NN is connected to the first of two input terminals of an AND gate 249. Otherwise, flip flop 245 is connected in Figure 16 as it was in Figure 14. A timing oscillator, Just as in Figure 14, generates signal B, a very long pulse in comparison to the pulse wldths of signal A. Signal B is applied not only to the enable input terminal of counter 231 but also to the second of the two input terminals of AND
20 gate 247 and to an inverter 251. The signal at the output of AND gate 247~ signal D, is connected to the C
terminal of a second D-flip ~lop ~53. Flip flop 253 also receives rese~ signal RSl at its reset terminal.
The output signal from the primary terminal Q+ of flip 25 flop 253 is connected to a setting circuit 255 for establishing the sign of visual display 243 according : to the direction of the change of the frequency of signal A. The output terminal of inverter 251 at which the complement of signal B, ~, appears is connected 30 to the second input terrninal of AND gate 249. The output signal o~ AND gate 249, slgnal E, is likewise connected to an input terrninal of a third D-~lip flop 257, having the same reset connection to RS1. The output slgnal at the primary output terminal Q_ of flip 35 flop 257 is connected to a second setting circuit 259 ~., .
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-2,-for establi~hing the sign of digital visual display 243 according to the direction of change of the frequency of signal A. Signals D and E, respectively, are connected to the two input terminals of an OR gate 261.
The output terminal of OR gate 261 is connected to the enable terminal E of the driver counter means, including counters 235 and 237 as in Figure 14. The AN~ and OR
gates, together with flip flop 245, com?rise a decision means receiving the first enabling signal appearing at terminal QN of counter 233 when, as before, 128 pulses have been counted. A first timing signal, the low-high transition of signal B, is generated to begin an interval and a second timing signal, the high-low transition of signal B is generated during the interval, to determine whether the frequency of signal A is increasing or decreasing. The decision means also receives these timing signals and determines whe-ther the oscillator frequency is increasing or decreasing. The result of that determination is the generation oE a-t least one direction signal, such as signals D and E, and the slgnals supplied to the setting circuits 255 and Operation of the circuitry of Figure 16 is further understood by reference to the timing diagrams of Figure 17. The top five time scales in Figure 17 illustrate operation of the circuitry when the frequen-cy source is quiescent, i.e. when it is operating at its base frequency. This si-tuation may include a re-~luctance transducer with no force applied to it. Sig-nal A is constant in frequency over the entire inter-val. Signal B starts the interval with its low to high transition and later during the interval, preferably at its midpoint, generates as a second tir,ling signal by undergoing a high low transition. At the beginning of the interval, signal B goes high, but the signals at : ~
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terminals QN and QNN are low because the RSl and RS2 signals had already reset the network in preparatlon for -the new intervals. As a result, signals D and E, and those at Q+ and Q terminals of flip flops 253 and 257, are low. When 128 pulses have been counted, the ~ignals at QN and QNN g high, but in thls quiescent state, signal B drops to its low state at the same time. As a result, signal D remains low because of the transition in signal B and signal E remains low since the signal at terminal ~NN drops to its low state in the B signal transition. The driver counter 235, 237 is not enabled, no dlrection signal is generated and the ST pulse causes display 243 to register the ~ero signal at the output of counters 235~ 237.
The sixth through ninth timing scales o~
Figure 17 illustrate the operation of the circuit when a positive stimulus, a stimulus causing an increase in frequency, is applied to the source of signal A. The increased frequency Or signal A means that 128 pulses will be counted during the high level of signal B, and the signals at terminals QN and QNN will go high during the early part of an interval, i.e. before the high-low transition o~ signal B. In response, signal D goes hi~h, until the high~low transition in signal B, and display counter 235, 237 is enabled through OR gate 261. When signal D ~oes high~ a direction signal.
appears at the Q+ terminal of ~lip rlop 253 so that setting circuit 255 establishes the sign on display 243 as positive. The display counters 235, 237 then count the puIses in signal C until the high-low transition in signal B, which switches signal D to its low state. At that point, the output of flip flop 245 has already latched with QNN terminal signal high and QNN termi-nal signal low, so that signal E remains in its low state. The output signal of OR gate 261 goes low, ;; ' ,: ' ':" '':,, :
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disabling display counter 235, 237. The display counter generates a frequency change slgnal that i8 transmitted to display 243 by the ST pulse and which displays a value proportional to the number o~ pulses of signal C that were counted, a nwnber that is propor-tional to the lncrease in frequency of signal A over the base frequency.
When the stimulus is in the opposite sense causing the rrequency of signal A to decrease, the situation shown in the last ~our time scales of Figure 17 results. In this case~ from the time the interval begins when the rirst timing signal is given, i.e., when signal B goes from low to high, until the second timing signal is generated, i.e., at the high-low transition of signal B, fewer than 128 pulses are counted by cycle counter 231, 233. Therefore~ the signals at terminals QN and QNN remain low during the first portion of the interval. With the high-low transition of signal B, the ~ signal at the output of inverter 251 goes high and since the signal at ~NN
has remained high, signal E goes high enabling driver counter 235, 237 through OR gate 261. That is, the driver counter begins counting the pulses Or signal C
when signal B switches from high to low. Of course, when 128 pulses have been counted, the signals at ter-minals QN and QNN still go high, meaning the signal atQNN goes low, switching signal E to its low state.
Signal D never goes high in this situation, Display counter 235, 237 is then stopped and the rrequency change signal indicating the n~nber Or pulses counted is transmitted by pulse ST and appears on display 243 indicating the amount of the decrease in frequency, or, orce or pressure according to the scaling. When sig-nal E goes high, a direction signal is produced as a high level signal at the Q terminal Or rlip ~lop 257 ,, :.~
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-25~ 7~ ~1 activating setting circuit 259 to set the sign Or dis-play 243 as negative.
No matter what scenario takes place during the interval, l.e. between the low-high transitions in signal BJ at the end Or each interval, reset signals RSl and RS2 are generated in a conventional way to reset the cycle counter and display counter. Signal ST
is also generated to save the value in the counter and display it on display 243. Another interval may begin immediately thereafter or there may be a "dead" time between intervals.
Obviously, the measwrement interval in any of the circuits should be much shorter than the minimum duration of variations in the ~requency being detected.
This same performance criteria applies whether measurements are made constantly or the circuitry is intermittently operated as described above to reduce power consumption. It is also important to realize that the digital displays 243 o~ Figures 14 and 16 may be replaced with other types of displays and, as dis-cussed in Figure 18 below~ their drive signals can be used for other runctions 3 digital or analog. The cir-cuitry of Figures 14 and 16 is particularly useful because it may be conveniently constructed 3 except ~or visual displays~ on a single totally digital integrated circuit chip.
As suggested above~ the drive signals (D and E) that are developed from the interrogatioM o~ the applied ~orce or pressure can be used ror other userul functions. For example, a plus and minus digital to analog converter can be made by integrating the length Or either or both of the D and E intervals to produce an analog signal level indicative Or the parameter being measured. This type Or circuitry will be useful .
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gate 270. Switch 272 is connected to a resistor 276, and a grounded resistor 278 is connected to the line interconnecting switch 272 and resistor 276. A signal VADp(l~ is applied to resistor 276. The output of resistor 276 is connected to each of a switch 280, a capacitor 282 and to the negative input of an amplifier 15 284. Switch 274 is connected to a resistor 286, and a grounded resistor 288 is connected to the line inter-connecting switch 274 and 286. A signal VADp( 2) is applied to resistor 286. The output of resistor 286 is connected to the positive input of amplifier 284~ to a 20 capacitor 289 and to a switch 290. The latter switch is connected across capacitor 289, and the capacitor is connected to ground. A RESET signal can be applied to ~ each of switche~s 280 and 290. The output signal of ; amplifier 284 is designated VO~ and the output line of 25 amplirier 284 is connected to switch 280, to capacitor ` 282, and optionally to a switch 292 whose output is designated VOS. In the operation of the foregoing circuit 3 amplif1er 284 of the network will respond to the E interval,through OR gate 270 and by closin~
30 sw1tch 272 when E is high. In this case, a fixed volt-age appears at the input of resistor 276 connected to the inverting port of amplifier 284 resulting in the output of amplifier 284 having a negative moving ramp with a fixed slope, the length of which is dictated by ~the length of E. Resistor 278 references the inverting ~ ' :~ ~
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input to ground uhen switch 272 is open. In a simllar manner, ampllrier 284 responds to the D interval through OR gate 270 and by closing switch 274 to place a ~ixed voltage on the input of resistor 286 which is connected to the non-inverting port o~ amplirier 284;
the output of amplifier 284 generates a positive moving ramp with a fixed slope, the length of which is dic-tated by the length of the D interval. As before, resistor 288 references the non-lnverting input to ground when switch 274 is open. In this way, a series Or short ramps, all of equal positive or negative non-unitary slopes (i.e. having values other whole numbers) and each having a length (and therefore a final ampli-tude) wh~ch is directly related to the length of time the signal appears. If nelther E or D appears during a measurement interval, the output of amplifier 284 re-mains unchanged which is indicative of the ract that the measured parameter is the same as the reference and no correction is needed. In this case, OR gate 270 remains inactive until the next occurrence o~ either the D or E lnterval. In essence, the system integrates intermittent and variable intervals o~ time over the continuous progression o~ time, a unique and difrerent concept in the art o~ control system theory. It should be noted that the integration time constants for the positive or negative corrections do not have to be equaI; this would be especially useful i~ the correc-tlon in one direction requires a greater weight than that o~ the opposite direction. Further, the slope, or correction could~also be adaptive by allowing the adapting input signal to autornatlcally change the inte-gration time constant in response to certain pre-selected and properly weighted system parameters. This is suggested by the VADp signals to the now variable input resistors 276 and 286.
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Fln~lly, capacitors 282 and 2a9 are the reac-tive portion Or the inte~ratlon Slme const~nt, and since they represent the storage elements in the con-trol network, switches 280 and 290 along with the reset pulse shown are used to either lnitialize the system or to clear it as requlrements dictate.
As an alternatlve to the output slgnal dls-cussed above, sample and hold function 292 (shown in phantom) could be added to the output. In this case, each and every measurement interval for the generation of the D or E signals would result in a brand new out-put signal VO whose absolute value ls a direct repre-sentation of the measured parameter rather than a cor-rection of the old VO as previously described. The new value would then be stored in capacitor 294 by virtue Or the momentary closure Or switch 292 when the sample pulse occurs.
The inventlon has been described with refer-ence to certain preferred embodiments. Various substi-tutlons and modificatlons wlthout departlng from thespirlt Or the lnvention will occur to those Or sklll in the art. Accordingly, the scope Or the inventlon is limited solely by the following claim~.
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Claims (6)
PRIVILEGE ARE CLAIMED IS DEFINED AS FOLLOWS:
1. A reluctance transducer comprising a Schmitt trigger invertor-type regenerative oscillator actuable to continuously generate a direct current having a square wave train, an inner inductive coil for generating a magnetic field in response to the flow of said current, reluctance means proximate and surrounding said coil for modifying the reluctance presented to said magnetic field in response to changes in the relative positions of said coil and said reluctance means, and flexible coupling means for moving said coil relative to said reluctance means in response to applied force.
2. The invention of claim 1, wherein said reluctance means comprises a tubular receiving means mounted on said coupling means for receiving said coil within it.
3. The invention of claim 2, wherein said coil is wound on a form including an air core and said reluctance means includes a rod mounted within said cylinder and received by said air core.
4. The invention of claim 1, wherein said reluctance means comprises a magnet.
5. The invention of claim 4, wherein said magnet has a concave face opposite said coil.
6. The invention of claim 1, wherein said coupling means comprises a deflectable beam and said reluctance means comprises a magnet mounted on said beam opposite said coil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000485408A CA1267201A (en) | 1985-06-26 | 1985-06-26 | Inductance systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000485408A CA1267201A (en) | 1985-06-26 | 1985-06-26 | Inductance systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1267201A true CA1267201A (en) | 1990-03-27 |
Family
ID=4130841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000485408A Expired - Fee Related CA1267201A (en) | 1985-06-26 | 1985-06-26 | Inductance systems |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1267201A (en) |
-
1985
- 1985-06-26 CA CA000485408A patent/CA1267201A/en not_active Expired - Fee Related
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