CA1264825A - Circuit logique a fet a couplage direct - Google Patents

Circuit logique a fet a couplage direct

Info

Publication number
CA1264825A
CA1264825A CA000532354A CA532354A CA1264825A CA 1264825 A CA1264825 A CA 1264825A CA 000532354 A CA000532354 A CA 000532354A CA 532354 A CA532354 A CA 532354A CA 1264825 A CA1264825 A CA 1264825A
Authority
CA
Canada
Prior art keywords
photodiode
fet
gate
circuit element
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA000532354A
Other languages
English (en)
Inventor
Bruce Alan Richardson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to CA000532354A priority Critical patent/CA1264825A/fr
Application granted granted Critical
Publication of CA1264825A publication Critical patent/CA1264825A/fr
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
CA000532354A 1987-03-18 1987-03-18 Circuit logique a fet a couplage direct Expired - Fee Related CA1264825A (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA000532354A CA1264825A (fr) 1987-03-18 1987-03-18 Circuit logique a fet a couplage direct

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA000532354A CA1264825A (fr) 1987-03-18 1987-03-18 Circuit logique a fet a couplage direct

Publications (1)

Publication Number Publication Date
CA1264825A true CA1264825A (fr) 1990-01-23

Family

ID=4135215

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000532354A Expired - Fee Related CA1264825A (fr) 1987-03-18 1987-03-18 Circuit logique a fet a couplage direct

Country Status (1)

Country Link
CA (1) CA1264825A (fr)

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Legal Events

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MKLA Lapsed