CA1255020A - Pseudo random framing generator circuit - Google Patents

Abstract

PSEUDO RANDOM FRAMING GENERATOR CIRCUIT
ABSTRACT OF THE INVENTION
This invention is a circuit for generating a framing pattern consisting of a pseudo random shift register sequence.
This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position.

Description

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PSEUDO RANDOM_FRAMING GENERATOR CIRCUIT
C~OSS-REFERENCE TO REI~TEp APPLICATIONS

The present application is related to copending Canadian Patent Application 497,540~5, which is assigned to the same Assignee and has the same inventive entity as the present case.
BA~KGROUND OF ~HE INVEN~ION

The present invention pertains to digital communications and transmission systems and more particularly to framing in~ormation transmi~ted along with data used to identify various ~ields within the data stream.
In the past, framing patterns have been limited to a small n~mber of bits. For example, the T-carrier systems used in telephony originally employed a framing pattern consisting of alternating ones and zeros. Later, khis framing pattern was replaced by two interleaved patterns, one to identify grames and a second pattern to identify a "sup~r~rame", a larg~r ~rame consisting of 12 ordinary frames. The ~irst pattern is a basic pattern of alternating ones and zeros. These framing bits occur in alternate ~raming bit positions and identify the framing bit position within a frame of 193 bits. The second fr~ming pattern, interleaved with the ~irst, is a pattern of (111000~. This framing patte~n identifies the alignment o~ the superframe relative to the ordinary ~rames .
Another modiication to the framing pattern introduced ~xtended superframe. Extended superframin~ is a technique wherein ~he basic fxaming pattern occurs only every fourth ~rame and identifies a 2~ ~rame pattern.
Since this framing pattern is only 6 bits long, a relativaly high potential ~or ~alsa framing is created.
~hi~ can occur when a particular data bit pattern corresponds to the framing bit pattern.
In a super~rame transmission system, the alternating ones and zeros with a period o~ four frames was sometimes imita~ed by the sign bit of a PC~ encoded 2 KHZ sine wave ~rom certain types o~ data modems. If the carrier sys~em lost ~raming while ~his ~ KHZ modem signal was being transmltted on one o~ tha voice "

channels, the framing circuit could mistake the sign bit of the voice channel for the framing bit. rhis situation would result in mis~raming for ~ll 2~ channels for considerable periods of time.
Similar problems would result with other framing patterns.
The above problem could be solved by use of a longer and more complex framing pattern9 but this introduces several new problems when previously known techniques are employed. The ~irst problem is that as the framing pattern length is increased, the amount of hardware needed to generate and detect the framing pattern increases correspondingly. For example, a 12 bit framing pattern would require twice as much transmission and detection hardware as a 6 bit framing pattern. Thus, longer framing patterns necessitate increased pattern generation and detection hardware.
A second problem is that as the framing pattern length ls increased, the time required to transmit the entire raming pattern increases proportionally. For T carrier systems, the framing bit position is 1 bit out of a 193 bits and occurs only eight thousand times per second. For the extended superframing situation, the framing bit occurs only two thousand times per secsnd. Since the entire framing pattern must be received before it can be recognized, searching for a long pattern through all possible bit positions in either the original T1 carrier or the extended superframing systems would require a great amount of time ~5 if a longer pattern were used.
Another pro~lem with short framing bit patterns arises when multiple levels of multiplexing are employed in a system.
Unless a different framing pattern is used for each multiplexing level, there i9 a danger of a higher level framing circuit falsely locking onto a lower level framing bit pattern. Separate framing patterns for each le~el would require long patterns, so that the pattern at each level could be orthogonal to patterns at lower levels. In present day T-carrier multiplexers, the problem is dealt with by using different frame length for each level of multiplexing. This causes lower level patterns to slide through ~ 2S5~

the higher ]evel patterns, eliminating confusion between them.
However, the s-ltuation also requires demu]tlplexing of all channels in the high level stream in order to recover even one data channel at the lowest level of multiplexing.
SUMMARY OF T~IE INVENTION
In modern telecommunications J systems are interconnected via transmission equipment to transmit data at relatively high rates of speed. For reco~ering this transmitted data, framing data is interleaved with the transmission data.
This framing data is generated by a pseudo random framing generator circuit.
The pseudo random framing generator circuit includes a cloc~. which is operated to produce a signal of a predetermined frequency. A frame sizing circuit adjusts the predetermined frequency of the clock signal to produce a new periodic signal, which has a period equal to the length in bits of the framing data combined with the transmission data.
A shift register arrangement is connected to the frame sizing circuit and to the transmission equlpment. The shift-register arrangement has a single lnput and a number of tap outputs. The shift-register arrangement cyclically operates in response to the new perlodic signal of the frame sizing circuit to produce a number of signals on each of the corresponding number of tap outputs. ~t least two of the tap outputs are connected via a gating circuit to the input of the shift-register arrangement.
Each connected tap output corresponds to a logic 1 bit representation of any polynomial of maximal length defined for a particular si7e of the shift-register arrangement.
The gating clrcuit is connected between the input and the tap outputs of the shift-register arrangement. The gating circuit also cyclically operates ln response to the connec~ed tap OUtpl1t signals to produce the framing data. The 8ating circuit is connected to the transmission equipment equipment and transmits the Eraming data to the transmission equipment.

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A ERIEF DESCRIPrION OF THE D~AWINGS
Figure 1 is a schematic diagram of a pseudo randam framing transmitter circuik emkodying the principles of operation of the present invention.
Figure 2 is a pselldo randam framing detector ci~cuit embo~ying the principles of op~ration of the presenk invention.
DESCR PTION OF IHE PREFERRED EMBODIMENT
Referring to Figure 1, khe transmltter section of a pseudo random framing circuit is shown. Bit clock 101 is connected to divide by M circuit 102. Divide by M circuit 102 is connected to the clock input o~ N-stage shift-register 103.
N-stage shift-registex 103 has two or m~xe oukput tap connec~ions to exclusive OR gate 104. Exclusive OR gake 104 has its output connected to the input of N-stage shifk-register 103. In addition, the outpu~ of exclusive OR gate 104 is also connected to the tra~smission equipment via the FR~MING BITS OUT leadO
Thus, tha framing pattarn output on the FR~MING RITS c~r lead is genera~cd using a transmit shift-register with feedkack logic which implements a polynomial which gives a maximal length pseudo random pattern. The input to the first stage of the shi~t-register (and aLso the framing pattern output) is the output o~ the ~eedback logic 104.
With a maxi~L length polynomlaL, the length of a repeating pattern is (2 raised to the pcwer N) minus 1 or (2 where N is the len~th in bits of a shi~register. This relationship is ~hown in Chapker 3 of SHIFT REGISTER SEQUENCES by Golomb Soloman, revised editi~n, 1981, publishe1 by Aegean Park Press. For example, a lO bit s~Lf~-reg:Lster produces a random pattern of 1023 bits before the same pattern is repeat0d. This is accomplished by having the shift-register 103 shift to the right by 1 bit position each time a frc~m mg bit is required. ~he lc~rger th~ vaLue of N ~hosen, the less the probability that a data seguence will imltate a fr~NL~g seguence. A 10 bit shift-register seems to be a practical implem~ntation. Although, shift-register si~es in the range of all int~gers frcm 3 to 64 seem to be most practical, the shift-register size may be an intRger in the range great~r than 64.

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The N-stage shift-regis-er 103 has tap outputs available from each bit or stage of the shift-register. Some of these tap outputs are shown connected to the lnpttt of exclusive OR
gate l04. The number of connections from the shift-register 103 to gate 104 and their relative position within the shift-register may be inferred from tables found in the Soloman reference cited above. For example, a 10 bit shift~register would provide a period of 1023 bits before repeating a sequence. One polynomial corresponding to this period is ~011 octal or base eight. To determine the connections from the shift-register to the exclusive OR gate for this polynomial, the octal representation should be depicted in binary. With this binary depiction, the first 10 bits from the right are chosen. Each bit position corresponds to one tap output of the shift-register. In the binary form of this polynomial~ a 1 in a particular bit position indicates a connection from that corresponding tap output to the exclusive OR
gate 104. For the polynomial 2011, connections from the shift-register to exclusive OR gate 104 would exist for bit position O ~the right most bit position) and bit pos:Ltion 3.
For each shift~register length, N, there are a number of different tap output configurations (polynomials) which give maximal length sequences. These polynomials may be found in the Soloman reference. For example, for a 10 bit shift-register, the Soloman reference shows many polynomials of maximal length, that is 1023. Table III-5 of the Soloman reference indicates there would be 60 possible poLynomials however, not all would ~e of maximal length. It has been shown that maximal length pseudo random sequences produced by polynomials are optimum with respect to auto~correlation and cross-correlation. Thus, for the same length shift-register N, numerous sequences can be generated, each having minimum correlation with shifted versions of itself or with sequences produced by o~her polynomials. As a result, use of different polynomials to generate different tap output configurations permits multiple levels of multlplexing data without confusLon between framing bits of different levels. In ~:255~

addition, th-ls eliminates the need for different frame lengths for each level of multiplexing.
A simple example will serve to illustrate the principles discussed above. Assume that the length of shift-register 103 is 4 bits. For a 4 bit long shiEt-register, the Soloman reference indicates that there are three possible polynomials. Two of these three polynomials are of maximal length~ The octal representation of these two maximal length polynomials is 23 and 31. For our example~ we will consider the maximal length po:Lynomial 23 in octal. The octal 23 yields a binary representation of 10011. Since, we are working with a 4 bit shift-register, the first 4 bits from the right are chosen, which yields 0011, reading from left to right. In this case, bit positions 0 and 1 (right justified) are connected from shift-register 103 to exclusive OR gate 104.

-STATE # BIT POSITIONS
-

2 1000

3 0100

4 O010 Table 1 shows the contents for a 4 bit shift register 103 with tap outpu~ connected for polynomial 23 octal. The bit positions of shift-register 103 are shown for each state of the shift-register sequence. m e shift-register state of all fowr zeros is illegal. qhe bit position shown Table 1 are bits 0 through 3, right justified. Bit 3, the left most bit, for example, of state #1 contains a 1 in bit position zero and a zero in bit positions 1, 2 and 3. Bit 3 is a zero for state #1, as can be seen from Table 1.
As shown in Table 1, the output of exclusive OR gate 104 generates 15 pseudo randcm states before state #1 is repeated.
Ihis is exactly what is expected, since as previously sta~ed a maximal length polyncmial yields (2N)-l pseudo random states. For this example, N is equal to 4. Therefore, we should see (24)-1 or 15 different states. Ihis is exactly what is observed from Table lo Circuit 101 generates the frequency of clock signals.
The rate at which divider 102 divides the clock, pr~duced by bit clGck 101, is given b~ M. Where M is the number of bits Ln a frame including the framm g bit. For example, in standard Tl carrier f ~ g, M would be equal to 193, 192 data bits plus 1 framing bit.
Use of divide by M circuit 102 allows framin~ to be achie~ed without the necessity of transmitting fr~m m g bits in data bit positions. Thus, this invention allows identification of the one framing or synchronization bit within a large group of data bits without utilizing or m~di~ying t`he data bits. m e framing pattern generated by this device is positionally independent of the relationship between data an~ framing bits.
Now turning to Figure ~, the ~eceiver section of the pseudo random fram1ng circuit is ahown. m e outpu~ of the receiver portion of the t~ansmission equipment (not ~hown) is connected via the ~EC$IVED EITS IN lead to bit d ock reccvery 201 and to switch 205. In addition, the transmission equipment is also conne~t3d via the RECEIVED BITS IN lead to framing control circuit 206.
Bit clock recovery 201 is connected to divide by M
circuit 202. Divide by M circuit 202 has lts output connected to the cloGk input of framlng contr~l circuit 206 and to the clock r~ 7 ,~

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input of N-stage shift register 203. Framing control circuit 206 is connected to the REsh~r lead of divide by M circuit 202.
Further, framing control circuit 206 is connected to switch 205.
Switch 205 is a signal pole double thraw switch, or a logic circuit wired to perform ~he switch function, normally operated to gate the output of exclusive OR gate 204 to the input of N-staye shift-register 203. Switch 205 may be operated by framing control circuit 206 to disconnect the output of exclusive OR gate 204 fram the input of N-stage shift-register 203 and to connect the output of the transmission equipment ~lrectly to N-stage shift-register 203 via the RE OE IVE BITS IN lead.
N-stage shift-register 203 is connected to exclusive OR
gate 204 via a nuTbber of tap outputs fram shift-registe~ 203. me output of exclusive O~ gate 204 is connected to switch 205, as m~ntioned above. In addition, the output of exclusive OR gate 204 is corn~ected to framing control circuit 206. Lastly, framing control circuit 206 is connec~ed to the logic of th~ digital commNnications system via the IN FRAME lead.
Receive bits are applied via the RE OE IVED BITS IN lead to hit clock recovery circuit 201. Bit clock recovery circuit 201 drives divide ~y M circuit 202. M is the number of bits including framing bits wit~in a particular frams. Divide by M circuit 202 produces a prelLmm ary framing signal. Since the divide ration M
is equal to the numb2r of bits per frame, a candidate fram m g bit, which may or may not be the actual framing bi~, is identified in the incoming bit stream.
The output of divide by M circuit 202 causes the N-stage shlft-register 203 to shift l bit to the right. Initially, framing oontrDl cireuit 206 operates switch 205 such that the RECEIVED BITS IN lead is eonneeted to the input o~ the N-stage shift-regis~er 203. Ihis ~hifting eontinues for N ecmplete cyeles of the divide circuit 202. At that time, if the candidate bit is the actual fram m g bit, the contents of the receive shift-register 203 will agree with the contents of the transmit shift-register.
At this time, the frame control eireuit 206 may opexate switch 205 so that ~he proper pseudo randam framing pattern is cont muously ,.~ 8 .~'`

generated locally by 203 and 204, without reference to the inc ~ng received bits.
Framing control circuit 206 compares the predicted fram mg bits from the output of exclusive OR gate 204 with the candidats framing bits which are received via ~he transmission channel. Framung control logic 206 may be implemented by using an up/down counter for counting the number of agreements in a known number of bits. If ~he framm ~ control circuit 206 concludes that there is sufficient agreement between the candidate and the predicted framing bits, it produces a signal on the IN FR~ME lead.
If framing control logic 206 determines that there is insufficient comparison between the candidate and predicted framing bits, control circuit 206 indicates via the RESET lead to divide by M
circuit 202 to reset divide circuit 202, and at the same time operates switch 205 so that the input of shift-register 203 i~
connected to the RE OE IV~D BITS IN lead. As a result, divide by M
circuit 202 selects a different candidate bit positio~ within the frame to be tested as the ram m ~ bit. This process continues until proper ccmparison is found~ At that time, the corresponding signal on the IN FRAME lead is produced to indicate th~
ca~arlson.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various mcdifications may be made therein without depart~ng fram the spirit of the invention or ~rom the sccpe of the appended clam~.

Claims (5)

WHAT IS CLAIMED IS:

1. In a digital telecommunications system, a pseudo random framing generator circuit for producing periodic framing bit data, said framing bit data being contained one bit at a time in bit positions regularly interleaved with transmission data for transmission to another digital telecommunications system via transmission equipment, said pseudo random framing generator circuit comprising:
clock means being operated to produce a periodic clock signal of a predetermined frequency;
frame sizing means connected to said clock means and being operated in response to said periodic clock signal to produce a second periodic signal, said second frequency being equal to said predetermined frequency divided by the number of bits of said transmission data and said framing bit data, said value of said framing bit data being independent of any values of said transmission data;
exclusive OR gating means connected to said transmission equipment;
shift-register means connected to said frame sizing means, to said exclusive OR gating means and to said transmission equipment, said shift-register means including a plurality of tap outputs and an input, said shift-register means being cyclically operated in response to said second periodic signal to produce a plurality of tap output signals on said corresponding plurality of tap outputs, at least two of said tap outputs being connected to said input via said exclusive OR gating means and each said connected tap output being a logic one bit positional representation corresponding to any polynomial of maximal length for a particular size of said shift-register means.

2. A pseudo random framing generator circuit as claimed in claim 1, said shift-register means including a clock input connected to said frame sizing means via a second periodic signal lead corresponding to said second periodic signal, said shift-register means being operated to displace by one bit position each current tap output signal unidirectionally and to produce said displaced tap output signals on said connected tap outputs.

3. A pseudo random framing generator circuit as claimed in claim 2, said shift-register means including a shift-register of size in bits of all integers in the range of 3 to 64.

4. A pseudo random framing generator circuit as claimed in claim 3, said shift-register means including a shift-register of size in bits of all integers in the range greater than 64.

5. A pseudo random framing generator circuit as claimed in claim 3, said exclusive OR gating means including a plurality of inputs and at least one output, said connected tap outputs being connected to corresponding ones of said exclusive OR gating means inputs and said exclusive OR gating means output being connected to said input of said shift-register.