CA1253234A - Method and apparatus for obtaining reliable synchronization over a noisy channel - Google Patents
Method and apparatus for obtaining reliable synchronization over a noisy channelInfo
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- CA1253234A CA1253234A CA000506433A CA506433A CA1253234A CA 1253234 A CA1253234 A CA 1253234A CA 000506433 A CA000506433 A CA 000506433A CA 506433 A CA506433 A CA 506433A CA 1253234 A CA1253234 A CA 1253234A
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Abstract
METHOD AND APPARATUS FOR OBTAINING RELIABLE
SYNCHRONIZATION OVER A NOISY CHANNEL
Abstract of the Disclosure Method and apparatus for synchronizing a transmitter and a receiver in a synchronous serial transmission system by serially transmitting a plurality of pseudo-random, coded sync words in an interlaced fashion with corresponding bits of each word transmitted in sequence.
At the receiver, received bits are first directed to a plurality of registers to undo the interlacing process and then decoded with the decoded word being compared by an autocorrelation technique to a known reference to thereby establish or reestablish synchronization between transmitter and receiver.
SYNCHRONIZATION OVER A NOISY CHANNEL
Abstract of the Disclosure Method and apparatus for synchronizing a transmitter and a receiver in a synchronous serial transmission system by serially transmitting a plurality of pseudo-random, coded sync words in an interlaced fashion with corresponding bits of each word transmitted in sequence.
At the receiver, received bits are first directed to a plurality of registers to undo the interlacing process and then decoded with the decoded word being compared by an autocorrelation technique to a known reference to thereby establish or reestablish synchronization between transmitter and receiver.
Description
3~3~
.
~D 15,365 _ METHOD AND.APPARATUS FOR OBTAINING .-RELIABLE SYNC~RONIZATION OVER ~-NOISY CHANNEL---Backqround of the Invention This invention relates to data communication and more particularly to obtaining reliable synchroniza-tion between a transmitter and a receiver over a noisy communication channel.
Synchronous methods of data transfer are often preferred when serial communication media are used because these methods permit higher throughput capability than asynchronous techniques. For proper functioning of synchronous systems, synchronization betwëen a receiver and a transmitter is essential. When a communication system operates in a noisy environment, receiver synch-ronization is often lost due to noise. In order to permit the receiver to acquire and maintain synchroni-zation with the transmitter, a commonly employed scheme periodically transmits binary synchronizin~ words includ-ing predetermined or pseudo random bit patterns. The receiver uses these synchronizing words to verify synchro-nization and to re-synchronize, if necessary. If the ~.
~ ~ ~5323~
RD-~5,366 communication channel is noisy, synchronizing words may become corrupted, e.g., the transmitted bit pattern may be randomly altered, causing the receiver to ~ose synchronization and may ultimately result in failure 05 to re-achieve it.
When noise characteristics of a communication medium are bursty, it is desirable to employ an inter-leaved message structure and forward error correction coding in order to overcome corruption of information due to noise. Further, it is also desirab-e to overcome corruption of synchronizing words due to noise and stil~ achieve both bit and message synchronization and ~e able to re-acquire synchronization of the receiver after it has been lost.
~5 In order to provide bounding, which gives an indication or where one message ends and the next message begins, it is often necessary to include delineation bits or code as part of the header and/or trailer along with the message being sent. Such bounding information contributes to overhead of the system in that it uses a portion of the available bandwidth which may be more efficient~y allocated to intel-igence data transmission.
Accordingly, it is an object of the present invention to provide a method and apparatus for bit and/or message synchronization.
Another object is to obtain accurate bit and/or message synchronization in a noisy environment, even if message bits are corrupted.
Yet another object is to provide a method and apparatus which permits rapid resynchronization after a receiver has lost synchronization with a transmitter.
Summary of the Invention In accordance with the present invention, a method for encoding and decoding information so as to be able ~ ~5~34 RD-15,365 to communicate over a noisy channel using bl~ck structured messages comprises transmitting a "no-op" or predetermined synchronizing word at predetermined intervals to permit both bit synchronization and message synchronization 05 at a receiver. The method is particularly well suited to systems in which a p-urality of remote receiver stations must be synchronixed with respect to a single master transmitter stationl especially those systems in which the electrical quality of transmission medium between the master stat:on and respective remote stations may independently randomly vary. In the communications protocol, messages and no-op words are interlaced to enable remote stations .o verify that synchronization is maintained and to resynchronize, if necessary, through-out communication contact with the transmitter. It is possible to achieve synchronization when bits in the synchronizing no-op word are corrupted due to noise or other unwanted disturbances by using a tracking decoder at receiver stations.
The features of the invention believed to be novel are set forth with particularity in the appended claims.
The invention itself, however, both as to organization and method of opera~ion, together with further objects and advantages thereof, may best be understood by reference to the detailed description taken in connection with the accompanying drawing.
Descripticn of the Drawinq Fig. l is a block diagram of a receiver in accordance with the present invention.
Figs. 2A through 2C are diagrams of an exemplary pseudo-random code and associated auto-correlation characteristics.
3L;~53~34 RD-15,366 Fig. 3 is a diagram of an example of a pilot no-op message word in accordance with the present invention.
Detailed Description This invention relates to a method and apparatus for coding and decoding information which permits better synchronization of block structured messages in synchronous communication schemes operating in noisy environments. Message synchronization is improved in the presence of random and/or burst bit errors (multiple contiguous bit errors), such as may be caused by noise.
Verifying synchronization and re-establishment of synchronization by the receiver may be readily effected.
Referring to Fig. l, a block diagram of a receiver useful with the present invention is shown. The receiver comprises an interface unit 10, a bit counter 12, and a sequencer 15. Bit counter 12 and sequencer 15 include a respective input coupled to a respective output of interface unit 10 for receiving a conditioned synchronizing word signal. Typically, interface unit 10 will include coupling means and a modem for obtaining the synchronizing word from a transmission medium and for conditioning the synchronizing word to be compatible with receiver circuitry respectively, as is known in the art.
The receiver further comprises a microprocessor 20, including an output connected to se~uencer 15 for providing timing signals thereto, and an input and output coupled to a respective input and output of a read only memory (ROM) 25. ROM 25 has stored therein predetermined code words, as is explained in detail in U.S. Patent 4,648,091, issued March 3, 1987 to Gajjar. Microprocessor 20 may comprise a type 8051 integrated circuit, or the like, manufactured by Intel, which includes ~53~3~
RD-15,366 a ROM. If the integrated circuit selected does not include a ROM then one may be provided, as is known in the art.
The receiver additionally comprises a plurality of data registers 30-l through 30-n, a plurality of code word registers 40-l through 40-n, and a plurality of error pattern registers 50--l through 50-n. Each data register 30 has a corresponding respective code word register 40 and a corresponding respective error pattern register 40 associated therewith to form a tracking decoder, as is described in the above-identified patent application. A respective output of sequencer 15 is respectively coupled to an input of each data register 30-l through 30-n in order t supply appropriate bits of the synchronizing word thereto.
Another output of microprocessor 20 is coupled to an input of sequencer 15 for providing timing signals thereto. Sequencer 15 functions as a steering device wherein each serial bit of the synchronizing word is directed to appropriate data register 30-l through 30-n. Bits of the synchronizing word are directed by sequencer 15 under control of microprocessor 20 such that any bit interleaving or other bit combination performed at the transmitter (not shown) prior to transmission is undone so that only bits associated with a single code word will be directed to each respective data register 30-l through 30-n.
Code word registers 40-l through 40-n, respec-tively, and error pattern registers 50-l through 50-n, respectively, each include an input and an output respectively coupled to an output and an input of micro-processor 20. Operation and interaction of code word registers 40-l through 40-n, error pattern registers 50-l through 50-n, and data registers 30-l through ~X3~3~ RD-15,36~
30-n are explained in detail in the aforementioned United States Patent Number 4,648,091.
Briefly, as each bit of a synchronizing word is received, it is steered into an appropriate data register 30-1 through 30-n by sequencer 15 under control of microprocessor 20. Generally, there are required as many data registers 30-1 through 30-n as there are independent code words used to form the synchronizing word. In a preferred embodiment, five Golay (24,12) code words are interleaved to form the synchronizing word, and thus five data registers 30-1 through 30-n along with five associated codle word registers 40-1 through 40-n and error pattern registers 50-1 through 50-n (i.e., n = 5) are required. Each data register is updated when a bit from the synchronizing word is directed thereto, the new contents thereof are compared with the contents of the respectively associated code word register are updated using an appropriate predetermined code word register are updated using an appropriate predetermined code word stored in ROM 25, as described in the above-identified patent. Thus, by using pseudo-random data words, which are encoded to generate associated code words, and interleaving the code words to form a synchronizing word, precise bit and message synchronization can be obtained at a receiver even when the synchronizing word is corrupted.
A method in accordance with the present invention comprises implementing an encoding and decoding scheme, wherein a suitable forward error correction code is used to encode a set of pseudo-random information sequences.
These sequences are selected to have many 0-1 and 1-0 transitions in order to facilitate establish-~3 ,j,.....
~2~53~23~
RD~15,366 ing and maintaining bit synchronization. The encodedset of sequences is transmitted, preferably in an interleaved manner to reduce the effect of burst errors to form a synchronizing word. Bit synchronization includes distinguishing at what instant the boundary between consecutively received bits occurs. If using broadband transmission, i.e., modulated carrier, bit synchronization permits the receiver local oscillator source to be locked into synchronization with the transmitter local oscillator source.
In order to establish message synchronization, the receiver first attempts to obtain bit synchronization using transitions in the received synchronizing word.
Once bit synchronization has been achieved, the receiver shifts each received bit into one of a plurality of data storage areas or registers. The number of data registers required is equal to the number of encoded sequences used to construct the synchronizing word. The plurality of data registers parses the received set of sequences in order to undo interleaving, if it was performed at the transmitter, and separately stores each received sequence. For each data register, there is a corresponding code word register for storing a code word having the smallest Hamming distance from the contents of the corresponding data register and a corresponding error pattern register for use as a scratch pad. As each bit is received, the contents of the data register in which the received bit is placed and those of the corresponding code word register are updated. A decoding method and apparatus applicable with the present invention for updating the data and code word registers is disclosed in aforementioned U.S.
ratent No. ~,648,091.
3~3~L
RD-L5,366 After storing each received bit in a respective data register and updating the corresponding code word reqister, the data portion of the code word register (the contents of the code word register comprises a 05 data portion containing a pseudo-random sequence and a redundancy portion) is compared with the last of the predetermined set of pseudo-random sequences which form the synchronizing worcl. If they do not correspond exactLy, the receiver waits for the next bit to arrive.
If they do correspond exactLy, the da~a portion of the code word corresponding to the last received bit is compared with the penultimate pseudo-random sequence.
Comparison proceeds untiL a point is reached when all message portions identically compare with predetermined corresponding pseudo-random sequences. Exact bit-by-bit correspondence over the entire set of predetermined pseudo-random sequences indicate~ the point of message synchronization to th`e receiver. Subsequently, this type of comparison can be employed by the receiver, to check if it is synchronized, whenever a synchronizing word is received. The process can also be used by the receiver to re-acquire synchronization whenever the receiver determines loss of synchronization has occurred.
In an exemplary embodiment of the present invention, the synchronizing word has a length of 120 bits and contains a predetermined ~0-bit data portion of interleaved pseudo-random sequences followed by 60 corresponding interleaved GoLay red~ndancy bits of a Golay (24,12) code word for each sequence. Thus, the synchronizing word comprises five Golay (24,12) code words, wherein each Golay (24,12) code word includes 12 data bits and 12 redundancy bits.
An ll-bit pseudo-random sequence plus a 12th even parity bit form a basic pseudo-random da~a word. An _~ _ ~;~53;~34 RD-15,366 appropriate 12-bit secuence and its complement, e.g., 111000100101 and 000111011010, respectively, are shown in Fig. 2A. The auto-correlation function of the 12-bit sequence, for whic:^ each bit-match with the reference 05 sequence is counted +l and each bit-mismatch is counted -1, is shown in Fig. 23. This selection for the basic predetermined data word message is optimal for applica-tion with the present invention because of the sharp peak of +11 obtained when an ll-bit matched condition exists. The peak may be used for deriving precise message timing for detarmining message synchronization at remote receiver units.
Further, selectior. of a 12-bit basic data word permits an extended Goiay (24, L2) code word to be ~enerated therefrom. An extended Golay (24,12) code is a forward error correcting code ~hich permits up to three bit values in the 24-bit code word to be corrected if they are detected as being incorrectly received. This enables more accurate message synchronization to be performed when app~ied according to the teachings of the present invention.
The auto-correlation function o~ Fig. 2B is obtained for a pseudo-random seGuence in the clear, i.e., no bits preceding nor foll~wing it. The progression of correlation values (out?ut ~ ), as a sequence is received one bit at a time, moves toward an exact match with reference sequence as is shown in Fig. 2C.
Twelve bits are needed for the basic data word if an extended Golay (2~ ,12) code is to be used. The 12th bit is selected to provide even parity so that the correlation value plunges to -I on the 12th shift as shown in Fig. 2C. T:~e 12th bit may be selected to provide odd parity; however, this generates a correlation value of +L at the 12th shift, a slightly less advanta-geous condition.
_g _ ~ ~:53~3~
RD-15,366 A 60-bit data field permits using five basic data words in construction of the synchronizing word.
As illustrated in Fig. 3A, these data words are inter-laced and are alternately complemented. Alternate 05 basic data word se~uences are complemented in order to provide a pilot transmission having many 0 to l and I to 0 bit transitions in order to facilitate deriving bit synchronization at the receiver. For clarity in identifying the five individual sequences, the bits L0 are staggered vertically in Fig. 3A.
Message synchronization may be derived on the basis of a unanimous or majority logic upon determin-ing correlation peaks of +IL on five successive bits (for example, bits #51 through ~55 of Fig. 3A), when the pseudo-random se~uences are fully received. It is very unlikely that errors will occur in just the right sequence to cause simultaneous, false, full-ampli-tude correlation peaks in all or even a majority of the five sequences and thus cause message synchronization to be determined at tAe wrong time by a receiver.
Corresponding Golay redundancy bits for the five pseudo-random sequences in the da~a field (bits ~1 to #60) of the synchronizing word occupy bits ~61 to $120 of the synchronizing word and are shown in Fig.
3B. Again, these are staggered to better expose their association with the five corresponding pseudo-random data words.
Thus has been illustrated and described a method and apparatus for obtaining reliable synchronization between a transmitter and a re~eiver over a noisy communicatior channel.
While only certain preferred features of the invention have been shown by way of illustration, many modifications and chanyes will occur to those skilled in the art.
~53~3~
RD l5,366 It is to be understood that the appended claims are intended to cover all such modifications and changes as fa~l within the true spirit and scope of the invention.
.
~D 15,365 _ METHOD AND.APPARATUS FOR OBTAINING .-RELIABLE SYNC~RONIZATION OVER ~-NOISY CHANNEL---Backqround of the Invention This invention relates to data communication and more particularly to obtaining reliable synchroniza-tion between a transmitter and a receiver over a noisy communication channel.
Synchronous methods of data transfer are often preferred when serial communication media are used because these methods permit higher throughput capability than asynchronous techniques. For proper functioning of synchronous systems, synchronization betwëen a receiver and a transmitter is essential. When a communication system operates in a noisy environment, receiver synch-ronization is often lost due to noise. In order to permit the receiver to acquire and maintain synchroni-zation with the transmitter, a commonly employed scheme periodically transmits binary synchronizin~ words includ-ing predetermined or pseudo random bit patterns. The receiver uses these synchronizing words to verify synchro-nization and to re-synchronize, if necessary. If the ~.
~ ~ ~5323~
RD-~5,366 communication channel is noisy, synchronizing words may become corrupted, e.g., the transmitted bit pattern may be randomly altered, causing the receiver to ~ose synchronization and may ultimately result in failure 05 to re-achieve it.
When noise characteristics of a communication medium are bursty, it is desirable to employ an inter-leaved message structure and forward error correction coding in order to overcome corruption of information due to noise. Further, it is also desirab-e to overcome corruption of synchronizing words due to noise and stil~ achieve both bit and message synchronization and ~e able to re-acquire synchronization of the receiver after it has been lost.
~5 In order to provide bounding, which gives an indication or where one message ends and the next message begins, it is often necessary to include delineation bits or code as part of the header and/or trailer along with the message being sent. Such bounding information contributes to overhead of the system in that it uses a portion of the available bandwidth which may be more efficient~y allocated to intel-igence data transmission.
Accordingly, it is an object of the present invention to provide a method and apparatus for bit and/or message synchronization.
Another object is to obtain accurate bit and/or message synchronization in a noisy environment, even if message bits are corrupted.
Yet another object is to provide a method and apparatus which permits rapid resynchronization after a receiver has lost synchronization with a transmitter.
Summary of the Invention In accordance with the present invention, a method for encoding and decoding information so as to be able ~ ~5~34 RD-15,365 to communicate over a noisy channel using bl~ck structured messages comprises transmitting a "no-op" or predetermined synchronizing word at predetermined intervals to permit both bit synchronization and message synchronization 05 at a receiver. The method is particularly well suited to systems in which a p-urality of remote receiver stations must be synchronixed with respect to a single master transmitter stationl especially those systems in which the electrical quality of transmission medium between the master stat:on and respective remote stations may independently randomly vary. In the communications protocol, messages and no-op words are interlaced to enable remote stations .o verify that synchronization is maintained and to resynchronize, if necessary, through-out communication contact with the transmitter. It is possible to achieve synchronization when bits in the synchronizing no-op word are corrupted due to noise or other unwanted disturbances by using a tracking decoder at receiver stations.
The features of the invention believed to be novel are set forth with particularity in the appended claims.
The invention itself, however, both as to organization and method of opera~ion, together with further objects and advantages thereof, may best be understood by reference to the detailed description taken in connection with the accompanying drawing.
Descripticn of the Drawinq Fig. l is a block diagram of a receiver in accordance with the present invention.
Figs. 2A through 2C are diagrams of an exemplary pseudo-random code and associated auto-correlation characteristics.
3L;~53~34 RD-15,366 Fig. 3 is a diagram of an example of a pilot no-op message word in accordance with the present invention.
Detailed Description This invention relates to a method and apparatus for coding and decoding information which permits better synchronization of block structured messages in synchronous communication schemes operating in noisy environments. Message synchronization is improved in the presence of random and/or burst bit errors (multiple contiguous bit errors), such as may be caused by noise.
Verifying synchronization and re-establishment of synchronization by the receiver may be readily effected.
Referring to Fig. l, a block diagram of a receiver useful with the present invention is shown. The receiver comprises an interface unit 10, a bit counter 12, and a sequencer 15. Bit counter 12 and sequencer 15 include a respective input coupled to a respective output of interface unit 10 for receiving a conditioned synchronizing word signal. Typically, interface unit 10 will include coupling means and a modem for obtaining the synchronizing word from a transmission medium and for conditioning the synchronizing word to be compatible with receiver circuitry respectively, as is known in the art.
The receiver further comprises a microprocessor 20, including an output connected to se~uencer 15 for providing timing signals thereto, and an input and output coupled to a respective input and output of a read only memory (ROM) 25. ROM 25 has stored therein predetermined code words, as is explained in detail in U.S. Patent 4,648,091, issued March 3, 1987 to Gajjar. Microprocessor 20 may comprise a type 8051 integrated circuit, or the like, manufactured by Intel, which includes ~53~3~
RD-15,366 a ROM. If the integrated circuit selected does not include a ROM then one may be provided, as is known in the art.
The receiver additionally comprises a plurality of data registers 30-l through 30-n, a plurality of code word registers 40-l through 40-n, and a plurality of error pattern registers 50--l through 50-n. Each data register 30 has a corresponding respective code word register 40 and a corresponding respective error pattern register 40 associated therewith to form a tracking decoder, as is described in the above-identified patent application. A respective output of sequencer 15 is respectively coupled to an input of each data register 30-l through 30-n in order t supply appropriate bits of the synchronizing word thereto.
Another output of microprocessor 20 is coupled to an input of sequencer 15 for providing timing signals thereto. Sequencer 15 functions as a steering device wherein each serial bit of the synchronizing word is directed to appropriate data register 30-l through 30-n. Bits of the synchronizing word are directed by sequencer 15 under control of microprocessor 20 such that any bit interleaving or other bit combination performed at the transmitter (not shown) prior to transmission is undone so that only bits associated with a single code word will be directed to each respective data register 30-l through 30-n.
Code word registers 40-l through 40-n, respec-tively, and error pattern registers 50-l through 50-n, respectively, each include an input and an output respectively coupled to an output and an input of micro-processor 20. Operation and interaction of code word registers 40-l through 40-n, error pattern registers 50-l through 50-n, and data registers 30-l through ~X3~3~ RD-15,36~
30-n are explained in detail in the aforementioned United States Patent Number 4,648,091.
Briefly, as each bit of a synchronizing word is received, it is steered into an appropriate data register 30-1 through 30-n by sequencer 15 under control of microprocessor 20. Generally, there are required as many data registers 30-1 through 30-n as there are independent code words used to form the synchronizing word. In a preferred embodiment, five Golay (24,12) code words are interleaved to form the synchronizing word, and thus five data registers 30-1 through 30-n along with five associated codle word registers 40-1 through 40-n and error pattern registers 50-1 through 50-n (i.e., n = 5) are required. Each data register is updated when a bit from the synchronizing word is directed thereto, the new contents thereof are compared with the contents of the respectively associated code word register are updated using an appropriate predetermined code word register are updated using an appropriate predetermined code word stored in ROM 25, as described in the above-identified patent. Thus, by using pseudo-random data words, which are encoded to generate associated code words, and interleaving the code words to form a synchronizing word, precise bit and message synchronization can be obtained at a receiver even when the synchronizing word is corrupted.
A method in accordance with the present invention comprises implementing an encoding and decoding scheme, wherein a suitable forward error correction code is used to encode a set of pseudo-random information sequences.
These sequences are selected to have many 0-1 and 1-0 transitions in order to facilitate establish-~3 ,j,.....
~2~53~23~
RD~15,366 ing and maintaining bit synchronization. The encodedset of sequences is transmitted, preferably in an interleaved manner to reduce the effect of burst errors to form a synchronizing word. Bit synchronization includes distinguishing at what instant the boundary between consecutively received bits occurs. If using broadband transmission, i.e., modulated carrier, bit synchronization permits the receiver local oscillator source to be locked into synchronization with the transmitter local oscillator source.
In order to establish message synchronization, the receiver first attempts to obtain bit synchronization using transitions in the received synchronizing word.
Once bit synchronization has been achieved, the receiver shifts each received bit into one of a plurality of data storage areas or registers. The number of data registers required is equal to the number of encoded sequences used to construct the synchronizing word. The plurality of data registers parses the received set of sequences in order to undo interleaving, if it was performed at the transmitter, and separately stores each received sequence. For each data register, there is a corresponding code word register for storing a code word having the smallest Hamming distance from the contents of the corresponding data register and a corresponding error pattern register for use as a scratch pad. As each bit is received, the contents of the data register in which the received bit is placed and those of the corresponding code word register are updated. A decoding method and apparatus applicable with the present invention for updating the data and code word registers is disclosed in aforementioned U.S.
ratent No. ~,648,091.
3~3~L
RD-L5,366 After storing each received bit in a respective data register and updating the corresponding code word reqister, the data portion of the code word register (the contents of the code word register comprises a 05 data portion containing a pseudo-random sequence and a redundancy portion) is compared with the last of the predetermined set of pseudo-random sequences which form the synchronizing worcl. If they do not correspond exactLy, the receiver waits for the next bit to arrive.
If they do correspond exactLy, the da~a portion of the code word corresponding to the last received bit is compared with the penultimate pseudo-random sequence.
Comparison proceeds untiL a point is reached when all message portions identically compare with predetermined corresponding pseudo-random sequences. Exact bit-by-bit correspondence over the entire set of predetermined pseudo-random sequences indicate~ the point of message synchronization to th`e receiver. Subsequently, this type of comparison can be employed by the receiver, to check if it is synchronized, whenever a synchronizing word is received. The process can also be used by the receiver to re-acquire synchronization whenever the receiver determines loss of synchronization has occurred.
In an exemplary embodiment of the present invention, the synchronizing word has a length of 120 bits and contains a predetermined ~0-bit data portion of interleaved pseudo-random sequences followed by 60 corresponding interleaved GoLay red~ndancy bits of a Golay (24,12) code word for each sequence. Thus, the synchronizing word comprises five Golay (24,12) code words, wherein each Golay (24,12) code word includes 12 data bits and 12 redundancy bits.
An ll-bit pseudo-random sequence plus a 12th even parity bit form a basic pseudo-random da~a word. An _~ _ ~;~53;~34 RD-15,366 appropriate 12-bit secuence and its complement, e.g., 111000100101 and 000111011010, respectively, are shown in Fig. 2A. The auto-correlation function of the 12-bit sequence, for whic:^ each bit-match with the reference 05 sequence is counted +l and each bit-mismatch is counted -1, is shown in Fig. 23. This selection for the basic predetermined data word message is optimal for applica-tion with the present invention because of the sharp peak of +11 obtained when an ll-bit matched condition exists. The peak may be used for deriving precise message timing for detarmining message synchronization at remote receiver units.
Further, selectior. of a 12-bit basic data word permits an extended Goiay (24, L2) code word to be ~enerated therefrom. An extended Golay (24,12) code is a forward error correcting code ~hich permits up to three bit values in the 24-bit code word to be corrected if they are detected as being incorrectly received. This enables more accurate message synchronization to be performed when app~ied according to the teachings of the present invention.
The auto-correlation function o~ Fig. 2B is obtained for a pseudo-random seGuence in the clear, i.e., no bits preceding nor foll~wing it. The progression of correlation values (out?ut ~ ), as a sequence is received one bit at a time, moves toward an exact match with reference sequence as is shown in Fig. 2C.
Twelve bits are needed for the basic data word if an extended Golay (2~ ,12) code is to be used. The 12th bit is selected to provide even parity so that the correlation value plunges to -I on the 12th shift as shown in Fig. 2C. T:~e 12th bit may be selected to provide odd parity; however, this generates a correlation value of +L at the 12th shift, a slightly less advanta-geous condition.
_g _ ~ ~:53~3~
RD-15,366 A 60-bit data field permits using five basic data words in construction of the synchronizing word.
As illustrated in Fig. 3A, these data words are inter-laced and are alternately complemented. Alternate 05 basic data word se~uences are complemented in order to provide a pilot transmission having many 0 to l and I to 0 bit transitions in order to facilitate deriving bit synchronization at the receiver. For clarity in identifying the five individual sequences, the bits L0 are staggered vertically in Fig. 3A.
Message synchronization may be derived on the basis of a unanimous or majority logic upon determin-ing correlation peaks of +IL on five successive bits (for example, bits #51 through ~55 of Fig. 3A), when the pseudo-random se~uences are fully received. It is very unlikely that errors will occur in just the right sequence to cause simultaneous, false, full-ampli-tude correlation peaks in all or even a majority of the five sequences and thus cause message synchronization to be determined at tAe wrong time by a receiver.
Corresponding Golay redundancy bits for the five pseudo-random sequences in the da~a field (bits ~1 to #60) of the synchronizing word occupy bits ~61 to $120 of the synchronizing word and are shown in Fig.
3B. Again, these are staggered to better expose their association with the five corresponding pseudo-random data words.
Thus has been illustrated and described a method and apparatus for obtaining reliable synchronization between a transmitter and a re~eiver over a noisy communicatior channel.
While only certain preferred features of the invention have been shown by way of illustration, many modifications and chanyes will occur to those skilled in the art.
~53~3~
RD l5,366 It is to be understood that the appended claims are intended to cover all such modifications and changes as fa~l within the true spirit and scope of the invention.
Claims (13)
1. A method for synchronizing a transmitter and a receiver in a synchronous serial transmission communication system comprising the steps of:
serially transmitting a plurality of sync words encoded as code words of a forward error correction code, said words being transmitted in an interlaced fashion, corresponding bits of each word being transmitted in sequence, directing received bits of said sync words into different registers for processing, each register containing bits corresponding to a different word, decoding said sync words to provide decoded words; and detecting by correlating techniques correspondence between a preselected number of said decoded words and a known reference to thereby establish synchronization between said receiver and said transmitter.
serially transmitting a plurality of sync words encoded as code words of a forward error correction code, said words being transmitted in an interlaced fashion, corresponding bits of each word being transmitted in sequence, directing received bits of said sync words into different registers for processing, each register containing bits corresponding to a different word, decoding said sync words to provide decoded words; and detecting by correlating techniques correspondence between a preselected number of said decoded words and a known reference to thereby establish synchronization between said receiver and said transmitter.
2. The method of claim 1 wherein the step of serially transmitting comprises alternately transmitting the complement of said sync word.
3. The method of claim 2 wherein said decoding step comprises generating an updated decoded word corresponding to received synchronous words on a received bit-by-bit basis.
4. The method of claim 3 wherein said synchronous word is selected to be pseudo-random in character and relatively high in transitions between transmitted states.
5. The method of claim 1 further including the steps of beginning and terminating the transmission of encoded data with said sync words in order to delineate the beginning and end of a data stream.
6. The apparatus for synchronizing a transmitter and a receiver in a synchronous serial transmission communication system comprising:
means for serially transmitting a plurality of sync words encoded as code words of a forward error correction code, said words being transmitted in an interlaced fashion, corresponding bits of each word being transmitted in sequence, a plurality of data registers, means for directing received bits of said sync words into different of said registers for processing, each register containing bits corresponding to a different word, means for decoding said sync words to provide decoded words; and correlation means for detecting the correspondence between a preselected number of said decoded words and a known reference to thereby establish synchronization between said receiver and said transmitter.
means for serially transmitting a plurality of sync words encoded as code words of a forward error correction code, said words being transmitted in an interlaced fashion, corresponding bits of each word being transmitted in sequence, a plurality of data registers, means for directing received bits of said sync words into different of said registers for processing, each register containing bits corresponding to a different word, means for decoding said sync words to provide decoded words; and correlation means for detecting the correspondence between a preselected number of said decoded words and a known reference to thereby establish synchronization between said receiver and said transmitter.
7. The apparatus method of claim 6 further including means for alternately transmitting the complement of said sync word.
8. The apparatus of claim 7 wherein said means for decoding comprises means for generating an updated decoded word corresponding to received synch words on a received bit-by-bit basis.
9. The apparatus of claim 8 wherein said sync word is selected to be pseudo-random in character and relatively high in transitions between transmitted states.
10. The apparatus of claim 9 wherein said transmitting means includes means for transmitting encoded data intermediate said sync words to delineate the beginning and end of said data.
11. A method of synchronizing a transmitter and a receiver in a synchronous serial transmission system comprising the steps of:
transmitting with each message block a sync word encoded as a code word of the forward error correction code being employed for the message block;
decoding said sync word at the receiver to provide a decoded sync word; and comparing said decoded sync word with a known reference to establish synchronization between said transmitter and receiver.
transmitting with each message block a sync word encoded as a code word of the forward error correction code being employed for the message block;
decoding said sync word at the receiver to provide a decoded sync word; and comparing said decoded sync word with a known reference to establish synchronization between said transmitter and receiver.
12. The method of claim 11 wherein said transmitting step comprises:
transmitting said sync word in the form of a plurality of subwords, each subword being a codeword of said forward error correction code, said subword being transmitted in interlaced fashion and wherein said decoding step comprises de-interlacing said sync word to reform and decode each of said subwords.
transmitting said sync word in the form of a plurality of subwords, each subword being a codeword of said forward error correction code, said subword being transmitted in interlaced fashion and wherein said decoding step comprises de-interlacing said sync word to reform and decode each of said subwords.
13. The method of claim 12 further including the step of processing said decoded sync word at said receiver by correlation techniques to detect correspondence between said reformed sync word and a known reference, said correspondence serving to establish synchronization between the receiver and transmitter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000506433A CA1253234A (en) | 1986-04-11 | 1986-04-11 | Method and apparatus for obtaining reliable synchronization over a noisy channel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000506433A CA1253234A (en) | 1986-04-11 | 1986-04-11 | Method and apparatus for obtaining reliable synchronization over a noisy channel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1253234A true CA1253234A (en) | 1989-04-25 |
Family
ID=4132866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000506433A Expired CA1253234A (en) | 1986-04-11 | 1986-04-11 | Method and apparatus for obtaining reliable synchronization over a noisy channel |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1253234A (en) |
-
1986
- 1986-04-11 CA CA000506433A patent/CA1253234A/en not_active Expired
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