CA1252524A - Electronic delay circuits - Google Patents

Electronic delay circuits

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Publication number
CA1252524A
CA1252524A CA000209509A CA209509A CA1252524A CA 1252524 A CA1252524 A CA 1252524A CA 000209509 A CA000209509 A CA 000209509A CA 209509 A CA209509 A CA 209509A CA 1252524 A CA1252524 A CA 1252524A
Authority
CA
Canada
Prior art keywords
voltage
circuit
impact
sustained
fuze
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000209509A
Other languages
French (fr)
Other versions
CA209509S (en
Inventor
Iain T. Robertson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Secretary of State for Defence
Original Assignee
UK Secretary of State for Defence
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UK Secretary of State for Defence filed Critical UK Secretary of State for Defence
Priority to CA000209509A priority Critical patent/CA1252524A/en
Application granted granted Critical
Publication of CA1252524A publication Critical patent/CA1252524A/en
Expired legal-status Critical Current

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Abstract

ABSTRACT OF THE DISCLOSURE
A delayed action circuit including input connections, a voltage - limiting circuit connected to the input connections, a resistance - capacitance integrating network connected to the voltage-limiting circuit and a threshold circuit connected to the integrating network, characterised in that the threshold circuit has a control input connected to the input connections for controlling its threshold voltage in response to the peak voltage of any signal applied to the input connections and thereby providing a longer delay in response to a higher peak input voltage.

Description

52~L~

`;
This inven-tion rela-tes to electronic delay circuits and in particular to delayed switch circuits whereby a switch, which may be an electronic switch~ is closed in response to a stimulus~ the switch being closed after so~e predetermined d~lay following the application of the stimulus.
In a known type of delayed swi-tch circuit the stimulus provides a voltage across a resistor and a timing capacitor connected in series.
A threshold circuit is connected to the timing capacitor and is constructed so that it will effectively close a circuit when the voltage across the timing capacitor reaches some predetermined value. The delay between the application of the stimulus and the closing of the circuit depends on the applied voltage, a larger voltage producing a shorter delay. If a constant delay switch circuit is required, the delay being approximately independent of the strength of the stimulus, the voltage provided by the stimulus can be applied to the timing capacitor through a voltage-limiting network. ~or example the voltage can be applied to a Zener diode and a resistor in series and the voltage across the Zener diode can be used to oharge the timing capacitor.
According to the present invention a delayed action circuit includes input connections, a voltage-limiti~g circuit connected to the input connections, a resistance-capacitance in-tegrating network connected to the voltage-limiting circuit~ and a threshold circuit connected to the integrating network~ characterised in that the threshold CiICUit has a control input connected to the input connections for controlling its threshold voltage in response to the peak voltage of any signal applied to the input connections and thereby providing a longer delay in response to a higher peak input voltage.

3 Ir--The threshold circllit may include a programm~ble unijunction transistor (~JT) having its gate electrode connected to receive a voltage derived from the input signal and its source electrode connected to receive an output from the integrating network.
The gate voltage may be derived from the input signal by means of a network inclu~ ng a Zener diode, the network being such that the gate voltage cannot exceed the maximum voltage to which the capacitance of the integrating network can be charged.
The delayed action circuit may be incorporated into ~nelectronic fuze for an explosive device in which the input signal is provided by the rectified output of a piezo~electric transducer and in which the closing of a switch circuit effected by the delayed action circuit operates a detonator. The voltage output of the transducer D~ay act as a power 9Upply for the detonator so that no separate power supply is required.
An embodiment of the invention will now be described by way of example only with reference to the accompanying drawing which is a circuit diagram of an electronic fuze for an explosive device.
The circuit shown is suitably positioned within an explosive device (not shown) such as a bomb.
A piezo-electric transducer 1 is ~o positioned within ~he bomb (not shown) that it will receive a mechanical blow when the bomb impacts with a target. The mechanical force of the blow i9 converted by the transducer 1 to an electrical voltage the magnitude of which is related to the magnitude of the mechanical force.

2q~

The voltage output of the piezo-electric transducer 1 is rectified by a diode bridge 2 and applied to a storage capacitor 3.
A resistor 4 and a Zener diode 5 are connected in series across -the storage capacitor 3 and the voltage across the Zener diode 5 is applied to a resistor 6 and a timing capacitor 7 connected in series.
In parallel with the storage capacitor 3 is a potential divider chain comprising two resistors 8 and 9 in series. A Zener diode 10 is connected in parallel with the resistor 9 so as to limit the output voltage of the potential divider which is applied as a gate voltage to a PU~ 11. In parallel with the timing capacitor 7 is a resistor 12 connected in series with the main current path -through the PUT 11. The voltage developed across the resis-tor 12 is applied to a gate input of a silicon controlled rectifier (SCR) 14.
~he main current path of the SCR 14 is connected in series with a detonator 15 and together they are connected in parallel with the storage capacitor 3. ~ .-In operation, wh0n the bomb impacts a target of a given material~the rectified output of the transducer charges the storage capacitor 3 to a corresponding voltage level. The stored charge provides the stimulus voltage for the delayed switch and also the power supply for the detonator 15. ~he resistor 4 and the Zener diode 5 provide a voltage which is substantially independent of the magnitude of the stimulus voltage from which the timing capacitor 7 is charged through the resistor 6. The resistors 8 and 9 and the Zener diode 10 derive a gate voltage for the PU~ 11 which is proportional to the stimulus voltage up to a predetermined value of the stimulus vol-tage determined
2~

by the Zener diode 10 and is substantially constant for higher values.
The threshold vol-tage of the PU~ controlled by the gate voltage, so that a higher stimulus vol-tage, up -to the predetex~ined value, will raise the threshold voltage.
~ hen the ~oltage across the timing capacitor 7 reaches the threshold voltage, the PUT 11 will become conducting and a voltage will be developed across the resistor 12 which will cause the SCR 14 to become conductive. The storage capacitor 3 will then discharge through the detonator 15. The capacitor 13 prevents transients from reaching the SCR 14 and causing premature detonation. The higher the tbleshold voltage the longer will be the time delay before the threshold voltage is reached. Hence the stimulus voltage controls the time delay between the occurrence ofthe stimulus and the detonation, so that a larger stimulus causes a longer delay.
Many variations and modifications of the embodiment described will suggest themsélves to those skilled in the art. For example the bridge rectifier circuit 2 can be replaced by a diode in series with the input ofthe delay circuit. ~his arrangement is more suitable if the output of -the transducer 1 is expected to be a series of pulses since then the storage capacitor 3 will become charged to a voltage proportional to the magnitude o~ the largest of these pulses.
A Zener diode may also be placed in parallel with the storage capacitor 3 to limit the maximum voltage that can be applied across the SCR 14 to a value less than the maximum rated forward blocking voltage of the SCR 14.

1~`

Claims (8)

WHAT I CLAIM IS: -
1. A fuze circuit for an explosive device comprising an impact transducer for producing a sustained voltage in response to an impact, such that a higher voltage will be produced in response to a hard impact and a lower voltage in response to a soft impact, and a delayed-action detonator circuit connected to the impact transducer, the detonator circuit including a voltage limiting circuit connected to receive the sustained voltage and adapted to derive therefrom a predetermined voltage;
a resistance-capacitance integrating network connected to the voltage limiting circuit to receive the predetermined voltage and to derive therefrom an increasing voltage; and a threshold circuit connected to the integrating network to receive the increasing voltage and to produce a detonating signal when the increasing voltage reaches a threshold voltage derived from the sustained voltage and said detonating circuit being adapted to produce a detonating signal in response to the sustained voltage after a delay following the impact.
2. A fuze circuit as claimed in claim 1 wherein the threshold circuit includes a programmable unijunction transistor having its gate electrode connected to receive a voltage whose magnitude is dependent on the magnitude of the sustained voltage.
3. A fuze circuit as claimed in claim 2 wherein the gate electrode is connected to an intermediate point in a resistive potential divider chain which is connected to receive the sustained voltage.
4. A fuze circuit as claimed in claim 3 wherein a voltage limiter is connected to the gate electrode so that the threshold voltage cannot exceed the maximum value of the increasing voltage.
5. A fuze circuit as claimed in any of claim 1, 2 or 3, wherein the impact transducer comprises a piezo-electric transducer device, connected via a rectifier to a storage capacitor, the sustained voltage being the voltage developed on the storage capacitor.
6. A fuze circuit as claimed in any of claim 1, 2 or 3, wherein the detonating signal is applied to a switching device connected in series with a detonator device so as to cause the sustained voltage to be applied to the detonator device when the detonating signal is produced, thus activating the detonator.
7. A fuze circuit as claimed in any of claim 1, 2 or 3 in which the impact transducer is arranged to act as a power supply so that no separate power supply is required.
8. A fuze circuit as claimed in claim 1, 2 or 4, where said impact transducer comprises a piezo-electric transducer device, connected via a rectifier to a storage capacitor, the sustained voltage being the voltage developed on the storage capacitor, and wherein said impact transducer is arranged to act as a power supply so that no separate power supply is required.
CA000209509A 1974-09-19 1974-09-19 Electronic delay circuits Expired CA1252524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA000209509A CA1252524A (en) 1974-09-19 1974-09-19 Electronic delay circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA000209509A CA1252524A (en) 1974-09-19 1974-09-19 Electronic delay circuits

Publications (1)

Publication Number Publication Date
CA1252524A true CA1252524A (en) 1989-04-11

Family

ID=4101176

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000209509A Expired CA1252524A (en) 1974-09-19 1974-09-19 Electronic delay circuits

Country Status (1)

Country Link
CA (1) CA1252524A (en)

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