CA1249370A - Method for processing informations and processors for the working of said method - Google Patents

Abstract

Method for processing informations and processors for the working of said method.
ABSTRACT

There is described a method for processing infor-mations carried by a document, wherewith said informations are converted into digital signals which are then analysed by means of algorithms, which comprises performing the primary algorithm with a processor with a high clock frequency, simulating said primary algorithm performing on a computer to determine the cri-tical points and most repetitive tasks of said primary algorithm, isolating said tasks to assign same to dedicated processors for the performing thereof, causing each said processors to work according to a microprogramme gathering secundary algorithms for said most repetitive tasks, said processors each comprising a specialized operating unit comprised of an address unit and at least one logic or arithmetic execution unit. There are also described processors for the working of said method.

Description

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The invention has for object a method for proces-sing informations carried by a document, which comprises conver-ting said informations into digital signals which are then analyzed by means of algorithms.
The processing of documents and the character recognition are not new art. A large number of algorithms have already been studied and proposed. A large number of document reading machines are commercially available. One of the main features of image processing lies in the difficulty to implement the algorithms in the conventional data-processing systems. To reach a processing time of interest, it is absolutely imperative to resort to dedicated equipment. The link between the algorithm and the equipment is direct: such dedicated equipement may gene-rally not be used to implement other algorithms.
There is now proposed an original method which is based on a specific architecture which may be applied to many systems or algorithms.
The main capacities of said method are as follows:
- a general nature which allows fast implementing of many al-20 gorithms, - a high computing power due to the presence of many specific combinative means, - the processing unit of the processor may be implemented in a dedicated integrated circuit, which allows reducing the comple-25 xity thereof while retaining the performances thereof.
For this purpose according to the invention, the primary algorithm is being performed by a processor with a high clock frequency, the performing of the primary algorithm is si-mulated on a computer to determine the critical points and most 30 repetitive taks of said primary algorithm, said tasks are singled-out to assign same to dedicated processors for the perfor-ming thereof, each said processors is caused to work according to a microprogramme gathering secundary algorithms for said most repetitive tasks, said processors each comprising a specialized

2 ~ 33~0 operating unit comprised of an addressing unit and at least one other logic or arithmetic execution unit.
The invention also has for object processors for the working of said method.
There are already specialized processors which perform particular algorithms which are specific to a system and which may but with difficulty or even not all be used in other systems .
Should the known methods and mf~ans be used to make a processor which is easily implemented, there would be obtained an extremely intricate and specially extremely slow processor .
The invention has for object to obviate such draw-backs and to provide a compact processor which is fast and easy to implement.
In an advantageous embodiment of the invention, the processor operating unit comprises an addressing unit, a logic unit, an arithmetic unit and a computing unit for special functions.
Other details and features of the invention will stand out from the following description, given by way of non limitative example and with reference to the accompanying dra-wings, in which:
Figure 1 is a flow-chart of the primary algorithm.
Figure 2 is a block diagram of the processing method according to the invention.
Figure 3 shows one example of a secundary algo-rithm .
Figure 4 is a block diagram of a dedicated pro-cessor according to the invention.
Figure 5 is a block diagram of the operating unit from the processor as shown in figure 4.
The method according to the invention is notably intended for processing informations such as texts, photographs,

3. ~ 37~

graphics..., carried by documents. According to said method, said informations are converted into digital signals which are analyzed by means of algorithms. The algorithms being used may vary from one application to another. It is however possible to determine base routines which are to be found in most methods.
Said routines comprise the critical part of the system as regards the execution speed. The task which lies in chaining said rou-tines, processing the results, and controlling the good develop-ment of the algorithm, does not require specialized functions and lO may without any problem be performed by a conventional proces-sing system. This is not the case for the base routines. Said routines are grouped in a microprogramme which is defined as a specialized logic system which performs a set of dedicated instructions for a spccific algorithm type.
Said instructions thus comprise the critical and repetitive parts of the implemented algorithms. The way said functions have been determined, is of importance. The ob ject is to cover as many algorithms as possible to make the system as general as possible.
By determining the main critical points from the most-used algorithms and by implementing said critical functions, the "algorithm on silicon" character is withdrawn from the spe-cialized equipment, to impart thereto a general use feature.
The process is as follows: the selected algorithms 25 are studied and simulated on a computer by using a conventional programming language. The critical points are detected.
A three-way choice is then faced:
- the function will be performed by the standard microprocessor;
- the function will be performed by the specialized processor 30 in the form of a microprogramme;
- the function will be performed by a specialized integrated cir-cuit .
Depending on the frequency the functions are being used with and the difficulty in implementing such functions on

4. ~ i37~:3 a standard microprocessor, the second or third choice will be selected .
With reference to figure 1, there will now be des-cribed an example of primary algorithm being used. The informa-

5 tions originating from the reading of a document undergo a binari-zation in 1, and a half-tint coding in 2. From both said informa-tions, the document undergoes a block segmentation in 3, followed in 4 by a classification thereof. There are thus obtained image blocks in 5, text blocks in 6, and graphic blocks in 7. In 8, 10 a hierarchy-]ike segmentation of text characters is performed, said characters being recognized in 8 ' and arrayed in lines in 12 . The character recognition in 8 ' is obtained in the following way: the characters are converted in 9, extracted in 10 and clas-sified in 11. The informations originating from step 12, as well 15 as the classification outputs for image in 5 and for graphics in 7, are fed to a document coding step in 13.
As it appears from figure 2, the processing method may be considered as subdivided into four levels. On the highest level, there is found a processor 14, generally called "Master n, 20 which controls the whole system and which insures the good de-velopment of those algorithms to be executed. The second level is comprised of standard processors 15 the main proceesing steps are associated with (for example binarization, segmentation, reco-gnition, coding). Said standard processors 15 execute those al-25 gorithms which are specific to the step which is imparted there-to. Said algorithms are computer-simulated to determine the cri-tical points and most-repetitive tasks of said algorithms. Such tasks will be performed by dedicated processors 16 which com-prise the third level. Each said most-repetitive tasks is part 30 of a microprogramme from one of said dedicated processors 16.
On the lowest level, there is provided a specialized integrated circuit 17 which performs the algorithm elementary functions and which comprises the processing unit of a microprogrammed dedi-cated processor.

5. ~ 37~

An example of secundary algorithm is shown in figure 3. It is a character skeletonnization algorithm. The dedi-cated processor processes the given character by suppressing black dots until a one-unit thickness is obtained for the lines.
5 The control of said algorithm is performed by the microprogram-me. The elementary operations on the image are performed in the specialized operative part.
The typical architecture of the dedicated proces-sors is given in figure 4. This is the architecture for a micro-10 programmed processor. Said processor is interfaced in 18 witha standard bus, as for example the VME or Multibus, not shown.
A microprogrammed procedure is associated with each instruction.
The execution of an instruction takes several clock cycles.
The microprogramme is recorded in memories 19.
15 It is thus rather easy to load and there may be considered ad-ding or changing instructions within the scope of specific applica-tions .
The processor may be subdivided in a plurality of blocks:
20 - the interface with the external bus 18, all data transfers are made through a double-port memory 20, - the management system for sending and receiving interrupts 21, - the control unit 22, - the microprogramme memory 19, 25 - the image memory 23, - the specialized operating unit 24.
The dedicated processor further comprises a con-trol clock 25, an address bus 26, a data bus 27, a control bus 28, a micro-instruction register 29, an internal bus interface 30, 30 a bus access logic 31, an instruction register 32, and a status register 33.
To the exception of the operating unit 24, the other processor parts are conventional and made from standard circuits. The operating unit 24 of the dedicated processor is on

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the other hand, completely specific. It does comprise the heart of the system and this is where the operations will actually be performed .
Said unit 24 comprises the last level in embodying 5 the document processing system. The features thereof are determi-native for the general system performances. The circuit archi-tecture is specific and original. The novelty thereof does not originate essentially from the components the circuit is comprised of, but rather from the assembly and the obtained final result.
10 The selection of this architecture -is directly linked with the kind of problem which had to be solved. Such selection would absolutely not be justified for a general-purpose standard logic system .
In the case of document processing, the accesses 15 to the image memory are very frequent. The address computing is thus very critical. The operations which have to be performed on the data which originate from the memory, are essentially logic. At the same time, it is often required to perform counting functions. There is added thereto the problem of special functions such as skeletonnization, which are to be performed in a mini-mum time.
There results from these considerations that there should be provided in the operating unit 24, at least three dis-crete units which can work in parallel and perform simultaneously one operation or transfer per cycle.
Figure 5 shows by way of example, a specialized operating unit 24 which is comprised of four discrete units. The first unit 34 is intended for computing the address in the image memory. The address is subdivided in two fields: the first one addresses an image line, while the second one selects a column.
Said unit 34 has a set of registers the function of which is to store working pointers or limit values, as for example the coordi-nates of the image window to be analyzed. Unit 34 is capable of performing elementary arithmetic operations such as incremen-

7. ~ 7~

ting. decrementing, and comparing between two addresses.
The second unit 35 is an arithmetic unit. Saidunit is intended for performing arithmetic operations of the kind A + B, A - B, A + 1, A - l, z .... A few registers store 5 the algorithm parameters and some intermediate values.
The third unit 36 is a logic unit. Said unit 36 accesses the image memory 23 ( see figure 4 ), it receives the data, processes same and possibly changes the memory content.
Said operations are essentially logic operations (Boolean functions 10 AND, OR, NOT, SHIFT), to the exception of means which allow the fast computing of the density by determining in one cycle, the number of black dots contained in one word. The logic unit also has a Boolean capacity for computing masks, as well as a "barrel shifter " .
Indeed depending on the data which are being received from the memory, it is often necessary to increment or decrement a parameter. The possibility of performing such operations in parallel allows a substantial time gain.
The fourth unit 37 is a computing unit for special 20 functions. In said unit 37, all the special functions are implemen-ted in a programmable logic array. (PLA: programmable logic array ) . Some such functions can not be performed in one cycle and are sequentialized. The unit 37 for such functions, is self-contained for a few cycles and acts as a small complete sequential 25 machine.
Depending on the programme it does contain, unit 37 may be used to perform such operations as binary image con-verting, counting binary image features, half-tint image coding, and multiplication and/or division operations useful for image 30 processing in grey levels (binarization, pre-processing).
- Should such units be implemented by using stan-dard circuits, the processor intricacy would become such that it would loose any interest. The option has been taken to integra-te the whole processing unit in a specialized integrated circuit.

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Such a circuit type is new, there is no equivalent thereof on the component market.
There has further been shown in figure 5, the following elements from operating unit 24:
- 38: address port - 39: data port - 40: status variable port - 41: clock phase generator - 42: main bus - 43: local bus - 44: amplifiers for the control signals - 45: decoder - 46: operative code.
According to this method, two microprogrammed dedicated. processors have been designed and perform the criti-cal tasks.
The first said dedicated processors, called DAN
(Document analysis), is specialized for document analysis and character segmentation. It provides an instruction set in the fol-lowing areas:
- segmentation into blocks, which is based on detecting boundary zones where the information or black dot density is low, - classification of the blocks into three types "Image-graphics-textn. A double imaging of the informations is provided for the processor: a binary imaging and a half-tint imaging which better imparts the grey notion and which allows a better showing of images and photographs. Image detecting is made by studying the correlation between both imagings. Text and graphics are separated on the base of the segmentation system capacities to demarcate characters, and the recognition system capacity to reco-gnize same.
- character segmentation.
Character segmentation is based on a hierarchical and iterative approach to the problem. The main implemented algorithms are ~. 12~3~7~

as follows:
- segmentation by sensing white columns;
- segmentation by sensing the outline;
- segmentation by histogram;
- segmentation by arbitrary decision.
The whole document is not completely stored in the image memory 23. This would require too much memory capa-city. A few lines only are stored. The number of such lines should be at least equal to the maximum height of a character.
The processing procedure comprises a plurality of steps:
- The processor analyses the content of the oldest line, the so-called "reference line " .
- When an information is sensed, the processor initializes a seg-15 mentation procedure to isolate the information.
- The processor classifies the information and processes the con-tent thereof.
- When the processing is completed, the image memory is erased.
The processor proceeds with the analysis of the "reference line", 20 and if a new information is sensed, it initializes said segmentation procedure .
- When the analysis of the "reference line" is completed, a new line is read and stored instead of the "reference line " . The po-sition of the reference line is incremented by one position.
The integrated circuit which comprises the opera-ting unit 24 from the DAN processor, does comprise in the one version thereof, but an address unit 34, a logic unit 36 and an arithmetic unit 35, the special function computing unit 37 being dispensed with to reduce the processor intricacy.
The second dedicated processor, called STAN
(Structure Analysis), is intended to perform the tasks of image processing and extracting the usefule features for recognizing the c haracter s .
As regards the binary images, the STAN processor 10. ~ 2~37~

provides an instruction set which allows to modify the image and to compute characteristics:
- binary pre-processing - outline sensing - skeletonnization - centering the character - histogram - line density - characteristic counting As regards the images in grey levels, the STAN
processor may execute algorithms for:
- binarization - pre-processing (smoothing, etc. ) - half-tint coding.
15 The functions performed by the processor are part-ly dependent on the programme implemented in the programmable logic array 37.
A feature specific to the STAN processor lies in same having been designed to be easily extensible to an "array 20 processor n machine . In such a case, the image is cut out into an array of sub-images, one processor being associated to each sub-image or a sub-image group. Each processor operates in parallel on the image zone thereof.
The integrated circuit which comprises the opera-25 ting unit 24 from the STAN processor, in the one version thereof, does comprises but an address unit 34, an arithmetic unit 35 and a special function computing unit 37, the logic unit 36 being dis-pensed with to reduce the processor intricacy.
It must be understood that the invention is in 30 no way limited to the above embodiments and that many changes may be brought thereto without departing from the scope of the invention as defined by the appended claims.

Claims (16)

The embodiments of the invention in which an exclusive property of privilege is claimed, are defined as follows:

1. A method for processing information conveyed by a document by converting said information into digital signals which are then analyzed using algorithms, compri-sing the steps of:
executing a primary algorithm using a processor which operates at a high clock frequency;
simulating a primary algorithm performing on a computer, which operates on said computer at a first clock frequency;
determining critical points and repetitive tasks of said primary algorithm from said simulating;
isolating said critical points and said tasks;
assigning each of said points and said tasks to a dedicated processor;
programming each of said dedicated processors to operate according to a respective microprogram gathering secondary algorithm corresponding to one of said points and said tasks; and executing said primary algorithm on a processor at a second clock frequency greater than said first clock frequency with said critical points and said tasks executed by said secondary algorithms in said dedicated processors.

2. Method as defined in claim 1, further comprising the additional step of providing a specialized operating unit, a logic unit and a special function computing unit.

3. Method as defined in claim 1, further compri-sing the additional step of providing a specialized operating unit, an arithmetic unit and a special function computing unit.

4. Method as defined in claim 1, further comprising the additional step of providing a specialized operating unit, a logic unit and an arithmetic unit.

5. Method as defined in claim 1, further compri-sing the additional step of providing a specialized operating unit, a logic unit, an arithmetic unit and a special function computing unit.

6. An apparatus for processing information conveyed on a document, comprising:
simulating means for simulating an operation of a primary algorithm which converts said information into digital signals to determine certain speed enhancing points of said algorithm which include critical points and repeti-tive tasks of said algorithm;
a plurality of dedicated processors, each compri-sin a specialized operating unit which includes a logic unit for executing a speed enhancing point of said primary algorithm according to a special program, and a special function computing unit for executing a speed enhancing point of said primary algorithm as a dedicated function of said special function computing unit, each said dedicated processor for executing one of said speed enhancing points PAUL JESPERS, et al -- Application No. 501,508 of said primary algorithm using at least one of said logic unit or said special function unit of said each dedicated processor; and main processing means for executing said primary algorithm without said speed enhancing points.

7. An apparatus as in claim 6 wherein said special-ized operating unit further comprises an address unit for performing addressing functions on said logic unit.

8. An apparatus as in claim 6 further comprising a removable memory for storing said special program.

9. A method for processing information conveyed by a document by converting said information into digital signals which are then analyzed using algorithms, comprising the steps of:
simulating a primary algorithm performing on a computer, which operates on said computer;
determining critical points and repetitive tasks of said primary algorithm from said simulating;
isolating said critical points and said tasks;
assigning said points and said tasks to at least one dedicated processor;
programming said dedicated processor to operate according to a microprogram gathering secondary algorithm corresponding to said points and said takss; and executing said primary algorithm on a processor with said critical points and said tasks executed by said secondary algorithms in said dedicated processor.

10. Method as defined in claim 9, further comprising the additional step of providing a specialized operating unit, a logic unit and a special function computing unit.

11. Method as defined in claim 9, further comprising the additional step of providing a specialized operating unit, an arithmetic unit and a special function computing unit.

12. Method as defined in claim 9, further comprising the additional step of providing a specialized operating unit, a logic unit and an arithmetic unit.

13. Method as defined in claim 1, further comprising the additional step of providing a specialized operating unit, a logic unit, an arithmetic unit and a special function computing unit in addition to said address unit.

14. An apparatus for processing information conveyed on a document comprising:
simulating means for simulating an operation of a primary algorithm which converts said information into digital signals to determine certain speed enhancing points of said algorithms which include critical points and repeti-tive tasks of said algorithm;
at least one dedicated process, comprising a specialized operating unit which includes a logic unit for executing a speed enhancing point of said primary algorithm according to a special program, and a special function computing unit for executing a speed enhancing point of said PAUL JESPERS, et al -- Application No. 531,508 primary algorithm as a dedicated function of said special function computing unit, said dedicated processor for exe-cuting said speed enhancing points of said primary algorithm using at least one of said logic unit or said special func-tion unit of said dedicated processor; and main processing means for executing said primary algorithm without said speed enhancing points.

15. An apparatus as in claim 14 wherein said special-ized operating unit further comprises an address unit for performing addressing functions on said logic unit.

16. An apparatus as in claims 14 or 15 further comprising a removable memory for storing said special program.