CA1246670A - Uninterruptible power supply - Google Patents
Uninterruptible power supplyInfo
- Publication number
- CA1246670A CA1246670A CA000455780A CA455780A CA1246670A CA 1246670 A CA1246670 A CA 1246670A CA 000455780 A CA000455780 A CA 000455780A CA 455780 A CA455780 A CA 455780A CA 1246670 A CA1246670 A CA 1246670A
- Authority
- CA
- Canada
- Prior art keywords
- inverter
- output
- power supply
- battery
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
- H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
- H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
- H02J9/062—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for AC powered loads
Landscapes
- Business, Economics & Management (AREA)
- Emergency Management (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stand-By Power Supply Arrangements (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
Power supplies are known which normally derive power from commercial AC power mains but, in the event of a power inter-ruption, switch over to battery power. The switch-over is accom-plished by a relay which results in a brief interruption in the output of the power supply. This interruption cannot be toler-ated in some applications, e.g. computing devices and electronic cash registers. The present invention avoids this problem by providing an inverter which is normally connected to the output of a rectifier connected to the AC mains and also to a battery.
During normal operation the battery is charged by a charger cir-cuit. In the event of a mains interruption, the battery continues to power the inverter with no interruption of the AC output of the power supply. If the rectifier voltage drops below a predetermined level, the battery is disconnected so as not to discharge it. If the output of the inverter drops below another predetermined level, the load is connected directly to the AC mains.
Power supplies are known which normally derive power from commercial AC power mains but, in the event of a power inter-ruption, switch over to battery power. The switch-over is accom-plished by a relay which results in a brief interruption in the output of the power supply. This interruption cannot be toler-ated in some applications, e.g. computing devices and electronic cash registers. The present invention avoids this problem by providing an inverter which is normally connected to the output of a rectifier connected to the AC mains and also to a battery.
During normal operation the battery is charged by a charger cir-cuit. In the event of a mains interruption, the battery continues to power the inverter with no interruption of the AC output of the power supply. If the rectifier voltage drops below a predetermined level, the battery is disconnected so as not to discharge it. If the output of the inverter drops below another predetermined level, the load is connected directly to the AC mains.
Description
~L2~ 7~
This invention relates to a power supply and in par-tic-ular to an uninterruptible power supply (UPS).
Arrangements are known whereby a device is normally sup-plied with alternating current from commercial power mains but, in the event of a power interruption, is supplied with alternating current from a battery-powered inverter. A relay switches the device to the inverter if there is a power interruption. See, for example, Canadian patent No. 893,349 of K. Apel, issued April 18, 1972. However, in an arrangement of this type, there is a short delay, following the power interruption, before ~he device starts to receive power from the inverter. In some applications this delay is of no consequence, but in others it cannot be -tolerated, e.g. computing devices and electronic cash registers.
The present invention avoids the foregoing problem by providing what may be termed an uninterruptible power supply, or UPS for brevity, so that switch-over times are not encountered.
Of course no power supply can be totally uninterruptible in the sense of being immune to malfunction, physical damage, etc. and the term "uninterruptible power supply" is not lntended to be so broad. The term is used herein to mean that there is no interrup-tion of the power supplied to a device (load~ connected to -the output of the power supply when the power supply switches over ~
from mains to battery, or vlce versa. The power supply according to the invention also provides excellent surge and transient pro-tection to guard equipment connected thereto against malfunc-tion or potential break-down.
The preferred embodiment of the invention utilizes a crystal controlled regulating inverter to supply current to a load, iZ~667~
thus effectively isolating the load from the commercial power source, whe.reby the load is protected against potential malfunc-tions due to frequency variations, amplitude variations, transient over-or under-voltages, and failures of the commercial power source.
The equipment is so configured that the load is at all times fed from the regulating inverter, thus avoiding momentary perturbations in power which are a characteristic of prior art equipment in which the load is normally supplied by commercial power mains with transfer to the inverter occurring only after detection of an abnormal behaviour of the commercial power supply.
An incidental result of the equipment configuration is that it can he employed as a frequency converter with the load be:ing supplied at a frequency different from that of the commercial power source.
Thus, in accordance with. a broad aspect of the invention, there is provided a po~er supply compxising rectifier means having an input for connection to an AC mains source and an output connected to an input of an inverter, an input of a low voltage sensing c.ircuit, and to an input of a battery charger, said battery charger having an output connected to a battery and to switching means controlled by an output o.f said sensing circuit whereby, when the voltage at the input of said inverter is hi.gher than a predetermined level, the switching means connects the battery and the rectifier means to the:.input of the inverter whareas, if the output voltage of tha rectifier is lower than ~ : said predetermined level, the switch~ng means disconnects the : battery from tha input of the inverter to prevent the battery from discharging, said inverter having an AC output~
~6~
27288~16 The invention will no~ be Eurther descr~ed in conjunc tion ~Ith the accompanying drawings, in which :~:
: ~
-2a-:
. , .
' .
FIGURE 1 is a block diagram of a power supply according to the invention, and FIGURES 2, 3 and 4, which fit together as shown in FIGURE 5, comprise a detailed schematic of the power supply accor-ding to the invention.
Referring to FIGURE 1, it can be seen that the AC mains input to the power supply, generally desi~nated 10, is vla an in-put OFF/ON thermal breaker 12. As will b~ seen in the description of FIGURES 2-4, voltage for control circuitry of the power supply is also applied from the battery 13 through part 12' of the ther-mal breaker, and a voltage regulator 14 having -terminals L and H
indicated in both FIGURES 1 and 2.
The AC :Erom the -thermal breaker 12 is fed through an auto-transformer 16. The outpu-t of -the au-to-trarlsformer 16 is rectified by rectifier 18 and then filtered by filter 20 to prod-uce a DC voltage. The DC voltage is chopped by a switcher device 22 at a predetermined rate, e.g. 60 Hz, and the chopped voltage is fed to a ferro-resonant transformer 24. The ferro-resonant trans-former 24 produces an AC voltage which is connected to an AC out put via an AC transfer circuit 26.
A line synchronization circuit 30 synchroni.zes the power supply to the AC mains. It has an input connected to the auto-transformer16 and an output which feeds pulses (at 60 Hz in this example) to a crystal oscillator 32. The oscillator 32 uses the pulses from sync circuit 30 to reset its internal clock. ~he out-put oE the oscillator 32 provides a crystal controlled 60 Hz -to the switcher 22.
-: - 3 7~
A low vol-tage bat-tery disconnect circuit 3~ monitors the DC voltage level at the output of the rectifier 18. If the DC
voltage level drops to too low a level, the low volta~e battery disconnect circuit 3~ produces an output signal which operates a battery disconnect switch 36 to disconnect the battery from -the input of filter 20, thus preven-ting deep discharge of the battery.
The power supply also includes a battery charger 38 which provides a constan-t output vol-tage to normally keep the battery 13 charged whenever the AC mains power is present. The input of the battery charger is connected -to the output of the rectifier 18.
In the event of a malfunction in -the switcher sec-tion 22 an inverter failure sense circuit 40 will actua-te the AC trans-fer circuit 26 to disconnec-t the AC output from the ferro-resonant transformer 24 and connec-t it directly to the AC mains input via line 42 and breaker 12. An LED in -the front panel of the power supply~ not shown in FIGURE 1, will extinguish to indicate failure of the inverter.
Turning now ko the detailed schematic of FIGURES 2 to 4, a plug Pl is shown at the lef-t of FIGURE 2, this being for con-nection of the power supply to the commercial AC power mains.
Assuming the circuit breaker 12, 12' is closed, power is applied via lines 50, 51 -to the end terminals Hl and H5 of the winding of auto-transformer 16, also designated Tl in FIGURE 2. The out put of auto-transformer 16 at taps H2 and H5 is connected to a full wave bridge rectifier 18 comprislng diodes BRl~ and BRlB, khe center tap H3 of the auto-transEormer winding being connected ~ . .
. .
6~i7~
to the negative side of filter capacitor 20, also designated Cl in FIGURE 2. The positive terminal of capacitor 20 is connected to the output 52 of rectifier 18. The filtered DC voltage across capaci-tor 20 is fed to outpu-t switching silicon con-trolled rect-ifiers CR20 and CR22 via line 54, fuse F2, and the primary winding 56 of ferro-resonant transformer T2 (FIGURE 3). The voltage across capacitor 20 is also fed to the battery charger circuitry 38 via a series voltage regulator Ql, reverse blocking diode CR7 and fuse F30 The battery 13 is connected to line 54 via a block-ing diode CR8 and normally open contacts of relay Kl.
A varistor (voltage dependent resistor) VRl is connected across lines 50 and 51 to reduce high voltage spikes or surges present on the input of the unit.
A reference voltage for the ba-ttery charger 38 is deve-loped across the series combination of Zener diode CR4 and diode CR5 at junction 56, this diode combination being fed current from line 54 via current limiting resistor R2. The reference voltage is fed to the base of NPN transistor Q2 which is connected as an emitter follower. The output of Q2, i.e. the emitter, is connected -to the base of the series regulator transistor Ql. The output volta~e on the emitter of Ql is fed through the parallel combin-ation of resistor R3 and potentiometer R4 to blocking diode CR7 which is connected via fuse F3 to battery 13. Current will flow ln this path whenever the voltage of the battery 13 is lower than the battery reference voltaae at junction 56 until the battery voltage is equal to the reference v~ltage when AC mains power is present. The voltage at the wiper of potentiometer R~ is fed -to the base of transistor Q3. If the charging current exceeds a ;7G~
certain level, dependent on the setting of potentiometer R4, trans-istor Q3 starts to conduct~ thus increasing the current in resistor R2 which reduces the available current drive to transistors Q~ and Ql and thus reduces the charging current.
The current flow through Q3 is also controlled by Zener diode CR3. If the voltage across transistor ~1 exceeds the Zener voltage value of CR3, CR3 conducts and current flows through R7, R6 and R4. This causes Q3 to conduct more, thus reducing the avail-able current drive for Q2 and Ql and hence providing current limit-ing for overload conditions or short circuits on -the charger output.
Capacitor C2 provides a high frequency noise by-pass across the voltage reference and capacitor C32 provides AC feedback -to limit the AC gain and prevent oscilla-tions.
Control circuits of the power supply are powered fro~ a series regulator 14 fed from breaker 12'. When breaker 12' is closed, volta~e from battery 13 is connected to the battery connect relay Kl and the AC transfer relay K2 (FIGURE 4) via line 70. The series regulator 14~ comprising transis-tor Q4 and rela-ted compon ents, is connected through blocking diode CR9~ Capacitor C3 provides hold-over voltage to allow the system to continue to run and discharge after the power is turned o. The collector of Q4 is connected to line 54 via resistor R9 and diode CRll so as to receive voltage until capacitor Cl is discharged. Resistor R8 limits the current to reference Zener diode CR10. Capacitor C4 bypasses any stray high frequency noise which might be present.
The series re~ulator transistor Q9 is connected as an emitter fQl-lower which provides a DC output voltage for all the control cir-cuitry.
The AC line synchronization circuit 30 comprises anoperational amplifier ICl with a current limiting resistor R12 connected between its non-inverting input and tap H4 of auto-transformer 18. This input i5 protected by diodes CR12 and CR13 to prevent excursions of the reference voltage, either plu5 or minus. The inverting inpu-t of operational amplifier ICl is con-nected to a voltage divider formed by resistors R10 and Rll con-nected across the control voltage supply ~rom transistor Q4. When-ever the voltage at the posi-tive (non-inverting) input exceeds the voltage on the negative (inverting) input, the amplifier ICl is -turned on. Since the amplifier operates wi-thout any feedback circuit, it has full gain and a square wave is produced a-t its output through pull-up resistor R13. This square wave is differ-entially coupled via capacitor C5 and resistor R14 to pin 6 of IC2. Positive voltage transitions on R14 above the control ref-erence voltage are clipped by diode CR14. The input to pin 6 of IC2 consists of positive pulses synchronized to the 60 Hz incoming AC mains.
IC2 comprises a crystal controlled oscillator which is re-started by each pulse applied on pin 6 from line sync circuit 30. IC2 generates a 1.956 MHz clock rate signal which is divided by two at output pin 5 and connected to pin 11 of IC3. The frequ-ency of IC2 i5 set by the components connected to pins 10 and 11, i.e. crystal Xl, resistor R15 and capacitors C6 and C7. The square wave applied to pin 11 of IC3 is divided again ~y IC3 to produce a square wave at its output pin 15~ The output on pin 15 7~
of IC3 is coupled to inverter IC5, capacitor C8 r resis-tor Rl6 and resistor Rl7, producing a differential signal on the gate of FET
(Field Effect Transis-tor) Q5 which turns i.t on. When Q5 conducts it generates a pulse in transformer T3. The energy of ~he collap-sing flux in T3 when the pulse ends is damped by diode CR15.
Similarly, on alternate half cycles, inverters IC6 and IC7 apply pulses to C10, ~l9 and R20 to turn on Q6 which generates a pulse in transformer T4. The pulses from T3 turn on CR20 (a SCR) and the pulses from T4 turn on CR22 (also a SCR) so that current flows alternately in the two halves of the primary of ferro-resonant transformer 24, also designated T2 in FIGURE 3. At -this time contac-ts 3, 4 and 5, 6 of relay K2 of AC transfer ci.rcui-t 26 are closed while contacts 2, 7 are open so voltage is applied -to out-let sockets Jl-l and Jl.-2 from the secondary of ferro-resonant transformer T2.
IC4 is a NAND gate which produces a low output on pin 8 only when its inputs 9, 10, 12 and 13 are all high. These inputs are connected to pins 6, 13, 14 and 15 of counter IC3, which pins are all high only for a count between 7/8 and 8/8 of one cycle at 59.7 Hz. When -the count is as stated, pin 8 of NAND gate IC4 goes low. This low on IC4 pin 8 is inverted by IC8 and the resulting high is applied to pin 5 of NAND gate ICll, pins l and 2 of which : are already high by virtue of their connection to Line 75. When ICl goes low, inverter IC9 applies a high to pin 4 of ICll; with all inputs now high, ICll produces a low at its output pin 6 which is applied to pin 13 of counter IC3 and pin 12 of oscillator IC2, thus xesetting both IC2 and IC3. The frequency o~ 59.7 Hz was sel-ected as an appropriate frequency less than the nominal 60 Hz line , . ., : . .
ii67~
frequency so that the oscillator can be synchronized by the line frequency.
Thus, -there is provided a "window" of 1/8 cycle of time at 59.7 Hz. This window of 1/8 of a cycle each cycle allows the input synchronization signal from -the AC mains to pin 6 of IC2 to lock in.
Counter IC3 and oscilla-tor IC2 are reset to zero when the synchronization signal on pin 4 o~ ICll is high at the same time that pin 5 is high when counter IC3 is between 7/8 and 8/8 of its total count cycle. Once this has occurred, counter IC3 and oscillator IC2 will be reset at a predetermined point in time during the 60 Hz line input period. If the input frequency goes lower than 59.7 Hz, synchroniza-tion will only occur periodically for one cycle since the window for the allowable synchronization time period will be already closed, i.e. more than 8/8ths of 1 cycle. If the input frequency goes greater than 7/8 of 1 cycle in time period, the same thing will be -true, since the gate ICll will not yet be enabled. Thus the synchronization period accom-modates synchronization of frequencies from 59.7 Hz to 67.57 Hz, i.e. - 0.3 Hz to ~ 7.57 Hz of the nominal 60 Hz.
The low voltage battery disconnect monitor 34, FIGURE 4, senses the voltage on capacitor Cl via lead ~0 and resistors R23 and R24 which form a voltage divider. Capacitor C16 bypasses any high frequency noise reaching the voltage divider. The operation-al amplifier IC12 has a feedback hysteresis resistor R29 and a resistor R25 on the monitor input. The negative input of the operational amplifier IC12 is connected as shown to a voltage divider comprised of capacitor C17, resistors R26 and R27 and : - g 7~3 variable resistor R28. Variable resistor R28 adjusts the drop-out level for the disconnect relay Kl. The output of IC12 is connected to a pull-up resistor R30. Resistors R31 and R32 form a voltage divider for the input of F~T Q7. The output of Q7 oper-ates relay Kl which s-tays operated as long as -the voltage on Cl is above the disconnect level. Resistor R44 limi-ts the current to ligh-t emitting diode CR 3~ which lights to show that the battery 13 is connected.
The power supply is also equipped with an inverter fail-ure alarm. This alarm monitors the s~uare wave generated at the inverter via capacitors C20 and C21. The diodes CR27 and CR28 rectify the signals from -the inverter on lines 62 and 64 to prod-uce a voltage which is divided by resistors R41 and R39. The volt-age at junc-tion 66 is filtered by C19 and fed to -the positive in-put of operational amplifier IC13 . This operational amplifier has resistors R36 and R46 as a hysteresis feedback network. To the negative input of IC13 is connected the voltage divider R40, R37, R38, variable resistor R47 and capacitor C18. ~his negative input is the reference for the comparator. When the voltage on the positive input is below the reference voltage, relay K2 rel-eases. In the event of failure of the inverter, the output volt-age of IC13 will go low, switching Q8 off and dropping relay K2.
Diode CR26 protects Q8 from reverse voltages created by the collap-sing field of relay K2. (CR25 similarly protec-ts Q7 when Kl drops out.) Resistor R43 provides current limiting for light emit-ting diode CR29 which illuminates whenever the inverter is oper-.
.
ating. I~ the inver-ter fails, relay K2 drops out causing, via its contacts in AC transfer circuit 26, FIGURE 3, a load transfer from the inverter output to -the AC mains, via lines 71 and 72.
The inverter (switcher) 2 2 comprises -two silicon control-led rectifiers CR20 and CR22 which are alternately triggered by -the outputs of transformers T3 and T4, respectively. The conduc-tion of either SCR coming on causes a sharp increase in current in induc-tor Ll. This produces a large reverse voltage on the other SCR
causing commutation or turn-off of the SCR which has no gate voltage on it. The SCR' s are pro-tected by clamping diodes CRl9 and CR21. The diodes CR23 and CR24 couple the commu-tation vol-tage on Ll across -the anodes and cathodes of -the SCR' s. Capacitor C13 is discharged through the conducting SCR and this current aids in the commutation.
The switched current in the ferro-resonant transformer primary winding results in resonating currents in the secondary and tertiary windings across which is connected a capacitor C15.
This causes the output voltage at Xl and X2 to be sinusoidal and regulated. Current limiting is provided automa-tically by the characteristics of the ferro-resonant transformer.
This invention relates to a power supply and in par-tic-ular to an uninterruptible power supply (UPS).
Arrangements are known whereby a device is normally sup-plied with alternating current from commercial power mains but, in the event of a power interruption, is supplied with alternating current from a battery-powered inverter. A relay switches the device to the inverter if there is a power interruption. See, for example, Canadian patent No. 893,349 of K. Apel, issued April 18, 1972. However, in an arrangement of this type, there is a short delay, following the power interruption, before ~he device starts to receive power from the inverter. In some applications this delay is of no consequence, but in others it cannot be -tolerated, e.g. computing devices and electronic cash registers.
The present invention avoids the foregoing problem by providing what may be termed an uninterruptible power supply, or UPS for brevity, so that switch-over times are not encountered.
Of course no power supply can be totally uninterruptible in the sense of being immune to malfunction, physical damage, etc. and the term "uninterruptible power supply" is not lntended to be so broad. The term is used herein to mean that there is no interrup-tion of the power supplied to a device (load~ connected to -the output of the power supply when the power supply switches over ~
from mains to battery, or vlce versa. The power supply according to the invention also provides excellent surge and transient pro-tection to guard equipment connected thereto against malfunc-tion or potential break-down.
The preferred embodiment of the invention utilizes a crystal controlled regulating inverter to supply current to a load, iZ~667~
thus effectively isolating the load from the commercial power source, whe.reby the load is protected against potential malfunc-tions due to frequency variations, amplitude variations, transient over-or under-voltages, and failures of the commercial power source.
The equipment is so configured that the load is at all times fed from the regulating inverter, thus avoiding momentary perturbations in power which are a characteristic of prior art equipment in which the load is normally supplied by commercial power mains with transfer to the inverter occurring only after detection of an abnormal behaviour of the commercial power supply.
An incidental result of the equipment configuration is that it can he employed as a frequency converter with the load be:ing supplied at a frequency different from that of the commercial power source.
Thus, in accordance with. a broad aspect of the invention, there is provided a po~er supply compxising rectifier means having an input for connection to an AC mains source and an output connected to an input of an inverter, an input of a low voltage sensing c.ircuit, and to an input of a battery charger, said battery charger having an output connected to a battery and to switching means controlled by an output o.f said sensing circuit whereby, when the voltage at the input of said inverter is hi.gher than a predetermined level, the switching means connects the battery and the rectifier means to the:.input of the inverter whareas, if the output voltage of tha rectifier is lower than ~ : said predetermined level, the switch~ng means disconnects the : battery from tha input of the inverter to prevent the battery from discharging, said inverter having an AC output~
~6~
27288~16 The invention will no~ be Eurther descr~ed in conjunc tion ~Ith the accompanying drawings, in which :~:
: ~
-2a-:
. , .
' .
FIGURE 1 is a block diagram of a power supply according to the invention, and FIGURES 2, 3 and 4, which fit together as shown in FIGURE 5, comprise a detailed schematic of the power supply accor-ding to the invention.
Referring to FIGURE 1, it can be seen that the AC mains input to the power supply, generally desi~nated 10, is vla an in-put OFF/ON thermal breaker 12. As will b~ seen in the description of FIGURES 2-4, voltage for control circuitry of the power supply is also applied from the battery 13 through part 12' of the ther-mal breaker, and a voltage regulator 14 having -terminals L and H
indicated in both FIGURES 1 and 2.
The AC :Erom the -thermal breaker 12 is fed through an auto-transformer 16. The outpu-t of -the au-to-trarlsformer 16 is rectified by rectifier 18 and then filtered by filter 20 to prod-uce a DC voltage. The DC voltage is chopped by a switcher device 22 at a predetermined rate, e.g. 60 Hz, and the chopped voltage is fed to a ferro-resonant transformer 24. The ferro-resonant trans-former 24 produces an AC voltage which is connected to an AC out put via an AC transfer circuit 26.
A line synchronization circuit 30 synchroni.zes the power supply to the AC mains. It has an input connected to the auto-transformer16 and an output which feeds pulses (at 60 Hz in this example) to a crystal oscillator 32. The oscillator 32 uses the pulses from sync circuit 30 to reset its internal clock. ~he out-put oE the oscillator 32 provides a crystal controlled 60 Hz -to the switcher 22.
-: - 3 7~
A low vol-tage bat-tery disconnect circuit 3~ monitors the DC voltage level at the output of the rectifier 18. If the DC
voltage level drops to too low a level, the low volta~e battery disconnect circuit 3~ produces an output signal which operates a battery disconnect switch 36 to disconnect the battery from -the input of filter 20, thus preven-ting deep discharge of the battery.
The power supply also includes a battery charger 38 which provides a constan-t output vol-tage to normally keep the battery 13 charged whenever the AC mains power is present. The input of the battery charger is connected -to the output of the rectifier 18.
In the event of a malfunction in -the switcher sec-tion 22 an inverter failure sense circuit 40 will actua-te the AC trans-fer circuit 26 to disconnec-t the AC output from the ferro-resonant transformer 24 and connec-t it directly to the AC mains input via line 42 and breaker 12. An LED in -the front panel of the power supply~ not shown in FIGURE 1, will extinguish to indicate failure of the inverter.
Turning now ko the detailed schematic of FIGURES 2 to 4, a plug Pl is shown at the lef-t of FIGURE 2, this being for con-nection of the power supply to the commercial AC power mains.
Assuming the circuit breaker 12, 12' is closed, power is applied via lines 50, 51 -to the end terminals Hl and H5 of the winding of auto-transformer 16, also designated Tl in FIGURE 2. The out put of auto-transformer 16 at taps H2 and H5 is connected to a full wave bridge rectifier 18 comprislng diodes BRl~ and BRlB, khe center tap H3 of the auto-transEormer winding being connected ~ . .
. .
6~i7~
to the negative side of filter capacitor 20, also designated Cl in FIGURE 2. The positive terminal of capacitor 20 is connected to the output 52 of rectifier 18. The filtered DC voltage across capaci-tor 20 is fed to outpu-t switching silicon con-trolled rect-ifiers CR20 and CR22 via line 54, fuse F2, and the primary winding 56 of ferro-resonant transformer T2 (FIGURE 3). The voltage across capacitor 20 is also fed to the battery charger circuitry 38 via a series voltage regulator Ql, reverse blocking diode CR7 and fuse F30 The battery 13 is connected to line 54 via a block-ing diode CR8 and normally open contacts of relay Kl.
A varistor (voltage dependent resistor) VRl is connected across lines 50 and 51 to reduce high voltage spikes or surges present on the input of the unit.
A reference voltage for the ba-ttery charger 38 is deve-loped across the series combination of Zener diode CR4 and diode CR5 at junction 56, this diode combination being fed current from line 54 via current limiting resistor R2. The reference voltage is fed to the base of NPN transistor Q2 which is connected as an emitter follower. The output of Q2, i.e. the emitter, is connected -to the base of the series regulator transistor Ql. The output volta~e on the emitter of Ql is fed through the parallel combin-ation of resistor R3 and potentiometer R4 to blocking diode CR7 which is connected via fuse F3 to battery 13. Current will flow ln this path whenever the voltage of the battery 13 is lower than the battery reference voltaae at junction 56 until the battery voltage is equal to the reference v~ltage when AC mains power is present. The voltage at the wiper of potentiometer R~ is fed -to the base of transistor Q3. If the charging current exceeds a ;7G~
certain level, dependent on the setting of potentiometer R4, trans-istor Q3 starts to conduct~ thus increasing the current in resistor R2 which reduces the available current drive to transistors Q~ and Ql and thus reduces the charging current.
The current flow through Q3 is also controlled by Zener diode CR3. If the voltage across transistor ~1 exceeds the Zener voltage value of CR3, CR3 conducts and current flows through R7, R6 and R4. This causes Q3 to conduct more, thus reducing the avail-able current drive for Q2 and Ql and hence providing current limit-ing for overload conditions or short circuits on -the charger output.
Capacitor C2 provides a high frequency noise by-pass across the voltage reference and capacitor C32 provides AC feedback -to limit the AC gain and prevent oscilla-tions.
Control circuits of the power supply are powered fro~ a series regulator 14 fed from breaker 12'. When breaker 12' is closed, volta~e from battery 13 is connected to the battery connect relay Kl and the AC transfer relay K2 (FIGURE 4) via line 70. The series regulator 14~ comprising transis-tor Q4 and rela-ted compon ents, is connected through blocking diode CR9~ Capacitor C3 provides hold-over voltage to allow the system to continue to run and discharge after the power is turned o. The collector of Q4 is connected to line 54 via resistor R9 and diode CRll so as to receive voltage until capacitor Cl is discharged. Resistor R8 limits the current to reference Zener diode CR10. Capacitor C4 bypasses any stray high frequency noise which might be present.
The series re~ulator transistor Q9 is connected as an emitter fQl-lower which provides a DC output voltage for all the control cir-cuitry.
The AC line synchronization circuit 30 comprises anoperational amplifier ICl with a current limiting resistor R12 connected between its non-inverting input and tap H4 of auto-transformer 18. This input i5 protected by diodes CR12 and CR13 to prevent excursions of the reference voltage, either plu5 or minus. The inverting inpu-t of operational amplifier ICl is con-nected to a voltage divider formed by resistors R10 and Rll con-nected across the control voltage supply ~rom transistor Q4. When-ever the voltage at the posi-tive (non-inverting) input exceeds the voltage on the negative (inverting) input, the amplifier ICl is -turned on. Since the amplifier operates wi-thout any feedback circuit, it has full gain and a square wave is produced a-t its output through pull-up resistor R13. This square wave is differ-entially coupled via capacitor C5 and resistor R14 to pin 6 of IC2. Positive voltage transitions on R14 above the control ref-erence voltage are clipped by diode CR14. The input to pin 6 of IC2 consists of positive pulses synchronized to the 60 Hz incoming AC mains.
IC2 comprises a crystal controlled oscillator which is re-started by each pulse applied on pin 6 from line sync circuit 30. IC2 generates a 1.956 MHz clock rate signal which is divided by two at output pin 5 and connected to pin 11 of IC3. The frequ-ency of IC2 i5 set by the components connected to pins 10 and 11, i.e. crystal Xl, resistor R15 and capacitors C6 and C7. The square wave applied to pin 11 of IC3 is divided again ~y IC3 to produce a square wave at its output pin 15~ The output on pin 15 7~
of IC3 is coupled to inverter IC5, capacitor C8 r resis-tor Rl6 and resistor Rl7, producing a differential signal on the gate of FET
(Field Effect Transis-tor) Q5 which turns i.t on. When Q5 conducts it generates a pulse in transformer T3. The energy of ~he collap-sing flux in T3 when the pulse ends is damped by diode CR15.
Similarly, on alternate half cycles, inverters IC6 and IC7 apply pulses to C10, ~l9 and R20 to turn on Q6 which generates a pulse in transformer T4. The pulses from T3 turn on CR20 (a SCR) and the pulses from T4 turn on CR22 (also a SCR) so that current flows alternately in the two halves of the primary of ferro-resonant transformer 24, also designated T2 in FIGURE 3. At -this time contac-ts 3, 4 and 5, 6 of relay K2 of AC transfer ci.rcui-t 26 are closed while contacts 2, 7 are open so voltage is applied -to out-let sockets Jl-l and Jl.-2 from the secondary of ferro-resonant transformer T2.
IC4 is a NAND gate which produces a low output on pin 8 only when its inputs 9, 10, 12 and 13 are all high. These inputs are connected to pins 6, 13, 14 and 15 of counter IC3, which pins are all high only for a count between 7/8 and 8/8 of one cycle at 59.7 Hz. When -the count is as stated, pin 8 of NAND gate IC4 goes low. This low on IC4 pin 8 is inverted by IC8 and the resulting high is applied to pin 5 of NAND gate ICll, pins l and 2 of which : are already high by virtue of their connection to Line 75. When ICl goes low, inverter IC9 applies a high to pin 4 of ICll; with all inputs now high, ICll produces a low at its output pin 6 which is applied to pin 13 of counter IC3 and pin 12 of oscillator IC2, thus xesetting both IC2 and IC3. The frequency o~ 59.7 Hz was sel-ected as an appropriate frequency less than the nominal 60 Hz line , . ., : . .
ii67~
frequency so that the oscillator can be synchronized by the line frequency.
Thus, -there is provided a "window" of 1/8 cycle of time at 59.7 Hz. This window of 1/8 of a cycle each cycle allows the input synchronization signal from -the AC mains to pin 6 of IC2 to lock in.
Counter IC3 and oscilla-tor IC2 are reset to zero when the synchronization signal on pin 4 o~ ICll is high at the same time that pin 5 is high when counter IC3 is between 7/8 and 8/8 of its total count cycle. Once this has occurred, counter IC3 and oscillator IC2 will be reset at a predetermined point in time during the 60 Hz line input period. If the input frequency goes lower than 59.7 Hz, synchroniza-tion will only occur periodically for one cycle since the window for the allowable synchronization time period will be already closed, i.e. more than 8/8ths of 1 cycle. If the input frequency goes greater than 7/8 of 1 cycle in time period, the same thing will be -true, since the gate ICll will not yet be enabled. Thus the synchronization period accom-modates synchronization of frequencies from 59.7 Hz to 67.57 Hz, i.e. - 0.3 Hz to ~ 7.57 Hz of the nominal 60 Hz.
The low voltage battery disconnect monitor 34, FIGURE 4, senses the voltage on capacitor Cl via lead ~0 and resistors R23 and R24 which form a voltage divider. Capacitor C16 bypasses any high frequency noise reaching the voltage divider. The operation-al amplifier IC12 has a feedback hysteresis resistor R29 and a resistor R25 on the monitor input. The negative input of the operational amplifier IC12 is connected as shown to a voltage divider comprised of capacitor C17, resistors R26 and R27 and : - g 7~3 variable resistor R28. Variable resistor R28 adjusts the drop-out level for the disconnect relay Kl. The output of IC12 is connected to a pull-up resistor R30. Resistors R31 and R32 form a voltage divider for the input of F~T Q7. The output of Q7 oper-ates relay Kl which s-tays operated as long as -the voltage on Cl is above the disconnect level. Resistor R44 limi-ts the current to ligh-t emitting diode CR 3~ which lights to show that the battery 13 is connected.
The power supply is also equipped with an inverter fail-ure alarm. This alarm monitors the s~uare wave generated at the inverter via capacitors C20 and C21. The diodes CR27 and CR28 rectify the signals from -the inverter on lines 62 and 64 to prod-uce a voltage which is divided by resistors R41 and R39. The volt-age at junc-tion 66 is filtered by C19 and fed to -the positive in-put of operational amplifier IC13 . This operational amplifier has resistors R36 and R46 as a hysteresis feedback network. To the negative input of IC13 is connected the voltage divider R40, R37, R38, variable resistor R47 and capacitor C18. ~his negative input is the reference for the comparator. When the voltage on the positive input is below the reference voltage, relay K2 rel-eases. In the event of failure of the inverter, the output volt-age of IC13 will go low, switching Q8 off and dropping relay K2.
Diode CR26 protects Q8 from reverse voltages created by the collap-sing field of relay K2. (CR25 similarly protec-ts Q7 when Kl drops out.) Resistor R43 provides current limiting for light emit-ting diode CR29 which illuminates whenever the inverter is oper-.
.
ating. I~ the inver-ter fails, relay K2 drops out causing, via its contacts in AC transfer circuit 26, FIGURE 3, a load transfer from the inverter output to -the AC mains, via lines 71 and 72.
The inverter (switcher) 2 2 comprises -two silicon control-led rectifiers CR20 and CR22 which are alternately triggered by -the outputs of transformers T3 and T4, respectively. The conduc-tion of either SCR coming on causes a sharp increase in current in induc-tor Ll. This produces a large reverse voltage on the other SCR
causing commutation or turn-off of the SCR which has no gate voltage on it. The SCR' s are pro-tected by clamping diodes CRl9 and CR21. The diodes CR23 and CR24 couple the commu-tation vol-tage on Ll across -the anodes and cathodes of -the SCR' s. Capacitor C13 is discharged through the conducting SCR and this current aids in the commutation.
The switched current in the ferro-resonant transformer primary winding results in resonating currents in the secondary and tertiary windings across which is connected a capacitor C15.
This causes the output voltage at Xl and X2 to be sinusoidal and regulated. Current limiting is provided automa-tically by the characteristics of the ferro-resonant transformer.
Claims (7)
- THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
l. A power supply comprising rectifier means having an input for connection to an AC mains source and an output connected to an input of an inverter, an input of a low voltage sensing circuit, and to an input of a battery charger, said battery charger having an output connected to a battery and to switching means controlled by an output of said sensing circuit hereby, when the voltage at the input of said inverter is higher than a predetermined level, the switching means connects the battery and the rectifier means to the input of the inverter whereas, if the output voltage of the rectifier is lower than said predetermined level, the switching means disconnects the battery from the input of the inverter to prevent the battery from discharging, said inverter having an AC output. - 2. A power supply as claimed in claim 1 wherein said inverter is controlled by a crystal oscillator.
- 3. A power supply as claimed in claim 2 wherein said oscillator is synchronized to the AC mains.
- 4. A power supply as claimed in claim 3 wherein said rectifier is connected to the input of said inverter via a filter.
- 5. A power supply as claimed in claim 4 wherein the output of said inverter is connected to said AC transfer circuit via a ferro-resonant transformer.
- 6 o A power supply as claimed in claim 1, 2 or 3, including an inverter failure sensing circuit which controls an AC transfer circuit whereby, when the inverter produces an output voltage above a second predetermined level, it is connected via the AC transfer circuit to AC output terminals of the power supply whereas, when the output voltage of the inverter is below said predetermined level, the inverter failure sensing circuit actuates the AC transfer circuit to disconnect the AC output terminals from the inverter and connect them instead to the AC mains.
- 7, A power supply as claimed in claim 4 or 5 including an inverter failure sensing circuit which controls an AC transfer circuit whereby, when the inverter produces an output voltage above a second predetermined level, it is connected via the AC transfer circuit to AC output terminals of the power supply whereas, when the output voltage of the inverter is below said predetermined level, the inverter failure sensing circuit actuates the AC transfer circuit to disconnect the AC output terminals from the inverter and connect them instead to the AC mains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000455780A CA1246670A (en) | 1984-06-04 | 1984-06-04 | Uninterruptible power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000455780A CA1246670A (en) | 1984-06-04 | 1984-06-04 | Uninterruptible power supply |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1246670A true CA1246670A (en) | 1988-12-13 |
Family
ID=4128020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000455780A Expired CA1246670A (en) | 1984-06-04 | 1984-06-04 | Uninterruptible power supply |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1246670A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106953402A (en) * | 2017-03-31 | 2017-07-14 | 杭州电子科技大学 | The magnetic powder brake driving continued a journey based on super capacitor and under-voltage protecting circuit |
-
1984
- 1984-06-04 CA CA000455780A patent/CA1246670A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106953402A (en) * | 2017-03-31 | 2017-07-14 | 杭州电子科技大学 | The magnetic powder brake driving continued a journey based on super capacitor and under-voltage protecting circuit |
| CN106953402B (en) * | 2017-03-31 | 2023-03-31 | 杭州电子科技大学 | Magnetic powder brake driving and undervoltage protection circuit based on super capacitor endurance |
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