CA1243369A - High-fidelity audio frequency amplifier - Google Patents
High-fidelity audio frequency amplifierInfo
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- CA1243369A CA1243369A CA000496060A CA496060A CA1243369A CA 1243369 A CA1243369 A CA 1243369A CA 000496060 A CA000496060 A CA 000496060A CA 496060 A CA496060 A CA 496060A CA 1243369 A CA1243369 A CA 1243369A
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Abstract
HIGH-FIDELITY AUDIO FREQUENCY AMPLIFIER
Abstract A high frequency audio amplifier in which the positive and negative bias ports of an operational amplifier are employed to drive two oppositely phased current mirror circuits. Addition-ally, the outputs of the current mirror circuits are current reg-ulated in terms of the number of base emitter voltage drops in power amplifier circuitry following the current mirrors. Fur-ther, the output stage employs parallel connected radio frequency type transistors.
Abstract A high frequency audio amplifier in which the positive and negative bias ports of an operational amplifier are employed to drive two oppositely phased current mirror circuits. Addition-ally, the outputs of the current mirror circuits are current reg-ulated in terms of the number of base emitter voltage drops in power amplifier circuitry following the current mirrors. Fur-ther, the output stage employs parallel connected radio frequency type transistors.
Description
~33~i~
~IIGH-FII~ELITY Al)D10 FREOUENCY AMPLIFIER
Technical Field This invention relates generally to audio freouency ampli-fiers, and particulaxly to a transformerless, high-fidelity, audio freouency amplifier.
_cXqround Art There have been tremendous advances in the past lO years or so in the design of high-fidelity audio frequency amplifiers, and some might say that ~ear perfection has already been achieved.
~]owever, it seems that with each increment of improvement, new flaws are discovered, often not noticed until previously observed ones have been elimina~ed.
Perhaps one of the principal remaining areas of imperfection lies in the inability of perhaps most amplifiers to preserve at the output the precise time relationship bet~een sounds of dif-ferent frequencies ~hich are embodied in the input signal to theamplifier. An e~cellent example of the problem is that of repro-ducing the fundamental and all of the harmonically related compo-nents co~ing from a musical instrument without some discrepancy in time of reproduction of the multitude of frequencies present (group delay).
It is the object of this invention to Drovide an ampLi~ier which reduces the group delay in the time domain and in general improves the quality of reproduction and has a ver~ large phase margin at the output stage.
Su~mary of the Invention In accordance with this invPntion, an input signal is irst amplified in voltage by an operational amplificr. The signal is 3~
separated into positive and negative signal components fox fur-ther and balanced amplification without the reauirement of a separate phase inversion stase. This is acco~plished by using the ~ bias port5 of the operational amplifier as 180~ phase re-versed signal output sources. The positive port drives a posi-tive polarity current amplification mirror, and the negative por~
drives a negative polarity current amplification ~irror. lhe thus derived two, oppositely phased, current signals are then subjected to current regulation precisely in terms of the base emitter junctions which the signal must traverse thereafter in the amplifier. In this way, temperature variations which effect each junction ~ay be summed in effect and compensated for, where-by variations in base-emitter junction impedance with temperature whiah may greatly affect the operating point of an amplifier are precisely compensated for. These and other features, as will be described, esse~tially eliminate ti~e domain aistortion effects currently observable with many amplifiers.
Brief Description-Of the Drawinqs _ Fig. l ia an electrical sche~atic diagram of an embodiment of the inven~ion.
Fis~ 2 is a plan view illustrating the output amplifier stage of the invention, portions of which are shown schematic-ally.
Fig. 3 is a side view oE the output stage shown in Fig. 2.
De~ailed Description of the Invention Referring initially to Fig. l, a source lO of audio frc-quency signals would be applied bet~een the positive, or non-inverting, input o operational amplificr 12 and ground across a small capacitor 14, e.g., 30 PF, and rcsistor l6. This 3~
r~sistance-capacitance combination provides a rolloff of response above about 100 XHz.~ The inverting~input of the amplifier i5 connected across resistor 1~ to ground. Operational amplifier 12 functions ~5 a ~oltage amplifier, and the amplified voltage provides drive to current amplifiers or current mirrors 20 and 22 which mirror in terms of current the positivë and negative volt-age components of the ;nput signal amplified by amplifier 12.
Positive and ~egative compor)ents are 5eparately provided to cur-rent amplifiers ~0 and 22 by feeding an input to positive compo-nent current amplifier 20 from what would normally be the posi-tive bias D.C. port 24 of oprational amplifier 12 and feeding an input to negative component current amplifier 22 from what would normally be the negative bias D~Co port 26 of operational ampli-fier 12.
I~. order to provide a Gompatibility between operating bias levels, that for operational amplifier 1~ of approximately lS
volts, and that for the bias level of the balance of the ampli-fiers at a siqnificarltly higher level, for example, 65 volts, positive level shifter 30 is connected between positive bias port 20 24 of operational ampli~ier 12 and current amplifier 20, and negative potential level shifter 32 is connected between the negative bias port 26 and negative polarity current amplifier 22.
As an example of the two, level shifter 30 employs NPN transistor 34 with its collector-emitter circuit between current amplifier and operational arnplifier 12 and a referencc lS volts applied to its base by virtue of a lS-volt zcner diode 36, in parallel uith capacitor 3a, ~onnected between ground and the base of resistor 3q The base is powered through bias resistor 40 from positive bias rail 42 (~6S volts). In this manner, thc emittcr of transistor 34, and thus the positive port 24 of opcrational amplifier l~t i5 held at esse~tially 15 volts, actually, lS volts 33~
less the voltage drop ~approximately 0.3 volt~ across ~he base-emitter junction~of transistor 34 Level shiftër32 employs PNP transistor 44 and is coupled and operates in a li~e manner to that of level shifter 30 and in-cludes liXe components which are like labele~. Its base isbiased from negative bias rail 46 through resistor 40.
of the ~wo current amplifiers 20 and 22, current amplifier employs PNP transistor 50, and there are two current paths between positi~e bias rail 42 and the collector of transistor 50, one path beinq via resistor 52, diode 54, and diode 56 in series, and the other being through emitter resistor 58, the emitter base circuit of transistor 50, and ~iode 60. With this configuration, the current amplification ratio between current through resistor 52 and the output of the circuit through resistox 58 is deter-mined by the ratio of the values of resistor 52 (e.g., 300 ohms) and resistor 58 (e.g., 100 ohms), thus a ratio in this case of3:1. Diode 54 is employed to provide a forwara semi-conductor junction parallel to that of ~he emitter-base junction of ~ran-sistor 50, and thus with like ambient temperatures~ subject to both junctions, the ~oltage drops across each will be essentially identical, and thereby there i5 preserved the impedance ratio between the two current paths, and thus there is stabily pre-served the current amplification of the amplifier.
Diode 60 is connected between the collector of transistor 50 and the collector of transistor 34, poled for forward flow in the order of this connection, and diode 56 is connected, in a forward current flow mode between the base of transistor 50 and the collector of transistor 34. The pur~ose of these two diodcs is ~o insure that the voltage at the base of transistor 50 will ai~ays be of a value less than the collector voltage of transis-tor 50; and, in fact, by virtue of these two diodes, the voltagc 6~ 1 at ~he base o 'ransistor S0 will always be less by a value of at least the sum o the forward diode voltages of these two d;odes.
This prevents saturation cut-off and ~hus distortion effects that could occur in transistor 50.
EY~cept that current amplifier 22 is coupled through level shifter 32 bet~een negati~e bias rail 46 and negative bias port 26 of operational amplifier 12 and employs an NPN transistor, and thus current flow is ooposite, the connections and operation of current amplifier 22 are identical to that of current amplifier 20.
The output of operational amplifier 12 is terminated by resistor 70, it~ function being merely to maintain z no~mal load on operational amplifier 12 ~e.g., 400 to 600 ohms), and it is not employed as a signal output.
The signal varying output currents of current amplifier 20 and current amplifier 22 flow through signal bus leads 72 and 74 through the base-emitter input circuits of NPN txansistor ampli-fier 76 and PNP amplifier transistor 78, respectively, which function as drive amplifiers for power output stage 80. As a means of maintaining D.C. stability for the system and at an essentially constant operating point, a current regulator 81 is connected between signal buses 72 and 74. It employs an NPN
transistor 85 conventionally treversed biased) connected (collector-emitter) bet~een these buses, and its impedance is regulated by a plurality of forward connected diodes D connected between bus 72 and the base of transistor 85. Resistor 87 is connected between the base and emitter of transistor 85. The function of ehis regulator circuit is to compensate for ambicnt temperature produced changes in forward current flow to transis-tors 7~ and 78 and beyond, this being effected by the regulatorproviding a shunt path which would reduce the driv~ l~vel with ._ 5 3~i~
increase in temperature to thus generally rnaintain a constant operating level. Three diodes D and the basc-emitter ~unction of transistor 8S are employed to stimulate four base-emitter volt-ages which may vary with temperatures, these being: one repre-sented by transistor 76; one represented by transi~tor 78; onerepresented by the parallel combination of power output transis-tors 82a, 82b, 82c, 82d and 82e; and one represented by the voltage drops across the parallel combination of power transis-tors 84a, 84b, 84c, 84d and 84e.
As a further circuit protective means, voltage limiters 86 and 88 are also connected to signal buses 72 and 74, voltage limiter 86 being connected between signal bus 72 and amplifier output bus 90, and voltage limiter 88 being connected between signal bus 74 and output bus 90. These limiters prevent the voltage at the input of transistors 76 and 78 from rising above a selected value and thereby overdriving the circuitry and possibly damaging it.
As a further protective eature, diodes Dl and D2 are con-nected in a reverse direction between the positive and negative rails and output bus. This prevents a voltage swing from an inductive load (a speaker) from raising the effective voltage appli~d to the output stage transistors above the applied biases plus the junction voltage drops of junctions of the~e diodes.
~s a further protective feature, selected degrees of peak operating levels are indicated by means of a pair o overload indication circuits 92 and 94, one for each polarity of the output amplifier. Basically, these would be conventional adjust-able peak voltage indicators. ~n some instances, it may be deemed acceptable to employ only one such indicator.
It is a particular featur~ of this invention that ~11 of the transistors employed are high-frequency transistor~ and prefer-ably having a cut-off no lower than 10 megacycles. Further, circuit layout is in accordance with RF (radio frequency) ~cir-cuitry standards whereby ~tray cap3citances and inductances are ~inimized.
The power output stage 80 of the presen~ amplifier is a balanced amplifier wherein five NPN high-requency t~ansistors 82a-82e are connected in parallel between positive rail 42 and output bus 90 of small value ~e.g., 0.33 ohm) resistors R being connected between the emitter of each and output bus 90. Simi-larly, five P~P transistors 84a-84e are connected in parallel bet-~een negative rail 46 and output bus 90 through like resistors R. The base inputs of transistors 82a-8~e are fed from the emitter output of transistor 76 app~aring across resistor 96 connected between its emitter and output bus 90. Similarly, ~he base inputs of transistors 84a-84e are fed from the emitter output of ~ransistor ~a appearing across its emitt r resistor 98 connected between the emitter of transistor 78 and output bus 90.
~y the employment of several high-frequency parallel transistors, it is possible to hold down the total capa~itance or storage effects and thereby maintain excellent high-frequency operation.
The output of power output stage 80 appears between outpu~;
bus terminal 99 and ground at terminal 100, the ~id point for bias sources 102 and 104 supply the ~65 volts to positive and negative rails 42 and 46. A loudspeaker would typially be con-nected across terminals 99 and 100. The po~er bias sources would typically comprise basic A.C. rectifier type power supplies (or a single supply), provi~ing the ~ bias voltages shown. The purity of these voltages is maintained by the employment of a plurality of filter capacitors for each polarity and the capacitors having different chasacteristics. Thus, in addition to having a basic high value capacitor 106, for example, of 100 MF for capacitor ., - 7 -~2'~33~
106, there i6 al5Q included capacitor 108 ~aving a capacitance of i UF, and capacitors 110 haviny capacitances of 0.1 UF~ Each has a low effective series resistance. The resistancne in each case would be chosen such that the inverse of the R-C time constant of that capacitor would be gre~ter than all fre~uencies of interest.
I~ this manner~ it has been found that the power supply i~ quite flat insofar as it providing a very low impedance to all amplified frequencies.. Actually, as will be noted, there are sever~i of czpacitors havi~g 0~1 MF capacitance.
10As will be further noted, capacitor~ 110 are shown connected to the collector buses, or circui~ board traces 42 and 46 via an arrow which i~ intended t~ indicate that the connection points are variable. In order to locate them, inpu~ sig~al 10 to the circuit is varied over a frequency of 20 ~z 20KH~, ~nd the 15efective load between output terminals 99 and 100 is varied through a range o~ resistive, capaci~ive and induct~ve loading thereby ~arying the power factor between a~out ~1 and 1. When all t~is i~ done, certain combinations of frequencies and loads may generate spurious oscillations at the outp~t of the amplifier at various output voltage levels. These will be accompanied by maxl~um volt~ge or high impedance poin~s appearing along the collector buses 42 and 46. Then, one of the capacitors 110 is connected at each such voltage maximum point. By thls sys~em of connection, the spurious oscillations ~re essentially climinated, enabllng ~ extremely pure and stable output. As a matter of fact, the range of unaffected frequencies is easily from 10 ~z to 75 K~S~.
Inverse fe~dback is provided from output terminal 99, back throuyh resistor 114, and across resistor 18 to the inverting input of operational amplif~er 12. ~esistor 18 is approximately 1/22 of thc valuc of resistor 114, ~nd accordingly, this fraction -- 8 ~
~l2~3~
of the output voltage is fed back to thc inverting input of operational amplifier 12. By virtue of the essentially absolute voltage-to-current ~irror effect of the current amplifiers with respect tv the voltage outputs of operational amplifier 12, there is a negligibly small phase shift between operational amplifie-12 and the output of the amplifier. This enables a high degree of inverse feedback employed ~ithout the occurrence o~ instabil-ity. This, of course, enables the concurrent ~uite high effec-tive damping effect on a speaker connected to the output of the amplifier to thu~ provide a very pzecise control of the speaker.
The increased ability to provide higher inverse feedback also, of course, generally enables a lower distortion oùtput of the arnpli-fier.
As a further feature of the applicant's amplifier, small, 30 PF, inverse feedback capacitors 109 and 118 are connected from outputs of transistors 50 to the inverting input of operational amplifier 12. This enables a very low~ less than 0.~ total harmonic distortion output without feedback from output stage 80.
Likewise, there is enabled a high phase margin, ana thus extreme stability, up to the megacycle range and up to a point where the amplifier has unity gain. Actually, a high degree of inverse feedback is employed via resistor 114 as described above, the feedback providing a very high dampening factor te.g., on the order of 500) and thus achieving a significantly reduced output impedance.
Figs. 2 and 3 illustrate, as one feature of this invention, a p~rticular mechanical construction and arrangement of compo-nents f~r the output stage of applicant's amplifier. ~he output ~ransistOrs 82a-82e and 84a-84e are mounted on a circular metal he~t sink 120, having heat radiating fins 122 positioned between adjacent transistors. As one feature of this arransement, the ~33~i~
emitter leàds are of identical length and are maintained as short as possible. This enables the distsibuted inductance, capaci-tance and resistance to be equal and thus load evenly shared by the transistors. Beyond ~his, the circular construction permits general symmetry of interconnections which enhances the operation of the amplifier.
By virtue of the total system of the invention a5 described, and the extremely small phase shift through the amplifier, and the fact that there is achieved essentially identical (and small) throughput delays of all frequencies, the amplifier provides an unusual degree of clarity and purity of reproduction. Thus, the relationship between harmonic frequencies and their fundamentals are maintained fixed, and sounds which may be rich in harmonics are faithfully reproduced. Beyond its employ~ent for audio ap-plications, the amplifier is ideally suited for a wide range ofother applicztions, including industrial, space and military applications, anywhere a transducer n~ust be driven by an ampli-fied signal in accordance ~Jith the characteristics herein de-scribed.
,
~IIGH-FII~ELITY Al)D10 FREOUENCY AMPLIFIER
Technical Field This invention relates generally to audio freouency ampli-fiers, and particulaxly to a transformerless, high-fidelity, audio freouency amplifier.
_cXqround Art There have been tremendous advances in the past lO years or so in the design of high-fidelity audio frequency amplifiers, and some might say that ~ear perfection has already been achieved.
~]owever, it seems that with each increment of improvement, new flaws are discovered, often not noticed until previously observed ones have been elimina~ed.
Perhaps one of the principal remaining areas of imperfection lies in the inability of perhaps most amplifiers to preserve at the output the precise time relationship bet~een sounds of dif-ferent frequencies ~hich are embodied in the input signal to theamplifier. An e~cellent example of the problem is that of repro-ducing the fundamental and all of the harmonically related compo-nents co~ing from a musical instrument without some discrepancy in time of reproduction of the multitude of frequencies present (group delay).
It is the object of this invention to Drovide an ampLi~ier which reduces the group delay in the time domain and in general improves the quality of reproduction and has a ver~ large phase margin at the output stage.
Su~mary of the Invention In accordance with this invPntion, an input signal is irst amplified in voltage by an operational amplificr. The signal is 3~
separated into positive and negative signal components fox fur-ther and balanced amplification without the reauirement of a separate phase inversion stase. This is acco~plished by using the ~ bias port5 of the operational amplifier as 180~ phase re-versed signal output sources. The positive port drives a posi-tive polarity current amplification mirror, and the negative por~
drives a negative polarity current amplification ~irror. lhe thus derived two, oppositely phased, current signals are then subjected to current regulation precisely in terms of the base emitter junctions which the signal must traverse thereafter in the amplifier. In this way, temperature variations which effect each junction ~ay be summed in effect and compensated for, where-by variations in base-emitter junction impedance with temperature whiah may greatly affect the operating point of an amplifier are precisely compensated for. These and other features, as will be described, esse~tially eliminate ti~e domain aistortion effects currently observable with many amplifiers.
Brief Description-Of the Drawinqs _ Fig. l ia an electrical sche~atic diagram of an embodiment of the inven~ion.
Fis~ 2 is a plan view illustrating the output amplifier stage of the invention, portions of which are shown schematic-ally.
Fig. 3 is a side view oE the output stage shown in Fig. 2.
De~ailed Description of the Invention Referring initially to Fig. l, a source lO of audio frc-quency signals would be applied bet~een the positive, or non-inverting, input o operational amplificr 12 and ground across a small capacitor 14, e.g., 30 PF, and rcsistor l6. This 3~
r~sistance-capacitance combination provides a rolloff of response above about 100 XHz.~ The inverting~input of the amplifier i5 connected across resistor 1~ to ground. Operational amplifier 12 functions ~5 a ~oltage amplifier, and the amplified voltage provides drive to current amplifiers or current mirrors 20 and 22 which mirror in terms of current the positivë and negative volt-age components of the ;nput signal amplified by amplifier 12.
Positive and ~egative compor)ents are 5eparately provided to cur-rent amplifiers ~0 and 22 by feeding an input to positive compo-nent current amplifier 20 from what would normally be the posi-tive bias D.C. port 24 of oprational amplifier 12 and feeding an input to negative component current amplifier 22 from what would normally be the negative bias D~Co port 26 of operational ampli-fier 12.
I~. order to provide a Gompatibility between operating bias levels, that for operational amplifier 1~ of approximately lS
volts, and that for the bias level of the balance of the ampli-fiers at a siqnificarltly higher level, for example, 65 volts, positive level shifter 30 is connected between positive bias port 20 24 of operational ampli~ier 12 and current amplifier 20, and negative potential level shifter 32 is connected between the negative bias port 26 and negative polarity current amplifier 22.
As an example of the two, level shifter 30 employs NPN transistor 34 with its collector-emitter circuit between current amplifier and operational arnplifier 12 and a referencc lS volts applied to its base by virtue of a lS-volt zcner diode 36, in parallel uith capacitor 3a, ~onnected between ground and the base of resistor 3q The base is powered through bias resistor 40 from positive bias rail 42 (~6S volts). In this manner, thc emittcr of transistor 34, and thus the positive port 24 of opcrational amplifier l~t i5 held at esse~tially 15 volts, actually, lS volts 33~
less the voltage drop ~approximately 0.3 volt~ across ~he base-emitter junction~of transistor 34 Level shiftër32 employs PNP transistor 44 and is coupled and operates in a li~e manner to that of level shifter 30 and in-cludes liXe components which are like labele~. Its base isbiased from negative bias rail 46 through resistor 40.
of the ~wo current amplifiers 20 and 22, current amplifier employs PNP transistor 50, and there are two current paths between positi~e bias rail 42 and the collector of transistor 50, one path beinq via resistor 52, diode 54, and diode 56 in series, and the other being through emitter resistor 58, the emitter base circuit of transistor 50, and ~iode 60. With this configuration, the current amplification ratio between current through resistor 52 and the output of the circuit through resistox 58 is deter-mined by the ratio of the values of resistor 52 (e.g., 300 ohms) and resistor 58 (e.g., 100 ohms), thus a ratio in this case of3:1. Diode 54 is employed to provide a forwara semi-conductor junction parallel to that of ~he emitter-base junction of ~ran-sistor 50, and thus with like ambient temperatures~ subject to both junctions, the ~oltage drops across each will be essentially identical, and thereby there i5 preserved the impedance ratio between the two current paths, and thus there is stabily pre-served the current amplification of the amplifier.
Diode 60 is connected between the collector of transistor 50 and the collector of transistor 34, poled for forward flow in the order of this connection, and diode 56 is connected, in a forward current flow mode between the base of transistor 50 and the collector of transistor 34. The pur~ose of these two diodcs is ~o insure that the voltage at the base of transistor 50 will ai~ays be of a value less than the collector voltage of transis-tor 50; and, in fact, by virtue of these two diodes, the voltagc 6~ 1 at ~he base o 'ransistor S0 will always be less by a value of at least the sum o the forward diode voltages of these two d;odes.
This prevents saturation cut-off and ~hus distortion effects that could occur in transistor 50.
EY~cept that current amplifier 22 is coupled through level shifter 32 bet~een negati~e bias rail 46 and negative bias port 26 of operational amplifier 12 and employs an NPN transistor, and thus current flow is ooposite, the connections and operation of current amplifier 22 are identical to that of current amplifier 20.
The output of operational amplifier 12 is terminated by resistor 70, it~ function being merely to maintain z no~mal load on operational amplifier 12 ~e.g., 400 to 600 ohms), and it is not employed as a signal output.
The signal varying output currents of current amplifier 20 and current amplifier 22 flow through signal bus leads 72 and 74 through the base-emitter input circuits of NPN txansistor ampli-fier 76 and PNP amplifier transistor 78, respectively, which function as drive amplifiers for power output stage 80. As a means of maintaining D.C. stability for the system and at an essentially constant operating point, a current regulator 81 is connected between signal buses 72 and 74. It employs an NPN
transistor 85 conventionally treversed biased) connected (collector-emitter) bet~een these buses, and its impedance is regulated by a plurality of forward connected diodes D connected between bus 72 and the base of transistor 85. Resistor 87 is connected between the base and emitter of transistor 85. The function of ehis regulator circuit is to compensate for ambicnt temperature produced changes in forward current flow to transis-tors 7~ and 78 and beyond, this being effected by the regulatorproviding a shunt path which would reduce the driv~ l~vel with ._ 5 3~i~
increase in temperature to thus generally rnaintain a constant operating level. Three diodes D and the basc-emitter ~unction of transistor 8S are employed to stimulate four base-emitter volt-ages which may vary with temperatures, these being: one repre-sented by transistor 76; one represented by transi~tor 78; onerepresented by the parallel combination of power output transis-tors 82a, 82b, 82c, 82d and 82e; and one represented by the voltage drops across the parallel combination of power transis-tors 84a, 84b, 84c, 84d and 84e.
As a further circuit protective means, voltage limiters 86 and 88 are also connected to signal buses 72 and 74, voltage limiter 86 being connected between signal bus 72 and amplifier output bus 90, and voltage limiter 88 being connected between signal bus 74 and output bus 90. These limiters prevent the voltage at the input of transistors 76 and 78 from rising above a selected value and thereby overdriving the circuitry and possibly damaging it.
As a further protective eature, diodes Dl and D2 are con-nected in a reverse direction between the positive and negative rails and output bus. This prevents a voltage swing from an inductive load (a speaker) from raising the effective voltage appli~d to the output stage transistors above the applied biases plus the junction voltage drops of junctions of the~e diodes.
~s a further protective feature, selected degrees of peak operating levels are indicated by means of a pair o overload indication circuits 92 and 94, one for each polarity of the output amplifier. Basically, these would be conventional adjust-able peak voltage indicators. ~n some instances, it may be deemed acceptable to employ only one such indicator.
It is a particular featur~ of this invention that ~11 of the transistors employed are high-frequency transistor~ and prefer-ably having a cut-off no lower than 10 megacycles. Further, circuit layout is in accordance with RF (radio frequency) ~cir-cuitry standards whereby ~tray cap3citances and inductances are ~inimized.
The power output stage 80 of the presen~ amplifier is a balanced amplifier wherein five NPN high-requency t~ansistors 82a-82e are connected in parallel between positive rail 42 and output bus 90 of small value ~e.g., 0.33 ohm) resistors R being connected between the emitter of each and output bus 90. Simi-larly, five P~P transistors 84a-84e are connected in parallel bet-~een negative rail 46 and output bus 90 through like resistors R. The base inputs of transistors 82a-8~e are fed from the emitter output of transistor 76 app~aring across resistor 96 connected between its emitter and output bus 90. Similarly, ~he base inputs of transistors 84a-84e are fed from the emitter output of ~ransistor ~a appearing across its emitt r resistor 98 connected between the emitter of transistor 78 and output bus 90.
~y the employment of several high-frequency parallel transistors, it is possible to hold down the total capa~itance or storage effects and thereby maintain excellent high-frequency operation.
The output of power output stage 80 appears between outpu~;
bus terminal 99 and ground at terminal 100, the ~id point for bias sources 102 and 104 supply the ~65 volts to positive and negative rails 42 and 46. A loudspeaker would typially be con-nected across terminals 99 and 100. The po~er bias sources would typically comprise basic A.C. rectifier type power supplies (or a single supply), provi~ing the ~ bias voltages shown. The purity of these voltages is maintained by the employment of a plurality of filter capacitors for each polarity and the capacitors having different chasacteristics. Thus, in addition to having a basic high value capacitor 106, for example, of 100 MF for capacitor ., - 7 -~2'~33~
106, there i6 al5Q included capacitor 108 ~aving a capacitance of i UF, and capacitors 110 haviny capacitances of 0.1 UF~ Each has a low effective series resistance. The resistancne in each case would be chosen such that the inverse of the R-C time constant of that capacitor would be gre~ter than all fre~uencies of interest.
I~ this manner~ it has been found that the power supply i~ quite flat insofar as it providing a very low impedance to all amplified frequencies.. Actually, as will be noted, there are sever~i of czpacitors havi~g 0~1 MF capacitance.
10As will be further noted, capacitor~ 110 are shown connected to the collector buses, or circui~ board traces 42 and 46 via an arrow which i~ intended t~ indicate that the connection points are variable. In order to locate them, inpu~ sig~al 10 to the circuit is varied over a frequency of 20 ~z 20KH~, ~nd the 15efective load between output terminals 99 and 100 is varied through a range o~ resistive, capaci~ive and induct~ve loading thereby ~arying the power factor between a~out ~1 and 1. When all t~is i~ done, certain combinations of frequencies and loads may generate spurious oscillations at the outp~t of the amplifier at various output voltage levels. These will be accompanied by maxl~um volt~ge or high impedance poin~s appearing along the collector buses 42 and 46. Then, one of the capacitors 110 is connected at each such voltage maximum point. By thls sys~em of connection, the spurious oscillations ~re essentially climinated, enabllng ~ extremely pure and stable output. As a matter of fact, the range of unaffected frequencies is easily from 10 ~z to 75 K~S~.
Inverse fe~dback is provided from output terminal 99, back throuyh resistor 114, and across resistor 18 to the inverting input of operational amplif~er 12. ~esistor 18 is approximately 1/22 of thc valuc of resistor 114, ~nd accordingly, this fraction -- 8 ~
~l2~3~
of the output voltage is fed back to thc inverting input of operational amplifier 12. By virtue of the essentially absolute voltage-to-current ~irror effect of the current amplifiers with respect tv the voltage outputs of operational amplifier 12, there is a negligibly small phase shift between operational amplifie-12 and the output of the amplifier. This enables a high degree of inverse feedback employed ~ithout the occurrence o~ instabil-ity. This, of course, enables the concurrent ~uite high effec-tive damping effect on a speaker connected to the output of the amplifier to thu~ provide a very pzecise control of the speaker.
The increased ability to provide higher inverse feedback also, of course, generally enables a lower distortion oùtput of the arnpli-fier.
As a further feature of the applicant's amplifier, small, 30 PF, inverse feedback capacitors 109 and 118 are connected from outputs of transistors 50 to the inverting input of operational amplifier 12. This enables a very low~ less than 0.~ total harmonic distortion output without feedback from output stage 80.
Likewise, there is enabled a high phase margin, ana thus extreme stability, up to the megacycle range and up to a point where the amplifier has unity gain. Actually, a high degree of inverse feedback is employed via resistor 114 as described above, the feedback providing a very high dampening factor te.g., on the order of 500) and thus achieving a significantly reduced output impedance.
Figs. 2 and 3 illustrate, as one feature of this invention, a p~rticular mechanical construction and arrangement of compo-nents f~r the output stage of applicant's amplifier. ~he output ~ransistOrs 82a-82e and 84a-84e are mounted on a circular metal he~t sink 120, having heat radiating fins 122 positioned between adjacent transistors. As one feature of this arransement, the ~33~i~
emitter leàds are of identical length and are maintained as short as possible. This enables the distsibuted inductance, capaci-tance and resistance to be equal and thus load evenly shared by the transistors. Beyond ~his, the circular construction permits general symmetry of interconnections which enhances the operation of the amplifier.
By virtue of the total system of the invention a5 described, and the extremely small phase shift through the amplifier, and the fact that there is achieved essentially identical (and small) throughput delays of all frequencies, the amplifier provides an unusual degree of clarity and purity of reproduction. Thus, the relationship between harmonic frequencies and their fundamentals are maintained fixed, and sounds which may be rich in harmonics are faithfully reproduced. Beyond its employ~ent for audio ap-plications, the amplifier is ideally suited for a wide range ofother applicztions, including industrial, space and military applications, anywhere a transducer n~ust be driven by an ampli-fied signal in accordance ~Jith the characteristics herein de-scribed.
,
Claims (9)
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A high frequency audio frequency amplifier comprising:
an operational amplifier having an inverting input, a non-inverting input, a positive bias port, a negative bias port and an output, the non-inverting input being a signal input;
a positive potential bias source having a reference terminal and a positive terminal;
a negative potential bias source having a negative terminal and a reference terminal common with said reference terminal of said positive potential bias source;
a first current amplifier having an input coupled between said positive bias terminal and said positive bias port of said operational amplifier and having a first current amplified output;
a second current amplifier having an input coupled between said negative bias terminal and said negative bias port of said operational amplifier and having a second current amplified output;
a first transistor amplifying circuit comprising a first transistor, an amplifier output terminal, a first emitter resistor connected between said amplifier output terminal and the emitter of said first transistor, and the output of said first current amplifier being connected as an input to the base-emitter circuit of said first transistor through said emitter resistor to said amplifier output terminal, and the collector of said first transistor being connected to said positive terminal;
a second transistor amplifying circuit comprising a second transistor of opposite polarity type to said first transistor, a second emitter resistor connected between said amplifier output terminal and the emitter of said second transistor, and the output of said second current amplifier being connected as an input through the base-emitter circuit of said second transistor through said second emitter resistor to said amplifier output terminal;
a first power amplifier comprising at least one third transistor having its input connected to the emitter of said first transistor and its collector connected to said positive terminal, and a third emitter resistor connected between the emitter of said third transistor and said amplifier output terminal;
a second power amplifier comprising at least one fourth transistor of opposite polarity type to said third transistor and having its input connected to the emitter of said second transistor and having its collector connected to said negative terminal, and a fourth emitter resistor connected between the emitter of said fourth transistor and said amplifier output terminal, the combined outputs of said first and second power amplifiers appearing between said amplifier output terminal and said reference terminal;
a temperature compensating current control comprising a fifth transistor connected in emitter-to-collector configuration and between the bases of said first and second transistors, and a plurality of serially connected diodes connected in a forward mode from the base of one of said first and second transistors to the base of said fifth transistor, a negative feedback circuit comprising a feedback resistor connected between said amplifier output terminal and said inverting input of said operational amplifier, a first capacitor connected between the base of said first transistor and the inverting input of said operational amplifier, and a second capacitor connected between the base of said second transistor and the inverting input of said operational amplifier; and a plurality of capacitors including a first plurality of capacitors in turn including capacitors different capacitances connected between said positive terminal and said reference terminal, and a second plurality of capacitors, including capacitors of different capacitances connected between said negative terminal and said reference terminal.
an operational amplifier having an inverting input, a non-inverting input, a positive bias port, a negative bias port and an output, the non-inverting input being a signal input;
a positive potential bias source having a reference terminal and a positive terminal;
a negative potential bias source having a negative terminal and a reference terminal common with said reference terminal of said positive potential bias source;
a first current amplifier having an input coupled between said positive bias terminal and said positive bias port of said operational amplifier and having a first current amplified output;
a second current amplifier having an input coupled between said negative bias terminal and said negative bias port of said operational amplifier and having a second current amplified output;
a first transistor amplifying circuit comprising a first transistor, an amplifier output terminal, a first emitter resistor connected between said amplifier output terminal and the emitter of said first transistor, and the output of said first current amplifier being connected as an input to the base-emitter circuit of said first transistor through said emitter resistor to said amplifier output terminal, and the collector of said first transistor being connected to said positive terminal;
a second transistor amplifying circuit comprising a second transistor of opposite polarity type to said first transistor, a second emitter resistor connected between said amplifier output terminal and the emitter of said second transistor, and the output of said second current amplifier being connected as an input through the base-emitter circuit of said second transistor through said second emitter resistor to said amplifier output terminal;
a first power amplifier comprising at least one third transistor having its input connected to the emitter of said first transistor and its collector connected to said positive terminal, and a third emitter resistor connected between the emitter of said third transistor and said amplifier output terminal;
a second power amplifier comprising at least one fourth transistor of opposite polarity type to said third transistor and having its input connected to the emitter of said second transistor and having its collector connected to said negative terminal, and a fourth emitter resistor connected between the emitter of said fourth transistor and said amplifier output terminal, the combined outputs of said first and second power amplifiers appearing between said amplifier output terminal and said reference terminal;
a temperature compensating current control comprising a fifth transistor connected in emitter-to-collector configuration and between the bases of said first and second transistors, and a plurality of serially connected diodes connected in a forward mode from the base of one of said first and second transistors to the base of said fifth transistor, a negative feedback circuit comprising a feedback resistor connected between said amplifier output terminal and said inverting input of said operational amplifier, a first capacitor connected between the base of said first transistor and the inverting input of said operational amplifier, and a second capacitor connected between the base of said second transistor and the inverting input of said operational amplifier; and a plurality of capacitors including a first plurality of capacitors in turn including capacitors different capacitances connected between said positive terminal and said reference terminal, and a second plurality of capacitors, including capacitors of different capacitances connected between said negative terminal and said reference terminal.
2. An amplifier as set forth in Claim 1 wherein said capacitors connected between said reference terminal and said positive and negative terminals include capacitors connected to points on said terminals at which there appears a voltage peak arising from a standing wave arising out of spurious oscillation.
3. An amplifier as set forth in claim 1 further comprising a first voltage level shifter coupled between said positive bias port of said operational amplifier and said first current ampli-fier, and a second voltage shifter connected between the negative bias port of said operational amplifier and said second current amplifier.
4. An amplifier as set forth in claim 3 wherein said capac-itors include capacitors connected between said reference termi-nal and power terminal, including capacitors connected to points on said power terminal at which there appears a voltage peak arising from a standing wave arising out of spurious oscillation
5. An amplifier as set forth in claim 4 further comprising a first voltage limiter connected between said amplifier output terminal and the base of said first transistor, and a second voltage limiter connected between said amplifier output terminal and the base of said second transistor.
6. An amplifier as set forth in claim 5 further comprising a first diode connected in a reverse bias mode between said amplifier output terminal and said postive terminal, and a second diode connected in a reverse bias mode between said amplifier output terminal and said negative terminal.
7. An amplifier as set forth in claim 6 further comprising a first overload voltage indicator connected between the emitter of said third transistor and said amplifier output terminal, and a second overload voltage indicator connected between the emitter of said fourth transistor and said amplifier output terminal.
8. A high frequency audio frequency amplifier comprising:
an input amplifier having an inverting input, a non-inverting input, a positive bias port, a negative bias port and an output, the non-inverting input being a signal input;
a positive potential bias source having a reference terminal and a positive terminal;
a negative potential bias source having a negative terminal and a reference terminal common with said reference terminal of said positive potential bias source;
a first current amplifier having an input coupled between said positive bias terminal and said positive bias port of said input amplifier and having a first current amplified output;
a second current amplifier having an input coupled between said negative bias terminal and said negative bias port of said input amplifier and having a second current amplified output;
a first transistor amplifying circuit comprising a first transistor, an amplifier output terminal, a first emitter resistor connected to the emitter of said first transistor, the output of said first current amplifier being connected as an input to the base of said first transistor, the collector of said first transistor being connected to said positive terminal;
a second transistor amplifying circuit comprising a second transistor of opposite polarity type to said first transistor, a second emitter resistor connected between the emitter of said second transistor and the first emitter resistor, the output of said second current amplifier being connected as an input to the base of said second transistor;
a first power amplifier comprising at least one third transistor having its input connected to the emitter of said first transistor and its collector connected to said positive terminal, and a third emitter resistor connected between the emitter of said third transistor and said amplifier output terminal;
a second power amplifier comprising at least one fourth transistor of opposite polarity type to said third transistor and having its input connected to the emitter of said second transistor and having its collector connected to said negative terminal, and a fourth emitter resistor connected between the emitter of said fourth transistor and said amplifier output terminal, the combined outputs of said first and second power amplifiers appearing between said amplifier output terminal and said reference terminal;
a temperature compensating current control comprising a fifth transistor connected in emitter-to-collector configuration and between the bases of said first and second transistors, and current conducting means connected from the base of one of said first and second transistors to the base of said fifth transistor;
a negative feedback circuit comprising a feedback resistor connected between said amplifier output terminal and said inverting input of said input amplifier, a first capacitor connected between the base of said first transistor and the inverting input of said input amplifier, and a second capacitor connected between the base of said second transistor and the inverting input of said input amplifier; and a plurality of capacitors, including a first plurality of capacitors in turn including capacitors of different capacitances connected between said positive terminal and said reference terminal, and a second plurality of capacitors, including capacitors of different capacitances connected between said negative terminal and said reference terminal.
an input amplifier having an inverting input, a non-inverting input, a positive bias port, a negative bias port and an output, the non-inverting input being a signal input;
a positive potential bias source having a reference terminal and a positive terminal;
a negative potential bias source having a negative terminal and a reference terminal common with said reference terminal of said positive potential bias source;
a first current amplifier having an input coupled between said positive bias terminal and said positive bias port of said input amplifier and having a first current amplified output;
a second current amplifier having an input coupled between said negative bias terminal and said negative bias port of said input amplifier and having a second current amplified output;
a first transistor amplifying circuit comprising a first transistor, an amplifier output terminal, a first emitter resistor connected to the emitter of said first transistor, the output of said first current amplifier being connected as an input to the base of said first transistor, the collector of said first transistor being connected to said positive terminal;
a second transistor amplifying circuit comprising a second transistor of opposite polarity type to said first transistor, a second emitter resistor connected between the emitter of said second transistor and the first emitter resistor, the output of said second current amplifier being connected as an input to the base of said second transistor;
a first power amplifier comprising at least one third transistor having its input connected to the emitter of said first transistor and its collector connected to said positive terminal, and a third emitter resistor connected between the emitter of said third transistor and said amplifier output terminal;
a second power amplifier comprising at least one fourth transistor of opposite polarity type to said third transistor and having its input connected to the emitter of said second transistor and having its collector connected to said negative terminal, and a fourth emitter resistor connected between the emitter of said fourth transistor and said amplifier output terminal, the combined outputs of said first and second power amplifiers appearing between said amplifier output terminal and said reference terminal;
a temperature compensating current control comprising a fifth transistor connected in emitter-to-collector configuration and between the bases of said first and second transistors, and current conducting means connected from the base of one of said first and second transistors to the base of said fifth transistor;
a negative feedback circuit comprising a feedback resistor connected between said amplifier output terminal and said inverting input of said input amplifier, a first capacitor connected between the base of said first transistor and the inverting input of said input amplifier, and a second capacitor connected between the base of said second transistor and the inverting input of said input amplifier; and a plurality of capacitors, including a first plurality of capacitors in turn including capacitors of different capacitances connected between said positive terminal and said reference terminal, and a second plurality of capacitors, including capacitors of different capacitances connected between said negative terminal and said reference terminal.
9. An amplifier as set forth in Claim 8 wherein said capacitors connected between said reference terminal and said positive and negative terminals include capacitors connected to points on said terminals at which there appears a voltage peak arising from a standing wave arising out of spurious oscillation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000496060A CA1243369A (en) | 1985-11-22 | 1985-11-22 | High-fidelity audio frequency amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000496060A CA1243369A (en) | 1985-11-22 | 1985-11-22 | High-fidelity audio frequency amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1243369A true CA1243369A (en) | 1988-10-18 |
Family
ID=4131950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000496060A Expired CA1243369A (en) | 1985-11-22 | 1985-11-22 | High-fidelity audio frequency amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1243369A (en) |
-
1985
- 1985-11-22 CA CA000496060A patent/CA1243369A/en not_active Expired
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