CA1238404A - Remote data link controller - Google Patents

Abstract

A REMOTE DATA LINK CONTROLLER
ABSTRACT OF THE DISCLOSURE

A remote data link controller for processing control data in a telecommunications switching system.
The telecommunications switching system includes a peripheral processor and at least one digital link for sending and receiving data messages to and from at least one other telecommunications switching system.
The remote data link controller includes a peripheral processor output buffer arranged to receive and store control data in the form of data words from the periph-eral processor. A formatter connected to the periph-eral processor output buffer and to the digital link is arranged to assemble the data words into a data message for transmission over the digital link.
reformatter disassembles a received data message from the other telecommunications switching system to data words. A peripheral processor input buffer receives the reformatted data words allowing for the subsequent access of the data words by the peripheral processor.

Description

I
A REMOTE DATA LINK CONTROLLER
CROSS-REEERENCE TO RELATED Applications The present application is related to the following co-pending Canadian Patent applications all having the same inventive entity and being assigned to the same assignee:
Serial No. 469,809-6, titled, "A Remote Data Link Controller Having Multiple Data Link Handling Capabilities;"
Serial No. 4697818-5, titled, "A Remote Data Link Receive Data Reformatted;"
lo Serial No. 469,817-7, titled, "A Remote Data Link Transmit Data Formatter;"
Serial No. 469,816-9, titled, "A Remote Data Link Address Sequencer and a Memory Arrangement for Accessing and Storing Digital Data;"
Serial No. 469,815-1, titled, "A Data Format Arrangement For Communication Between the Peripheral Processors of a Telecommunications Switching Network."
BACKGROUND OF THE INVENTION
The present invention relates in general to data transmission between the switching systems of a telecommunications network and more particularly to a remote data link controller for formatting, transmitting and receiving control data between the peripheral processors of each switching system.
In modern digital telecommunication switching systems a concept of network modularity has been designed allowing the interconnection of small switching systems remote to a larger host system. These remote switching systems have capacities to handle between a few hundred and a few thousand telephone subscribers.
The remote switching systems are normally used in areas where the installation of a large switching system would be uneconomical.
A high speed digital data link typically interfaces the host switching system to the remote ~4~7 Lo system through which large amounts of voice and con-trot data are exchanged. The voice data normally comprises subscriber calls switched through either the host or the remote system. The control data may 5 be status exchanges between the host and the remote, i.e. centralized administration, billing and Maine-nuance, or the direct control of the operation of the remote by the host.
The control data exchanges are originated 10 in the sending system peripheral processor transmitted over the high speed digital data link to the receiving system peripheral processor where the data is inter-preyed. In order to relieve each peripheral processor from the burden of controlling the data link a remote 15 data link controller is implemented in each system which performs all tasks involved in the formatting, transmission and reception of the control data The remote data link controllers are con-netted to each other via digital spans These digital 20 spans may be To, To or Tic, To carriers using DSl, DS2 or DSlC, DS3 data formats, respectively. These digital spans transmit data at high speeds serially at a rate of approximately 1.5-45 megabit per second.
Accordingly, it is the object of the present 25 invention to provide a remote data link controller for formatting, transmitting and receiving controlled data over a dedicated data link between the peripteral processors of a host and remote switching system.
SUMMARY OF THE INVENTION
In accomplishing the object of the present invention there is provided a remote data link con-troller for processing control data in a telecommuni-cations switching system. The telecommunications switching system includes a peripheral processor and 35 at lest one digital link for sending and receiving data messages to and from at least one other telecommuni-cations switching system.

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The remote data link controller of the present invention comprises a per ipheral processor output buffer connected to the peripheral processor The output buffer is arranged to receive and store control data in the form of data words from the pew referral processor.
A formatter is connected to the peripheral processor output buffer and to the digital link.
The formatter is arranged to assemble the data words from the peripheral processor output buffer into a data message. The data message it then subsequently transmitted to the other telecommunications switching system via the digital link.
A reformatted is also included which is connected to the digital link and arrange to disk assemble a receive data message from the other tote-communications switching system into data words Finally, a peripheral processor input buffer connected to the peripheral processor and to the reformatted receives the data words from the reformatted and stores the data words for the subsequent access of the da a words by the peripheral processor BRIEF DESCRIPTION Ox TOE DRUNKS
Fig. 1 is a block diagram of a telecommuni cations switching system including the remote data link controller of the present invention.
Fig 2 is a bit map of a channel and frame of a To digital span.
Fig. 3 it a bit map representation ox the data format developed and transmitted by the remote data link controller of the present invention.
Fig. 4 is a detailed block diagram of the remove data link controller of the present invention.
Fig. 5 is a bit map of a data byte, and 35 time utilization diagram of a remote data link con-troller channel DESCRIPTION OF THY PREFERRED El~lBODIMENT
Referring to Fig. 1, a time-space-time digital switching system along with the corresponding common control is shown. Telephone subscribers, such as subscribers 1 and 2, are shown connected to analog line unit 13. Analog line unit 13 is connected to both copies of the analog control unit 14 and 14'.
Originating time switches 20 and 20' are connected to a duplex pair of space switch units 30 and 30' which are in turn connected to a duplex pair of ton-minuting time switches 21 and 21'. Terminating time switches 21 and 21' are connected to analog control units 14 and 14' and ultimately to -the telephone subscribers 1 and 2 via analog line circuit 13.
Digital control units 15, 15' and 16, 16' connect the digital spans to the switching system. Digital span equipment may be implemented using a model 9004 To digital span, manufactured by GUT Len Kurt, Inc.
Similarly, analog trunk unit 18 connects trunk circuits to the digital switching system via analog control units 17 and 17'.
A peripheral processor CPU 70 controls the digital switching system and digital and analog con-trot units. Analog line unit 13 and a duplex pair 25 of analog control units 14 and 14' interface to tote-phone subscribers directly. A duplicate pair of digital control units 15, 15 ' and I 16 ' control the incoming PAM data from the digital spans. Similarly, the analog trunk unit 13 and a duplex pair of analog control units 17 and 17' interface to trunk circuits.
The analog and digital control units are each dipole-acted for reliability purposes.
The network of Fig. 1 also includes a REMOTE
DATA LINT CONTROLLER (Rl)LC) 100 which provides for-matting and control of data transmitted and received between the peripheral processors of two or more switching systems. The RDLC can provide up to 16 t 64 kilobytes per second data links arranged for full duplex open-anion and is configured so that it can provide one I
full duplex data link for each of the 16 To spans.
RDLC 100 can operate together with one or two digital control units (DCU)/ with each DCU capable of pro-voiding up to eight To carrier facilities.
RDLC 100 includes a duplicated data link processor and control 80 and 80' and a duplicated peripheral processor (PUP) I/0 buffer 60 and 60'.
Prior to examining the detailed operation of the RDLC 100, it is helpful to understand the format and protocol of the messages which are trueness milted and received by the RDLC. Each message con-sits of eight, 8-bit bytes of data for a total of 64 bits. The peripheral processor I/0 buffer provides four transmit message buffers and four receive message buffers for each of the 16 possible data links.
Mortally, peripheral processor software writes a message into a transmit message buffer of PUP I/0 buffer 60 and I associated with a data link and then issues a transmit command to data link pro-censor and control 80 and 80'. The data link pro-censor and control 80 and 80' responds by taking the message out of the transmit message buffer, formatting the data so that it can be transmitted over a To carrier and then transmits the message to the distant end of the data link through the appropriate DCU and digital span.
when a message is received, the data link processor and control 80 and 80l reformats the no-ceiled data and places the message into an appropriate receive message buffer in the PUP I/0 buffer 60 and 60'. Data link processor and control 80 and 80' then causes an interrupt, alerting peripheral processor 70 and 70' to the fact that a message has been no-ceiled. The RDLC will queue up to three received messages for each data link. It should be noted that under normal conditions the RDLC functions in a duplex configuration, that is, it matches all outgoing signals performed in the DCUs. With this arrangement there is one RDLC circuit for each of the two copies of the DCUs. 5 I
The nettler of a To data and its format is shown in Fig. JO Normally, each To span transmits and receives voice samples organized together into a frame. Each frame includes 24 voice samples with each voice sample associated with one channel of voice (or data). The channels renumbered 0-23. Normally, the RDLC will insert its data bytes in channel 0.
The S bit carries a periodic pattern which, when detected, is used to identify the beginning of each frame of data.
Turning to Fig. 3, the complete data format for one message is shown. The data format is byte oriented with one 8-bit byte being transmitted during each To data frame for each data link. When the link is idle and not transmitting the transmitter sends idle patterns consisting of all ones. The beginning of a message is indicated by sending a control byte containing one or more zeros which may contain in-formation conveying the sequence number of messages transmitted or received and/or acknowledgments between the ~DLCs. As can be seen in Fig. 3 only six control bits are used ~XC, XB, ZOO ARC, RUB, I in the control byte. The first data bit to be transmitted is in-sorted in the bit 1 position of the control byte.
The control byte further includes an odd parity bit in bit position 0. 'rho next nine bytes contain the remaining 63 bits of data, each byte containing seven bits of data plus an odd parity bit. The final message byte contains seven vertical parity bits plus an odd parity bit for the vertical parity byte. Each vertical parity bit provides even parity for ten of the pro-ceding bits, i.e. Pi for bit 1 in each of the pro-ceding ten bytes, Pi for bit 2, Pi for bit 3, etc.
The next byte will contain idle pattern.
It should be noted that the idle pattern is unique in thaw it has even parity. This makes it easy for the receiver to synchronize with the incoming data stream and greatly reduces the chance that a receiver would accept an incorrect message because of improper synchronization.
Turning now to Fig. 4 a block diagram of the data link processor and control 80, 80' for a single data link of RDLC 100 is shown. The PUP I/0 buffer 60 is a 64 x 8 bit memory providing storage for up to four transmit and four receive messages.
As explained in Fig 3, each message is eight bytes long. It should be noted what only three of each of these four message buffers can have data queued up at any one time. The peripheral processor (PUP) accesses the PUP I/O buffer I either to store messages prior to transmission or to extract messages after reception.
The active transmit buffer store 83 and active receive buffer store 84 are each 2-bit fog-inters identifying which one of the four transmit message buffers and which one of the four receive message buffers respectively is available for PUP
access. The PUP provides a 4-bit address identifying which word to access and whether the access is for a transmit or a receive buffer. The transmit/receive address bit selects the contents of one of the two stores 83 or 84. The two bits from the store are !
appended to the PUP address providing a complete 6-bit address used to access the PUP I/O buffer 60.
The status register 82 is a 4-bit register containing status information to the PP. This status information includes how many transmit buffers are available for a PUP access and how many receive buffers contain data and are available for PUP access.
Transmit data from the PUP IT buffer 60 is processed and formatted in the transmit formatter.
The transmit formatter is comprised of a transmit receive buffer (ORB) 91, transmit parallel to serial convertor (XP2SC) 92, vertical parity generator ~VPG~
US, horizontal parity generator PUG 94~ transmit son tat to parallel converter (XS2PC) 93 and transmit bit counter (XBC) 97.

A message to be transmitted is formatted a byte at a time. One message byte is read from the PUP I/O buffer I and transferred into ORB 91. The ORB 91 provides an asynchronous interface between the PUP I/O buffer Jo and XP2SC 92. The ORB 91 ensures that data is always immediately available to XP2SC
92 without any contention with PUP accesses. ORB 91 may be thought of as providing a look-ahead or data prefetch for the XP2SC 92. When XP2SC 92 is empty a byte of data is transferred from ORB 91 into XP2SC
92. Simultaneously, XBC 97 is reset to 0. Each time a bit is shifted out of XP2SC go XBC 97 is incremented.
When the XBC counts up to eight, it means the XP~SC
is empty and the process repeats itself. Data is shifted out of XP2SC 92 a bit at a time into XS2PC
93. During the shifting of the data bits out of XP2SC
92, vertical parity and horizontal parity is generated by VPG 95 an HUG 94 respectively.
When seven data bits have been accumulated in XS2PC 93 the convents of PUG 94 is appended to the seven data bits to form an 8-bit byte which is transferred to the DCU output buffer ~DCUOB) 200 During channel 0 of the appropriate To carrier, the data byte in DCUOB 200 is passed to the DCU and subsequently transmitted over the T carrier.
The timing of this process is arranged to generate one data byte every 125 microseconds for each link.
The inverse of this process takes place in the receiver reformatted. The receiver reformatted comprises a receiver parallel to serial convertor (RP2SC) 103, vertical parity checker (VPC) 105, horn zontal parity checker (HPC) 104, pattern recognize 106 receiver bit counter (RBC) 107, receive serial to parallel converter (RS2PC) 1~2 and receive write buffer RUB 101.
Data from the To carrier and DCU is stored in the DCU input buffer (DCUIB) 201. It is then transferred to RP2SC 103. The received data byte is then shifted out of RP2SC 103 one bit at a time L

to RS2PC 102. horizontal and vertical parity checks are performed on the shifted data byte by HPC 104 and VPC 105 respectively and are both arranged to abort the reformatting process.
RBC 107 keeps track of the number of data bits in RS2PC 102. When eight data bits are accumulated in RS2PC 102 they are transferred to RUB lo and from there to the PUP I/O buffer 60. The ROB lo provides the same kind of asynchronous interface that the ORB
lo 91 provides in the transmit formatter.
Idle pattern is generated by jamming the input of X52PC 93 to logic l. The vertical parity byte is transmitted by selecting the VPG 95 output as an input to XS2PC via the 2/l multiplexer 98.
The control byte is transmitted by disabling ORB 91 and loading XP2SC 92 with six bits of control data from the data link processor 81.
The control byte is formatted by presetting the XBC 97 to a count of 2 then loading XP2SC 92 with the six control bytes. When the six control bytes have been transferred to XS2PC 93 the XBC 97 will initiate the transfer of the first data byte into XP2SC 92 from ORB 91. The first data bit, Do, will thence shifted out as part of the control byte.
The receive section also includes a pattern recognize 106 which monitors the data shifted out of RP~SC 103 and recognizes the idly pattern. As long as idle pattern is being received pattern fee-ogni~er 106 OUtplltS a signal to the data link pro-censor that the link is idle.
In this particular embodiment it should be understood that the RDLC 100 would be used for a single data link; it an individual circuit for link 0, link 1, link 2, etc.
Turning now to Fig. 5, the overall timing that repeats for every frame is shown. As can be seen the frame is divided into three intervals, interval A, interval B and interval C.

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During interval A, each RDLC circuit devotes all its resources to the task of transferring data to and from the DCUs. Data for all 16 data links would be exchanged during this 5.184 microsecond interval. No processing occurs during this time although the peripheral processor may access the I/O
buffer or the status register for status information.
During interval B, the RDLC devotes its time to formatting and reformatting data.
During interval C, the RDLC waits for the beginning of the next frame. This waiting period lasts approximately 16 microseconds. Therefore, the entire RDLC channel within each frame lasts approxi mutely 125 micro~econdsO
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit owe the in-mention or from the scope of the appended claims

Claims (7)

WHAT IS CLAIMED IS:

1. A remote data link controller for processing control data in a telecommunication switching system, said telecommunication switching system further includ-ing a peripheral processor and at least one digital link for sending and receiving data messages to and from at least one other telecommunication switching system, said remote data link controller comprising:
peripheral processor output buffer means compris-ing a memory having a plurality of memory locations, connected to said peripheral processor, each memory location is arranged to receive and store control data in the form of a data word from said peripheral, said remote data link further including an active transmit buffer store register containing control data identify-ing which of said plurality of memory locations can be accessed by said peripheral processor;
formatting means connected to said peripheral processor output buffer means and said digital link arranged to assemble said data words from said periph-eral processor output buffer means into a data message for transmission of said data message to said other other telecommunication switching system via said digital link;
reformatting means connected to said digital link arranged to disassemble a received data message from said other telecommunication switching system into data words; and, peripheral processor input buffer means comprising a memory having a plurality of memory locations, connected to said peripheral processor and said refor-matting means, each memory location is arranged to receive and store control data in the form of a data word from said reformatting means for the access of said data words by said peripheral processor, said remote data link further including an active transmit buffer store register containing control data identify-ing which of said plurality of memory locations can be accessed by said peripheral processor.

2. A remote data link controller as claimed in claim 1, wherein: each data word includes 8 bits of data and said formatting means assembles 8 data words into said data message containing 10 data bytes, including a first data byte having 6 control bits, a data bit and a parity bit, and nine subsequent data bytes each including 7 data bits and a parity bit, said formatting means comprising:
transmit receive buffer means connected to said peripheral processor output buffer means arranged to receive and store in parallel data form a data word from said peripheral processor output buffer means when said transmit receive buffer means is empty;
transmit parallel to serial converter means having a parallel data input connected to said transmit receive buffer means and arranged to receive said data word from said transmit receive buffer means, said transmit parallel to serial converter means further including a serial data output arranged to output said data word in serial format responsive to formatting means clock signal;
a transmit bit counter connected to said format-ting means clock signal arranged for counting said serial data bits output by said transmit parallel to serial converter means, said transmit bit counter causing said transmit parallel to serial converter means to be loaded with a second data word from said transmit receive buffer means when 8 bits of data have been output by said transmit parallel to serial converter means;
transmit serial to parallel converter means including a serial input connected to said transmit parallel to serial converter means output, arranged to receive said data bits output by said transmit parallel to serial converter means converting 7 of said received serial data bits to parallel form for output via a parallel output;
horizontal parity generator means connected to said transmit parallel to serial converter means output arranged to generate a parity bit after 7 data bits have been output by said transmits parallel to serial converter means, said parity bit appended to said 7 parallel data bits formed in said transmit serial to parallel converter means forming a data byte of said data message, said 8th data bit left in said serial to parallel converter means forming the first bit of the next data byte of said data message; and digital link output buffer means connected to said parallel output of said transmit serial to parallel converter means, said digital link output buffer means arranged to receive said data message data byte for transmission to said other telecommunication switching system via said digital link.

3. A remote data link controller as claimed in claim 2, wherein: said remote data link controller further includes a data link processor and said data link processor includes an output connected to said transmit parallel to serial converter means input, said data link processor arranged to output to said transmit parallel to serial converter means said 6 control bits of said first data byte.

4. A remote data link controller as claimed in claim 2, wherein: said data message further includes a eleventh data byte comprising 7 vertical parity bits and a horizontal parity bit for the eleventh data byte, and said formatting means further includes a vertical parity generator means having an input connected to the serial output of said transmit parallel to serial converter means and responsive to the serial data output of said transmit parallel to serial converter means, a vertical parity bit is formed and stored in said vertical parity generator means, and after 10 data bytes have been formatted, said transmit parallel to serial converter means is disabled and said vertical parity generator means outputs serially 7 vertical parity bits to said transmit serial to parallel con-verter means formats and said horizontal parity genera-tor means, whereby, said transmit serial to parallel converter means formats said 7 vertical parity bits in parallel form and said horizontal parity generator means outputs a horizontal parity bit appending said horizontal parity bit to the 7 vertical parity bits, said transmit serial to parallel converter outputs said eleventh data byte to said digital link output buffer means for transmission.

5. A remote data link controller as claimed in claim 4, wherein: said formatting means further includes multiplexer means having a first input con-nected to said transmit parallel to serial converter means serial output and a second input connected to said vertical parity generator means serial output, said multiplexer means including a serial output connected to the input of said transmit serial to parallel converter means, whereby for the first 10 data bytes of said data message said multiplexer connects the output of said transmit parallel to serial convert-er means to the input of said transmit serial to parallel converter means and on the eleventh data byte said multiplexer disables the output of said transmit parallel to serial converter means and connects the output of said vertical parity generator means to the input of said transmit serial to parallel converter means.

6. A remote data link controller as claimed in claim 1, wherein: said data message includes 10 data bytes including, a first data byte having 6 control bits, a data bit and a parity bit, and 9 subsequent data bytes each having 7 data bits and a parity bit, said reformatting means comprising:
data link input buffer means having parallel data inputs and outputs, said inputs connected to said data link and arranged to receive a data byte of said data message storing said data byte therein;
receive parallel to serial converter means having a parallel data input connected to said data link input buffer means output, arranged to receive the data bytes stored by said data link input buffer means outputting said data byte serially;
a horizontal parity checking means having a serial input connected to said receive parallel to serial converter output arranged to check for correct horizon-tat parity for said received data byte output by said receive parallel to serial converter means and to output an error signal to said peripheral processor if a parity failure is detected;
receive serial to parallel converter means having a serial input connected to said receive parallel to serial converter means output and a parallel output, said receive serial to parallel converter means arranged to receive said data bits output from said receive parallel to serial converter means responsive to a reformatting means clock signal;

a receive bit counter connected to said reformat-ting means clock signal, arranged for counting said serial data input by said receive serial to parallel converter means, causing said receive serial to paral-lel converter means to output its contents when 8 data bits of a data word have been received; and receive write buffer means including parallel inputs and outputs and having said receive write buffer means parallel input connected to said receive serial to parallel converter means parallel output and said receive write buffer means output connected to said peripheral processor input buffer, said receive write buffer arranged to receive the reformatted data words from said receive serial to parallel converter means, outputting said data word to said peripheral processor input buffer for subsequent access of said data word by said peripheral processor.

7. A remote data link controller as claimed in claim 6, wherein: said data message further includes an eleventh data byte comprising 7 vertical parity bits and a horizontal parity bit for the eleventh data byte, and said reformatting means further includes a vertical parity checking means having a serial input connected to said receive parallel to serial converter means serial output and responsive to the eleventh data byte output by said receive parallel to serial converter means said vertical parity checking means inputs the 7 vertical parity bits and outputs an error signal to said peripheral processor responsive to a detected vertical parity failure.