CA1233545A - Arrangement for sensing remote binary inputs - Google Patents

Abstract

ARRANGEMENT FOR SENSING
REMOTE BINARY INPUTS

Abstract of the Disclosure An improved switch input arrangement for a system that remotely controls distributed electrical loads. The switch input arrangement is part of a transceiver decoder that receives commands from central controller for controlling the state of latching relays for controlling the power circuits of the loads. The improvements include: monitoring the state of contact closure inputs to the trans-ceiver decoder, selectively enabling/disabling specific contact closures to control the masking of switch inputs, inclusion of an accumulated switch buffer to store the last actuation state of all relays, an answerback to insure that action occurs responsive to a switch input, a shifting threshold and multiplexing technique for more accurate reading of contact closure switch inputs, and the inclusion of a power-up reset message annunciated to the central controller to alert it that certain commands may have to be issued in order to reestablish the desired states of the transceiver.

Description

~233~;4S

ARRANGEMENT FOR SENSING REMOTE BINARY INPUTS
Background of the Invention There has been developed a system for remotely controlling electrical loads distributed over a wide area (such as a large office building or factory) from a micro-processor based central controller. That system is disclosed in U.~. Pat. 4,367,414 ~ Miller et al, issued Jan. 4, 1983. In the Miller '~14 system, control instructions are issued by the central controller 50 and are transmitted to various transceiver-decoders 56 via a twisted pair cable 58 constituting a bi-directional communications channel. A particular transceiver-decoder that is "addressed" carriers out the command by actuating one or more particular relays to make or break an electrical connection as desired. The central controller issues its control instructions in accordance with a predetermined schedule, in response to a measured parameter (such as light level or temperatllre~ or i~ r~sp~e to ~
user switch actuation sensed by a switch processor in the transceiver decoder and transmitted to the central controller over the bi-directional C - - - _. .__ ___ , '' ". " '' '' - ~ ~ . - . ' l~lS~5 LD 091a6 communications link, or in response to a user command telephonically transmitted to the central controller.
Although the Miller '414 system operates effectively as disclosed, further enhancements are now possible. This patent is directed to improve-ments in the transceiver-decodPr, particularly to a switch input arrangement for processing various binary closure inputs to the transceiver decoder to be transmitted to the central controller to give it information or request a relay state change.
The enhanced transceiver-decoder is configured in a modular fashion. Separate switch and relay "modules" are provided to allow a user of the product to configure a remote control panel to meet his specific application needs. This modular construction is field adaptable allowing an electrician who has no electronic expertise to easily install r replace and service the panels. To do this, small modules are developed so that they can be easily handled and configured in the field.
It i5 now possible to further enhance means for sensing the ON/OFF condition of binary contacts to make appropriate control decisions~ In the system depicted in ~IGURE 1 of Miller '414, central - controller 50 could interrogate binary inputs located on a remotely located transceiver and determine the proper control output needed in response to the condition of those binary sensors.
This is particularly useful where a thermostat is employed as a binary input to the central controller which would turn ON and Off or cycle heating ventilation air conditioning systems according to the ON/OFF condition of the thermostat switch which 3~

would be preset to a predetermined temperature threshold. Additionally, a photo relay or switch can be connected to these binary inputs to determine which lights are to go ON and OFF within a perimeter office in response to the amount of sunlight entering the area.
It is desirable to be able to selectiYely disable the response to certain or specified individual switch inputs thereby allowing certain switch inputs to be masked outO As previously disclosed in Miller '414, the actuation (either opening or closing) of a contact causes immediate transmission back to the controller so that appropriate control information can be transmitted forcing the proper load state. It may be desired at certain times of day, however, to disable selected switches so that no action occurs ignoring its ON/OFF condition. A typical application would include night setback thermostats where two thermostats would be connected to two binary inputs such that one thermostat would be enabled and so set - for normal working periods while the second thermostat would be set and enabled during off hours providing the night setback function. This selective enabling and disabling of contact closure or binary sensors are achieved by commands from the central facility means.
It is also desirable to provide a positive acknowledgement from the central facility means to the remote input transceiver verifying the action of the chan~e of state of binary contact closures. In the prior art, a transmission would be immediately initiated by the transceiver to the central controller means upon the enabling of a binary 3~S

input. Only one transmission was made such that if the central controlled means missed the message no action would take place. Since this is undesirable for use with critical inputs such as alarms, demand, security and other binary input functions, an answer back function was added. This answer back scheme would result in the input transceiver to periodically transmit to the central controller the action of the binary sensor until the reception of a positive acknowledge that the message was received from the central controller means.
It is also desirable to provide improved self diagnostics such that the central controller can detect the erroneous resetting or subsequent application of power to remotely located transceivers. This power-up and reset annunciation will insure the integrity of the distributed data base while providing a diagnostic means to trace failed devices.

Summary of the Invention This invention relates to improvements in transceiver-decoders 56 shown in Figure l of Miller '414. Now, each transceiver-decoder has separate processors for carrying out switch functions (sensing a condition chan~e or a user initiated contact closure and sending a message to central controller 50) and receiving a command from central controller 50 and controlling in response to that command, one or more relays in the power circuits of electrical loads to be controlled.

5 ~:33~

T~e transceivers according to this invention have some physical and functional differences from those of the Miller '414 patent.
These differences are upward compatible with ~he Miller '414 design and therefore, interchangeable in the field. The notable physical and functional improvements are:

- New reset button function whic~ would cycle loads both on and off.
- Built-in installation test scenario.
- New built-in functions for future product offerings.
- Smaller enclosure and plus-in modular design.
- No switch inputs - allow add ON switch input modules.

Swit~h~Only-Transceivers A switch-only-transceiver can be configured as an add-on plug in module. It can be a "piggy-back" module for any new transceiver.

Pulse-Output Transceiver This transceiver provides a means to pulse high current contactors or motor startersO This product has solid-state outputs capable of driving a maximum of 1 amp at 120 VAC for 100 msec's. In the alternative, this function can be carried out as a relay output function. The product is configured in 5~5 8 outputs and should fit into the same case as the stand alone switch-only-transceiver.
All of the above products are configures to operate at 115V, 230V, and 277V AC (50/60 ~z) s desirable to have these multiplicity of input voltages be compatible with every product so there is no distinction due to input voltage.

Power Suppl~

A universal power input circuit is provided for all products rated for an input voltage range of lOOVAC to 320VAC (RMS) at 47 to 100 Hz.
The power dissipation of the transceiver is kept as low as possible to eliminate the need of costly cooling techniques. The maximum steadystate power (not pulsing relays) does not exceed 700 mW
per transceiver.

Watchdog Reset A watchdog reset circuit is provided to reset the microcomputer chip in the unlikely event noise causes it to adversely execute erroneous instructions and latchings in a closed loop. The watchdog reset physically resets the computer causiny it to execute a power-up sequence described below.

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Switch Input Processin~

A switch input interface for both a standard 3 wire momentary and ~ wire maintain with a user selectable jumper is to be provided in the same fashion as the Miller '414 transceiver. The switch connects to the transceiver over number 20 AWG wires of up to 250 feet in length. The switch interface circuitry on the transceiver must provide a high enough voltage, typically qreater than 20 VDC, so as to breakdown typical oxides that form on the switch contacts.

Switch Interface S~ecifications Description Notes* Min. Max. Typ. Units Electrical - Switch Closed Contact Resistance 1 700 Ohms - Open Contact Volta~e 2,5 20 40 30 VDC
- Current Supply At 18 VDC 3,5 1.8 5 2 ma - Switch Input Threshold 4,5,6 8 12 10 Volts Functional Timing - Response To Valid Switch Closure 7 40110 50 msec (Debounce Period) - Switch Input Noise Filtering 8 10 KHz (Cut Off Frequency) Special Function Device Loadin~ With lB vdc Minimum 3 10k Ohms _ * See the following notes for a description of the specificatlon.

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Switch Spe~ification Notes:

1. The switch contact resist~nce is the maximum impedance that a switch device can have and properly be interpreted as a switch closure. This specification is particularly important for electronic switching means connected to the transceiver.

2. The open contact voltage is a specifi-cation to ensure that a minimum voltage is provided or impressed by the transceiver on the switching device to break down oxides that typically form on switch contacts.
~urthermore, it i5 also necessary to ensure a wide noise margin with a large voltage swing. The maximum spec. of 40 VDC is limited by NEC
Class 2 circuit requirements.

3. The current supply specification is for special function devices that derive its power from the switch inputs of the transceiver. For example, the BPHOTO-4 photoswitch is a low current device that can derive its operating power from the signal inputs. Therefore, to ensure proper noise immunity, an 18 VDC minimum must be maintained at 1.8 ma current to supply power to the special function device so as not to be mistakenly read as a switch closure. Therefore, the maximum DC operating impedance or load .
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on a switch input cannot be less than 10K Ohms. If the special function peripheral device is less than 10K
Ohms, an external power supply is needed for it to derive its power.
This spec. also indicates the current limiting required on the switch input circuitry at 0 volts or in the closed contact condition.
- 10 4. The switch input threshold is the minimum voltage below which a switch is considered closed or in tAe "make"
condition. Similarly if a switch input is above its maximum voltage it is considered open or in the "break"
condition. More significant is the DC
impedance on the contact device itself needed to cause this maximum voltage on the switch input terminals.
5. All voltages are referenced to the circuit common.
6. Power to the switches is solely supplied by the transceiver. At no time can a switching device impress a - 25 voltage on or power to a switch input of a transceiver. All current notations indicate the positive flow from the transceiver switch terminals to the switching device.
7. Switch debouncing of more than 40 msec's should be provided to guard against multiple switch closures. The debounce period simply means that a switch reading must take place between ' ~ ' ' ' , ' :' .
.. : -. . :
, -, 10 ~33~i4S

40 and 110 msec's. It is not required to have the switch be enabled for two or more switch periods before a reading is taken.
B. During a switch reading sequence appropriate noise rejection and filtering is needed to guard against spurious signals coupled into the switch wire affecting it's reading.
To insure the reading of a DC level and not the affects of noise, appropriate low pass filtering is needed (both digital and analog).
After the debounce timeout a switch reading is taken. ~uring the switch reading protocol noise filtering can be achieved by sampling the switch closure continuously for 100 microseconds. If the switch changes state or is not stable during the switch reading interval then it is to be rejected and read again after the next debounce periodO

Special Switch Only Transceiver Function In order to improve the systems switch input processing capabilities, a special extension feature is to be provided in the switch only - transceiver products. A user selectable switch input enable mask is provided. When a switch is disabled no state change is recorded or can cause a transmission. However, when the switch input is subsequently enabled the state of the switch is to be transmitted to the controller it is in any of its known steady states~ Therefore, the enabling of a switch is equivalent to a switch state change which causes the appropriate transmission as if it were actually mechanically actuated.
Specifically:
o If in the maintained switch mode, a transmission will be made indicating the ON/OFF state of the switch after the switch input is enabled by the controller.
o If in the momentary switch mode the ` switch is enabled, a transmission is to take place if and only if the switch input is in any one of its' "make" contac~ states, i.e. on or off.
The enabling and disabling oE switch inputs adds a powerful dimension to our energy management control system. Th~y can be used in our scheduling, telephone and switch input control scenarios. For example, scheduling of night set back thermostats and improved demand control scenarios are possible.

Special Switch Transmission Feature Two forms of switch transmissions are to be provided selected by a factory installed jumper.
They are the regular and secure mode of switch transmissions.
The regular switch transmission mode is similar to the Miller '414 configuration such that a switch activation causes an open loop transmis-.

12 ~ i45i sion. If the controller is in the manual or "down"
mode this transmission will be missed and therefore not acted upon. For wall switches this is apparently not a significant problem and is probably the desired scenario. The user may simply try activating the switch again. ~owever, when connected t~ demand control equipment or special purpose devices, it is desirable to have the system catch up to these command inputs once returning to the automatic mode.
Therefore, a secure mode of switch transmission is defined whereby a transceiver would transmit a witch action at 1 second intervals until receiving a switch acknowledgement from the central controller. This will provide a secure and fully closed loop system.
Only a reset command, switch acknowledge-ment, or a power-up can abort this answer back switch protocol. This feature will again provide the most secure system while maintaining system throughout.

Power-Ue Sequence - When power is first applied, the transceiver is to enter ~ "power-up" sequence. The power-up sequence consists of an internal reset protocol plus special func~ions.
The reset protocol has the folllwing functions.
o Delay 100 mse~'s to allow power supplies and external circuits to precharge. This must be the first . ... . .. .. . . . . -, ., ~L23~

function performed after initializing I/O lines.
o Disable any relay processing action or pendin~ action (do not change the state of relays3.
o Disable switchleg activation.
o Clear any switchleg mask words.
Enable all swit~hleg input cir~uits~

o Clear any transmission requests.

- o Reset the receiver section to wait for a line free.

o Do not alter the internal memory containing the states of the relays.
Many times a power-up due to a watchdog reset will not affect the validity of the relay state work stored in its internal memory.
o Initialize the switch input section so as not to cause the transmission of the present switch states. It should be noted the action on switches are taken only when there is a change of state or condition. The switch enable mode and switch read command are the only exceptions.
In addition to the above reset_protocol the following two special functions are included durin~
a power-up sequence.
o Set an Internal Reset Bit which is used the central controller to indicate there has been a power-up . . .. . . . . ..
- ' -' ' ' : ',' ~ ' ' ' " ' ' ~ 3~ii4~

sequence. This internal bit can be read by a controller for self clearing system functions. This internal reset ` bit is cleared only after a command is 5 - received affecting either relays or switchleg functions. It can be used ~ to cause a transmission upon a command to the central controller (see the central control interface section for details~.
- o Set-up to cause a single transmission ~ indicating a power-up sequence took - place. This is random access unsolicited transmission to the central controller who could decide to take command action. Only one transmission of this message is allowed. ~he Internal Reset Bit is not to be cleared after this transmission.
Note There is a distinction between the "reset protocol'l and power-up sequence. The reset protocol although a subset of the power-up sequence can be activated by a command from the centr~l controller. When nvoked by the controller the internal reset bit is to be cleared since it is only associated with a physical reset of the microcomputer.
A power-up sequence can only be executed either by a true power-up, watchdog reset trip, or by activating the reset butt~n. A reset protocol ' ' .

.

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sequence can be executed by either a power-up sequence or on command from the central controller.

Addres~in~

The transceiver product will have a 10 bit address similar to the existing product conigurations. However, the address scheme will support the Eollowing extensions:

~ardware The hardware for the enhanced transceiver according to the present invention includes the following:
A. Data line transmitter/receiver circuit B. Watchdog reset & voltage monitoring circuit C. Jumper selection circuit D. hddress decode circuit E. Switch input module circuit The following is a list of particular objectives of the present invention:
A first object of the invention is to provide the ability to monitor binary input sensors upon command from a central Eacility over a shared or common data communications link.
Another object of the inventicn is to provide a means to selectively disable individual switch inputs so that they can be ignored and no action take place during certain conditions deined by the central facility means. When a switch input ~6 ~L~3~

t ran~mi ss ion or any act i place upon the subsequent change of state of said masked input.
Urther Object of ~he iny ti provide a novel switch threshold multiplexing ith improved input ~ilt multiplexing scheme is achieved by shifting the reShold to comparators so th multiplicity o~ switch input lines can be multi-pl~xed into a microprocessor for subseguentprocessing- This threshold shifting means as a mUltiPlexing is disting i ces PreViOusly Used in OR T
onto a common bus.
t ther ~ject o~ the inve ti he ability to ~ead a~ acc nSmitted for eac~ individ 1 monitored by the input transceiver. This accumulated state memory would not only contain the ~ two wire maintained co t also tbe last state of actuation of previously actuated three wire momentary contact~. Since a momentary contact input disappears, its ON/OF~
condition is lost unless it is remembered. The in stat ~n Provided to rememb allow it to be interrog command ~y a central controller means.
An eYen still further object of the s to provide a secure or binary input aCtuationS
Sponding device will ha acknowledged the switch actuation. This is needed eSponse due to critical i __ _ _ ~33~5 as alarms, demancl, light levels, and temperatu~e changes.
Another object of the invention is to provide or the annunciation of input module power-up or erroneous reset. This annunciation will insure the integrity of the distributed data base while enha~cing the system's diagnostics and self correction capabilities.
To accomplish these and other obje~ts, a lo separate input transceiver module was developed extending the capabilities of the Miller '414 system. The switch input or binary input transceiver module is config~red to plug into a mother board similar to that of the relay transceiver ldescribed in case LD 9147). It can be housed in a panel where there are both binary inputs and relay outputs provided. A5 in the prior art, this input transceiver connects to the low voltage twisted pair data communications link connecting all remotely located transceivers or load control processors to the central controller means. The binary input transceiver is responsible for providing a simple contact closure input port for control override commands to the c ntral controller means. Upon the actuation (change of state) of any oE the monitored binary inputs, an automatic transmission back to the controller is initiated by the transceiver. The specific improvements in this invention allow the central controller to monitor binary sensor inputs to determine appropriate control action. These binary inputs are read on command from the controller but further improv~ment was made to allow for the masking of certain ~L23~S

switches disabling them in accordance wi~h comm~nds from the central facility.
An additional feature was provided to insure the actuation in response to binary inputs.
This feature is known as the answer back or secure - mode switch transceiver which periodically transmits the actuati^on of the binary input until receiving a positive acknowledgement from the central controller means that the sensor was read. Additional diagnostic capability was provided to interrogate the last state accumulated of all momentary and maintained binary input sensors.

Brief Descri~tion of the Drawin~s FIGU~E 1 is a block diagram of the switch input module according to the present invention;
~J~
FIGURE 2 (including FIGURES ~A~ is a schematic diagram of the switch module with the data line transceiver omitted. A schematic diagram of the data line transceiver portion of the relay module can be found in the Miller '414 patent, FIGUX~ 8, incorporated by reference into this application;

- FIGURE 3 is a block diagram showing the various functional blocks of the firmware associated with the switch processor (microcomputer~ shown in FIGURE l;

19 ~3~

FIGURE 4 is a further block diagram illustrating the function of firmware associa~ed with the switch processor (microcomputer) shown in . FIGURE l;

FIGURES 5-38 are detailed flow charts illustratin~ the functiois carried ~ut by ~irmware associated with the relay processor; and APPENDIX 1 is a complete listing of the object code associated with the switch processor which carries the functions illustrated in FIGURES 3-38.

Detailed Description of the Preferred Embodiment Referring now to Figure 1 there is shown a block diagram o~ the switch module, according to the present invention.
The central controller (Reference numeral 50 shown in Fi~ure 1 of the Miller '414 patentj communicates with a plurality of transceiver decoders via bi-directional communication link. In 2C the preferred embodiment, this bi-direction communication link is constituted by a twisted pair 58 lcorrespondong to twisted pair 58 shown in Figure 1 of the Miller '414 patent). A switch processor 300, preEerably an 8049 microcomputer,,receives commands from twisted pair 58 and sends in~ormation to the twisted pair via a data line transceiver 400.
Data line transceiver 400 was shown in detail in Figure 8 of the Miller '414 patent and therefore will not be detailed in schematic form.

_ _ = _ _~ _ __ . _. . = ~ . _ _ _ _ . _ . _ , . .. . . .

2~ ~33S~

Data line transceiver 400 couples relay processor 300 to the common communication link (twisted pair 58) used to transmit serial data to ~ and from the central controller ~not shown but S corresponding to central controller'50 in the,Miller '414 patent~. Data line transceiver 400 contains both a receiver and a transmitter to facilitate bi-directional data communication. Both the transmitter and receiver are optically isolated from any ground reference thereby providing a noise immune balanced driver capable of rejecting common mode disturbances and receiving differential signals. Serial data is transmitted in a similar fashion as described in the Miller '414 patent and i~ received from the data line over the SOD line.
Transmitted, output data such as for example information related to switch contact closures is impressed onto the data line via the SID line.
Associated with processor 300 is a watchdog reset circuit 500 including a watchdog timer 500 and associated circuitry. Watchdog reset circuit 500 is responsible for causing or generating a reset pulse to processor 300 under the following conditions:
A. Power on; when power to the system is 2s first applied.
B. Low power; when the power to the system falls below a predetermined operating voltage.
C. Watchdog Time-out which,results when the processo. 300 fails to retrigger the watchdog timer 500 within a predetermined time interval. $he trigger to the watchdog timer is reset ever,y time processor 300 causes a 35~Si pulse on the watchdog out line. This line i5 AC collpled to the watchdog circuit to insure only transitions cause a reset. By forcing processor ; 5 300 to pulse its watchdog output line, it is insured that the system will - remain in a deterministic state. If for any reason processor 300 fails to reset the watchdog timer within a predetermined time interval, timer 440 will ~orce a reset on the reset line of processor 300 in an attempt to restart it. This will self correct the system to a deterministic state reducing the systems vulnerability to spurious signals. A reset pulse is generated periodically until the watchdog reset signal appears acknowledging the proper operation of processor 300. After a reset, pro essor 300 will annunciate the - occurrence on the data line.
A jumper selection matrix 600 is used to select an operating mode of a relay module. This allows a multiplicity of functions to be achieved with essentially one apparatus configuration. By the use of the jumper selection matrix 600, the apparatus can be particularly configured for a special application. The jumpers are:
Wl ~selects normal or answerback switch inputs), W2 (not applicable), W3 (not applic~bie), W4 (8 or 16 switch input select), , :

` 22 ~233~5 W5 ~communcation, new or old formatl, W5 (3 wire or 2 wire (momentary or ~aintained, respectively) switch configuration).
An address input multiplexer 700 provides for the multiplexing of address bits into processor 300. This allows the multiple use of a common set of input/output lines to processor 300.
A switch input circuit 800 couples external contact closures or switch inputs to process~r 300.
The circuit provides the necessary buffering and protection against transients that can couple on to externally routed switch cables. There are 4 banks 850 of 4 3 wire inputs that are multiplexed into the microcomputer. Each switch input (3 wire) has a red ~ON) and black (OFF) and a common wire. ~hereEore, - three (3) lines are required for each switch to read an ON/OFF contact closure into the microcomputer.
In the 2 wire configuration only the red ~ON) wire or line is utilized to determine the state of a switch contact.
A switch power supply circuit 900 provides two power outputs, the switchleg power VSL and the reference power V30. The VSL will to breakdown oxides that may form on switch contacts while providing the necessary noise immunity. The V30 supply ac~s as a reference to the switch enable input for each bank. ~hen a bank is enabled V30 is divided by 2 to provide a reference threshold voltages used to read the switch input~ When the - bank is disabled the enable lines are pulled to V30 thereby disabling the switch bank~ This enabling/
- disabling requires tha$ V30 > VSL + 1 volt.

23 ~ 3S~

There is further provided a five volt regulator 950 for supplying power to the logic circuits.
Switch processor 300 functions as a sequential logic machine that is configured by firmware to perform all the control and communication processes discussed above.
A detailed schematic diagram of the switch module ~o~n in FIGURE 2, including .3 10 FIGURES
The Watchdog circuit 500 has several functions. The first function is a power-on reset function. The second unction is a voltage monitoring function that holds the microprocessor in reset whenever the microprocessor power goes below limits. The third function is to act as a watchdog or the microprocessor~ In normal operation the microprocessor will send a string of signals through Pin 25, the Prog pin, to constantly reset an RC
combination. Should the microprocessor get hung up in an endless loop, or get "lost" in its program, the RC combination will time out and provide a series o~ reset pulses to the microprocessor, allowing the system to restart without manual intervention by the customer. The watchdog sequence starts with pulses appearing on Pin 25 of the microprocessor. This pin is under software control in the microprocessor. It is directly connected to Pin 9 of U~2 which is an inverter~ The inverter in 3~ this case is used as a buffer. This buffer drives ~-10, a 470 picofarad capacitor which in turn drives the base oE Q-10 a 2N2907. When microprocessor signal goes high causing the inverted buffered signal to go low, the base of Q-10 conducts current ~L~3~

pushin~ a pulse of current into C-7 through the collector of Q-10 and charging C-7. R-15 is ~he time constant determining resistor~ The combination - Ot R-lS and C-7 determine how often the pulses must come from the microprocessor to prevent a watchdog reset, In this case, the time constant is 100 millisecon~s. R-14 is connected across the base emitter junction of Q-10 and serves to turn off Q-10. CR-2 provides a current path to the current on C-10 when the signal from the buffer inverter is a high level going signal. The primary purpose of C-10 is to provide DC isolation of the reset signals from the microprocessor. In this type of coupling it is not the absolute level of the signal from the microprocessor that determines when a watchdog reset occurs, rather it is the period between transistions of the microprocessor signal that determins when a watchdog reset will occur. Assuming a high level voltage on C-7, R-lS, this high level voltage appears on the minus input Pin 8 of the comparator U-6. Since the minus input is at a higher voltage than the position input~ then the output of this comparator on Pin 14 will be low. This low level signal is directly connected to the minus input of comparator input Pin 10, another section of U-6, and since in this case the minus input is less than the positive input, the output of this comparator section on Pin 13 will go into the high impedance state allowing R 13 to pull up the reset line, although delayed by C-18. C-18's prime function is to provide a power-on reset. It will hold the microprocessor in reset upon the event of power-on for approximately 500 milliseconds. Should the watchdog pulses cease to occur, Q-10 will stop 2s ~-~33S9LS

charging C-7; C-7 will discharge thru R-lS and the voltage on Pin 8 will drop below the voltage on Pin 9 of the comparator, forcing Pin 14 into a high impedance ~tate,. R-12 will charge C-6 until the point that the voltage on Pin 10, the minus input of the comparator, will exceed that o Pin 11, the position input of the comparator. The comparator will then clamp low on the output Pin 13 and put the microprocessor into a reset state. It will be held in that reset state until R-12 discharges C-6. This time constant is approximately 20 milliseconds~
Thus when the microprocessor fails to give watchdog pulses, the reset line will be given a,series of 20 millisecond reset pulses. The rise time on this reset pulse will be determined by R-13 and C-l~ and will be very slow as a result. This is of no consequence to the processor which has built in reset h~steresis. R-10 and R-ll provide hysteresis in the comparator circuit for the RC time constant just as R-9 and R-13 provide the hysteresis for the oscillator function. The savings of t~o resistors was achieved by using R-7 and R-5 combination as a voltage reference. This provides the voltage reference of approximately 2.5 volts and is used in several instances. The low voltage reset circuit operates using R-20 and CR-4 as a 4.3 volt reference into the comparator U-9. This voltage reference is fed into a minus input Pin 10 and is compared to the 5 volt supply of the microprocessor on Pin 11, the positive input. When the microprocessor supply drops below 4.3 volts~ the microprocessor is held in reset through this comparator output Pin 13. The jumpers in jumper selectin matrix 600 use the ' internal pullups of the 8049 and are activated by ~6 ~L~33~S

coupling jumpers to ground. The first jumper, W-l, is called the feature jumper. The second jumper W-2 is not used. The third jumper, W-3, is the type jumper. The fourth jumper, W-4 selects the size.
The fifth jumper W-5 is the communications mode jumper. C-8 and C-9 are the start-up and harmonic filter for-the crystals Y-l.

Address Decode Circuitry of the S~itch Module Address decoder 700 decodes the address bits one at a time using a 74LS156 as a decode mechanism. The 74LS15b is used in the dual two-line to four-l;ne decoding mode. This is nècessary because it shares control lines with the switch multiplexing circuits. Pins 3 and 13 are used as the data input while Pin 15, Pin 1, and Pin 2, Pin 14 connected together are used as enable lines.
Using these three lines of control enable allows the multiplexing of control information and address information. The combination of Pin 2 and 14 can be viewed as an overall chip enable. It is active low. Pin 1 can be viewed as the enable pin for the first two-line-to-four-line converter. It is active high and enables the outputs on Pins 7 through 4.
The second two-to-four converter enable pin is Pin 15 and is active low~ In order to determine which address lines are set on the dip switch pull Pin 2 and 14 low and then choose one of the two banks of two-to-four converters. For example, one might put Pin 1 high enabling the first bank of two-to-four conversion. If then both Pins 2 and 13 were zeroes, that i~ low levels, then Pin 7 would be activated by a low on the output. If the address line zero dip 27 ~33~4~

switch is closed, the output of the LS 156 pulls the input line going to port 1, data bit 4, low. If that address line dip switch is open, the pull-up resistor connected in conjunction with this dip switch-pulls the line high and a hish 1evel signal would be read. If one now wanted to read the next address bit-location, one again pulls Pin 2 and 1 low as a chip enable, put Pin 1 high as the first bank of two-to-four selector enable while leaving Pin 15 high to disable the second bank of two-to-four conversion, set Pin 3 address 1 input low and set Pin 13 a zero input high. This wouild enable Pin 6 low on the output side which is connected through the address switch selector to port 1, data bit 4, input. Similarly, the other address lines ma.y be read when using the second two-line to four line converter. Pin 1 is put in a low state, Pin 2 and 14 are enabled and Pin 15 i5 put into a low state to enable the second bank, that i5, outputs 9 through 12. Pin 1 and 15 could not be tied to~ether and Pin 2 and 14 used as the enable lines because when 1 and 15 are tied together, one of the two decoders will always be enabled. When a relay is being pulsed, this output could inte~fere with proper pulsing of the relays.
- The 5 volt regulator consists of a 3 terminal regulator, a 78MO5, which is designatad Q-6, and its associated decoupling capacitors. Worse case power dissipation occurs with a 20~ error on the high side of the 9 volt source. The power dissip tion in a worse case current draw of 150 milliamperes is .7 watt. This would mean that without a heat sink this regulator will have a 43 de~ree C rise in temperature. This is acceptable - : .

2~ ~3~

given tha~ the ambient environment will not exceed ~0 degrees C and the rated junction operating temperature is 150 degrees C. We will safely be at 100 de~rees C worse case operating temperature.
When ~umper W-3 is inserted as a jumper on port 2, data bit 4 of the microprocessor, it indicates to the processor that it is an input type of module. In this case, input mode will be switchlegs. In a switchleg module all circuits are the same as in the relay module with the exception of the relay driver section, which is an output section. That section is transformed into an input section~
A switch is read using a compàrator which compares the switch input voltage to a 12 volt reference. If the switch input voltage is greater than 12 volts, the switch is considered in the open conne~tion. If the switch voltage is less than 12 volts, the switch is considered in the closed position. The output of the comparator is fed directly to a data bus input line. A typical input starts with a 3.9K pull-up resistor to 24 volts connected to one of the switch contacts and the other switch contact connected to ground. A switch closure then connects the two contacts. The connection of the contact with the pull-up resistor is brought through a lOK resistor to the comparator - input. In Switch Number 1, the comparator input would be Pin 6 of U-8 the negative input. This input also has a .1 microfarad capacitor connected to ground. The lOK resistor and the .1 capacitor - form a RC noise filter with a 1 millisecond time constant. Further filtering of the signal is done in software. This signal is compared to the :
.

29 ~LX33~i45 positive input terminal, Pin 7 in this case of U-8. Normally this pin is pulled up to approximately 30 volts. This makes the comparator output a high impedance state. When the microprocessor wishes to read this comparator, the microprocessor activates port l, data bit 7. This pin is connected also to a comparator, Pin 8 of U-12, the inverting input. When this comparator input is activated, low, its output goes low and the voltage on U-8, Pin 7 is cut in half through R-23.
This makes the voltage at Pin 7 of U-8 approximately 12 to 15 volts as opposed to the previous 30 volts. The microprocessor can now read the data bus port as an input and this switch #l will appear on lS D-0 Pin 12 ofthe microprocessor, which is pulled up by a 4.7K resistor. When the switch is not active the DB0 will be low. When the switch is active, that is grounded, the DB0 will then go high. T~ use the processor efficiently, eight switch inputs are read at a time. That is port l, data bit 7 en~bles eight comparators at one time. In this case, it was convenient for software processing to read eight switch inputs of the same indication, that is, ON or OFF. For example, when port l, data bit 7 isenabled, we read the "ON" input of switch 1, 2, 3,

4~ 5, 6, 7 and 8 of the low address transceiver.
When port l~ data bit 6 is enabled, we read the "OFF" switch input of switch l, 2, 3, 4~ S, 6, 7 and 8 of the lower address. The optional high order address switch inputs work in the same manner except that the "ON" switch bank select is port l, data bit 4 and the "OFF" switch bank select is port l, data bit 5.

5A~;

In the switch power supply circuit 900, a 34 volt source is fed into the daughter board.
- Noise is decoupled by C54,.01 microfarad - capacitor. Q-5 in conjunction with R-30 and CR-7 form a voltage regulator regulating the input voltage down to approximately 31 volts. This is necessary ~o protect the LM339 which have a maximum operating voltage of 36 volts. Should something happen to the power supply, and the nominal 34 volts go above specification, this regulator will protect the 339's. Furthermore, in ordinary opera~ion this regulator will reduce the stress on the ~39's increasing the MTBFc C-55, a 150 microfarad capacitor, is a filter capacitor to hold up the 30 volt lines while rel~ys are pulsing. The 30 volt supply is used for the 339 positive input and for the bank select of the comparators. The 30 volts also feeds a 24 volt 3 terminal regulator.
T~e 24 volt supply supplies the reference voltage and pull-up voltage for the switch inputs.
Each switch input is connected to this 24 volt supply via a 3.9K pull-up resistor. Worse case power dissipation in Q-4 occurs if all switch inputs were activated to some state. In this case Q-4 would dissipate approximately 1.4 watt, caused by a 200 milliamp current drain and a 7 volt differential. This would cause an 84 degree C rise in Q-4, where the allowable junction temperature in 150 degrees C.
When a switch is activated it causes a current of 6.15 milliamps to flow through its corresponding pull-up resistor. The power dissipated in this 10~ resistor is .15 watts;
maximum power allowable dissipated by a single - ' `' 31 ~233~i~5 resis~or is .2 watts in this type of sin~le inline packaged resistor network. This represents a 25%
power margin. ~owever, at the packa,ge level, the networks have been wired such that red and blacks were on and offs of same switches are connected to the same SIP. This means that at any given time only one-half of the resistors in a n~twork can be activated so that the power dissipated at a package level is less than 50% of the allowable power.
Using this type of margin insures a long life for the resistor packages. With the same li~e consideration reasons, the decoupling capacitors and filtering, capacitors are 50 volt capacitors wlth 24 volts applied. This type of derating insures long 5 life for the product.
The following table sets forth a pin-out of processor 300.
Pin Function Pin ~unction 1 N.C. 21 ADDR8

5 N.C. 25 WD5TB

6 Vcc 26 Vcc

7 GND 27 G2ADRS
N.C. 28 ADRINl 9 N.C. 29 ADRINO
10 N.C. 30 ADRSEN
11 N.C. 31 ADRINP/G20Nl 12 SLINPl 32 GlADRS/G30FFl 14 SLINP3 34 GlOFFO

16 SLINP5 3S N.C.

20 GND 40 Vcc 3~ ~33~

SLINPx 1 - MAKE, O = BREAK
MODE O ~ MOMENTARY, 1 - MAINTAIhED
FEATURE O = SECURE, 1 = NORMAL
SIZE O = ONE ADDR 1 = TWO ADDR
S COMM O = NEW 1 = NEW ~ OLD

The following table sets forth switch group selector.
ON SLINPl-SLINP8 GOONO GlOFFO G20Nl G300Fl NO SWITCHES O O O O

BREAK is a "O" or low impedance on SLINPx.
MAKE is a "1" or high impedance on SLINPx.

Referring now to FIGURES 3 and 4 there are shown block diagrams of the functions performed by the firmware associated with the switchleg processor.
The Switch Transceiver comprises the previously described hardware apparatus and several software or firmware procedures and processes described below. The block diagram of the Switch - Transceiver is depicted in FIGURES 3 and 4, and provides a functional description of each of the software process blocks. The firmware is embodied in the object code listing set forth in complete form in Appendix I.
: Referring to FIGURE 3, the sequential control unit is formed by the TIMINT (timer interrupt service routine) and the Executive (EXEC) routines. The purpose of this section is to provide the 6 msec timing si~nal and monitor the status of - ~ ,. ': ~ . ' . -.

~35~
the various other processes. It is further responsible for the task dispatching to all process functions.
The address input sequencer and address and jumper buffer holding registers described in the MODIDN process provides a means of uniquely identifying a switch transceiver, as well as configuriny the product via user or manufacturing installed jumpers to support various selectable features.
The command decoder operates upon data contained in the memory buffer area consisting of messages received from the data line receiverO The DECODE process checks the validity of the messages (through parity or checksum calculations), the proper address (ADRCHK process) and the command type. The co~mand decoder will place the proper data into the memory buffer area and status registers o~ the sequential control unit for subsequent dispatching to the proper task to perform the desired action. The decoding of a valid message results in the incrementing of a good message count register used for internal system diagnostics.
(description of RCUSRV & XMTSRV~
A receiver means (RCVSRV) similar to that described in Miller '~14 can be utilized in order to convert the incoming serial data stream into a parallel ~orm in the memory buffer area suitable for command decoding.
In addition, a transmitting means (XMTSRV) similar to that described in Miller '414 can be utilized in order to convert parallel data from the memory buffer area to the serial format of the common data line.

~33S~lL5i FIGURE 4 describes the processes associated with the sensing of binary inputs. The switchleg input sequencer (SLSRV) works in conjunctin with the switchleg 48ms timer (TIMINT) to control the reading and subsequent transmission of switch or input actuations or ~tates.
Upon command from the switchleg input sequencer the switch input buffer tREADsL) will input the proper bank of switches through a 100 microsecond digital noise filter from the multiplexins apparatus.
A comparator function compares the original switch reading register (from the previous reading) to the current input value, and places those inputs whose state have changed into a switch change registQr IGETSWT).
The switch mask processor will eliminate any non-enabled switch changes from the switch state word indicated by the switch mask register (user programmable).
The switchleg output processor (UPDSL~ will operate on the generated switch state word and place it into the memory buffer for subsequent transmission. In addition, an accumulated switch register which is user interrogata~le, is formed and contains the last state values of all switches that have been actuated.
Finally, a 1 second acknowledgement retransmission timer in conjunction with the switch acknowledgement register (from the UPDSL process) allows for a switch to be retransmitted repeatedly until it is confirmed and removed from the switch acknowledgement register. This provides for a more , ~ 33~;4~;

secure means of transmitting a switch actuation, and guarantees th~t it will be received.
FIGURES 5-38 detail in flow chart form the specific functions of the switch module.

Swi~ch Inpu-t Processin~

The purpose of the switch input processing section is to read contact closures or switchleg inputs. During this process, the switch inputs are Eiltered, interpreted and are appropriately setup ~or transmission onto the data line. This includes specifically the handling of both maintained (2 wire) and momentary (3 wire) switches and maintaining a queue of swtiches that have been activating for subsequent transmission out over the data line to be received by appropriate sensing or controlling devices.
The transmission of these switch inputs (which may or may not involve a special answer-back or secured mode transmission sequence) i5 also handled in this section. If the transceiver is in the answer-back mode, then a process is established which will keep transmitting actuated switches until an acknowledgement is received back from the controlling or sensing device indicating its - 25 reception of valid switch data. This answer-back or secured transmission process involves waiting for a period o~ approximately one second for an acknowledgement after a transmission of actuated switches were made. If after this one second interval an acknowledgement has not been received by this transceiver the switch actuation message will .:

36 ~335~

be repeated and retransmitted back over the common c~mmunication link (or the data line). It should be noted that during this subsequent transmission that if there are any new switch actuations that have occurred since the first (or previous) transmission, that these new switch actuations will be included and thereb~ queued in the switch actuation message that is transmitted over the data line.
Furthermore, when a new switch position has been activated while waiting this one second interval ~or a previous switch acknowledgement the switch information which includes the past transmission plus the new switch will be transmitted immediately upon the actuation of this new switch even if it - 15 occurred before the one second period for the acknowledgement has elapsed.
The switch acknowledge, or secured mode switch process, is a selectable feature which is invoked by a jumper inserted in the printedcircuit board during manufacture. This feature, which could have been programmable through commands over the communications linkl was implemented as hardware invokable so as to avoid any possibility of spurious signals causing the complex electronic circuits to assume this answer-back function. It was desired to provide this feature for future applications that may involve interfacing to external machine, computing devices or threshold responsive sensors to insure that no data is lost during the normal action in a centralized control system. However, other devices such as normal wall-mounted switchlegs for purposes of turning ON and OFF lighting and other load~, which are typically human actuated, are not desired to continuously transmit until an 37 ~L~33~i~5 acknowledgemen~ is received. This is to avoid taking deferred action on human actuated devices when, in fact those actions are no longer needed when the system returns to its normal operation state ater a long period of down time which may occur in a centralized control system. In summary, this answeE-back ~eature provides an extra degree of security in the response to contact closure inputs to our central control system. This security is jumper selectable so that it can be applied electively to loads which need and desire such security The processing of switch inputs is performed in the followin~ sequence: 1. switch readings are made at no less than 4B millisecond intervals; 2. during the reading of switches they are appropriately filtered; 3. the switch inputs are then interpreted by considering it to be of either the 2 or 3 wire type; 4. a determination is made as to whether the switch is indeed allowed to be active and cause transmissions to take place over the common communication link. The resultant of this process, on a valid switch actuation, causes an appropriate transmission word indicating which switch and the state (ON/OFF) that has been actuated to be transmitted on the common communication link for further control or sensing processes by other devices.
A swit~h reading period takes place at no less than every 48 milliseconds. Thîs is to avoid multiple readings of the ON/OFF state of contact closures (switches) due to excessive mechanical bounce which are typical properties of both human actuated mechanical devices and electromechanical '.-- _~ _ ~_.___ _ _~ _ __ ._ _.. _ .. _ _ _. _ ____=. _ _.. _ .. _ _ _ _ _ . = _ = _ ~. _' --== ~ ' '' --' ~_-- :~ .__~.. ~.A~.. ~ ~_ ._._ .. ~____ __ ..
,_, ., ,. _ _ _~ _, . _ __ .. _ _ . _ __ _ .__ ... .. . ..

38 ~:33~

devices. 48 milliseconds was chosen to insure that the reading or measurement interval would be greater than this bounce period to reject erroneous multiple actions. Compensating for mechanical bounce of contacts usin~ this period measurement interval method will result in a switch reading that is said to be debounced. The maximum switch interval reading is nominally 100 milliseconds. Since this was determined to faster than multiple actions on a human actuated push button switch, this will insure that no switch request is lost since the measurement in~erval will always be faster than human inputs.
After the 48 millisecond switch reading interval, switches are then read for a period of 100 microseconds sampled at a high rate. This is to utilize digital filtering techniques, rejecting switch actuations caused by spurious signals. This 100 microsecond sampling period for switch readings yields a 10 kilohertz cutoff requency low pass filter. It should be noted that in addition to the digital filtering techniques, hardware signal filtering is provided with appropriate lumped elements. This further insures the integrity and validity of any contact closure or switch inputs.
After the switch is read, a determination is made whether to process the contact closure inputs as either 2 or 3 wire devices. This determination is made by a customer selection provided on the ~ransceiver. The 2 wire switch, organized as a single-pGle, single-throw device, operates such that an ON condition is considered the make of the contacts while an OFF condition is considered the break of the contacts. The 3 wire switch conforms to the single-pole, double-throw .

39 ~L~33S~

contact arrangement. In this arrangement, an ON
condition is considered when one side of the contarts are in the make condition. An OFF
condition, or st~te, is actuated when the other side, or contact, is in the make condition. Any break actions from either contact is considered no action, or change of previous state. This would allow applications of push-button momentary switches. It should be noted that the 3 wire single-pole double-throw switch arrangement is rejected if both contacts are actuated or in the make condition simultaneously. This is to avoid erroneous assumptions of the conditions of these switches since the simultaneous make states is defined by convention as a forbidden state.
After the determination of 2 or 3 wire - gwitches, the switch actuation is compared to a predetermined switch mask which specifies the switch positions that are enabled, that is, that are allowed to be actu~ted and cause subsequent communication to occur on the common communication link. The switch mask provides the capability to define selectively which switch is enabled. This selective definition is programmed via the common communication link by external devices. The setting of this switch mask is described in the command decoder section of this description.
After a switch is read and the appropriate state is determined (that is~ whether it is ON or OFF), it is compared to its last valid state read in the previous 48 millisecond interval. If, and only if, there is a change of state (that is an ON to an : OFF or an OFF to an ON condition), an automatic transmission will take place over the communication , 1;2~3~

link to inform remotely located devices of the switch change. This will effectively broadcast the switch actuation immediately so that ~ppropriate control or sensing functions can take place. If there is a messa~ge from the previous 48 millisecond interval that is still awaiting transmission due to a busy communications link~ the new switch actuation message will be queued and added to the pending outgoing message so that it can be included for transmission in the first free communication opportunity.
In addition to establishing a message to be transmitted over the communications link, the new switchleg input states are merged into the accumulated switchleg buffer. This buffer contains the accumulated history of all switch inputs since resetting this buffer. This historical lnformation recording the last ON/OPF condition of all contact closure inputs provides the ability to maintain a record of said states even when applied momentary contact or switch devices; that is, although a momentary contact is only in a temporary make condition indicating its ON/OFF state this accumulated buffer will hold this state for subsequent interrogation by other devices over the common communication link.
The process that performs the entire switch handling function is called switchleg service and is designated as "SLSRV". The process flow for the switchleg service function is described in Figure 5.
This process is performed on-command by the ma,n process executive. Referring now to Figure S upon entering the switchleg service process a check is made to see if this transceiver has been defined to q _ '~=~. ' ~. _.` _, __. . __--__ _ _ . =_ _ __ _.. G-.=:=:.::~---.=~=~==_=_.~_ =. _~.,_ ~ .. ~__ ._ ~_.. ______ .. __ _ ___ _ ,_ . . .. ,_ , _ . ~ _ . _ , , . . . . _ 4~ 5~

have switchleg capability. If not, it aborts and returns back to the exec for further processing. If it does, the interval timers for the switchleg reading and for the retransmitting of non-acknowled~ed switch transmissions are updated. The S updatinq of these timers includes the time elapsed from the last update or service which can occur any time. Using an internal 6 millisecond timer, the switchleg reading interval timer and the acknowledge retransmission timer are updated to reflect the time lapse, if any, from this last reading. This will insure when long messages are being received over the communications link that these timers will not be unduly neglected and can thereby be updated compensating for any lag due to alternate processing activity. After updating the timers, a check is made to determine if the unit has been selected to be in the answer-back mode. If the system is in the answer-back mode, a check is made to determine if the retransmission acknowledgement timer has timed out. I it has, a further check is made to see if there is still a message that needs to be transmitted over the common communication link. If there is, that message i5 moved to the appropriate output buffer for subsequent transmission and the acknowled~e retransmission timer i5 reset followed ~by a return to the system executive. It should be noted that this acknowledge retransmission timer is set to cause a retransmission of switch actuation at one second intervals if they have not been acknowledged. This will insure the integrity of the actuated switch inputs by proividing a hand shake with the external receiving device. If the system is not in an answer-back mode, or if it is in an 42 ~ ~33~

answer-back mode and the one second timer has not timed out, a check is made to see if the debounce interval timer has timed out. If it h~s not, urther processing is aborted and the system returns back to the system exec. If this timer has timed out, the system assumes it's now time to read switches f~r further processing. It should be noted that this timer is set for a minimum interval of 48 milliseconds to compensate for the worst case of mechanical bounce that may be associated with devices connected to the contact closure or switch inputs.
The system cont nues by reading the switch inputs by transferring control to a process titled "READSL". Continuing, after reading the switch inputs, a process called "GETSWT" takes control which is responsible or processing switch inputs and sets up any messages that are needed to be transmitted over the data line in response to switch actuations. After processing the switch inputs and determininy its type, various modes and effects of any switchleg mask that might have been defined, the system resets the debounce interval timer to set`up for the next switch reading and returns back to the system exec.
The reading of the switch inputs is handled by the process called "R~ADSL". The read switchleg process reads 4 groups of 8 switch lines each at a timeq These 4 banks are multiplexed in order to make use of an 8 bit bus structure. Each group is read and processed separately. The read switchleg proce~s results in an accurate reading of the state of the contact closures in each of the 4 groups stored in appropriate registers along with a 43 ~2~3S~;

register indicating whether noise was discovered in any of those switch poqitions.
Referring now to Figure 6. When entering the read switchleg process, the switch input apparatus, which contains the multiplexing hardware, is initialized along with the resetting of the switch noise indication registers and a register pointing to the first group.
- It should be noted that two out of four groups are associated together within a bank, and that there are two banks. Bank 0 is associated with groups 0 and l~ and Bank l is associated with groups 2 and 3. The association of two groups to a bank provides for the reading of 3 wire switches with their ON and OFF contact arrangement. Furthermore, the two banks, 0 and l, correspond to the multiple addresses allowed for the switch transceiver.
Although, as previously described, the switch input block is in a logical 8 position group, two blocks have been defined in one device allowing it to respond to two separate address locations for the purposes of communicating over the common communication link. In other words, due to the method in which switches are handled by 8 switch input ~roups, a 16 switch input module was achieved by having it respond to two independent addressesO
It should be further noted that this 8 position switch group was arbitrary and is, in fact, independent of this design.
After the initialization of registers and the apparatus, a group is now enabled for input (initially group 0). The 8 switch positions are now read and are taken as the first reading and saved as the actual switch state. After the first reading, 4~ 335~S

the group is now sampled again and a check is made to see ir i~ difered from the first reading. If it did, an indication of the bit position corresponding to the changed switch will be 5et and saved in a ; 5 noise register for later processing. This process of reading ~ group, comparing it with the first reading, and building a noise register based on any differences in the first reading and subsequent readings continues for a period of 100 microseconds. This 100 microsecond sampling loop, as indicated in Figure 6, provides the digita1 filtering needed to reject any high frequency noise. After this.100 microsecond group read loop has completed, the process continues by updating the group pointer to the next group (that is, the pointer will now point to group 1 if it previously pointed to group 0) in order to read the next 8 switch input or contacts. A check is made to see if there are any more groups to read. If so, the system loops back and enables the group for input and repeats the filtering process for the next group as indicated ;n the figure. After all the groups are read in, the actual switch state from all the groups (which represent the first reading) are stored in appropriate switch state registers and the noise registers are set as a result of subsequent readings being different from the first, the system exits back to the supervisory process~
The actual processing of the switchleg inputs and recognition of valid switch changes is perf~rmed by the process called "GETSWT". This GETS~T process is depicted in Figure 7. Upon entering the process, it assumes that switch information has been read.in and stored in the 45 ~335~S

actual switch state register and noise register as describèd above. The output of this GETSWT process will result in the transmitter output buffer being loaded with a valid switch change word (indicating secured switches or one of the two formats for standard switches) for subsequent transmission over the common communication link, if it has determined that, in fact, a switch change took place references to the previous valid switch reading.
Referring now to Figure 7, the first group of the Bank is processed by the "CHGBIT" process of Figure 9. Thi~ process takes the noise register, the previous valid switch or reading tor original switch register) and the new actual switch state reading and creates a register of valid switch changes indicating which switch positions actually changed and a register indicating the ON/OFF state of those switches with respect to the ~roup being processed. A make is defined as an ON or a logic 1 and a break is defined as a logic 0 or OFF. It should be further noted that in a 3 wire configuration this process is repeated for the other group and later further processed to determine the ON/O~F state based on make/make switch action.
After this switch is preprocessed, as was described above for the "CHG~IT" process routine, the system continues by checking if the switch - inputs are configured as 2 wire or 3 wire. For 2 wire inputst a state change word for the ON
condition is determined. This word is taken from the ON/OFF state word returned from the "CHG~IT"
process whieh is then masked with the switch enable mask to eliminate disabled ON switches. The result of this operation is then saved in the valid ON

. _= . ==, . ~ = , .
- .

q6 ~L~33~i45 change register. The above three steps are repeated for the OFF condition. This time the OFF state is determined from the inverted ON/OFF state word return from "CHGBIT" and the disabled OFF switches are masked out with the ersults saved in a valid OFF
change register. The process then creates an effected switch word by ORing the valid ON change register with the valid OFF change register established above. This will yield an effected switch regis~er such that a logic 1 represents an effected switch that had changed from the previous valid state and the logic 0 would indicate no change. Furthermore, the ON/OFF state word is defined to equal the valid ON change register, such that a logic level 1 is equal to the ON condition and 0 to the OFF. It should be noted, howevers that the respective bit positions startin~ from bit position 0 to bit position 7 in both the effected switch word and state word correspond to switch numbers 1 through 8 respectively~
Referring back to Figure 7 for the 3 wire switch configuration a state change word for the ON
condition is similarly determined and masked with the disabled ON switches which is then saved as the valid ON change register. However, the process then calls the "CHGBIT" process (Figure 9) for the second group in order to process the OFF state condition.
Similarly, as witll the ON, a valid OFF change register is formed by masking out the disabled OFF
switch positions. After this step, the process merges both the ON and O~F valid change registers togehter, eliminates simultaneous ON/OFF positions in those registers, and forms the effected switch registers which is then saved. The ONjoFF state ~7 ~ S ~ ~

word is further formed by ANDing the previous valid ON change register and the effective switch register to yield an ON/OFY state word suitable for transmission. After either the 2 wire or 3 wire configuration creates the effected switch word and appropriate state word, a check is made to see if there are any switches that have been affected or changed as indicated by Figure 8. If there is not, the process aborts and returns back to the calling supervisor. If there is a change called for, the process updates and builds a queue and resolves the accumula~ed switch buffer tperformed by the pr`ocess called "UPDSL"). ~he proper transmit flag word is selected to indicate secured switches or one of the two formats for non-secured switches. Finally, the process then takes these valid switch chanse messages and establishses the appropriate transmit buffer through the utility called "BLDTBF" which readies the information for subsequent transmission onto the common communication link. After this, the process is complete and control returns back to the requesting supervisor.
The procedure Get Switch, "GETSWT", described above invokes another procedure called Change Bit, "CHGBIT". The purpose of Change Bit is to combine the switch state and noise registers generated by the "READSL" procedure with the original reading of the switchlegs taken during the previous debounce interval. This process will result in the change register having a "1" value set into a position corresponding to a switchleg that has changed state and a bit set within the new state register which indicates the new state of the switchleg (a 1 is a make or ON condition while a 0 48 ~33S4S;

is a break or OFF condition). In addition, the previous original reading is replaced by an updated value reflecting the integration of the switch ~tate and noise registers with the oriqinal switch register.
Referring to ~iyure 9, describing the Changing ~it, "CHGBIT", routine, the process beings by logically ANDing the original group reading with the noise register to form the bit~ to keep of the 1~ original switch register. Next the noise register - is inverted and then logically ANDed with the switch register. This forms the bits to keep of the switch register. The bits to keep of the original switch reqister are logically ORed together with the bits to keep of the switch register resulting in the new switch register. The process continues by forming the Change Bit register which is equal to the exclusive OR of the new switch register with the original switch register. The Change Bit register will contain a "1" in each position corresponding to a switchleg changed its state. A O value will - indicate no change of state from the original reading. At this point, the original switch - register is updated and set equal to the new switch register completing the process which then exists to the calling supervisor.
The update switchleg routine "UPDSL"I whose use was described above for the "GETSWT" routine, is responsible for the building the transmit switch mask and state register as well as merging the new switchleg information into the accumulated switch regis~er. It should be noted that the accumulated switch register contains a history of all switchleg actions transmitted over the common data line and is C ! ~

.

5~

constantly updated with more recent actions. I~
should be further noted that the update switchleg routine will also com~ine the new switchleg actions with any recent actions that are pending transmis~lon due to a busy common data line. In addition, the update switchleg routine will combine the new sw~tch actions with any secured switches that have not been previously acknowledged. Figure 10 indi~ates that on entry to the UPDSL process a test is made to determine if the transceiver is an answer-back type. If so, then any sQ~ured switches pending transmission and the new switch information are combined by the "MERGE" routine. This merginy will also occur even if the transceiver is not an answer-back type; if there is switch data pending transmission in the output buffer. If no data is pending, then the new data replaces the old.
Continuing with Figure 10, the new switch information is then combined with~the historical information of, and saved as, the accumulated switch register; completing the process.
The merge routine, "MERGE" is a process used by the "UPDSL" routine to combine existin~
switchleg information in the form of a mask and state register with new switchleg information. This - process is carried out in such a manner as to keep ~ny uneffected old information and replace any old information that has been changed~
Referring to Figure 11, the ~rocess of flow for the "MERGE" routine, an updated switch mask is formed by logically Orin~ the old mask with the new mask. This new updated mask is then saved in the appropriate register. The bits to keep o~ the old state is formed by logically ANDing the old state .
.

50 ~3354~;

register with the logical complement of the new switch mask register. Continuing with the flow description~ an updated state register is then formed by logically ORing the bits to keep of the old state register with the new state register.
ThiS updated state is then saved in the appropriate register completing the process which then exits to the calling supervisor.
$his concludes the description of the switchleg handler which prodvides: 1. A means of inputting sixteen 2-wire or 3-wire switch contact closures over a multiplexed data bus; 2. A means of high frequency noise filtering for the contact closures; 3. A means of avoiding multiple actions lS due to mechanical bouncing of contact closures;
4. A means of processing these contact closures and generating effected switch mask and switch state information for subsequent transmission on the common data line: 5. A means for restricting undesired switch actions from transmission over the common data line; 6. A means of queuing a plurality of switch actions for transmission over the common data line; 7. A means of providing multiple transmissions of the same switch action to allow an asnwer-back acknowledgement of that switch action;

8. A means of queuing a plurality of new switch actions with previous switch actions that have yet to be acknowledged; 9. A means of providing an accumulated switch register which will contain the latest switch actions for all contact closure that have occurred (since the time that the accumulated switch register was last reset); l0. A means of formating the information for transmission in such a manner as to distinguish an answer-back switch _ _ _ ~, ~ = ~ = = . _ . = .. .. .. ,, _ .. . _ _ _ .... . _ .. . . . .. . . . .

~3~5~5 action from a normal switch action; 11. A means of transmittins normal switch actions in two different formats.

Decoder ~andler The purpose of the decoder handler is to monitor the receiver buffer and determine when a valid message has been received for decoding. When it is determined that a message is awaiting decoding, the message is verified for correctness of format, proper address and the proper check or parity ~ord at the end of the message. `Once the validity of ~he message has been determined, the decoder will recognize various commands for the device in question. The desired actions are then performed which might includes the manipulation of internal data buffers and possible transmission of a reply message to the controlling device via the common data line.
The Decoder Handler includes three main routines: the DECODE routine, responsible for decoding the flag portion of the messages as well as performing other supervisory tasks; the Address Check routine, ADRCHK, responsible for verifying the proper address and checksum or parity word; and the Transmission routine, SENDIT, which is responsible for the transmission of data re~uiring immediate or interac~ive t~ansmission.
The Decode, DECODE, routine is invoked by - the executive and is described in Figure 12.
Beginning with the entry point~ a test is made of the RVSTAT register to determine if the RCVFLG is 52 ~`233~5 set indicating the presence of a message in the receiver buffer. If not, then con~rol continues to ronnector B or DECODE2 with is an abort from the Decode utility that will clear the RCVFLG bank S indicators and new/old mode bits from RVSTAT and then return to the executive. If it is determined that there-is a message to be decoded in the Receiver Buffer, then the utility ADRCHK is invoked : in order to check the address and parity or checksum word of the message and build the flag, DF0 and DFl storage register as required. At Connector A, DECOD0, a test is performed on the RVSTAT register to determine if there is a message waiting decoding for either bank 0 or bank l. If not, then the ~5 routine aborts through Connector 8. Otherwise, the proper bank, either 0 or l, i5 indicated (by setting or resetting~F0). A test i~ then made to determine if the message is in a new format. If so, the ~ontrol continues at Connector D of Figure 13.
Otherwise, the process completes at connector B.
Figure 13 describes the decoding used for new type commands. Beginning with Connector D, the received flag is shifted two positions to the right in order to skip over the FAFB bits. A test is then performed to determine if the adjusted flag is equal to a value of 0. ~f so, then a reset command has been issued and the procedure continues with the reset process as shown in FI~URE 33. Otherwise, a test is made to determine if flag is equal to l indicating a desire to read data with an immediate or interactive transmission (continuing at Connector N of Figure l~). If the flag is equal to a value of 2, then a command requiring data to be read and transmitted in a deferred method is indicated and .

53 ~233S~

control continues at Connector 0 of Figure 14. A
~lag value of "5" will perform the set swi~ch mas~
process at connector ZZ on Figure 21. A flag value of "18" will perform the acknowledge answerback (secure) switch process at connector Z (Figure 20). If it is not possible to decode a new type flag, ~hen ~he procedure aborts connector B of Figure 12.
At connector F of Figure 15 the good message counter is incremented to indicate the decoding of a proper command and the bank indicator corresponding to the command just decoded is cleared in RVSTAT. Control then con~inues at Connector A of Figure 12 in order to process any information for the other bank.
The read status in new format command is described in Figure 16 at Connector Q. The TEMP1 re~ister is set equal to the A9JUMP value containin~
address bit A8 and the jumper definition for the TRD. TEMPl is equal to the STATUS register of the TRD. The flag register is then set to a value of 4CH anda pointer to TEMP0 is established.
Continuing at Connector L, an indication is made that two bytes of data are to be transmitted and the process continues at Connector M.
Connector R describes the read threshold in new format process. The IBGTHR register is pointed to and the flag is set equal to a value of 50/H.
Continuing through Connector U, four bytes of data are indicated to be sent. At Connector M, the previously determined line free requirement and the number of bytes to send are merged together. The process continues with the SENDIT routine described in Figure 24.

' 54 ~233S~

Connector ~ of Figure 14 is entered whenever there is an immediate or interactive request for data. A collision line free requirement is indicated and control continues at Connector P
(FIGURE 17). Connector O is entered whenever there is a deferred request ~or data and a deferred line free requirement is indicated with control continuing at Connector P.
Connector P of FIGURE 17 describes the decoding performed on the auxiliary fla~s for the read data request. Data Field DF~ is pointed to and a test is made of the auxiliary flag in that position to determine if it's equal to 0. If so, then a request for system status is indicated and control continues at Connector Q of Pigure 16, If 18 the auxiliary flag is equal to l, then receiver thresholds are being requested and control continues at Connector R of Pigure lS. An auxiliary flag value of 2 indicates a desire to return the data line counters ~good or bad message counts) and control continues at Connector ~ of Figure 18. An auxiliary flag value of 3 indicates a request for ROM code version handled at Connector V of Figure 18. An auxiliary flag value of "5" will perform the return switch mask function at connector W of ~igure l9. An auxiliary flag value of "6" will perform the return actual switch contact state function at connector X of Figure 19. An auxiliary flag value of "7" will perform the return accumulated switch buffer function at connector Y of Figure 20.
- 30 Figure 18, Connector T describes the process for returninq the data line counters. The GODMSG register is pointed to and the flag is set to . ' .

33S~

a value of 58H with control continuing a~ Connector U of Figure 16.
The return ROM code version request is handled at Connector V. A pointer to TEMP0 is established and T~MP0 is then set equal to the ROM
code version number. One byte of data to be sent is indicated, and the flag is set to a value o 5CH.
Control continues at Connector M of Figure 16.
Figure 19 lists the actions necessary to return a switchleg mask RSLMSK at Connector W. The red switchleg mask for the proper bank is selected and the TEMP0 register is set equal ~o that value.
Next the black switchleg mask for the projer bank is selected and TEMPl 5 set equal to that value.
Finally, TEMP0 is pointed to and the flag is set to the value of 30H. Control continuesd at Connector L
of Figure 16.
Connector X (Figure 19~ is invoked in order to return the actual switch contacts RSLCON. The original reading for the red swit&hlegs is pointed to and TEMP0 is set equal to that value. Next, the original reading for the black switchlegs is pointed to and TEMPl is set equal to that value. ~inally, a pointer to TEMP0 is established, the flag is set equal to a value of 34H, and control continues at Connector L of ~igure 16.
The return accumulated switch buffers RACUSL procedure is described at Connector Y of Figure 20. The accumulated switch register for the proper bank is pointed to and the flag is set equal to a value o~ 3C~ with control continuing at Connector L of Figure 16.
A command to acknowledge a secured switchles transmission is handled at Connector Z of . . - .
' ' .

5~ 3~

FIGURE 20 (ACKSLM). The acknowledgement message contained in data ield 0 is pointed to and the proper transmit mask corresponding to the de~ired bank is pointed to. Data field 0 is then inverted and ANDed with the transmit mask in order to clear the desired positions. This updated transmit mask is then saved. The updated mask is then ANDed with the transmit switch states in order to clear the desired states. This updated transmit switch states is then saved and the process continues at Connector F of Figure 15.
The set switchleg mask procedure is described in Figure 21 beginning with the Connector ZZ. This process is invoked whenever à change to - the current switchleg mask is desired and is responsible for updating the switchleg mask and generating any resultant switchleg transmission that might be caused by a disabled to enabled transition of a switchleg mask. The STATUS register for the TRD is cleared and a pointer to the proper red switch mask for the desired bank is established.
The new mask contained in data field 0 of the receiver buffer is exclusively ORed with the oriyinal switch mask in order to form a change value. This change value is then ANDed with the new mask in order to yield those 0 to 1 ~disabled to enabled) changes for the red or ON switch contacts. Next, the original red switch mask is set equal to the new red switch mask contained in data field 0 of the receiver buffer. The black switch mask for the desired bank is then pointed to. The new mask contained in data field 1 of the receiver buffer is then exclusively ORed with the original switch mask in order to form the change information.

s7 ~.~335;~S

This information is then ANDed with the new mask in order to yield those 0 to 1 (disabled to enabled) changes for black. The original black switchleg mask is then set equal to the new black switchleg mask value contained in the receiver buffer and a pointer to the original red switch reading Eor the proper bank is established. By ANDing the original red switch reading with the red 0 to 1 changes the ON part of the transmit switch mask is determined.
For momentary type switches control continues at Connector ZB o~ Figure 23. Otherwise, for maintained switches control continues at Connector - ZA of Figure 22.
For maintained type switches, at Figure 22 Connector ZA, the set switchleg ~ask process continues by restoring the original red switch reading. This reading is them complemented in order to have "1" values in O~F positions. This complemented value is then ANDed with the black 0 to 1 changes in order to yield the OFF portion of the transmit switch mask. The new transmit switch mask is then defined to be equal to the ON part ORed with the OFP part of the transmit switch mask with control continuiny at Connector ZC (Figure 22). The new transmit switch state is defined to be equal to the new transmit switch mask ANDed with the original red readin~. The new transmit mask is then restored and a test is performed to determine if anything is available for transmission. (If the t~ansmit mask equals to 0 then nothing is available for transmission.) If nothing is available, then the procedure continues at Connector F of Figure 15.
Otherwise, the original transmit switch mask and states are updated with the new values and the 5~ ~33S91~ -output buffer is formed with the required informa-tion for new or old and normal or secured type transmissions by the GETSWl procedure described : above. Upon completion of this, the proces~
continues at Connector F of Figure 15.
The required handling for momentary switches is described at Connector ZB of Figure 23.
The original black switchle~ readin~ is pointed to and then ANDed togPther with the black 0 to 1 changes in order to yield the OFF portion of the transmit switch mask. Any duplicate "Make"
conditions are then located by ANDing the OFF and ON
parts of the transmit switch mask (any duplicate switch closure will show as a "1" after this process). The resultant value is then complemented so that there will be "1" values in any valid positionsO The complemented value is then saved.
The complete mask is formed by ORing together the OFF and ON part and then duplicate makes are eliminated by ANDing the duplicate mask with the complemented mask. The result is saved as the new transmit switch mask and control continues at Connector ZC of Figure 22.
The SENDIT routine described in Figure 24 is responsible for placing data required for transmission into the output buffers and then determining if immediate transmission requirements are needed. If SENDIT performs the actual transmission of a message in an interactive data transmission then it will test the line free requirements in order to clear out previously established receiver thresholds iE the line goes free upon succe~sful transmission of the data~

_-- -~:r~_, ~:_~__ i _~_,__.__.. ~__,____~_.. __ _ .__ ___ ._ ., _ _ _ .. _ .. , . ,~ _._ . . ~ . _ 5~ 3~35~1S

SENDIT places the data being pointed to into the proper output buffer using the flag, line Eree request, and number of bytes to send by invoking the BLDTBF routine. A test is then perfo~m~d in order to determine if a deferred line free requirement is needed. If so, then the process CLRBNK is invbked~ which is described in Figure 15 at Connector F. Otherwise, if an immediate transmission is required, then a test is performed in order to determine if both banks are being requested. If so, then the immediate transmission of the first bank is postponed and the process continues with the CLRBNK routine. If only one bank of information is to be transmitted, then the line low timeout i5 set equal to the maximum in~erblock ga~ time and the line high timer is set to the minimum. The BITIMP routine is then invoked in order to wait for the final IBG of the interactive transmission message to complete; at which point the transmit process (similar to that disclosed in Miller '414) is invoked in order to transmit out the required data. If at any time during the transmi~sion a collision is detected, then the process will continue as indicated on the diagram.
Otherwise, a delay will be invoked in order to allow the line to go from its low impedance s~ate (from the final IBG) to the high impedance state (50 microseconds). The line high timeout is then set - equal to the line free threshold value and the process BITIN4 is invoked in order to determine if the line is active. If the line does not ~o active~
then RVSTAT is cleared indicating a line free condition and the process continues as indicated.
If -the line did go active then the controlling .

- ' - ' .~ ' " - .
. - - .
.
- .

~ ~,3 ~ ~ ~ 5 device has reestablished control of the data line.
Therefoxe, the receiver thresholds are not be cleared. The good message counter is incremented and the process continues at the DECOD2, Figure 12 Connector B.
The address check routine ADRCHK is described in Figure 25. It is responsible for verifying that a message in the receiver buffer is, in fac~, addressed to the proper transceiver decoder. In addition, it will verify the correctness of the message by pexforming a nibble parity check or checksum verification of the message~ If both the address and check portions of the message are correct, then three registers will be set to the proper values for the flag, data field 0, and da~a field 1.
The description of ADRCHK begins with Figure 25. The proper receiver buffer is pointed to for the desired bank along with the A8JUMP
register. ~he head of the buffer is fetched in order to get the flag. A test is then performed to determine if this is a possible new mode message by examining the FA bit (or bit D~1) of the flag to see if it is set. If so, then control continues at Connector G of Figure 27. Otherwise, address bit A8 of the transceiver decoder is compared with that received. I there is not an A8 match, then continuing the Connector A, the RCYPLG bank and mode indication are cleared from RVSTAT and the address check routine returns. Otherwise, if there is an address A8 match, then a further test is performed to determine if it is a two address TRD. If 50, then control continues at Connector E of Figure 26.
If the transceiver decoder is a single address 6~ 3;~5 device, then the address ~ield is pointed to ~nd compared with the TRD ~DRLO~ regis~er by the A~RCHD
procedure. If there is not a low address match, then the process aborts through Connector A
(Figure ~5). Otherwise, continuing through Connector B ~Figure 25), an old mode bank 0 message is indicate~. At Connector C (Figure 25), the parity word in the receiver buffer is pointed to and saved for later comparison. Next a nibble parity check is performed by the PARITY routine and a test is performed to determine if the receiv~d and calculated parity agree. If not, then ADRCHD aborts and clears the receiver flag RCVFLG at at Connector A (Figure ~5). Otherwise, the process continues at Connector D of ~i~ure 26.
Continuing with the description of the ADRCHK process at Conn~ctor D of Figure 26, the valid flag from the receiver buffer is saved and data field 0 in the buffer is pointed to along with DF0 storage by the ADRCHC procedure~ At Connector F
(~igure 26), the copy routine is invoked in order to copy the received data (0, 1 or 2 bytes) from the recei~er buffer to the DF0 and DFl storage registers as required. The desired mode bits and bank bits - 25 are then set within RVSTAT, which completes the process.
Connector E ~Figure 26) is entered whenever an old mode two address TRD is to be verified. The process ADRC~D is invoked in order to point to the address ield in the buffer and compare this with the TRD ADRLOW. Data bits DB0 of the result is then masked out. tThis least significant bit determines the bank that the message was intended for in a two address TRD. DB0 equals to 0 corresponds to bank 0 62 ~:3~

and DBQ equals to 1 corresponds to bank 1.) If there is no address match then the process aborts at Connector A of Figure 25. Otherwise, the old mode type message for hank 1 is indicated. A test is then performed to determine if the message in fact was to bank 1 by testing at DB0 of the received address field. If it was to bank 1, then the process continues at Connector C of Figure 25.
Otherwise, the process continues at Connector B of Figure 25.
Connector G of Figure 27 is entered whenever there is a possible new mode message. A
test i5 performed on Bit FB (DB0 of the flag word~
to determine if it i5 a 1. If so, then new mode addressing is not being used and the process aborts via Connector A of Figure 25. Otherwise, a test is performed of the universal address bit U within the high address word. If U is equal to 1, then the process continues at Connector I of Figure 29.
Otherwise, universal addressing is not being used.
The high address word is fetched from the buffer and it is compared with address bit AB of the TRD. If there is not a match, then the process aborts at Connector A (Figure 25). Otherwise, the low address field is pointed to in the buffer and compared to the ADRLO~ storage register by the routine ADRCHD.
A test is then performed to determine if the transceiver is a single address type. If so, then a test is made to determine if the low address 3Q received and that contained in the ADRLOW register compare. If not, the process aborts at Connector A. Otherwise, it continues as indicated on the diagram. If the device was a two address TRD, then Bit DB0 of the result of the comparison of ADRLOW

~3 and the received low address field is masked off.
If the remaining address bits do not compare then the process aborts at Connectox A. Otherwise, a new mode message ~or bank l is indicated and a test is performed on address bit A0 to see it it's set to 0 indicating a bank 0 message. If so, then the indication is changed to a new mode bank 0 message. Otherwise, it is left as a new mode bank l message and control continues at Connector H of Figure 28.
Continuing with the description of the new mode address checking at Connector H of Figure 28, the head of the receiver bu~fer is pointed to.
Following this 7 the number of bytes received is calculated by taking the l's complement of the sum of the byte counter register plus the l's complement of 7. The n~mber of data fields received is calculated by subtracting 4 from the total number of bytes received. Next the checksum register is initialized to a value of 80H. A byte from the receiver buffer is then summed into the checksum register and the pointer to the receiver buffer is incremented to the next byteO The number of bytes received is decremented and a test is made to determine if there are any additional bytes to sum into the checksum. If so, then the process of summing the bytes incrmented the pointer,and decrementing the byte count continues until all bytes have been summed into the checksum. When all bytes have been checked, then a test is made to determine if the final checksum value is equal to 0.
If not, then the process aborts at Connector A of Figure 25. Otherwise, the head of the buffer is saved as a valid flag, the low address field is - ' ' ~ -' -:' ' ' , . 64 1~33~5 pointed to and data field storage register is pointed to by the process ADRCHC. Data f;eld 0 is then pointed to in the receiver buffer by incrementing the buffer pointer and control continues at Connector F o~ Figure 26.
Whenever it is determined that universal addressing-is being used within a new mode, Connector I of Figure 29 is entered. A test is performed in order to dete~mine if all bits other than the U (or D~7~ bit of the high address field is equal to 0. If so, then a ~amily universal address is being used and control continues at Connector K
of Figure 30. Otherwise~ a test is made of the high address field to:determine if all of the bits are equal to 1. If not, and an improper address has been received then the routine aborts at Connector A
of Fi~ure 2~. Otherwise, the low address field is pointed to and a further test is performed to insure that it also is equal to all l's. I not, the process aborts. Otherwise, it continues at Connector J ~Figure 29). A new mode transmission for bank 0 is indicated and a test is performed to determin~ if the device is a single address TRD. If so, then control continues at Connector H of Figure 28. Otherwise, the indicator is updated to reflect a new mode transmission for both banks 0 and 1. (A
universally addressed message transmitted to a two bank TRD will result in actions being performed on both banks of that transceiver decoder).
FI~URE 30, connector R, describes the tests required to determine if a family address to a - switch transceiver decoder ITRD) is being used. The low address field is pointed to and checked to see if it is equal to "1". If so, then the process ~. . .

65 ~33~

continues at connector J of FIGURE 29. Otherwise it continues at connector A of FIGURE 2~.
Figure 31 describes the two subroutines required by the ADRCHK process. ADRCHC points to the head of the receiver buffer, gets the receive flag word, masks out the two least significant bits FAFB and sa-ves the result as the flag. Next~ ~RO
storage register is pointed to. Finally a value of 2 is added to the receiver buffer pointer such that i will point to data field 0 if an old type message or the low address field if it is a new type message. This completes the subroutine which then returns. ADRCHD is used in order to point to the ADRLOW storage register of the transceiver decoder, point to the low address field by in~rementing the receiver bu~fer pointer and to compare the low address in the buffer with the ADRLOW storage register. This completes the routine which then returns to the invoking procedure.
20 . This completes the description of the Decoder Handler Module ~hich provides a means of - verifying the addres of a message received; a means of distinguishing between one of two banks for a messa~e received; a means of recognizing two formats of messages (old and new); a means of aborting the decode of a message if an invalid format is used; a means of decoding multiple flag words; a means of eliminating the response to old format commands by evaluating the presence or absence of a COMM jumper which can be Manufacturing installed; a means of allowinq multiple number of data bytes to be input from the common data line; a means for decoding auxiliary flag commands for various types of devices which may or may not be jumper selectable; a means 66 12~33Si'~5i or indicating i~mediate or deferred response to requests for data transmission; a means of passing control of the data line from one device to the transceiver decoder in an immediate mode of transmission; a means of determining if the controlling device desires to regain control of the data line upon completion of an immediate transmission of data from the transceiver decoder; a means of deferring an immediate request for data if that request is to both banks simultaneously (as would be the case if a universal address command was used); a means for perorming a modified checksum against the received message with an initial value of 80H in order to avoid the proper decoding of a message with all 0 or all 1 values (homogenolls message) a means of performing a nlbble parity check as required for the old format message; a means for providing the proper setup of the switchleg mask buffer; a means of generating a switchleg actuation ~0 message if the enabling of a previously disabled switchleg results in the detection of a switch contact closure; a means of reading the following TRD data registers: the switchleg mask register, the accumulated switchleg buffer, the actual switchleg contact closures, the transceiver status, the receiver threshold register, the data line counter register, and the ROM code version; a means of counting the number of properly decoded messages by incrementing a good message counter; a means of automatically clearing the status register of the transceiver decoder upon reception of a command to reestablish the switchleg mask; and a mean~ of allowing the acknowledgement o~ secure or answer-back type switches.
.

~, ~:33~i4S

Powerup Executive and ~iscellaneou~ Module~

Switchleg processor 300, on Powerup, begins to execute its internal ROM memory code beginning with Address 0 (which corresponds to the PWRUP
- 5 routine). The powerup routine is responsible or ` proper initialization of the microprocessor and - associated external hardware and for placing a powerup-reset message into the transmitter output buffer for subsequent transmission over the common data line.
The powerup routine for the switchleg transceiver decoder is described in Figure 32. The external interrupts are disabled since none exist for the switch transceiver decoder and the stack and registers are reset. Following this the watchdog is strobed with 50 watchdog pulses and the RESET
procedure i5 invoked in order to initialize the I/O
internal registers and identify the module. A
powerup reset is indicated in the TRD status and a 25 second delay is invoked in order to allow the system to reach equilibrium. Following this, the powerup status message is placed into the output buffer. A flag value of 4CH is used.
Figure 33 indicates the reset process used by the switch transceiver decoder. This process in addition to other tasks will input the current switchleg reading and place it into the data structures in such a manner as to avoid transmission of any switch closure that might be in a "Make"
position on entry to the reset procedure. On entry to the RESET routine, the address multiplexer and - :

.

S8 ~ 33S~S

switch strobes are disabled along with the jumper input. All internal RAM is then cleared to ~ O
value. ~ODIDN is invoked in order to establish the address of the transceiver decoder (ADRLOW and ~8JUMP) along with the flas indicating the number of the address to which the TRD will respond. The process continues as indicated in the figure. Bank O switchleg mask is set to all l's in order to enable all switchlegs (this is done for both the black and red switch mask). A test is then made to det~rmine if-the device is a single address TRD. If not, then the Bank l switch masks will be enabled in a similar fashion. READSL is then invoked in order to read the current switch contact positions. The original switch readings are set e~ual to the new switch readings obtained by the READSL routine. Following this, RVSTAT is set equal to a line free error condition in order to require resynchronism of the receiver. Timer O is initialized and started (this is the 48 millisecond switch reading timer) followed by Timer l (this is the answerback or secured switch retransmission timer), completing the reset procedure which then returns to the supervisory function.
The executive is the main working procedure of the transceiver decoder. It is entered upon completion o the powerup procedure. Once the executive has been invoked, the only exit from the endless loop of the executive is via a reset (which would occur on powerup). However, it is possible for the activity controlled by the executive to be suspended for a brief interval of time in order to service the internal timer interrupt. It should be 69 :~2335~;

- noted that the internal timer is set for a 6 millisecond internval and is always active.
~ i~ure 34 describes the EXEC executive routine used by the relay transceiver. The stack is reset and the working set of registers selected.
Following this, the watchdog timer is recharged by issuing 10 ~trobes to the appropriate hardware. At this point, a receiver service is performed in order to input any possible data from the data line by involing the RCVSRV routine ~similar to that disclosed in Miller '414). On completion of this task, the DECODE process is invoked in order to decode any received data and to perform the desired actions. Following the decode of data a transmitter service is performed in order to output any possible data to the data line by calling the routine XMTSRV
~similar to that disclosed in Miller '414). Next a switchleg service is invoked in order to determine switch actionsO Pinally, the module is reidentified in order to keep the transceiver address and jumper registers set to the most current position ~it is possible to change the jumper or address configura-tion at any time). On completion of the MODIDN
process, the executive continues to recharge the watchdog timer and invoke the 5 main subroutines until such time that the microprocessor is reset due to a powerup, or watchdog.
Figure 35 describes the module identifica-tion routine used by the switch TRD. Since each transceiver decoder has a user selectable address to which it will respond as well as user and manufacturing installed jumpers which configure the method in which the transceiver decoder operates, the module identification routine is necessary in ~IL23~5~5 order to input the desired address and jumper confi~uration for subsequent later action and processing by the TRD. On entry to the MODIDN
procedure, a test is performed to determine if the data line is active. If so, then the MODIDN process aborts as indicated. (It would not be desirable to reidentify the module due to the lengthy process involved if the data line was active.) If, on the other hand, no current data line activity was indicated, then the jumper hardware would be enabled for input and the A8JUMP register would be set to the value obtained by inputting the jumper configuration. The jumper input hardware is then disabled in order to reduce power consumption and a flag is set indicating a one or two address TRD
based on the configuration of the 5ize jumper. A
temporary register is then ~stablished and cleared and an indication i5 made to input 8 bits of address data. Beginning with the loop on Figuxe 35, the temporary register is rotated one bit position to the left in order to position its contents for the next addres~ bit to be input. Following this an output word is fetched from a table of values based on the current bit number. The address multiplexer hardware is then enabled and a single bit of address data is input. This address bit is isolated and "ORedi' with the bits in the temporary register. The updated temporary is then saved and a test is performed to determine if all bits have been input. This procedure of rotating the temporary, selecting an output word to enable the proper address multiplexer, inputting the bit and merging it with a temporary continues until such time that all bits have been input. Once all addres bits are , 71 ~233S~5;

in, a test is made to determine if the device is a single address TRD. If not, then bit DB0 of the temporary is cleared. (A two address device will respond to two addresses. The even address, i.e., when DB0 equals 0 corresponds to Bank 0; the odd address when DBl equals 1 corresponds to Bank 1.
On the other hand, if the device was a single address TRD, then DB0 would not be altered and the resulting address could be either even or odd.
ADRLOW is then set equal to the 8 least signif_cant address bits contained in the temporary and then tAe address multiplex hardware i~ turned offO This completes the module identification process which then returns to the invoking utility.
As discussed above, the transceiver decoder has a continuously running i~ternal 6 millisecond timer which is used to sequence desired actions.
This timer~ is an internal programmable device which generates a timer interrupt whenever a programmed register has been incremented to a 0 value. This timer runs continuously and is disabled only when being serviced or updated.
Figure 36 describes the timer interrupt ser~ice routine TIMINT. The purpose of this routine is to service a timer interrupt which occurs every 6 milliseconds and to increment by 1 an elapsed timer counter. On detection of a timer interrupt, the timer is stopped and the timer registers are selected (this is Register Set 1 of the 8049 microprocessor, constituting the presently preferred embodiment of ~witch processor 300). The current accumulator value i5 saved in order to free the accumulator for other usages and the six (6) millisecond timer value is fetched. ~ollowing this, , , =, .. , .. - - ~ ,. - , 72 1 ~ ~ 3 ~ 5 the timer is initialized for the next 5 millisecond interrupt and the accumulator is restored to its value on entry to the TIMINT procedure. The elapsed timer counter is then incremented by l and the internal hardware timer flag is cleared in case it remains set. Upon exit from the timer interrupt service procedure, the currently active working register bank is stored (this is the standard register bank or register bank 0).
The elapsed timer is continuously updated by the 6 millisecond timer interrupts. Two additional timers can be driven off Qf this elapsed time counter in such a way that they may be maintained current by summing in the elapsed time counts. This is the responsibility of the TIMSRV
procedure described in Figure 37. On entry to the TIMS~V process the timer interrupt is disabled and the bank of timer registers are selected. Timer 0 is then set equal to the initial value of timer 0 plus the elapsed timer counter. $imer 1 is then set equal to the initial value of timer 1 plus the elapsed timer counter. The elapsed timer counter is then cleared and a test is made of the internal hardware timer flag to determine if it was set. If so, an immediate branch is taken to the TIMINT
procedure (the internal timer flag would be ~et if a timer interrupt occurred coincidentially with the entry to the TIMSRV process). If the timer interrupt flag was not set, then the working register bank would be restored and the procedure would complete and return to the invoking process.
It should be noted that the TIMSRV process is - asynchronous of the timer interrupts and could be entered at any time. A maximum delay of up 256 of 73 ~; :33~ 5 the 6 millisecond timer counts could expire before losing accuracy in the timer 0 counter and timer counter.
A proce~s exists, described in Figure 38,called CLRST0 for initializing and starting the timer 0 counter. ~he timer bank of registers is selected a~d the counts needed for the 6 millisecond interrupt duration are initialized. Following this, the timer is started by calling the TIMINT
process. Next the elapsed timer and timer 0 are both cleared and set equal to 0~ Finally, the timer interrupt is enabled and on exit from the routinc the working bank of registers is restored.
Figure 38 also indicates an additional routine present in the switch TRD called CLRSTl or Clear and Start Timer 1. The timer bank of registers is selected and timer 1 counter is set equal to 0. On exit ~rom the CLRSTl process, the original bank of working registers is restored. (In the switch transceiver timer 0 is utilized as the 48 millisecond switch reading internval timers while timer 1 is utilized as the 1 second answer-back acknowledge timer as described in the switchleg handler module.) The Powerup routine provides for the following: a means of generating a Powerup/Status message for subsequent transmission to a monitoring or controlling device; a means of invoking a reset procedure ~o initialize I/O devices and internal registers; a means of initializing the watchdog reset hardware a means of initializing the machine to a known internal state.
The executive provides for: a means of periodically strobing a watchdog timer in order to :
' 7~ 3~5 indicate normal operation; a means of resetting the stack and working register bank in order to counteract any possible incorrect action due to spurious signals which may have altered the machine state; and a means of providing the functionality of the transceiver decoder by executing an executive loop of the-desired functions forever.
The reset process provides for, a means o~
initializing I/O to a known condition; a means of initializing ~11 de5ired memory re~isters to 0; a means of causing the receiver to resynchronize on a maximum line free timeout; a means of clearing the good and bad message counter to 0 values; a means of clearing the accumulated switchleg buffer; a means of readiny any current swtich contact closures and establishing internal registers in such a way that any switches that are in the "make" condition will not cause subsequent transmission over the data line due to the reset procedure being invoked; a means of enabling all switchleg mask positions; a means of starting and clearing the proper timer counters: and a means of halting any current actions that might be pending in the transceiver decoder (such as messages awaiting decoding in the receiver buffer~.
The timer routin~s provide for: a means of establishing a periodic 6 millisecond internval timer: a means for counting the timer interrupts and retaining a sum of the number of times the interrupt - has occurred in an 8 bit elapsed timer counter; a means of providing one or more counters to which the elapsed time counter is added in order to provide for long intervals to be timed; a means of clearing to 0 and restarting onP or more timer counters; and ` 75 ~3~5~S

a means of deferring until a convenient time the servicing of the elapsed time counter.
The module identifier provides for: a : means of inputting a set of 8 user or manufacturing installed jumpers to dynamically or st~tically conEigure the transceiver decoder: a means of operating a multiplexer circuit in order to allow the inputting of 8 user selectable address lines; a means of identifying via a flag a one or two address transceiver decoder; a means of disabling the jumper input hardware in order to reduce power consumption;
a means of detecting and avoiding a conflict with the operation of the address multiplexer circuit and other external hardware; and a means of allowing the address inputs or mode selector jumpers to be dynamically varied by the user and detected and acted upon t:he transceiver decoder.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments but on the contrary, is intended to cover various modifications and equivalent arranqements included within the spirit and scope of the appended claims which scope is to be accorded the broadest interpretation so as to encompass all such modiications and equivalent structures.

Claims (9)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a system for controlling distributed electrical loads including a central controller for providing a data signal defining the manner in which said loads are to be controlled; plural transceiver devices, each device being connected to control a subset of said loads by controlling relays in respective power circuits of said loads and including means for receiving contact closure inputs and transmitting information related thereto to the central controller; and a single data line connecting said central controller with each transceiver device, and improved transceiver device, comprising:
means, coupled to said receiving means, for monitoring the current state of any contact closure input to said transceiver and transmitting information indicative thereof to the central controller.

2. In a system for controlling distributed electrical loads including a central controller for providing a data signal defining the manner in which said signal defining the manner in which said loads are to be controller; plural transceiver devices, each device being connected to control a subset of said loads by controlling relays in respective power circuits of said loads and including means receiving contact closure inputs and transmitting information related thereto to the central controller; and a single data line connecting said central controller with each transceiver device, and improved transceiver device, comprising:
means for selectively disabling a contact closure input such that a contact closure on the disabled input will not cause data indicative of that contact closure input to be transmitted to the central controller, thereby providing a masking override function for such an input.

3. In a system for controlling distributed electrical loads including a central controller for providing a data signal defining the manner in which said loads are to be controlled; plural transceiver devices, each device being connected to control a subset of said loads by controlling relays in respective power circuits of said loads and including means for receiving contact closure inputs and transmitting information related thereto to the central controller; and a single data line connecting said central controller with each transceiver device, and improved transceiver device, comprising:
means, coupled to said receiving means for accumulating contact closure inputs and maintaining a record of the last received contact closure for each contact closure input of said transceiver; and means for interrogating said accumulating means as to the last contact closure state of any switch input and transmitting data indicative thereof to said central controller.

4. A system for controlling distributed electrical load comprising:
a central controller for providing a data signal defining the manner in which said loads are to be controlled; plural transceiver devices, each device being connected to control a subset of said loads by controlling relays in respective power circuits of said loads and including means for receiving contact closure inputs and transmitting information related thereto the the central controller;
and a single data line connecting said central controller with each transceiver device;
means for providing from said central controller to said transceiver decoder an acknowledgement of received information indicative of a contact closure input to said transceiver decoder.

5. A system according to claim 4 further comprising means at said transceiver for periodically retransmitting information related to contact closures until receiving a positive acknowledgement of the information from the central controller.

6. In a system for controlling distributed electrical loads including a central controller for providing a data signal defining the manner in which said loads are to be controlled; plural transceiver devices, each device being connected to control a subset of said loads by controlling relays in respective power circuits of said loads and including means for receiving contact closure inputs and transmitting information related thereto to the central controller; and a single data line connecting said central controller with each transceiver device, and improved transceiver device, comprising:
means for providing a changeable threshold reference providing first and second threshold signals;
means for comparing a contact closure input with said first threshold signal; and means, in the event of a favorable comparison with said first threshold in accordance with predetermined criteria, for further comparing the contact closure input with said second threshold signal to determine whether a contact closure actually occurred.

7. An improved transceiver device according to claim 6 further comprising means for multiplexing contact closure inputs onto a number of lines less than the total number or contact closure inputs associated with the transceiver for coupling to a processor of said transceiver.

8. In a system for controlling distributed electrical loads including a central controller for providing a data signal defining the manner in which said loads are to be controlled; plural microprocessor-based transceiver devices, each device being connected to control a subset of said loads by controlling relays in respective power circuits of said loads and including means for receiving contact closure inputs and transmitting information related thereto to the central controller;
and a single data line connecting said central controlled with each transceiver device, and improved transceiver device, comprising:
a watchdog reset circuit coupled to said micro-processor for monitoring the operation thereof, and providing a reset signal thereto in the event of a failure of proper operation thereof, said watchdog reset circuit being AC coupled to said microprocessor so that its operation is not defeated by a malfunction that would cause a DC condition in a signal resetting a watchdog timer of the watchdog reset circuit; and means, responsive to a reset of said microprocessor for annunciating a reset message, via said data line, to said central controller.

9. An improved transceiver device according to claim 8 further comprising means, coupled to said watchdog reset circuit, for preventing erroneous switch transmissions from said transceiver to said central controller on power-up thereby preventing regeneration of a previously processed contact closure.