CA1223988A - Modular computing oscilloscope with high speed signal memory - Google Patents

Abstract

MODULAR COMPUTING OSCILLOSCOPE

WITH HIGH SPEED SIGNAL MEMORY

A B S T R A C T
An oscilloscope to sequentially store, process and display an electrical input signal according to various signal events and characteristics. The oscilloscope is physically and functionally modular having both selectable hardware configurations from among various "plug-in" modules and selectable processing and display features chosen from among a predetermined selection by software control contained, in part, within the plug-in modules. The particular control settings, as well as a representation of the signal itself, is recorded on a removable storage device, such as a magnetic disc. High frequency signals are sampled, digitized and stored in a high speed intercascaded signal memory, independent from the program and data memory associated with the oscilloscope signal processing.

Description

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.1 '`' FIELD OF THE INVENTION
The present invention relates to digital oscilloscopes and more particularly

2 to oscilloscopes including digital signal processing apparatus.
., , if BACKGROUND OF THE INVENTION

3 I The desirability of viewing representations of signals and their signal

4 ¦ characteristics either alone or in the context of other signals or events has

5 l¦ increased significantly over the years. The importance OX visual representation has

6 l¦ been increased by the multiple analytical methods which have been implemented

7 with fewer and fewer hardware components. More recently, it has been possible to

8 ¦ include these signal analyzers within the body of the oscilloscope to provide ! complex signal analysis within a relatively limited physical dimension. The signal 10 1 characteristics which can be displayed arise from generalized sampled data 11 Jo measuring instruments included within the oscilloscope. Time domain instruments I , such as digital storage oscilloscopes, also provide computing capabilities such as Al 13 ¦ rise-time, fall-time and pulse-width as well as additional signal processing capably-14 l¦ flies including filtering, spectrum analysis such as Fast Fourier Transform FIT
15 , and long term signal storage or liter recall and comparison. Signal processing 16 1 computers preallotted additional signal~measuremen~ and parameter display capably-17 l l flies. However, a digital computing oscilloscope incorporating all the above lo lo features cannot merely aggregate the individual instrument functions. Generalized 19 Gil expansion of the oscilloscope facility results in an instrument US unwieldy as an 20 1 entirely analog oscilloscope of the same capability having every parameter 21 1 adjustment assigned to a particular control among many controls. Each new 22 1 function, with its particular analog signal processing and control characteristics 23 I makes different requirements on the oscilloscope facilities. The functions must be 24 I integrated in a coherent manner to cooperate with each other.
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I One approach is to reduce the flexibility of each function to limit thy 2 number of controls by which the operator may adjust the instrument. However, the 3 sacrifice of flexibility is typically the opposite of what the instrument was created 4 to provide.
S ; An alternate approach is to generalize the system wherein its function is 6 i l determined according to a general computer program. One such system may 7 comprise a microcomputer and a rack of IEEE 4~8 bus-compatible instruments 8 l The user must be a programmer familiar with the use of each of the instruments

9 I and the specific communication protocol. A further disadvantage that often 1 results in such systems is that important parameters become embedded in the 11 I program arid are accessible only by tedious reassembly process. Checkout becomes 12 difficult when the immediate results cannot be easily scrutinized. In such systems, 13 the functions retain their flexibility but it is the user group which is limited, 14 primarily to a group sophisticated in the particular system assembled.
, In digital controlled equipment, when the proper parameter values have been 16 , established and the data taken for a particular reading, it is often necessary to 17 ;, reestablish and review the event occurrence. This is complicated through the need 18 to readjust the oscilloscope to various settings at several different sequential 19 ,', periods during the test operation. Moreover, comparisons to prior test results, such 20 l so comparison of one signal to a prior signal, has heretofore been limited to large 21 ' scale computer systems, and not for laboratory test instruments where they would 22 1 ! be most useful.
23 Furthermore the signal to be measured by a digital oscilloscope must be 24. l sampled with high accuracy and resolution in both sample amplitude and sample 25 I time period. Ultimately, the digital oscilloscopes' processing capability are limited 26 ; by the input signal frequency end resolution accuracy.

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According to the present invention there is pro-voided an improved oscilloscope comprising a modular unit comprising means to receive an input signal; means to pro-vise a plurality of signal samples; main processor to process said signal samples according to a process; and means to display said processed signal samples providing a visual display, wherein said modular unit is removably connected to said main processing means, said main processor providing at least part of said process, said process being determined by said modular unit.
Both the main processing system and the display may be housed in a mainframe unit which also includes additional control switches and a receptacle to receive a modular unit. The modular unit may be configured in alter-Nate versions snot shown) to each provide a specific lung-lion and/or signal processing capability. Moreover, the modular unit may be adapted to provide additional signal conditioning and measurement control such as input signal ground isolation.
In particular, the modular units in the described embodiment receive the analog input signals and provide for analog conditioning prior to the A to D conversion. In particular, the modular unit includes an amplifier to in-crease a low level signal and an attenuator to attenuate a signal of excessive amplitude. The modular unit also in-eludes circuitry to transfer the conditioned or adjusted signal as well as the parameter settings to the mainframe and subsequently to the display unit. The signal trays-erred in this manner may be a sampled and digitized signal on or it may be additionally processed or conditioned. The sampled signal forms a signal representation to be stored in ~L~Z239~

a memory which may be within the plug-in unit as shown here, or in the mainframe memory snot shown) of the pro-censor and recalled to provide an accurate representation of the signal for further processing and display on the oscilloscope according to the particular selected parameters.
The modular unit also includes a memory program storage element which when connected to the main processing circuitry enables the oscilloscope to function according to a selected particular process when the oscilloscope is operated. Moreover, the main processing system initiates a power-up sequence which initializes the various elements of the processing system. The main processing system scans the memory contained in -., , /

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each particular modular unit and identifies therein the particular processing 2 capability of that unit. The processing system then displays an appropriate 3 alphanumeric label and numeric value on the display indicating to the user the 4 ; particular oscilloscope plug-in unit housed and the work capabilities of that unit. ,¦
S I Typically, the plug-in includes an analog to digital convertor (ADO) wherein it I the received analog input signal is converted to a digital representation thereof and 7 'j stored or directly passed to the main processing system for visual display. The 8 I main processing system comprises a digital computer. The digital computer is 9 l l implemented with a microprocessor. The digital computer is housed in the I mainframe of the oscilloscope and is programmed to perform several mathematical 11 1 operations on the digital signal representation. The processes are selectable and 12 if alterable according to front panel switches from among the particular program 13 '¦ stored in the read-only memory program stored. Particular plug-in unit parameters 14 I are controlled by programs stored in the plug-in unit, and general operation are if selected from among the processes available by programs stored in the mainframe.
16 1 A wide variety of functions may be performed having minimal computer 17 l' redundancy and complexity combined with a flexible oscilloscope system capable of 18 l performing a virtually unlimited processing and analysis function. In addition, the 19 ¦ mathematical functions performed by the oscilloscope according to the present l invention may be concatenated or chained together to provide a complex signal 21 processing system which is responsive to a particular signal. Moreover, as the 22 signals change, the processing is a continuously renewed or updated. The values 23 resulting from the mathematical computation on the representative signal is 24 adjusted by prescaling before it is displayed on the display means, to insular the maximum resolution of the signal on display without extending beyond the edge of26 , the display. The oscilloscope provides labeled coordinate axes having the prescaled 27 coordinants displayed along with the signal representation on the display surface.

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Additional features of the oscilloscope according to the present embodiment include self diagnostic system checks residing within the main processing system and the particular plug-in module. Upon a system or signal input failure, the processing system provides an appropriate user message on the display device. Moreover, the part-cuter signal values, parameters and system processes employed during a particular operation may be stored on a long-term removable storage device, such as magnetic tape or disc memories. The memories may then be used in the future to restore the system to a previously predetermined opera-tying arrangement.
The particular embodiment of the oscilloscope shown also includes a high speed signal memory within the plug-in module to retain the sampled signal representation separate from the memory associated with the computer processes.
The separation of the stored sampled signal data in the high speed memory within the plug-in module and the computer data memory within the oscilloscope mainframe allows I repeated recalculation of values from the original sampled signal values without information loss through signal pro-cussing of the original data. The high speed signal memory comprises an inter cascaded memory having significant improvement in operational speed and a reduced power con-gumption in comparison to the standard random-access arch-lecture.
An embodiment of the invention will now be desk cried, by way of example, with reference to the accompany-in drawings in which:-Fig. 1 is a front view of the oscilloscope;
Fig. is a block diagram of the oscilloscope;

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Fig. 3 is a block diagram of the analog to digit tat conversion unit of Fig. 2;
Fig. 4 is a block diagram of the high speed signal memory of Fig. 2; and Fig. 5 is a timing diagram of the high speed signal memory of Fig. 4.
The digital computing oscilloscope according to the present embodiment and shown in Fig. 1 displays signals received by a signal input 52 on a display 54.
The signal received is first conditioned, sampled, and digitized by plug-in unit 56~ The plug-in unit 56 stores the sampled signal in a signal memory and is subsequently transferred to processing equipment within the mainframe 58 which also houses the display 54 and a plurality of operator controls discussed below. Some user controls are keys 60 located on the module 56; programmable keys 62 and power switch 64 are located on the oscilloscope mainframe 58. The plug-in 56 is received by the mainframe 58 through an opening 66 to which the plug in 56 extends a plug 68 to mate with a corresponding receptacle (not shown) within the mainframe 58.
The block diagram of the oscilloscope 50 is shown in Fig. 2. The plug-in AYE and mainframe AYE corresponds with the plug-in 56, with the mainframe 58 of Fig. 1. The plug-in AYE includes analog conditioning circuit 102 and typically comprising filtering, voltage isolation, off-set adjustments and other analog functions known in the art.
The signal is also adjusted in amplitude by attenuator circuit 104 before being sampled and converted to a digital signal by an analog to digital convertor (ADO) 106. Add-tonal input channels are part of the present invention, : l22;~

and although they are not shown, they are identical up to the ADO 106, which has a selector (discussed below) to select among different analog inputs. The resulting digital signals as well as the module parameter settings are stored within a signal memory 100 and in turn transferred to the mainframe AYE processing computer 108 according to the digital computer bus 110. The plug-in unit AYE also in-eludes the keys AYE having a plurality of user operated controls. The keys AYE include interface circuitry to transfer the corresponding signals to the computer bus 110.
The plug-in includes a process program read only memory (ROM) 112 which is then connected to the compute bus 110.
The program contained within the ROM 112 directs the part-cuter computer processes selected by the operator according to the operator controls, which include the keys AYE. The selected process is performed by the computer 108 according to the program stored within ROM 112 include designation of particular functions within the user control group AYE
corresponding to the keys 62 of Fig. 1. The keys AYE are connected to the computer bus 110 by interface circuits 114, which also provides analog signals to the CRT display AYE. The recorded and processed digital signals the user-selected oscilloscope functions and module parameter values (through control 101) are stored on an external memory device, such as a disc unit 59, connected to kimono gate with the oscilloscope through the bus 110. The analog circuits 102 and 104, and the interconnection of the digital circuits AYE, 112, 101, 108, AYE and 114 are generally known in the art and not discussed here. Moreover, although the interconnection ox signal memory 100 to the computer bus 110 is known in the art, the internal arch-~2;~3~

lecture of the signal memory 100 is part of the present invention, and is discussed further below.
The computer 108 comprises a microprocessor and an associated data and program memory (not shown) and is implemented by components available to those skilled in the art. The program ROM 112 within the plug-in module AYE augments the computer data program memory by occupying a particular location in the memory space to which the computer 108 microprocessor can access through the bus 110.
Similarly, resident within each program ROM 112 is a part-cuter identifier code corresponding to the mathematical and functional capabilities which may be performed by the mainframe computer 108 while the selected plug-in AYE is engaged on the computer bus 110. The computer 108 also provides a visual indication on the display AYE of the particular programs available within the program ROM 112 by included circuitry to Jo Jo - pa -. '` 'I f I

detect when the off switch 116 is operated. Moreover, the list of available a I programs can be recalled and displayed when one or more of the appropriate keys 3 AYE or AYE is actuated. Also included within the computer 108 are diagnostic 4 I programs which provide diagnostic information relating to the malfunction of the computer 108 or other oscilloscope 50 elements.
6 I The particular processes available within the oscilloscope 50 include 7 j processing and display of representative signal values according to a variety of 8 , ¦ mathematics processes. These processes may be concatenated wherein various 9 if equations may be subsequently used to provide multiple mathematical processes to 11 be performed on a particular signal. The processes may be arranged in a particular 11 combination or sequence according to a user selection of controls, which include 12 1 the push buttons within keys AYE and AYE. Also, as further signals are received by 13 1 the oscilloscope 50, the processes may be recomputed on a continuous basis to 14 i display a composite signal on the display device AYE. A typical mathematical 15 '' process includes the trend analysis function known in the art. Other mathematical 16 I I processes include geometric computations, time differentials and intervals of 17 l¦ particular signals. The computer also generates a coordinate signal to the display 18 1 54 which provides visual indication of coordinate axes and numeric labels spaced at 19 I scale intervals on the axes, corresponding to the axis parameter value at the ! I intervals. I
21 I The elements of ADO unit 106 of Fig. 2 are shown in the block 22 I diagram AYE of Fig. 3. The ADO unit 106 is selectable to operate in one of three 23 l modes: one channel 100MHz 7 bit resolution; one channel 50MHz 8 bit resolution;
24 l and two channel 50MHz 7 bit resolution, discussed below.
I The wires interconnecting the elements of the digital elements typically 26 I comprise a plurality of wires, typically 8 or 16 wires in p rallel, and for reasons of 27 i clarity will be shown in the figures as a single line. Moreover, the number of 28 conductors associated with each element may be varied as desired in alternate ' ' .

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embodiments. The analog inputs from attenuator 104 and others (not shown) are 2 received by ADO element 120 and by ADO elements 122 through switch 124 in 3 position A. Alternately, a second analog channel is received through switch 124, in 4 position B. The ADO elements 120 and 122 receive reference sign is through , switch 126. When switch 126 is in position A, the voltage dividers within each ADO
6 Al element 120 and 122 are connected in series to form single voltage divider; each ill ADO element provides the least significant bits (IJSB) and the overflow signal from I¦ ADO element 122 provides the most significant bit (MS13). Switch 128 selects one of the ADO element (120 or 122) output sign is according to the overflow signal:!¦ ADO element 122 output is selected unless an over flow is indicated, whereupon 11 1 ADO element 120 output is selected. The memory strays 210 and 250 receive the ~12 if representative digital signals through switch 130. The (combined) 8 bit output is 13 1¦ selected when the 8 bit resolution is desired, or each individual ADO element (120 14 or lea) output is simultaneously selected when two channel operation is selected, or sequentially selected by both memory arrays 210 End 250 when in high speed 16 l, (Loomis) mode.
17 The switches 124~ 126 and gate 130 are operable either manually or under 18 I computer 108 program control through bus 110; the gate and switches including 19 I switch 128 are implemented by solid state (or other) switches known in the art.
I The ADO elements 120 and 122 each provide a digital output upon the occurrence 21 if of a begin conversion" signal from ADO controller 132, which receives a signal 22 if from the high frequency (Loomis) oscilloscope clock 206. The relative phase 23 I relationship between the "begin conversion" signals AYE and 131B is selectable to 24 coincide or to be offset by 180, according to whether a 50MHz or Loomis data I rate is desired. When the ADO elements 120 and 122 are operated out of phase26 with a common input signal, and in conjunction with the memory 100 discussed 27 below, the oscilloscope effectively receives, samples, digitizes and stores input 28 I signals at a Loomis data rate. I

, The ADO unit operates in one of three modes by selections of switch 2 I positions according to Table 1, below:
3 l TABLE 1 ' 124 126 AYE, 131B

7 ¦ 1 Channel 100MHZ
h I 7 BIT A B 180 g 1 50 MHZ
8 BIT A . A 0 i .11 ¦ 2 Channel 50 MHZ
12 1 Bit B B 0 13 The particular implementation of the signal memory 100 is shown in the 14 block diagram of Fig. 4. The timing diagram 150 of jig. 5 shows the typical if address times 152 write signal 154 and data input signals 156 of a single random 16 access memory (RAM) and the addressed data signal timing relationship among the 17 I various RAM element of the memory 100. The horizontal coordinate shows 18 1 intervals ox 20 nanoseconds (no). For a typical RAM which requires the address 19 1¦ signal to be stable for a time of 120 nanoseconds, the input data must typically be 1 stable for approximately 60 nanoseconds, or one-half of the address time period 21 1 152. However, in the high frequency mode, the digital computing oscilloscope 50 22 provides a date stream 158 from the plug-in AYE at a much higher rate of 10 23 nanoseconds per data value. The signal memory 100 of the present invention 24 I combines sixteen Rams each having a characteristic shown by signals times 152, It 154 and Tao store a stream of data.
I j The signal memory 100 comprises two memory arrays 210 and 250, each 27 l being identical; however the memory arrays receive data in alternate sequence 28 from the ADO unit 106 when in the 100MHz mode. For clarity of explanation, If ~2~23~ 3 .

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11 except for the abuser mentioned differences, the memory array 210 and; the 2 , memory array 250 operates in an identical manner. In the timing diagram 150 of 3 ' Fig. 5, the signal values of 162, 164, 166, 168, 172, 174, 178 and 18û are received in 4 I digitized form by array 210; the sign is 163, 165, 16q, ~69, 173, 175, 179 and 181 S Jo are received by array 250 of Fig. 4. The signal values 178, 179 eta, alternately are 6 I converted by the ADO unit 108, and received by the memory lo to effectively 7 I sample the incoming oscilloscope signal at 10 nanosecond intervals. The alter-8 if namely converted signals are received by input distributors 220 and 260 which route the respective data stream to one ox eight memory elements within each array.
! The memory elements 211 through 218, and 251 through 258 respectively each if comprise CMOS Rams having the signal characteristics typified by signals 152, 154 12 1 and 156. The signals stored wither the above mentioned elements are then 13 1 selectively placed on the computer bus 110 by the operation of respective output 14 1 multiplexes 230 and 270~ The output multiplexes, and the memory elements are 1 controlled by control elements 240 Ed 280 respectively. The operation of the 16 array control elements and the input selector in gate 204 is operated according to a 17 l high frequency (lDOMHz) clock 206. According to the present invention, the 18 1 memory elements are multiplexed wherein two memory elements share each 19 1 address signal, data input signal and data output signal path. Specifically, the eight 20 1 memory elements receive four address signals A, B, C, and D generated by control 21 240, by arranging pairs of memory elements in the pairs 211 and 212, 213 and 214, 22 215 and 216, and 217 and 218 respectively. The corresponding elements 251 and 23 252, 253 and 254, 255 and 256, and 257 and 258 of array 250 receive the address 24 I signals A, B, C, and D, generated within array 250. The addresses B, C, and D are 25 1 typically identical to address value A but delayed in time as shown in Fig. 5. The 26 input distributor signal output ports P3,7 P4,8 P5,1 and P2,6 are each connected to 27 the corresponding input pairs of memory elements 213 and 217, 214 and 218, 211 . .
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l l Z35~8~3 'I and 215, Ed 212 and 216, respectively; the corresponding input signals of the array 2 250 to each memory element input are similarly provided by the distributor 260 and 3 , received each the respective memory elements as shown in Fig. 4. This manner of 4 shared memory element interconnections provides a particular significantreduction in the number of logic elements associated with the data Ed address 6 ' signals, which ore the highest speed devices and the most power consuming.
7 '¦ Therefore, the reduction of power consuming results devices a significant reduction 8 l in signal memory 109 power consumption. Typically, the input distributor 220 and 9 l¦ 260, output multiplexes 230 and 2~Q, and array control circuits 23û and 26Q are implemented with TTL circuits and the memory elements 211-218 end 251-258 ore 11 I implemented with CMOS Rams such as the Hitachi number HN6116LT menu-it I lectured by Hitachi Corporation of Japan.
13 ,¦ The memory elements 211 and 212 share a common address signal A, shown 14 ' in Fig. 4. According to the typical RAM specification shown in Fig. 5, the write I signal trailing edge transition 155 must occur in a specified period of time before 16 I the change of address sexual 152. At 150, a staple data input signal must exist for 17 ! a period of time 157 before the occurrence of the transition 155, as well as for a 18 period of time 159 thereafter. The sum of these two times 157 and 159 are lug I typically equal or less than one-h~lf of the stable address time 152. It is also 'j typical Rums that the signal transition 155, and the stable data input signal time 21 I period 156 occur entirely before a change of the address 152 data. This is shown in 22 I timing diagram 150 as the particular address signal 160 relative to the two 23 corresponding data input signals 162 and 164 from the input distributor 220 (or 260) 24 signal ports Ply and P2,6 respectively. For a stable data input time period (equal I to the sum of period 157 and 159) of approximately 60 nanoseconds, according to 26 t Fig. 5, the corresponding data input signals 162 and 164 exceed the minimum 27 requirements as shown. Therefore Roth memory C; I
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elements 211 and 212 can selectively receive different input data according to 2 signals from port Ply and P2,6 while receiving a common address signal A. The 3 offset in time of the data input signals 162 and 164 OX 20 nanoseconds is irrelevant 4 ; to the particular RAM requirements so long as the data is stable for a m~imum specified time, and occurs relative to the write signal transition 155 and the .0 1 Audrey signal 152 transition and as defined by the psrticul~r RAY M selected.
7 ,1 Addresses A, B, C and D are the some value but successively delayed in time.
3 ¦¦ Similarly, the next two pieces of data 166 and 168 from the data stream are shown 9 as signals AYE and AYE by the input distributor 220 ports P3,7 and P498. The I signals AYE and aye are then received by memory elements 213 and 214 11 1 respectively. The memory elements 213 and 214 shore a common address B signal 12 1 170 wherein the Saigon AYE and AYE are stored within the memory 213 and 214.
13 1 The data signals 172 and 174 are received by the memory elelnents 215 and 216 14 I from the input distributor 220 output ports Ply and P2,6 as data signals AYE and 1 172B respectively. These signals are stored in the memory elements 215 and 216 16 1 according to the memory address C signal 1~6. The signals 178 and 18û of the data 17 1 input art received by the memory elements 217 and 21~ as signals AYE and AYE
18 I from the input distributor 220 ports P3,7 and P4,8 respectively The input signals 19 .1 AYE and boa Are received and stored by the memories at the address D shown as 1¦ the, 182. The address sigslals A, B, C and D are provided by the array control 240 21 1 according to signals received from the computer bus 110. Similarly, each array 22 , memory element requires a write signal (not shown) corresponding to the typical 23 write signal 154 shown in the timing diagram 150. The array memory write signals 24 Wylie are produced within the array control 240. The array control produces a write signal 154 having a write pulse duration and transition 155 to meet or 26 exceed the requirements of the respectively chosen RAM memory element chosen.
27 The relive timing ox the write signals are adjusted to each corresponding data .

:! -signal (such as signal AYE) timing position. Similarly, each memory element may 2 also have a chip select (US) signal input (not shown); the specific operation of the 3 US input signals are not material to the memory of the present invention. The 4 array control 240 also provides the input distributor 220 with the appropriate control signals CUD and the output multiplexer 230 with the corresponding control 6 1 signals at lead CM. The input distributor 220, output multiplexer 230, array 7 I control 240 and clock 206 comprise digital circuitry known in the art, and not 8 discussed in detail here. Moreover, the interface elements necessary to commune 9 ,1 irate with the computer bus 110 are selected to function within the particular

10 ', computer bus parameters. Therefore, the present invention is not to be limited by

11 I modifications and alternate embodiments by those skilled in the art except as lo 11 defined in the claims which follow.

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Claims (15)

What is claimed is:

1. An improved oscilloscope comprising:
a modular unit comprising:
means to receive an input signal;
means to provide a plurality of signal samples;
main processor to process said signal samples according to a process; and means to display said processed signal samples providing a visual display, wherein said modular unit is removably connected to said main processing means, said main processor providing at least part of said process, said process being determined by said modular unit.

2. The oscilloscope of claim 1 further including:
means to identify said modular unit; and means to display the identity of said modular unit on said means to display.

3. The oscilloscope of claim 2 wherein said identity also identifies said process.

4. The oscilloscope of claim 2 further including initialization means to enable said means to identify.

5. The oscilloscope of claim 4 wherein said initialization means is operative upon start-up and reset events.

6. The oscilloscope of claim 1 further including diagnostic means providing a diagnostic signal to said display means indicating the existence and character of an oscilloscope malfunction.

7. The oscilloscope of claim 1 further including calculation means providing numeric signals representative of said representation signal according to a mathe-matical process.

8. The oscilloscope of claim 7 wherein said calculation means provides a continuous recomputation of said mathematical process as said representative signal changes.

9. The oscilloscope of claim 7 wherein:
said display has limits within which the values of signals to be displayed are restricted, said oscilloscope further comprising:
means to scale said signal samples according to a determined scale factor to adjust said signal samples to within said display limit values.

10. The oscilloscope of claim 9 further including coordinate means providing a coordinate signal to said display means wherein said coordinate signal includes coordinate value signals according to said scale factor to provide a labelled coordinate axis.

11. The oscilloscope of claim 7 further including equation chaining means providing sequential mathematical processes performed on a particular signal, said multiple mathematical process being arranged in a selected combination.

12. The oscilloscope of claim 7 wherein said mathematical prows includes a trend function.

13. The oscilloscope of claim 1 further including analog-to-digital conversion means contained within said modular unit.

14. The oscilloscope of claim 1 wherein said main processing means comprises a digital computer.

15. The oscilloscope of claim 14 wherein said process control means includes a digital computer memory.