CA1223946A - Arrangement for interfacing the space stage to the time stages of a t-s-t digital switching system - Google Patents

Abstract

AN ARRANGEMENT FOR INTERFACING THE
SPACE STAGE TO THE TIME STAGES A T-S-T
DIGITAL SWITCHING SYSTEM
ABSTRACT OF THE DISCLOSURE
An arrangement for interfacing the originating time stage (OTS) and terminating time stage (TTS) of a time and control unit (TCU) to the space stage of T-S-T
digital switching system. The space stage includes an intra-path through the space stage as well as an inter-path. The interface transmits PCM samples simultane-ously from the OTS to both the intra and interpaths of the space stage. PCM samples from the space stage are received by an intra buffer and an inter buffer from the intra path and inter path respectively. A TCU
control memory gates and connects either the intra buffer or inter buffer to the TTS.

Description

AN Arrangement FOR INTERFACING THE
SPACE STAGE TO THE TIME STAGES OF A TOT
DIGITAL SWITCHING SYSTEM
BACKGROUND OF TOE INVENTION
This invention relates in general to time-space-time (T-S-T) telecommunication switching systems, and in particular to an interface intercom-netting the space stage to the time stages in a T-S-T
switching system.
Time-space-time (T-S-T) switching systems are a configuration of digital switching elements providing both time and space translation between channels of time division multiplexed TO ~elecommu-nications transmission lines. The TOT network of a switching system interconnects digital bidirectional TAM communication lines with TAM communication in-valving the sharing of single transmission paths, individually, in lima, to provide multiple channels in a single transmission medium The construction of such a T-S-T network comprises the connection of a special stage between the two time stages.
In such a network, digitized data is pro-sensed to a time stage for momentary storage in memory.
At the appropriate time the data is bused to/from the space stage via a time shared switching path and then grated to a second time stage. Temporary buffering of the digitized data is normally required in order to ensure that the data transmitted or received is valid.
In T-S-T networks where the space stage is configured to provide a first switched path among a first or a second set of time stages (intra-path3 or a second switched path between the first and second set of time stages (inter-path) an interface between the time staves and the space stage is required to selectively send and receive the digitized data to both the intro path and inter path of the network.

r It therefore becomes the object of the present invention to provide an interface for each time stage of the digital switching system to inter-connect to the space stage of the network when con-figured with both intro and inter connecting paths between the time stages.
SUMMARY OF REINVENTION
The interface of the present invention allows for the sending and receiving of communications information (PAM samples) between a time and control unit (TCU) and a first and a second space stage.
The time and control unit includes an originating time stage having an information memory originating and a control memory originating and the terminal time stage including an information memory terminating and a control memory terminating. Both control memories are connected to a microprocessor interface and to a peripheral processor which provides a source of control signals.
The interface of the present invention in-eludes sending means comprising of a first set of bus dry rivers having their inputs connected to the information memory originating and their outputs connected via a PAM bus to the first space stage.
A second set of bus drivers has their inputs connected to the inputs of the first set of bus driver and their outputs connected via a PAM bus to the second space stage.
First receiving means comprising of a set of PAM buffers is connected to tube first space stage and arranged to temporarily store PAM samples sent to the interface. Second receiving means comprising a second set of PAM buffers is connected to the second space stage and also arranged to temporarily store PAM samples sent to the interface from the second space stage.
The PAM samples contained in the first and the second PAM buffers are transmitted to the informal lion memory terminating via selection means. The ., selection means comprises a first set of instate gates having their inputs connected to the first PAM
buffer and their outputs connected to the information memory terminating. A second set of instate gates has their inputs connected to the second set of PAM
buffers and their outputs connected to the outputs of the first set of instate gates. Each of the first and second set of instate gates includes con-trot inputs connected to the control memory terminating.
The control memory terminating via control signals from the peripheral processor determines from which space stage the PAM samples should be input into the information memory terminating. When samples from the first space stage should be input, a first control signal is sent to the first set of instate gates enabling the information in the first set of PAM buffers to be input into the information memory terminating When PAM samples from the second space stage should be input, a second control signal it sent to the second set of instate vales. Thus, enabling the PAM samples in the second PAM buffer to be input into the information memory terminating.
DESCRIPTION OF THE DRAWING
Figure 1 is a block diagram depicting the network structure of a digital switching system Figure 2 is a block diagram representing a 64 x 64 space stage configuration.
Figure 3 is a schematic diagram of a space stage unit configured to interconnect one to thirty-two originating time stages and terminating time stages.
Figure 4 is a diagram representing the interconnection of sixty-four time and control units (TCU) to the space stage.
Figure 5 is a block diagram of a time and control unit including the interface arrangement of the present invention.

DESCRIPTION OF TOE PREFERRED EMBODIMENT
Figure 1, is a block diagram showing the single rail structure of a time-space-time network of a digital switching system for switching a local telephone call. Telephone subscriber A is connected to analog facility interface unit (FOE 10. The analog FLU has a PAM voice connection to time and control unit (TCU) 0. The digital switching network may contain n number of Thus but will be limited to sixty four Thus for this embodiment. Each TCU
has two time stages associated with it, an originating time stage (OUTS) and a terminating time stage (TTS)o Each time stage JOTS or TT5) of each TCU
may be connected to up to four Flus. Therefore, the number of time control units (Thus) is modularly expandable and may grow to fit the needs of the switching system. Next, a connection is made from the OUTS of the particular TCU, in this example TV 0 to the space stage 30 and the terminating time stage of TCU 63.
The telephone subscriber B is then connected through analog FLU 20 to the TOTS of TCU 63.
voice transmission link is next established from subscriber B to subscriber A. This communication link is established via analog FLU 20, to the origin noting time stage (OUTS) of TCU 63~ through space stage 30, through the terminating time stage (TOTS) of TCU
0, and finally through analog FLU 10 to subscriber A. At this time, a two way talking path has been established between subscribers A and B.
Turning now to Figure 2, a representation of the 64 x 64 space stage 30 of Figure 1 is thus-treated. The space stage is comprised of four identical space stage units (SUE) 0, I 2, and 3. Each space stage unit is a 32 x 32 matrix having 32 inputs (0 to 31 for SUE I and SUE 2 and 32 to 63 for SUE 1 and SUE I and 32 outputs (0' to 31' for SUE 0 and SUE
3, and 32' to 63' -for SUE 1 and SUE 2). Connecting paths between the inputs and outputs of each SUE are controlled by a central control complex 60 through a space stage unit controller (SEIKO) 50. The SEIKO
interfaces the central control complex to each SUE
and controls and directs the data between the Swiss and the central control complex. The SEIKO communicates with each SUE module via a bus 51 which includes address, data and control lines.
Turning now to Figure 3, a schematic diagram representing a SUE of the present invention is thus-treated. It should be noted, that the SUE represented in Figure 3 is identical for each SUE, i.e. SUE 0, SUE 3, etc., shown in Figure 2.
PAM samples from the Thus of the T-S-T net-work enter and exit the SUE through a space stage driver/receiver (5SDR) interface ape. It should be noted twelve bits are required to represent the PAM sample, seven bits representing the amplitude of the voice signal, one bit represents the sign of the voice signal, three bits of supervisory signals and one parity bit Therefore, each input to the SUE from a TCU and each output to a TCU from the SUE
is twelve bits wide. Each SSDR includes drivers and receivers as well as buffers for temporarily storing PI samples before they are sent out to the space stage matrix units (SSMU). Each SSDR ape can interface thy OUTS and TOTS of two Thus to the SUE
For example, input 32 of SSDR aye would be connected to the OUTS of TCU 0 for SUE 0 and SUE 2 and to the OUTS of TCU 32 for SUE 3 and SUE 1. Output 33 of SSDR
aye would be connected to the TOTS of TO 0 or 32.
The space stage matrix provides a time shared switching path between the OUTS and TOTS of an individ-vat TCU or between the OUTS and TOTS ox different Thus.
The space stage matrix is comprised of four identical 16 x 16 space stage matrix units (SSMU) Audi.
Each SSMU is constructed from a plurality of 16:1 multiplexes. The multiplexes are combined into a 16 x 16 SSMU which is 12-bits wide. Control signals I.

supplied to each multiplexer selects and enables the appropriate multiplexes for switching through the space stage matrix. The control signals are applied to each SSMU via a space stage memory control (SMOKY).
Each space stage memory control aye consists of four control memories Cams (not shown) and their associated buffers. Each CM corresponds to a paretic-ular TCU TOTS. Each CM selects, through control data written within the CM, which one of the sixteen input samples will be output. Address, data and control information are read into each SMOKY via a space stage memory control interface ~SSMCI). The SSMCI 35 can control eight Smocks thereby interfacing each SUE to SEIKO 50 and central control complex 60 of Figure I
Finally a timing generator or master clock receiver/distributor ~MCRD) 37 is included which provides all the necessary timing signals for the operation of the SUE. The MUD terminates a master clock signal from a network clock unit UNCUT and distributes a timing reference to the SSDRs, the Smocks and the SSMCI.
With renewed reference to Figure 3, a de-ascription of the operation of a SUE will be explained.
PAM samples from the OUTS are written into a buffer within the appropriate SSDR, addressed and stroked with timing signals transmitted from the sending TCU
with the PAM samples. For example, in Figure 3 the sample is transmitted from the TCU 0 on input 32 into a buffer within SSDR aye. The written sample is latched out to the space slave matrix one time slot after the sample was written into the SSDR. This time slot is referred to as n l. In time slot no before time slot n + l, a path through the SUM is selected by reading the control memory within the appropriate SMOKY At the beginning of time slot n 1 the data written in the CM enables the appropriate multiplexes within the SSMU used to output the PAM

sample. The PAM sample available at the SSDR buffer at the beginning of time slot n -I 1 is allowed to ripple through the addressed multiplexes and latched into the selected SSDR for transmission to a TCU near the end of the time slot. For example r the data written into the control memory associated with the TOTS of TCU O of SMOKY aye, sets up a path through the space stage matrix from the O input to the O output of SSMU aye. The PAM sample is latched into the appropriate buffer within SSDR aye and sent to the TOTS of TCU 0. In this manner each SUE is selectively able to provide switching paths between the thirty-two originating time stages and terminating time stages of thirty-two Thus.
Turning now to Figure 4, the complete arrange-mint for a 64 x 64 space stage for a T-S-T network is illustrated. As can be seen the arrangement is comprised of a space stage which includes four Swiss;
Swiss 0, 1, 2, and 3. Each SUE shown in Figure 4, includes the requisite SSDR interfaces.
The four SUE modules are interconnected providing time shared switching paths to sixty-four Thus . The sixty-four Thus are divided into a first time group, including Thus O through 31 and a second time group, including Thus 32 through I Each SUE
is additionally categorized as either an intergroup, (SUE O and SUE I or an inter-group (SUE 2 and SUE
I The intergroup SUE O interconnects the OUTS and TOTS of Thus O through 31. Likewise, intergroup SUE
1 interconnects -the OUTS and TOTS of Thus 32 through 63. Time shared switching paths between the first time group of Thus (0-31) and the second time group of Thus (32-63) is accomplished with the inter-group Swiss; SUE 2 and SUE 3. SUE 2 connects the Otis of Thus O through 31 to the Toss of Thus 32 through 63 and SUE 3 connects the Otis of Thus 32 through 63 to the Toss of Thus O through 31.
I

For example, to establish a communications path from the OUTS to TCU O to the TOTS of TCU 31, TCU O is connected to SUE O
through sending line INTRO 0, SSDR 0, input line O of SUE 0, through the SUM to output line 313 SSDR 15 and finally to TCU 31 via receiving line INTRO 0. A return path interconnection can be effected between the OUTS of TCU 31 and the TOTS of TCU O via TCU
31s sending line INTRO 0, SSDR 15, input line 31 through the SUM
to output line 0, SSDR O and to TCU O via receiving line INTRO 0'.
Switching paths between the first time group Thus can be established in any combination through SUE O in the same manner described above.
Likewise, the second time group to Thus (32-63) can be interconnected via sending/receiving lines INTRO 1, INTRO 1' respectively and the input/output lines of SUE 1.
To effect a switching path from the OUTS of TCU O to the TOTS of TCU 63 a connection is made via sending line INTER 2 of TCU
0, SSDR O of SUE 2, to input line O of SUE 2, through the SUM to output line 63, SSDR 15, and receiving line INTER 2' to TCU 63.
The return connection to TCU O is effected through SUE 3 via the sending line INTER 3 of TCU 63 through SUE 3 to receiving line INTER 3' of TCU 0.
As can be readily seen in Figure I, SUE 2 is arranged to connect the Otis of Thus O through 31 to the Toss of Thus 32 through 63. Conversely, SUE 3 connects the Otis of Thus 32 through 63 to the Toss of Thus O through 31. Thereby, effectively interconnecting all sixty-four Thus in the T-S-T network through the space stage.
Figure 5, shows a particular TCU and the arrangement used to interface each TCU to the intro and inter Swiss. Each TCU
is controlled by a peripheral processor (PUP) 70. This processor may comprise the INTEL 8086 microprocessor or other similar INTEL
unit. INTEL is a trademark of the INTEL Corporation.

":~

Each stage of the TCU, i. e. originating time stage (OUTS) and terminating time stage TOTS includes an information memory and a control memory. For example, the OUTS shown, includes an information memory originating (IMP) 15 and a control memory originating 16~
Microprocessor interface 80 connects PUP
70 to each of the control memories. These connections include an address and data bus and suitable controls for reading and writing the memory, along with clock signals. The information memories 15 and 17 each contain information memory units with PAM samples.
As described previously in Figure 1 each TCU has a capability of being connected to four Flus. Each FLU provides for 193 channels of information to be transmitted to the information memory. Fish inform motion memory contains PAM samples representing the amplitude and sign of the voice signal. Twelve bits are required to represent the voice signal, seven bits representing the amplitude of the voice signal, one bit represents the sign of the voice signal, three bits of supervisory signals and one parity bit.
The control memory originating 16 and control memory terminating 18 each contain data which is provided by the PUP 70 defining the input-output time slot relationship of the IMP 15 and IT 17 respectively.
Mach channel originating from an FLU, is assigned a redefined time slot address in the IMP 15.
PAM samples are transmitted to the space stage units from the IMP 15 via a first bus 21 and intro SO driver 13 and a second bus 22 and inter SUE driver 14. Since each PAM sample is comprised of 12 bits each of the buses includes 12 lines as well as a driver for each line. Drivers I and 14 are identical and each transmit PAM samples to the space stage simultaneously. The intro and inter SUE
drivers 13 and 14 thereby send the same sample to both the intro and inter Swiss. The switched path I

through the space stage is selected by the central control complex by writing to the appropriate SMOKY
control memory corresponding to the receiving TCU, as described earlier in Figure 3.
Depending therefore upon the selected no-ceiling TCU the switched path through the space stage is either via one of the intro Swiss or one of the inter Swiss. The arrangement also allows for switching the PAM sample through both the intro and inter Swiss simultaneously to a receiving TCU in each time group, i.e. the sample may originate in TCU 00 and switched simultaneously to TCU 31 intro SUE) and TCU 63 (inter SUE). The sample sent to the non-selected SUE is ignored and replaced by the next PAM sample to key switched.
Intro SUE buffer 11 and inter SUE buffer 12 receive PAM samples from their respective Swiss along buses 23 and I respectively, for transmission to the IT 17 of the TCU TOTS. The outputs of each buffer 11 and 12 is connected to a instate gates 41 and 42 respectively Gates I 42 are controlled by the PUP 70 via the control memory terminating 18 and are selectively enabled to connect the output of SUE buffer 11 or the output of SUE buffer 12 Jo IT 17. Gate 41 is enabled via lead 13 when PAM data is within the same TCU set (0 through 31, 32 through 63). Gate 42 enabled via lead 21 when PAM data is from the inter Swiss or between groups 0 through 31 to groups 32 to I
It can be well appreciated by those skilled in the art that even though a single rail arrangement has been illustrated, a second duplicate copy of the space stage can be used in those T-S T networks em-plying A and B rails. For example, a fully indepen-deftly operating space stage would handle all time shared switching paths between Thus on the A rail and similarly a second space stage would handle all switching between Thus on the B rail. Both space { ? 'I

stages would be identical to the other working indepen~
deftly handling switching between the Thus connected to their respective rails. Thereby, the space stage described in this embodiment may be copied identically for each rail and is not limited thereto.
It can be appreciated that each one of the functional modules of Figure 3 can be configured into circuit cards. The circuit cards in turn can be plugged into unit frames forming the SUE. The circuit cards within the unit frames may be interconnected by a back plane arrangement. The SSDRs of each SUE
in turn can be connected to the Thus via the applicable bidirectional or unidirectional cables thereby, Sims plifying back plane wiring and the interconnections between the time stage and the space stage of the T-S-T network.
The present invention has been described to the reference of a specific embodiment thereof, for the purpose of illustrating the manner in which the invention may be used to advantage. It will be appreciated by those skilled in the art that the invention is not limited thereto Accordingly, any and all modifications, variations or equivalent arrange mints which may occur to those skilled in the art should be considered to be within the scope of the invention.

Jo

Claims (6)

WHAT IS CLAIMED IS:

1. An interface for a time-space-time network for sending and receiving communications information comprising PCM
samples between a time and control unit and a space stage matrix having at least first and a second space stage units, each space stage unit forming a separate and distinct path through said space stage matrix and said time and control unit including an originating time stage having an information memory originating for storing said communications information, said information memory originating connected to a source of control signals, and a terminating time stage including an information memory terminating and a control memory terminating said control memory terminating connected to said source of control signals, said interface comprising:
sending means including at least a first bus driver having an input connected to said information memory originating of said time and control unit and an output connected to said first space stage unit and at least a second bus driver having an input connected to said first bus driver input and said second bus driver output connected to said second space stage unit, said sending means arranged to simultaneously transmit said communications information from said originating time stages information memory originating to each of said first and second space stage units responsive to said control signals;
first and second receiving means connecting said time and control unit to each of said first and second space stage units respectively, said first and second receiving means each arranged to receive communications from said first and second space stage units respectively; and selection means connected to each of said first and second receiving means and to said control memory terminating, and responsive to control signals from said control memory terminating said selection means connects said first or alternatively said second receiving means to said information memory terminating transmitting said communications information to said terminating time stage.

2. An interface for a time-space-time network as claimed in claim 1, wherein said originating time stage further includes a control memory originating connected to said information memory originating and said source of the control signals is a peripheral processor connecting said control memory originating to said processor via a microprocessor interface.

3. The interface for a time-space-time network as claimed in claim 1, wherein said communication information comprises PCM samples and said first receiving means comprises a first PCM bus connected to said first space stage and a first set of PCM buffers, and said second receiving means comprises a second PCM bus connected to said second space stage and a second set of PCM buffers, each of said first and second set of PCM buffers arranged to receive and temporarily store PCM samples sent to said interface from each of said first and second space stages respectively.

4. An interface for a time-space-time network as claimed in claim 3, wherein: said first and said second set of PCM buffers each include an output bus, and said selection means comprises of at least one first switchable gate having an input and an output, said first switchable gate input connected to said first PCM buffer and said first switchable gate output connected to said information memory terminating, and at least one second switchable gate having an input and an output and said second switchable gate input connected to said second PCM buffer and said second switchable gate output connected to said first switchable gate output, said first switchable gate including a control input connected to said control memory terminating, whereby responsive to a first control signal said first switchable gate is enabled transmitting said PCM samples from said first PCM buffer to said information memory terminating.

5. An interface for a time-space-time network as claimed in claim 4, wherein: said second switchable gate includes a control input connected to said control memory terminating and responsive to a second control signal from said control memory terminating, said second switchable gate is enabled transmitting said PCM samples from said second PCM buffer to said information memory terminating.

6. An interface for a time-space-time network as claimed in claim 3, wherein said source of control information is a peripheral processor connected to said control memory terminating via the microprocessor interface.