CA1223800A - Method of fabricating integrated circuit structures using replica patterning - Google Patents
Method of fabricating integrated circuit structures using replica patterningInfo
- Publication number
- CA1223800A CA1223800A CA000453211A CA453211A CA1223800A CA 1223800 A CA1223800 A CA 1223800A CA 000453211 A CA000453211 A CA 000453211A CA 453211 A CA453211 A CA 453211A CA 1223800 A CA1223800 A CA 1223800A
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- Prior art keywords
- layer
- etching
- except
- semiconductor structure
- depositing
- Prior art date
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- Expired
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000059 patterning Methods 0.000 title abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 125
- 238000000034 method Methods 0.000 claims abstract description 94
- 238000005530 etching Methods 0.000 claims abstract description 57
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 238000000576 coating method Methods 0.000 claims abstract description 25
- 239000011248 coating agent Substances 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims description 235
- 239000004065 semiconductor Substances 0.000 claims description 60
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 26
- 239000000377 silicon dioxide Substances 0.000 claims description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- 230000003362 replicative effect Effects 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000009499 grossing Methods 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229960002050 hydrofluoric acid Drugs 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- NQLVQOSNDJXLKG-UHFFFAOYSA-N prosulfocarb Chemical group CCCN(CCC)C(=O)SCC1=CC=CC=C1 NQLVQOSNDJXLKG-UHFFFAOYSA-N 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
A METHOD OF FABRICATING INTEGRATED CIRCUIT
STRUCTURE USING REPLICA PATTERNING
ABSTRACT OF THE DISCLOSURE
A method of defining narrow regions in an underlying integrated circuit structure includes the steps of depositing a first layer of material 12 having selected etching characteristics on the underlying integrated circuit structure, depositing a second layer of material 13 having etching characteristics different from the first layer 12 on the first layer 12, anisotropically etching the first layer 12 and the second layer 13 from all of the underlying integrated circuit structure 10 except for a desired region having a periphery which includes the narrow region, forming a coating 15 of smoothing material over all of the underlying integrated circuit structure 10 except for the first layer 12, and isotropically etching the first layer 12 to remove it from the surface of the underlying integrated circuit structure 10 to thereby define the narrow region.
Use of the process to fabricate a compact bipolar transistor structure is also disclosed.
STRUCTURE USING REPLICA PATTERNING
ABSTRACT OF THE DISCLOSURE
A method of defining narrow regions in an underlying integrated circuit structure includes the steps of depositing a first layer of material 12 having selected etching characteristics on the underlying integrated circuit structure, depositing a second layer of material 13 having etching characteristics different from the first layer 12 on the first layer 12, anisotropically etching the first layer 12 and the second layer 13 from all of the underlying integrated circuit structure 10 except for a desired region having a periphery which includes the narrow region, forming a coating 15 of smoothing material over all of the underlying integrated circuit structure 10 except for the first layer 12, and isotropically etching the first layer 12 to remove it from the surface of the underlying integrated circuit structure 10 to thereby define the narrow region.
Use of the process to fabricate a compact bipolar transistor structure is also disclosed.
Description
8~
50.4154/8332-34~FFFF07A
A METHOD GF FABRICATING INTEGRAT~D CIRCUIT
STRUCTURES USING REPLICA PATTERNING
Backqround of the Invention Field of the Invention This invention relates to integrated circuit structures and methods of fabricating them, and to a technique for fabric~ting integrated circuit structures utilizing replicating coatings and lateral etching tecnniques to reliably de~ine smaller features in integrated circuit structures than heretofore possible.
The invention also relates to integrated circuit struc-tures fabricated utilizing such techniques.
Description of the Prior Art Integrated circuit fabrication technology utilizing lateral etching processes is known. For ex~mple, in U.S. Patent 3,940,288, M. Takati et al.
teach several techniques fo~ fabricating transistors and asso^iated electrical connections. Some of these
50.4154/8332-34~FFFF07A
A METHOD GF FABRICATING INTEGRAT~D CIRCUIT
STRUCTURES USING REPLICA PATTERNING
Backqround of the Invention Field of the Invention This invention relates to integrated circuit structures and methods of fabricating them, and to a technique for fabric~ting integrated circuit structures utilizing replicating coatings and lateral etching tecnniques to reliably de~ine smaller features in integrated circuit structures than heretofore possible.
The invention also relates to integrated circuit struc-tures fabricated utilizing such techniques.
Description of the Prior Art Integrated circuit fabrication technology utilizing lateral etching processes is known. For ex~mple, in U.S. Patent 3,940,288, M. Takati et al.
teach several techniques fo~ fabricating transistors and asso^iated electrical connections. Some of these
2~ techniques utilize lateral etching and double diffusion technology to fabricate transistor structures. M. Paffen 2t al. in U.S. Patent 3,783,047, teach the fabrication of different integrated circuit structures which may ~e ~abricated utilizing lateral etching techniques.
2~ ~. Kamioka et al. in "A New Sub-Micron Emitter ~or~a~ion with Reduced Base Resistance for Ul~ra Higl apeed Devices," presented in December 1974 to the International Electron Devices Meeting, and publi~h~d at page 279 ~f the Technical Digest of that meeting
2~ ~. Kamioka et al. in "A New Sub-Micron Emitter ~or~a~ion with Reduced Base Resistance for Ul~ra Higl apeed Devices," presented in December 1974 to the International Electron Devices Meeting, and publi~h~d at page 279 ~f the Technical Digest of that meeting
3~ teach the fabrication of a compact NPN vertical transis-tor. ~he structure shown therein utli~es lateral etching techniques to define the emitter region. W. ~unter in ''New Edge-Defined Vertical-Etch Approaches Eor Sub-micrometer MOSFET Fabrication" presen~;ed at the 1980 '~ Lnternational ~le~tron Devices Meeting an~ des-~ribod yi beginning on page 764 of the Technical ~igest of that meeting teaches the fabrication of regions in MOS devices utilizing la'cer-al etching techniques and conformal coatings.
Summary of the Invention This invention provides a process for fabricatiny inte-grated circuit structures having very narrow regions on the order of less than one micron. The invention further provides a tech-nique by which smoothing coatings may be utilized to fabricate arbitrarily spaced apart narrow regions in an underlying integrated circuit structure. A smoothing coating is one which tends to fill in depressions in the underlying structure, thus tending to smooth or flatten the surface.
Thus, in accordance with one broad aspect of the inven-tion, there is provided a method of defining narrow regions in an underlying semiconductor structure comprising:
depositing a first layer of material having selected etching characteristics on the underlying semiconductor structure;
depositing a second layer of material having different etching characteristics from the first layer on the first layer;
removing the first layer and second layer from all of the un-derlying semiconductor structure except for desired regions each having a periphery which includes a narrow region;
etching the first layer inward only from the periphery to the narrow region to thereby remove all of the first layer except for the narrow region;
- 2a -~2~8~
coating all of the underlying semiconductor structure except where overlaid by the first layer with a non-conformal material;
removing all of the non-conformal material except where over-laid by the second layer; and removing the first layer to thereby define the narrow region in the underlying semiconductor structure.
In accordance with another broad aspect of the invention there is provided a method of fabricating a substantially planar layer of material overlying a semiconductor structure having a 0 non-planar surface comprising:
depositing a first layer of non-conformal material across the integrated circuit structure;
removing portions of the first layer wherever the first layer traverses a region of the semiconductor structure which is non-planar to thereby create a smoother surface than in the original integrated circuit structure; and depositing a second layer of non-conformal material across the upper surface of the first layer.
In accordance with another broad aspect of the invention there is provided a method of fabricating a transistor structure in a semiconductor substrate including a buried layer of first conductivity type overlaid by epitaxial semiconductor material comprising:
depositing a region of first material having a periphery, and having selected etching characteristics, on the epitaxial material;
- 2b - ~2~8~
depositing an overlying layer of second material having etch-ing characteristics different from those of the first material on the first region;
etching the first material inward only from its periphery to thereby define a narrow region;
forming a layer of third material containing an opposite con-ductivity type impurity over all of the epitaxial material except the narrow region overlayed by the first material;
removing the ~irst material from the narrow region; forming 0 insulating material over all of the third material;
depositing fourth material containing first conductivity type impurities over at least the narrow region; and treating the third and fourth materials to cause some of the first and opposite conductivity type impurity therein to move in-to the epitaxial semiconductor material.
In accordance with another broad aspect of the invention there is provided a method of replicating a pattern in an underlying semiconductor structure having a surface comprising:
first defining a pattern of first material on the surface of the semiconductor structure, the first material extending above the surface a first greater thickness;
then depositing a non-conformal coating on the surface of the semiconductor substrate and not on the first material, the non-conformal coating extending above the surface a second lesser thickness;
~2~
- 2c then removing the pattern; and then introducing selected impurities into the surface of the semiconductor substrate except where overlaid by the coating.
In accordance with another broad aspect of the inven-tion there is provided a method of defining narrow regions and un-derlying semiconductor structure comprising:
depositing a first layer of material having selected etching characteristics on the underlying semiconductor structure;
depositing a second layer of material having different etch-ing characteristics from the first layer on the first layer;
removing the first layer and the second layer from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region, the narrow re-gion not overlaid by the first layer but only by the second layer;
introducing first conductivity type impurity into all of the semiconductor structure except where overlaid by the second layer;
removing the second layer;
introducing opposite conductivity type impurity into all of the semiconductor structure including the narrow region; and coating all of the underlying semiconduc-tor structure except where overlaid by the first layer with a non-conformal material.
In accordance with another broad aspect of the invention there is provided a method of defining narrow regions in an under-lying semiconductor structure comprising:
- 2d - ~2~
depositing first, second, third, and fourth layers of material in that order, each having selected etching characteristics, on the underlying semiconductor structure;
removing the second, third and fourth layers from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region;
etching the third layer inward only from its periphery to the narrow region to thereby remove all of the third layer except for a portion overlying the narrow region;
coating all of the first and second layers with a non-confor-mal material except where the second layer is overlayed by the third layer;
anisotropically removing the non-conformal material except where overlaid by the first layer;
removing all remaining portions of the first and second layers, and all of the third layer except where overlaid by the non-con-formal material;
laterally etching the second layer inward from all portions of the second layer not coaited with non-conformal material.
lZ23~
Brief Description of the Drawinqs Figures 1 and 2 illustrate the general tech-ni~ue of replica patterning.
Figure 3 is a cross-sectional view of an integrated circuit structure i~cluding overlying layers of materials having different etching characteristics.
Figure is a subsequent cross-sectional view after removing part of the top two layers.
Figure 5 is a subsequent cross-sectional ~iew after laterally etching one of the layers.
Figure 6 is a subsequent cross-sectional view after coating the structure with replicating material and etching it back.
Fi~res 7 and 8 illustrate one process which may ~e applied to the structure of Figure 6, with:
Figure 7 illustrating a subsequent cross-sectional view after selectively and anisotropic etching of the structure shown in Figure 6, and Figure 8 illustrating a subsequent cross-sectional view after removal of the l~terally etched layer.
Figure 9 illustrates another process which may be applied to the structure of Figure 6 in which the overlying layer and the laterally etched layer are removed.
Figure 10 is a cross-sectional view of a semiconductor structure.
Figure 11 is a subsequent cross~sectional view after formation of a smoothing coating.
Figure 12 is a subsequent cross-sectional view after definition of additional regions in the substrate.
Figure 13 is a cross-sectional view of a semiconductor structure.
~5 Figure 14 is a subsequent cross-sectiona]
view after etching of layer 18.
Figure 15 is a subsequent cross-sectional view after formation of layer lS.
, ''' 122;~300 Figure 16 is a subsequ~nt cross~sectional view after removal of layers 13 and 12, and portions of 15 and 18.
Figure 17 is a subsequent cross-sectional S view after lateral etchIng of layer 18.
Figure 18 a subsequent crass-se~tional view after anisotropic etching of layer 17.
Figure 19 is a cross-sectional view of a semiconductor stxuct~re which may be fab-ricated uti-lG lizing known processes.
Figure 20 is a cross-sectional view after etching the field regions~
Figure 21 is a subse~uent cxoss-sectional view after laterally etching a layer near the top of the structure.
Figure 22 is a subsequent cross-sectional view after--formation of a thin layer of silicon dioxide, a layer of silicon nitride, and formation of the field oxide regions.
~0 Figure 23 is a subse~uent cross-sectional view of the structure shown in Figure 22 after deposi-tion of a layer of polycrystalline silicon and an overlyi~-g layer of smoothing material.
Figure 24 is a subsequent cross-sectional 2r after removal of a portion of the polycrystalline silicon and the non-conformal material.
Figure 25 illustrates the completed transistor structure.
DescriFtion of the Preferred Embodiments ~V Figures 1 and 2 illustrate the generalized technigue which I have discovered and term "replica patterning." Generally, replica patterning allows the fabrication of numerous self-aligned regions in a semiconductor structure. The technique of replica patterning is s~own in Figures 1 and 2, and further . embodiments of the technigue are shown in the remaining Figures.
i~Z38~0 As shown in Figure 1, a semiconductor sub-strate 26 has formed on its upper surface a region of selected material 30. Substrate 26 may comprise silicon or other semiconductor material, or may be a partially S completed semiconductor structure. For example, sub-strate 26 may comprise a semiconductor structure or an integrate~ clrcuit already having numerous regions formed therein.
~egion 30 may be any materlal formed on the upper surface of substrate 26 using any well-known technique. Suitable techniques include known photo-lithographic processes in widespread use in the inte-grated circuit fabricatlon arts, or other known techniques. Of particular advantage is a lateral etching technique described below in conjunction with Figures 3 through 5. After formation of region 30, the overall structure shown in Figure 1 may ox may not be processed using other known integrated circuit fabrica-tion processes, depending upon the ultimately desired ~0 structure. As an example of such a processing technique, the structure shown in Figure 1 has been subjected to ion implantation across the entire width 31 of the structure depicted. By choosing suitable well-known ions and implant energies, material 30 will act as a ~' mask for the ion implantation. In this manner, ions 29 will be implanted into substrate 26 everywhere excep~
where substrate 26 is protected by overlying region 30.
As next shown by Figure 2, a layer of repli~
cating material 35 is deposited across the upper surface 3~ of substrate 26. By appropriate selection of materials and application techniques as describ~d below, material 30 will flow and generally smooth itself as depicted~
In general, replicating material 35 will be a non-conformal material, that is, a material which is gener-ally self-leveling, and therefore, tends to follow only the larger features in the topography of the integrated circuit structure. Suitable replicating materials include photoresist, or other suitable polymers which 1.2238~(3 are flowable. In one embodiment of the invention material 35 is deposited over and around regian 30 in a thicker layer than eve~tually desired and then etched back to the same ar thinner thickness as layer 30.
S After formation of replicating layer 35, which will be a material having different physical properties from layer 30, particularly resistance to various chemical etching solutions, reactive ion etchins or plasma gases, material 30 may be removed to define an opening 36. For example, in one embodiment of the invention, material 30 comprises silicon dioxide and material 35 comprises photoresist. Thus silicon dioxide 3~ may be removed using a solution containing hydro-fluoric acid, without materially altering region 35.
After removal of materi~l 30, material 35 may be used as a mask for a subsequent process step. In Figure 2 material 35 has been used as a mask for the subseguent ion implantation of positive ions 37 as shown.
By virtue of replica patterning, the region of positive ions 37 will be self-aligned to the region of negative ions 29, that is, the alignment between the regions of positive and negative ions will not depend upon the align~ent tolerances of any apparatus used to control the implantation of the ions, but rather upon the fact that the coating of material 35 extends over all of the surface of substrate 26 except where prevented by region 30.
In another embodiment of my invention the technique described in Figures 1 and 2 is reversed. In 3C this embodiment the structure of Figure 2 is created first, for example, by forming layer 35 across the surface of substrate 26 and then removing it from region 36, using well know~ techniques. Positive ions may then be introduced, followed by formation of a coating 30 in opening 36. The surrounding matexial 35 is next removed and negative ions 29 introduced as shown by Figure 1 ~x~
In the fabrication of integrated circuit structures it is desirable to defi~e regions as com-pac~ly as possible. This enables the fabrication of larger numbers of active and/or passive electronic components in a given area, and thereby low~rs the cost of producing circuits containing these components. The techniques described in conjunction wi~h Figures 3 through 9 illustrate several techniques for fabricating regions (such as region 30 depicted in Figures 1 a~d 2) with typically smaller dimensions than may be obtained using photolithographic techniques. Figure 3 i5 a cross-sectional view of an integrated circuit structure which includes an underlying substrate 10 having over-lying layers 11, 12 and 13. The underlying substrate 10 may include various regions of different conductivity type to thereby form particul2r active and~or passive elect~anic components therein. To simplify the drawings these active and/or passive regions are not sho~n, however, as will be evident the presence or absenc~ of 2C these regions generally does not effect the pxocess of this invention, however, the particular sandwich struc-~ure shown may be adapted to different underlying materials. The overlying layers shown in Figure 3 have the characteristic that the middle layer 12 etches much more rapidly in a selected etching solution than do the top layer 13 or the bottom layer 11. For example, layer 11 may comprise polycrystalline silicon, layer 12 may comprise silicon dioxide (SiO~), and layer 13 may comprise silicon nitride (Si3N4). Such material~
satisfy the criterion that the center layer etch morP
rapidly than the top and bottom layers, because silicon dioxide etches readily in a solution of ammonium fluoride and hydrofluoric acid while silicon and silicon nitride are essentially unaffected by that solution.
3~ Typically layer 11 will be as thick as the total thick~
ness of layers 12 and 13 combined.
The structure shown in Figure 3 is anisotropic-a~ly etched to define a region of desir~d width 1~
~2238~1~
shown in Figure 4. This may be achieved, after using known photolil~ho~raphic techniques to define a mask to protect region 14, by usIng a pl~sma reactor and an etch gas comprising carbon tetrafluoride and hydrQ~en 5 to etch layers 12 and 13. The resulting structure is depicted in Figure 4.
The center layer 12 -s then selecti~ely and partially etched in a lateral direction as shown by Figure 5. This may be achieved by immersing the struc-1~ ture depicted in Figure 2 in the above buffered etchant.Such a solution will remove layer 12 laterally from each exposed surface at a rate of about 0.1 microns per minute. Accordingly, by careful control of the time during which the structure is etched, region 12 may be laterally etched to create overhangs ha~tng widths which may be less than the smallest width 14 definable using photolithographic techniques.
Next, a uniformly thick layer of replicating ~aterial 15 is formed ac~ass the entire structure shown in Figure 5. If the material is sufficiently fluid the structure depicted may be created by simply applying the layer of material 15 and then curing or otherwise treating the layer to adhere the coating to the under-lying structure.
The man~er in which the replicating material 15 is applied to the surface of the integrated circuit structure will depend upon the particular topography of the integrated circuit structure and the physical properties of material 15. If material 15 is less ; 3~ fluid, then it may be deposited across the surface of an integrated circuit structure having relatively small, widely spaced features, for example as shown in ~igu-res 5 and 6. If the features are larger, or more closely arranged, or if the replicating material is 3S relatively viscous, then particular processing may ke ~2~
required to obtain a sufficiently flat upper surface of material 15.
The particular processing utilized to obtain a sufficiently flat upper s~rface for m~terial 15 will depend upon the material and the structure of the circuit. For ex~mple, one such process is to deposit 2 single relatively thick layer of the material and then etch the material from the highest regions of the integrated circuit using a special mask for that purpose or a mask used to define those higher features. A
~ecGnd layer of replicating material 15 is then deposited and anisotropically etched to cre~te the flat upper surface depicted in Figure 6. The above technique allows replicating both very coarse and very fine features, and in general it may only be necessary to remove the material above or around the coarser geometries.
After the replicating material 15 is deposited, the structure is planar etched ~o expose the top layer 13 as shown in Figure 6. This may be achieved using well-known plasma or reactive ion etching technology and an etchant suitable for removing positive photoresist 15 such as oxygen, or other suitable techniques.
The structure shown in Figure 6 then may be further processed utilizing either of two techniques.
The first technique is described ~n conjunction with Figures 7 and 8, while the second technique is described in conjunction with Figure ~.
A~cording to the first technique the aniso-~0 tropic etching process described in conjunction withFigure 6 is continued until the exposed regions of material 15 are removed from the surface of layer 11 everywhere exc~pt beneath the protective layer 13. Ir.
this manner the structure shown in Figure 7 is created.
3'; Next, nitride layer 13 is etched anisotropically to remove it except where overlaid by layer 12. Th~
remaining portion of silicon dioxide layer 12 may thPn be removed using a suitable chemic~l or plasma etchant, followed by removing the pQrtion of layer 11 thereby exposed. Depending upon the desired str~cture, the portion of polycrystalline silicon layer ll betweçn nonconformal regions 15a and 15~ may be removed either isotropically or a~isotropically. The resulting struc-ture is shown in Figure 8, and may be used as a mask t~
impl2nt further impurities into substrate 10, or for other desired uses.
An alternative process which may be applied to the structure shown in Figure 6 is depicted in Fi~ure 9. The structure show~ in Figure 9 may be achieved from that shown in Fi~ure 6 by removing layer 13, then underlying ~ayer 12, and lastly the $hereby exposed portion of layer 11. In this manner a si~gle narrow opening 22 is made to the surface of substrate 10~ Opening 22 may be used to define other regions in substrate--10.
The techniques described in conjunction with Figures 3 through 9 may also be employed to define a narrow region other than the narrow region directly beneath layer 12 in Figure 5. The narrow region may also be the region beneath that portion of layer 13 which overhangs layer 12. In this manner using the techniques explained in conjunction with Figures 6 through 8 an annular band of mas~ing material comprised of layers 11 and lS may be defined on the surface of the semiconductor structure, Alternatively the techniques described in coniunction with Figure may be used to create a plurality of small openings 22 to the surface of the semiconductor substrate lO. This is achieved by forming a plurality of structures comprising layers 12 and 13 (as depicted in Figure 5) across the surface of layer ll in various desired locations.
3~ Another application of my invention is de-scribed in conjunction with Figures lO throug~ 12. As shown in Figure lO a pair of layers 12 and 13 are deposited or otherwise formed on a substrat~ lO and lZ238~0 defined using the same technigues described in conjunction with Figures 3 through 5. Using ion implant~tion, regions 40 of selected conductivity type may be intro-duced in the surface of substrate 10. In Figure 10 regions 40 are N conductivity type.
Next, as shown in Figure 11, layer 13 is removed using known integrated circuit fabrication techniques. P conductivity type impurities 41 are t~en introduced into the thereby exposed re~ions of substrate lG 10. By appropriate selection of impurity concentrations, the P conductivity type regions 41 will not overdope the N conductivity type regions 40. A layer of repli-cating material lS is then deposited across the surface of the substrate.
As then shown by Figure 12, layer 12 is removed and a fuxther N co~ductivity type region 42 formed. In this manner a lateral NPN transistor is formed; or a pair of lateral transistors having either coupled emitters or collectors, depending upon the ~0 connections made to region 42. Of course the conduc-tivity types may be reversed to create a pair of PNP
~ateral transistors.
Another embadiment of the invention is de-scribed in conjunction with Figures 13 through 18. As shown in Figure 13 using known processing technioues, a semiconductor structure is created which includes a substrate 10, an overlying silicon dioxide layer 17, a layer of silicon nitride 18, a second layer of silicon dioxide 12 and an overlyins layer of silicon nitride 3~ 13. The upper two layers are defined and laterally etched as previously explain~d to create the structure depicted. As shown in Figure 1~, layer 13 is used as a mas~ for anisotropically etching layer 18, which need not be completely removed depending upon the subsequent desired structure. In so doing the thickness of layer 13 will be reduced. If it is desired not to reduce the thickness of layer 13 by this step, then layer 13 may be fabricated from a different material than layer 18, ~2;~8C)l~
1;2 that is, a material which is resistant to the etching process used to define layer 18. A replicating coating 15 is then formed across the upper surface of silicon dioxide 17 to create the structure depicted in Figure 15. This may be achieved using the processing tech-niques described above in conjunction witn Figure 6.
In some embodiments polycrystalline silicon will be used in place of silicon nitride because of the relative ease of forming thick high quality coatings having predicta~le etch rates.
Layer 13 is then used as a mask for aniso-tropically etching layer 15 to remove all portions of }ayer 15, except that portion disposed beneath the overhanging portion of layer 13. Layer 13 itself is then removed using a suitable che~ical or plasma etching process. In a similar manner layer 12 is removed to~ether with the thereby exposed regions of layer 18 to create the structure depicted in Figure 16.
The lateral etching process described in conjunction with Figure 5 is then performed to undercut layer 18 from beneath layer 15 as shown in Figure 17.
Layer 17 may then be patterned using layer 15 as a mask. The structure shown in either ~igure 17 or Figure 18 may then be processed using the techni~ues described in conjunction with Figures 3-9 to create desired regions in substrate 10. In the manner depicted in Figures 13 through 18 the technigue of this invention may be repeatedly used to create narrow regions spaced closely together.
Figures 19 through 25 illustrate how the particular fabrication techniques described above may be utilized to manufacture an extremely compact transistor structure. The structure shown in Figure 19 may be achieved by using a variety of known processes.
The structure includes a P conductivity type substrate 50, an N conductivity type buried layer 51, an instrinsic epitaxial layer 52, an overlying layer 53 of silicon ~ioxide, and a top layer 54 of silicon nitrid In ~e 8~0 preferred embodiment a very thin layer of sili~on nitride 55 is formed between the silicon dioxide 53 and layer 52. One technique for achieving the illustrated structure of subs~rate 50, buried layer 51, and epitaxial layer 52 is disclosed in United States Patent 3,648,125 issued io Douglas L~ Peltzer and entItled "Method of Fabricating Integrated Circuits with Oxid'7ed Isolation and the Resulting Structure." In the preferred embo~i-ment substrate 50 will be doped to a concentration of 10l5 - 1017 atoms per cubic centimeter of boron, whilP
buried layer 51 will be doped to a concentration of approximately 2 x 1019 to 102 atoms per centimeter of antimony or arsenic. After deposition of epitaxial layer 52, silicon nitride 55, silicon dioxide 53 and silicon nitride 54 may be dep~sited. Silicon nitride layer 55 is 50-200 Angstroms thick, and is deposited after hardening the underlying structure by ion implan-tation or formation of thin polycrystalline silicon.
Silicon dioxide layer 53 is approximately 7000 Angstroms thick and may be fabricated by chemical vapor deposition.
As shown ln Figure 20, the structure is then etched to remove portions of layers 52, 53 and 54, and portions of buried layer 51 and substrate 50. For other embodi-ments in which the buried layer 51 is not to interconnect various regions above different parts of layer 51, a deeper etch (to the dashed-line marked deep etch) i5 performed~, or a combination of deep and shallow etch.
In the preferred embodiment for a deep etch, plasma containing carbon tetrafluoride and hydrogen is used to etch through silicon nitride 54 and silicon dioxide 53, and a plasma containing chlorine is used to etch through silicon layers 52 and 51 and a portion of substrate 50. The remaining Figures 21 through 25 assume tha~ a shallow etch has been performed, however, as will be evident, the process descri~ed in conjunction with those Figures will be the same regardless of whether a shallow etch or a deep etch was performe~
.
122~8~
i4 The field regions of ~he integrated circuit structure are then ion implanted to create a P conduc-tivity type region 56 which will be formed at the lower surface of t~e field isolation regio~s. These P t~pe regions 56 will prevent field inversion and function as channel stops. The unetched portions of nitride 54 and underlying layers prevent implantation of the P conduc-tivity type impurity into the central portion of sub-strate 50. The P type impurity concentration is not ~fficient to reverse the conductivity of region 51.
The appearance of the structure after implanting the field 56 is shown in Figure 20.
Using any desired isotropic process, silicon dioxide layer 53 is next laterally etched as shown in Figure 21. In the preferred embodiment this is achieved using buffered hydrofluoric acid. Any photoresist overlying nitride 54 is then chemically removed together with the remai~ing portion of silicon nitride layer 54.
Next, a thin layer, on the order of 5~0 Angstroms ~hick, Q~ silicon dioxide 58 is formed across the surface of the exposed portio~ of substrate 50, and silicon layers 51 and 52. Layer 58 is shown in Figure 22. This thermal process will also have the effect of diffusing the ions 56 used to prevent channel Lnversion, thereby creating a uniformly doped region 56 between substrate 50 and overlying silicon dioxide 58.
A layer of silicon nitride 60 is then formed across the upper surface of silicon dioxide layers 53 and 58 and on thin nitride layer 55. In the preferred embodiment this is achieved by a chemical vapor deposition process and results in a silicon nitride layer approximately 700 Angstroms thick.
After formation of silicon nitride 60, a relatively thick layer of replicating material 62 is 3' ~eposited across the structure. In the preferred embodiment layer 62 comprises spin-on glass, which is then densified at 900C. Typically 2 much thicker 38~
layer than ultimately desired is deposited and then etched back to create the structure shown.
The nitride layers 50 and ~5 are next removed from the upper surface of layer 52, except where thin nitride 55 is protected by region 53. This may be achieved using an anisotropic etching process, for example, reactive ion etching using SF6. Next, using chemical vapor deposition, a layer of polycrystalline silicon 65 is deposited across the upper surface of the structure as shown in Figure 23. Because polycrystalline silicon is a conformal material, a substantially uniformly thick layer across the underlying st~ucture will result.
The polycrystalline silicon 65 will be doped with a suitable P conductivity type impurity, for example, boron, to make layer 65 electrically conductive. This doping operation may be performed as a subsequent step after chemical vapor deposition of undoped polycrystal-line silicon, or polycrystalline silicon 65 may be deposited already doped. In the preferred embodiment ~0 polycrystalline silicon layer 65 is 3000 Angstroms thick and is doped to an impurity concentration of approximately 102 atoms per cubic centimeter with boron.
Across the upper surface of polycrystalline silicon 65 a rel~tively thick layer of replicating material 67 is formed. In the preferred embodiment material 67 will comprise densified spin cn glass Material 67 is then etched back to expose the upoer portion of polycrystalline silicon 65. The resulting surface of material 67 is shown by the dashed lines in Figure 2~. Next, using an anisotropic etch, th thereby exposed region of polycrystalline silicon 65 shown in dashed lines in Figure 24 and surrounding material 67 are etched below the rounded shoulder of the silicon as shown by line 1 in Figure 23. Then silicon 65 is selectively etched to a point approximately flush with the upper surface of the polycrystallin~ silicon 65 elsewhere on layer ~2. The remaining regions of smoothing material 67 and silicon dioxide 53 are then remo~ed using any suitable process, for example, ~ipping in bu~fered hydrofluoric acid. After removal of the upper portions of silicon nitride 60, P conductivity type impurities are implanted into epitaxial layer 52 to create what will function as the transistor's active base region. In the preferred embodiment an impurity concentration of appraximately 1013 atoms per square ~0 centimeter of boron is used. The appearance of the structure after removal of silicon dioxide 53 a~d implanting of the base is shown by the solid lines in Figure 24.
A relatively thin layer of silicon dioxide 70 is next formed across the upper surface of polycrystal-line silicon 65. In the preferred embodiment silicon dioxide-layer 70 is 200Q Angstroms thick and is formed by heating the underlying structure to a tempexature o~
800C in steam. This relatively thin layer of silicon dioxide 70 functions to electrically isolate underlying polycrystalline silicon 65 from layers of materials deposlted on top of oxide 70. Thin nitride 55 is then removed.
As shown in Figure 25, another layer of ~'~ polycrystalline silicon 72 is then deposited across the surface of silicon dicxide 70 and epitaxial layer 52.
Layer 72 may be deposited as undoped polycrystalline silicon and then doped with N conductivity type impuri-ties, or may be deposited and doped simultaneously. In ~Q the preferred embodiment layer 72 is 2000 Angstroms thick and is doped to a concentration of abou~ 10 atoms per cubic centimeter of phosphorous.
After formation of layer 72, the entire structure is heated to a temperature of 900C fo~ 30 ~S minutes. During this process P and N conductivity type impurities present in layers 6~ and 70 will diffuse out of those layers to form base contact,s 7~ and emitter 75 12238~)[) Although several embodiments of the processes of this invention and structure which may be fabricated utilizing those processes have been descri~ed, these embodiments are intended to be illustrative of the invention rather than limiting it. The full spirit and scope of the in~ention may be ascertained from the appended claims.
Summary of the Invention This invention provides a process for fabricatiny inte-grated circuit structures having very narrow regions on the order of less than one micron. The invention further provides a tech-nique by which smoothing coatings may be utilized to fabricate arbitrarily spaced apart narrow regions in an underlying integrated circuit structure. A smoothing coating is one which tends to fill in depressions in the underlying structure, thus tending to smooth or flatten the surface.
Thus, in accordance with one broad aspect of the inven-tion, there is provided a method of defining narrow regions in an underlying semiconductor structure comprising:
depositing a first layer of material having selected etching characteristics on the underlying semiconductor structure;
depositing a second layer of material having different etching characteristics from the first layer on the first layer;
removing the first layer and second layer from all of the un-derlying semiconductor structure except for desired regions each having a periphery which includes a narrow region;
etching the first layer inward only from the periphery to the narrow region to thereby remove all of the first layer except for the narrow region;
- 2a -~2~8~
coating all of the underlying semiconductor structure except where overlaid by the first layer with a non-conformal material;
removing all of the non-conformal material except where over-laid by the second layer; and removing the first layer to thereby define the narrow region in the underlying semiconductor structure.
In accordance with another broad aspect of the invention there is provided a method of fabricating a substantially planar layer of material overlying a semiconductor structure having a 0 non-planar surface comprising:
depositing a first layer of non-conformal material across the integrated circuit structure;
removing portions of the first layer wherever the first layer traverses a region of the semiconductor structure which is non-planar to thereby create a smoother surface than in the original integrated circuit structure; and depositing a second layer of non-conformal material across the upper surface of the first layer.
In accordance with another broad aspect of the invention there is provided a method of fabricating a transistor structure in a semiconductor substrate including a buried layer of first conductivity type overlaid by epitaxial semiconductor material comprising:
depositing a region of first material having a periphery, and having selected etching characteristics, on the epitaxial material;
- 2b - ~2~8~
depositing an overlying layer of second material having etch-ing characteristics different from those of the first material on the first region;
etching the first material inward only from its periphery to thereby define a narrow region;
forming a layer of third material containing an opposite con-ductivity type impurity over all of the epitaxial material except the narrow region overlayed by the first material;
removing the ~irst material from the narrow region; forming 0 insulating material over all of the third material;
depositing fourth material containing first conductivity type impurities over at least the narrow region; and treating the third and fourth materials to cause some of the first and opposite conductivity type impurity therein to move in-to the epitaxial semiconductor material.
In accordance with another broad aspect of the invention there is provided a method of replicating a pattern in an underlying semiconductor structure having a surface comprising:
first defining a pattern of first material on the surface of the semiconductor structure, the first material extending above the surface a first greater thickness;
then depositing a non-conformal coating on the surface of the semiconductor substrate and not on the first material, the non-conformal coating extending above the surface a second lesser thickness;
~2~
- 2c then removing the pattern; and then introducing selected impurities into the surface of the semiconductor substrate except where overlaid by the coating.
In accordance with another broad aspect of the inven-tion there is provided a method of defining narrow regions and un-derlying semiconductor structure comprising:
depositing a first layer of material having selected etching characteristics on the underlying semiconductor structure;
depositing a second layer of material having different etch-ing characteristics from the first layer on the first layer;
removing the first layer and the second layer from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region, the narrow re-gion not overlaid by the first layer but only by the second layer;
introducing first conductivity type impurity into all of the semiconductor structure except where overlaid by the second layer;
removing the second layer;
introducing opposite conductivity type impurity into all of the semiconductor structure including the narrow region; and coating all of the underlying semiconduc-tor structure except where overlaid by the first layer with a non-conformal material.
In accordance with another broad aspect of the invention there is provided a method of defining narrow regions in an under-lying semiconductor structure comprising:
- 2d - ~2~
depositing first, second, third, and fourth layers of material in that order, each having selected etching characteristics, on the underlying semiconductor structure;
removing the second, third and fourth layers from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region;
etching the third layer inward only from its periphery to the narrow region to thereby remove all of the third layer except for a portion overlying the narrow region;
coating all of the first and second layers with a non-confor-mal material except where the second layer is overlayed by the third layer;
anisotropically removing the non-conformal material except where overlaid by the first layer;
removing all remaining portions of the first and second layers, and all of the third layer except where overlaid by the non-con-formal material;
laterally etching the second layer inward from all portions of the second layer not coaited with non-conformal material.
lZ23~
Brief Description of the Drawinqs Figures 1 and 2 illustrate the general tech-ni~ue of replica patterning.
Figure 3 is a cross-sectional view of an integrated circuit structure i~cluding overlying layers of materials having different etching characteristics.
Figure is a subsequent cross-sectional view after removing part of the top two layers.
Figure 5 is a subsequent cross-sectional ~iew after laterally etching one of the layers.
Figure 6 is a subsequent cross-sectional view after coating the structure with replicating material and etching it back.
Fi~res 7 and 8 illustrate one process which may ~e applied to the structure of Figure 6, with:
Figure 7 illustrating a subsequent cross-sectional view after selectively and anisotropic etching of the structure shown in Figure 6, and Figure 8 illustrating a subsequent cross-sectional view after removal of the l~terally etched layer.
Figure 9 illustrates another process which may be applied to the structure of Figure 6 in which the overlying layer and the laterally etched layer are removed.
Figure 10 is a cross-sectional view of a semiconductor structure.
Figure 11 is a subsequent cross~sectional view after formation of a smoothing coating.
Figure 12 is a subsequent cross-sectional view after definition of additional regions in the substrate.
Figure 13 is a cross-sectional view of a semiconductor structure.
~5 Figure 14 is a subsequent cross-sectiona]
view after etching of layer 18.
Figure 15 is a subsequent cross-sectional view after formation of layer lS.
, ''' 122;~300 Figure 16 is a subsequ~nt cross~sectional view after removal of layers 13 and 12, and portions of 15 and 18.
Figure 17 is a subsequent cross-sectional S view after lateral etchIng of layer 18.
Figure 18 a subsequent crass-se~tional view after anisotropic etching of layer 17.
Figure 19 is a cross-sectional view of a semiconductor stxuct~re which may be fab-ricated uti-lG lizing known processes.
Figure 20 is a cross-sectional view after etching the field regions~
Figure 21 is a subse~uent cxoss-sectional view after laterally etching a layer near the top of the structure.
Figure 22 is a subsequent cross-sectional view after--formation of a thin layer of silicon dioxide, a layer of silicon nitride, and formation of the field oxide regions.
~0 Figure 23 is a subse~uent cross-sectional view of the structure shown in Figure 22 after deposi-tion of a layer of polycrystalline silicon and an overlyi~-g layer of smoothing material.
Figure 24 is a subsequent cross-sectional 2r after removal of a portion of the polycrystalline silicon and the non-conformal material.
Figure 25 illustrates the completed transistor structure.
DescriFtion of the Preferred Embodiments ~V Figures 1 and 2 illustrate the generalized technigue which I have discovered and term "replica patterning." Generally, replica patterning allows the fabrication of numerous self-aligned regions in a semiconductor structure. The technique of replica patterning is s~own in Figures 1 and 2, and further . embodiments of the technigue are shown in the remaining Figures.
i~Z38~0 As shown in Figure 1, a semiconductor sub-strate 26 has formed on its upper surface a region of selected material 30. Substrate 26 may comprise silicon or other semiconductor material, or may be a partially S completed semiconductor structure. For example, sub-strate 26 may comprise a semiconductor structure or an integrate~ clrcuit already having numerous regions formed therein.
~egion 30 may be any materlal formed on the upper surface of substrate 26 using any well-known technique. Suitable techniques include known photo-lithographic processes in widespread use in the inte-grated circuit fabricatlon arts, or other known techniques. Of particular advantage is a lateral etching technique described below in conjunction with Figures 3 through 5. After formation of region 30, the overall structure shown in Figure 1 may ox may not be processed using other known integrated circuit fabrica-tion processes, depending upon the ultimately desired ~0 structure. As an example of such a processing technique, the structure shown in Figure 1 has been subjected to ion implantation across the entire width 31 of the structure depicted. By choosing suitable well-known ions and implant energies, material 30 will act as a ~' mask for the ion implantation. In this manner, ions 29 will be implanted into substrate 26 everywhere excep~
where substrate 26 is protected by overlying region 30.
As next shown by Figure 2, a layer of repli~
cating material 35 is deposited across the upper surface 3~ of substrate 26. By appropriate selection of materials and application techniques as describ~d below, material 30 will flow and generally smooth itself as depicted~
In general, replicating material 35 will be a non-conformal material, that is, a material which is gener-ally self-leveling, and therefore, tends to follow only the larger features in the topography of the integrated circuit structure. Suitable replicating materials include photoresist, or other suitable polymers which 1.2238~(3 are flowable. In one embodiment of the invention material 35 is deposited over and around regian 30 in a thicker layer than eve~tually desired and then etched back to the same ar thinner thickness as layer 30.
S After formation of replicating layer 35, which will be a material having different physical properties from layer 30, particularly resistance to various chemical etching solutions, reactive ion etchins or plasma gases, material 30 may be removed to define an opening 36. For example, in one embodiment of the invention, material 30 comprises silicon dioxide and material 35 comprises photoresist. Thus silicon dioxide 3~ may be removed using a solution containing hydro-fluoric acid, without materially altering region 35.
After removal of materi~l 30, material 35 may be used as a mask for a subsequent process step. In Figure 2 material 35 has been used as a mask for the subseguent ion implantation of positive ions 37 as shown.
By virtue of replica patterning, the region of positive ions 37 will be self-aligned to the region of negative ions 29, that is, the alignment between the regions of positive and negative ions will not depend upon the align~ent tolerances of any apparatus used to control the implantation of the ions, but rather upon the fact that the coating of material 35 extends over all of the surface of substrate 26 except where prevented by region 30.
In another embodiment of my invention the technique described in Figures 1 and 2 is reversed. In 3C this embodiment the structure of Figure 2 is created first, for example, by forming layer 35 across the surface of substrate 26 and then removing it from region 36, using well know~ techniques. Positive ions may then be introduced, followed by formation of a coating 30 in opening 36. The surrounding matexial 35 is next removed and negative ions 29 introduced as shown by Figure 1 ~x~
In the fabrication of integrated circuit structures it is desirable to defi~e regions as com-pac~ly as possible. This enables the fabrication of larger numbers of active and/or passive electronic components in a given area, and thereby low~rs the cost of producing circuits containing these components. The techniques described in conjunction wi~h Figures 3 through 9 illustrate several techniques for fabricating regions (such as region 30 depicted in Figures 1 a~d 2) with typically smaller dimensions than may be obtained using photolithographic techniques. Figure 3 i5 a cross-sectional view of an integrated circuit structure which includes an underlying substrate 10 having over-lying layers 11, 12 and 13. The underlying substrate 10 may include various regions of different conductivity type to thereby form particul2r active and~or passive elect~anic components therein. To simplify the drawings these active and/or passive regions are not sho~n, however, as will be evident the presence or absenc~ of 2C these regions generally does not effect the pxocess of this invention, however, the particular sandwich struc-~ure shown may be adapted to different underlying materials. The overlying layers shown in Figure 3 have the characteristic that the middle layer 12 etches much more rapidly in a selected etching solution than do the top layer 13 or the bottom layer 11. For example, layer 11 may comprise polycrystalline silicon, layer 12 may comprise silicon dioxide (SiO~), and layer 13 may comprise silicon nitride (Si3N4). Such material~
satisfy the criterion that the center layer etch morP
rapidly than the top and bottom layers, because silicon dioxide etches readily in a solution of ammonium fluoride and hydrofluoric acid while silicon and silicon nitride are essentially unaffected by that solution.
3~ Typically layer 11 will be as thick as the total thick~
ness of layers 12 and 13 combined.
The structure shown in Figure 3 is anisotropic-a~ly etched to define a region of desir~d width 1~
~2238~1~
shown in Figure 4. This may be achieved, after using known photolil~ho~raphic techniques to define a mask to protect region 14, by usIng a pl~sma reactor and an etch gas comprising carbon tetrafluoride and hydrQ~en 5 to etch layers 12 and 13. The resulting structure is depicted in Figure 4.
The center layer 12 -s then selecti~ely and partially etched in a lateral direction as shown by Figure 5. This may be achieved by immersing the struc-1~ ture depicted in Figure 2 in the above buffered etchant.Such a solution will remove layer 12 laterally from each exposed surface at a rate of about 0.1 microns per minute. Accordingly, by careful control of the time during which the structure is etched, region 12 may be laterally etched to create overhangs ha~tng widths which may be less than the smallest width 14 definable using photolithographic techniques.
Next, a uniformly thick layer of replicating ~aterial 15 is formed ac~ass the entire structure shown in Figure 5. If the material is sufficiently fluid the structure depicted may be created by simply applying the layer of material 15 and then curing or otherwise treating the layer to adhere the coating to the under-lying structure.
The man~er in which the replicating material 15 is applied to the surface of the integrated circuit structure will depend upon the particular topography of the integrated circuit structure and the physical properties of material 15. If material 15 is less ; 3~ fluid, then it may be deposited across the surface of an integrated circuit structure having relatively small, widely spaced features, for example as shown in ~igu-res 5 and 6. If the features are larger, or more closely arranged, or if the replicating material is 3S relatively viscous, then particular processing may ke ~2~
required to obtain a sufficiently flat upper surface of material 15.
The particular processing utilized to obtain a sufficiently flat upper s~rface for m~terial 15 will depend upon the material and the structure of the circuit. For ex~mple, one such process is to deposit 2 single relatively thick layer of the material and then etch the material from the highest regions of the integrated circuit using a special mask for that purpose or a mask used to define those higher features. A
~ecGnd layer of replicating material 15 is then deposited and anisotropically etched to cre~te the flat upper surface depicted in Figure 6. The above technique allows replicating both very coarse and very fine features, and in general it may only be necessary to remove the material above or around the coarser geometries.
After the replicating material 15 is deposited, the structure is planar etched ~o expose the top layer 13 as shown in Figure 6. This may be achieved using well-known plasma or reactive ion etching technology and an etchant suitable for removing positive photoresist 15 such as oxygen, or other suitable techniques.
The structure shown in Figure 6 then may be further processed utilizing either of two techniques.
The first technique is described ~n conjunction with Figures 7 and 8, while the second technique is described in conjunction with Figure ~.
A~cording to the first technique the aniso-~0 tropic etching process described in conjunction withFigure 6 is continued until the exposed regions of material 15 are removed from the surface of layer 11 everywhere exc~pt beneath the protective layer 13. Ir.
this manner the structure shown in Figure 7 is created.
3'; Next, nitride layer 13 is etched anisotropically to remove it except where overlaid by layer 12. Th~
remaining portion of silicon dioxide layer 12 may thPn be removed using a suitable chemic~l or plasma etchant, followed by removing the pQrtion of layer 11 thereby exposed. Depending upon the desired str~cture, the portion of polycrystalline silicon layer ll betweçn nonconformal regions 15a and 15~ may be removed either isotropically or a~isotropically. The resulting struc-ture is shown in Figure 8, and may be used as a mask t~
impl2nt further impurities into substrate 10, or for other desired uses.
An alternative process which may be applied to the structure shown in Figure 6 is depicted in Fi~ure 9. The structure show~ in Figure 9 may be achieved from that shown in Fi~ure 6 by removing layer 13, then underlying ~ayer 12, and lastly the $hereby exposed portion of layer 11. In this manner a si~gle narrow opening 22 is made to the surface of substrate 10~ Opening 22 may be used to define other regions in substrate--10.
The techniques described in conjunction with Figures 3 through 9 may also be employed to define a narrow region other than the narrow region directly beneath layer 12 in Figure 5. The narrow region may also be the region beneath that portion of layer 13 which overhangs layer 12. In this manner using the techniques explained in conjunction with Figures 6 through 8 an annular band of mas~ing material comprised of layers 11 and lS may be defined on the surface of the semiconductor structure, Alternatively the techniques described in coniunction with Figure may be used to create a plurality of small openings 22 to the surface of the semiconductor substrate lO. This is achieved by forming a plurality of structures comprising layers 12 and 13 (as depicted in Figure 5) across the surface of layer ll in various desired locations.
3~ Another application of my invention is de-scribed in conjunction with Figures lO throug~ 12. As shown in Figure lO a pair of layers 12 and 13 are deposited or otherwise formed on a substrat~ lO and lZ238~0 defined using the same technigues described in conjunction with Figures 3 through 5. Using ion implant~tion, regions 40 of selected conductivity type may be intro-duced in the surface of substrate 10. In Figure 10 regions 40 are N conductivity type.
Next, as shown in Figure 11, layer 13 is removed using known integrated circuit fabrication techniques. P conductivity type impurities 41 are t~en introduced into the thereby exposed re~ions of substrate lG 10. By appropriate selection of impurity concentrations, the P conductivity type regions 41 will not overdope the N conductivity type regions 40. A layer of repli-cating material lS is then deposited across the surface of the substrate.
As then shown by Figure 12, layer 12 is removed and a fuxther N co~ductivity type region 42 formed. In this manner a lateral NPN transistor is formed; or a pair of lateral transistors having either coupled emitters or collectors, depending upon the ~0 connections made to region 42. Of course the conduc-tivity types may be reversed to create a pair of PNP
~ateral transistors.
Another embadiment of the invention is de-scribed in conjunction with Figures 13 through 18. As shown in Figure 13 using known processing technioues, a semiconductor structure is created which includes a substrate 10, an overlying silicon dioxide layer 17, a layer of silicon nitride 18, a second layer of silicon dioxide 12 and an overlyins layer of silicon nitride 3~ 13. The upper two layers are defined and laterally etched as previously explain~d to create the structure depicted. As shown in Figure 1~, layer 13 is used as a mas~ for anisotropically etching layer 18, which need not be completely removed depending upon the subsequent desired structure. In so doing the thickness of layer 13 will be reduced. If it is desired not to reduce the thickness of layer 13 by this step, then layer 13 may be fabricated from a different material than layer 18, ~2;~8C)l~
1;2 that is, a material which is resistant to the etching process used to define layer 18. A replicating coating 15 is then formed across the upper surface of silicon dioxide 17 to create the structure depicted in Figure 15. This may be achieved using the processing tech-niques described above in conjunction witn Figure 6.
In some embodiments polycrystalline silicon will be used in place of silicon nitride because of the relative ease of forming thick high quality coatings having predicta~le etch rates.
Layer 13 is then used as a mask for aniso-tropically etching layer 15 to remove all portions of }ayer 15, except that portion disposed beneath the overhanging portion of layer 13. Layer 13 itself is then removed using a suitable che~ical or plasma etching process. In a similar manner layer 12 is removed to~ether with the thereby exposed regions of layer 18 to create the structure depicted in Figure 16.
The lateral etching process described in conjunction with Figure 5 is then performed to undercut layer 18 from beneath layer 15 as shown in Figure 17.
Layer 17 may then be patterned using layer 15 as a mask. The structure shown in either ~igure 17 or Figure 18 may then be processed using the techni~ues described in conjunction with Figures 3-9 to create desired regions in substrate 10. In the manner depicted in Figures 13 through 18 the technigue of this invention may be repeatedly used to create narrow regions spaced closely together.
Figures 19 through 25 illustrate how the particular fabrication techniques described above may be utilized to manufacture an extremely compact transistor structure. The structure shown in Figure 19 may be achieved by using a variety of known processes.
The structure includes a P conductivity type substrate 50, an N conductivity type buried layer 51, an instrinsic epitaxial layer 52, an overlying layer 53 of silicon ~ioxide, and a top layer 54 of silicon nitrid In ~e 8~0 preferred embodiment a very thin layer of sili~on nitride 55 is formed between the silicon dioxide 53 and layer 52. One technique for achieving the illustrated structure of subs~rate 50, buried layer 51, and epitaxial layer 52 is disclosed in United States Patent 3,648,125 issued io Douglas L~ Peltzer and entItled "Method of Fabricating Integrated Circuits with Oxid'7ed Isolation and the Resulting Structure." In the preferred embo~i-ment substrate 50 will be doped to a concentration of 10l5 - 1017 atoms per cubic centimeter of boron, whilP
buried layer 51 will be doped to a concentration of approximately 2 x 1019 to 102 atoms per centimeter of antimony or arsenic. After deposition of epitaxial layer 52, silicon nitride 55, silicon dioxide 53 and silicon nitride 54 may be dep~sited. Silicon nitride layer 55 is 50-200 Angstroms thick, and is deposited after hardening the underlying structure by ion implan-tation or formation of thin polycrystalline silicon.
Silicon dioxide layer 53 is approximately 7000 Angstroms thick and may be fabricated by chemical vapor deposition.
As shown ln Figure 20, the structure is then etched to remove portions of layers 52, 53 and 54, and portions of buried layer 51 and substrate 50. For other embodi-ments in which the buried layer 51 is not to interconnect various regions above different parts of layer 51, a deeper etch (to the dashed-line marked deep etch) i5 performed~, or a combination of deep and shallow etch.
In the preferred embodiment for a deep etch, plasma containing carbon tetrafluoride and hydrogen is used to etch through silicon nitride 54 and silicon dioxide 53, and a plasma containing chlorine is used to etch through silicon layers 52 and 51 and a portion of substrate 50. The remaining Figures 21 through 25 assume tha~ a shallow etch has been performed, however, as will be evident, the process descri~ed in conjunction with those Figures will be the same regardless of whether a shallow etch or a deep etch was performe~
.
122~8~
i4 The field regions of ~he integrated circuit structure are then ion implanted to create a P conduc-tivity type region 56 which will be formed at the lower surface of t~e field isolation regio~s. These P t~pe regions 56 will prevent field inversion and function as channel stops. The unetched portions of nitride 54 and underlying layers prevent implantation of the P conduc-tivity type impurity into the central portion of sub-strate 50. The P type impurity concentration is not ~fficient to reverse the conductivity of region 51.
The appearance of the structure after implanting the field 56 is shown in Figure 20.
Using any desired isotropic process, silicon dioxide layer 53 is next laterally etched as shown in Figure 21. In the preferred embodiment this is achieved using buffered hydrofluoric acid. Any photoresist overlying nitride 54 is then chemically removed together with the remai~ing portion of silicon nitride layer 54.
Next, a thin layer, on the order of 5~0 Angstroms ~hick, Q~ silicon dioxide 58 is formed across the surface of the exposed portio~ of substrate 50, and silicon layers 51 and 52. Layer 58 is shown in Figure 22. This thermal process will also have the effect of diffusing the ions 56 used to prevent channel Lnversion, thereby creating a uniformly doped region 56 between substrate 50 and overlying silicon dioxide 58.
A layer of silicon nitride 60 is then formed across the upper surface of silicon dioxide layers 53 and 58 and on thin nitride layer 55. In the preferred embodiment this is achieved by a chemical vapor deposition process and results in a silicon nitride layer approximately 700 Angstroms thick.
After formation of silicon nitride 60, a relatively thick layer of replicating material 62 is 3' ~eposited across the structure. In the preferred embodiment layer 62 comprises spin-on glass, which is then densified at 900C. Typically 2 much thicker 38~
layer than ultimately desired is deposited and then etched back to create the structure shown.
The nitride layers 50 and ~5 are next removed from the upper surface of layer 52, except where thin nitride 55 is protected by region 53. This may be achieved using an anisotropic etching process, for example, reactive ion etching using SF6. Next, using chemical vapor deposition, a layer of polycrystalline silicon 65 is deposited across the upper surface of the structure as shown in Figure 23. Because polycrystalline silicon is a conformal material, a substantially uniformly thick layer across the underlying st~ucture will result.
The polycrystalline silicon 65 will be doped with a suitable P conductivity type impurity, for example, boron, to make layer 65 electrically conductive. This doping operation may be performed as a subsequent step after chemical vapor deposition of undoped polycrystal-line silicon, or polycrystalline silicon 65 may be deposited already doped. In the preferred embodiment ~0 polycrystalline silicon layer 65 is 3000 Angstroms thick and is doped to an impurity concentration of approximately 102 atoms per cubic centimeter with boron.
Across the upper surface of polycrystalline silicon 65 a rel~tively thick layer of replicating material 67 is formed. In the preferred embodiment material 67 will comprise densified spin cn glass Material 67 is then etched back to expose the upoer portion of polycrystalline silicon 65. The resulting surface of material 67 is shown by the dashed lines in Figure 2~. Next, using an anisotropic etch, th thereby exposed region of polycrystalline silicon 65 shown in dashed lines in Figure 24 and surrounding material 67 are etched below the rounded shoulder of the silicon as shown by line 1 in Figure 23. Then silicon 65 is selectively etched to a point approximately flush with the upper surface of the polycrystallin~ silicon 65 elsewhere on layer ~2. The remaining regions of smoothing material 67 and silicon dioxide 53 are then remo~ed using any suitable process, for example, ~ipping in bu~fered hydrofluoric acid. After removal of the upper portions of silicon nitride 60, P conductivity type impurities are implanted into epitaxial layer 52 to create what will function as the transistor's active base region. In the preferred embodiment an impurity concentration of appraximately 1013 atoms per square ~0 centimeter of boron is used. The appearance of the structure after removal of silicon dioxide 53 a~d implanting of the base is shown by the solid lines in Figure 24.
A relatively thin layer of silicon dioxide 70 is next formed across the upper surface of polycrystal-line silicon 65. In the preferred embodiment silicon dioxide-layer 70 is 200Q Angstroms thick and is formed by heating the underlying structure to a tempexature o~
800C in steam. This relatively thin layer of silicon dioxide 70 functions to electrically isolate underlying polycrystalline silicon 65 from layers of materials deposlted on top of oxide 70. Thin nitride 55 is then removed.
As shown in Figure 25, another layer of ~'~ polycrystalline silicon 72 is then deposited across the surface of silicon dicxide 70 and epitaxial layer 52.
Layer 72 may be deposited as undoped polycrystalline silicon and then doped with N conductivity type impuri-ties, or may be deposited and doped simultaneously. In ~Q the preferred embodiment layer 72 is 2000 Angstroms thick and is doped to a concentration of abou~ 10 atoms per cubic centimeter of phosphorous.
After formation of layer 72, the entire structure is heated to a temperature of 900C fo~ 30 ~S minutes. During this process P and N conductivity type impurities present in layers 6~ and 70 will diffuse out of those layers to form base contact,s 7~ and emitter 75 12238~)[) Although several embodiments of the processes of this invention and structure which may be fabricated utilizing those processes have been descri~ed, these embodiments are intended to be illustrative of the invention rather than limiting it. The full spirit and scope of the in~ention may be ascertained from the appended claims.
Claims (29)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of defining narrow regions in an underlying semiconductor structure comprising:
depositing a first layer of material having selected etching characteristics on the underlying semiconductor structure;
depositing a second layer of material having different etch-ing characteristics from the first layer on the first layer;
removing the first layer and second layer from all of the underlying semiconductor structure except for desired regions each having a periphery which includes a narrow region;
etching the first layer inward only from the periphery to the narrow region to thereby remove all of the first layer except for the narrow region;
coating all of the underlying semiconductor structure except where overlaid by the first layer with a non-conformal material;
removing all of the non-conformal material except where over-laid by the second layer; and removing the first layer to thereby define the narrow region in the underlying semiconductor structure.
depositing a first layer of material having selected etching characteristics on the underlying semiconductor structure;
depositing a second layer of material having different etch-ing characteristics from the first layer on the first layer;
removing the first layer and second layer from all of the underlying semiconductor structure except for desired regions each having a periphery which includes a narrow region;
etching the first layer inward only from the periphery to the narrow region to thereby remove all of the first layer except for the narrow region;
coating all of the underlying semiconductor structure except where overlaid by the first layer with a non-conformal material;
removing all of the non-conformal material except where over-laid by the second layer; and removing the first layer to thereby define the narrow region in the underlying semiconductor structure.
2. A method as in claim 1 wherein the step of removing the first layer is preceded by a step of removing the second layer.
3. A method as in claim 2 wherein the underlying semicon-ductor structure comprises silicon, the first layer comprises silicon dioxide, and the second layer comprises silicon nitride.
4. A method as in claim 1 wherein the step of removing the first layer and the second layer comprises anisotropically etching the first layer and the second layer.
5. A method as in claim 4 wherein the step of etching the first layer inward comprises isotropically etching the first layer.
6. A method as in claim 5 wherein the step of removing the first layer comprises isotropically etching the first layer.
7. A method of fabricating a substantially planar layer of material overlying a semiconductor structure having a non-planar surface comprising;
depositing a first layer of non-conformal material across -the integrated circuit structure;
removing portions of the first layer wherever the first layer traverses a region of the semiconductor structure which is non-planar to thereby create a smoother surface than in the original integrated circuit structure; and depositing a second layer of non-conformal material across the upper surface of the first layer.
depositing a first layer of non-conformal material across -the integrated circuit structure;
removing portions of the first layer wherever the first layer traverses a region of the semiconductor structure which is non-planar to thereby create a smoother surface than in the original integrated circuit structure; and depositing a second layer of non-conformal material across the upper surface of the first layer.
8. A method as in claim 7 wherein the step of removing is accomplished by etching.
9. A method as in claim 8 wherein the non-conformal mater-ial comprises photoresist.
10. A method of fabricating a transistor structure in a semi-conductor substrate including a buried layer of first conductivity type overlaid by epitaxial semiconductor material comprising:
depositing a region of first material having a periphery, and having selected etching characteristics, on the epitaxial material:
depositing an overlying layer of second material having etch-ing characteristics different from those of the first material on the first region;
etching the first material inward only from its periphery to thereby define a narrow region;
forming a layer of third material containing an opposite con-ductivity type impurity over all of the epitaxial material except the narrow region overlayed by the first material;
removing the first material from the narrow region; forming insulating material over all of the third material;
depositing fourth material containing first conductivity type impurities over at least the narrow region; and treating the third and fourth materials to cause some of the first and opposite conductivity type impurity therein to move into the epitaxial semiconductor material.
depositing a region of first material having a periphery, and having selected etching characteristics, on the epitaxial material:
depositing an overlying layer of second material having etch-ing characteristics different from those of the first material on the first region;
etching the first material inward only from its periphery to thereby define a narrow region;
forming a layer of third material containing an opposite con-ductivity type impurity over all of the epitaxial material except the narrow region overlayed by the first material;
removing the first material from the narrow region; forming insulating material over all of the third material;
depositing fourth material containing first conductivity type impurities over at least the narrow region; and treating the third and fourth materials to cause some of the first and opposite conductivity type impurity therein to move into the epitaxial semiconductor material.
11. A method as in claim 10 wherein first material comprises silicon dioxide.
12. A method as in claim 11 wherein the step of etching comprises etching isotropically.
13. A method as in claim 10 wherein the third material com-prises polycrystalline silicon.
14. A method as in claim 13 wherein the fourth material com-prises polycrystalline silicon.
15. A method as in claim 14 wherein the insulating material comprises silicon dioxide.
16. A method as in claim 14 wherein the step of treating comprises heating the third and fourth materials.
17. A method of replicating a pattern in an underlying semi-conductor structure having a surface comprising:
first defining a pattern of first material on the surface of the semiconductor structure, the first material extending above the surface a first greater thickness;
then depositing a non-conformal coating on the surface of the semiconductor substrate and not on the first material, the non-conformal coating extending above the surface a second lesser thickness;
then removing the pattern; and then introducing selected impurities into the surface of the semiconductor substrate except where overlaid by the coating.
first defining a pattern of first material on the surface of the semiconductor structure, the first material extending above the surface a first greater thickness;
then depositing a non-conformal coating on the surface of the semiconductor substrate and not on the first material, the non-conformal coating extending above the surface a second lesser thickness;
then removing the pattern; and then introducing selected impurities into the surface of the semiconductor substrate except where overlaid by the coating.
18. A method as in claim 17 wherein following the step of defining a pattern a step of introducing other impurities into the substrate except where overlaid by the pattern is performed.
19. A method as in claim 18 wherein both the selected and the other impurities are introduced by ion implantation.
20. A method as in claim 19 wherein the pattern is defined photolithographically.
21. A method as in claim 20 wherein the coating comprises photoresist.
22. A method of defining narrow regions and underlying semi-conductor structure comprising:
depositing a first layer of material having selected etching characteristics on the underlying semiconductor structure;
depositing a second layer of material having different etch-ing characteristics from the first layer on the first layer;
removing the first layer and the second layer from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region, the nar-row region not overlaid by the first layer but only by the second layer;
introducing first conductivity type impurity into all of the semiconductor structure except where overlaid by the second layer;
removing the second layer;
introducing opposite conductivity type impurity into all of the semiconductor structure including the narrow region; and coating all of the underlying semiconductor structure except where overlaid by the first layer with a non-conformal material.
depositing a first layer of material having selected etching characteristics on the underlying semiconductor structure;
depositing a second layer of material having different etch-ing characteristics from the first layer on the first layer;
removing the first layer and the second layer from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region, the nar-row region not overlaid by the first layer but only by the second layer;
introducing first conductivity type impurity into all of the semiconductor structure except where overlaid by the second layer;
removing the second layer;
introducing opposite conductivity type impurity into all of the semiconductor structure including the narrow region; and coating all of the underlying semiconductor structure except where overlaid by the first layer with a non-conformal material.
23. A method as in claim 22 followed by the step of re-removing all of the non-conformal material except from beneath the second layer.
24. A method as in claim 22 followed by the step of remov-ing the first layer to expose the semiconductor substrate.
25. A method as in claim 22 followed by the step of re-moving the second layer.
26. A method as in claim 25 followed by the step of anis-otropically etching the non-conformal material to expose a nar-row region of the semiconductor substrate.
27. A method as in claim 26 followed by the step of intro-ducing impurities into the narrow region.
28. A method of defining narrow regions in an underlying semiconductor structure comprising:
depositing first, second, third, and fourth layers of mater-ial in that order, each having selected etching characteristics, on the underlying semiconductor structure;
removing the second, third and fourth layers from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region;
etching the third layer inward only from its periphery to the narrow region to thereby remove all of the third layer except for a portion overlying the narrow region;
coating all of the first and second layers with a non confor-mal material except where the second layer is overlayed by the third layer;
anisotropically removing the non-conformal material except where overlaid by the first layer;
removing all remaining portions of the first and second lay-ers, and all of the third layer except where overlaid by the non-conformal material;
laterally etching the second layer inward from all portions of the second layer not coated with non-conformal material.
depositing first, second, third, and fourth layers of mater-ial in that order, each having selected etching characteristics, on the underlying semiconductor structure;
removing the second, third and fourth layers from all of the underlying semiconductor structure except for desired regions, each having a periphery which includes a narrow region;
etching the third layer inward only from its periphery to the narrow region to thereby remove all of the third layer except for a portion overlying the narrow region;
coating all of the first and second layers with a non confor-mal material except where the second layer is overlayed by the third layer;
anisotropically removing the non-conformal material except where overlaid by the first layer;
removing all remaining portions of the first and second lay-ers, and all of the third layer except where overlaid by the non-conformal material;
laterally etching the second layer inward from all portions of the second layer not coated with non-conformal material.
29. A method as in claim 28 followed by the step of anis-otropically removing the first layer except where overlaid by the non-conformal material.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US490,622 | 1983-05-02 | ||
| US06/490,622 US4572765A (en) | 1983-05-02 | 1983-05-02 | Method of fabricating integrated circuit structures using replica patterning |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1223800A true CA1223800A (en) | 1987-07-07 |
Family
ID=23948834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000453211A Expired CA1223800A (en) | 1983-05-02 | 1984-05-01 | Method of fabricating integrated circuit structures using replica patterning |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4572765A (en) |
| EP (1) | EP0125174A3 (en) |
| JP (1) | JPS6041231A (en) |
| CA (1) | CA1223800A (en) |
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| KR890002801B1 (en) * | 1984-06-06 | 1989-07-31 | 가부시기가이샤 히다찌 세이사꾸쇼 | Plasma treating method and apparatus therefor |
| US4648173A (en) * | 1985-05-28 | 1987-03-10 | International Business Machines Corporation | Fabrication of stud-defined integrated circuit structure |
| US5114530A (en) * | 1985-10-31 | 1992-05-19 | Texas Instruments Incorporated | Interlevel dielectric process |
| US4654119A (en) * | 1985-11-18 | 1987-03-31 | International Business Machines Corporation | Method for making submicron mask openings using sidewall and lift-off techniques |
| US4631113A (en) * | 1985-12-23 | 1986-12-23 | Signetics Corporation | Method for manufacturing a narrow line of photosensitive material |
| US4670090A (en) * | 1986-01-23 | 1987-06-02 | Rockwell International Corporation | Method for producing a field effect transistor |
| JPS62199068A (en) * | 1986-02-27 | 1987-09-02 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US4737828A (en) * | 1986-03-17 | 1988-04-12 | General Electric Company | Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom |
| US4759821A (en) * | 1986-08-19 | 1988-07-26 | International Business Machines Corporation | Process for preparing a vertically differentiated transistor device |
| GB2202370B (en) * | 1987-02-27 | 1990-02-21 | British Telecomm | Self-aligned bipolar fabrication process |
| US4738624A (en) * | 1987-04-13 | 1988-04-19 | International Business Machines Corporation | Bipolar transistor structure with self-aligned device and isolation and fabrication process therefor |
| US4758306A (en) * | 1987-08-17 | 1988-07-19 | International Business Machines Corporation | Stud formation method optimizing insulator gap-fill and metal hole-fill |
| US4936930A (en) * | 1988-01-06 | 1990-06-26 | Siliconix Incorporated | Method for improved alignment for semiconductor devices with buried layers |
| US4927774A (en) * | 1988-06-10 | 1990-05-22 | British Telecommunications Plc | Self aligned bipolar fabrication process |
| JP2673380B2 (en) * | 1990-02-20 | 1997-11-05 | 三菱電機株式会社 | Plasma etching method |
| JP2615523B2 (en) * | 1992-02-19 | 1997-05-28 | 富士通株式会社 | Thin film circuit board and manufacturing method thereof |
| US5614146A (en) * | 1992-04-06 | 1997-03-25 | Sumitomo Heavy Industries, Ltd. | Method and apparatus of supplying labels to injection mold |
| DE69422234T2 (en) * | 1993-07-16 | 2000-06-15 | Matsushita Electric Industrial Co., Ltd. | Method of making a field emission device |
| US5667632A (en) * | 1995-11-13 | 1997-09-16 | Motorola, Inc. | Method of defining a line width |
| US6294102B1 (en) * | 1999-05-05 | 2001-09-25 | International Business Machines Corporation | Selective dry etch of a dielectric film |
| US7053005B2 (en) * | 2000-05-02 | 2006-05-30 | Samsung Electronics Co., Ltd. | Method of forming a silicon oxide layer in a semiconductor manufacturing process |
| KR100362834B1 (en) * | 2000-05-02 | 2002-11-29 | 삼성전자 주식회사 | Method for forming oxide layer in semiconductor manufacturing process and semiconductor device manufactured by using the same |
| KR100871967B1 (en) * | 2007-06-05 | 2008-12-08 | 주식회사 하이닉스반도체 | Method for forming fine pattern of semiconductor device |
| JP2009076867A (en) * | 2007-08-30 | 2009-04-09 | Sumitomo Electric Ind Ltd | Manufacturing method of semiconductor device |
| JP2009065000A (en) * | 2007-09-07 | 2009-03-26 | Tokyo Electron Ltd | Treating method for substrate, program, computer storage medium, and substrate treating system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| NL173110C (en) * | 1971-03-17 | 1983-12-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMI-CONDUCTOR DEVICE APPLICATING ON A SURFACE OF A SEMI-CONDUCTOR BODY AT LEAST TWO PART-LAYERS OF DIFFERENT MATERIAL COATING. |
| US3940288A (en) * | 1973-05-16 | 1976-02-24 | Fujitsu Limited | Method of making a semiconductor device |
| US4244799A (en) * | 1978-09-11 | 1981-01-13 | Bell Telephone Laboratories, Incorporated | Fabrication of integrated circuits utilizing thick high-resolution patterns |
| US4252582A (en) * | 1980-01-25 | 1981-02-24 | International Business Machines Corporation | Self aligned method for making bipolar transistor having minimum base to emitter contact spacing |
| US4387145A (en) * | 1981-09-28 | 1983-06-07 | Fairchild Camera & Instrument Corp. | Lift-off shadow mask |
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1983
- 1983-05-02 US US06/490,622 patent/US4572765A/en not_active Expired - Lifetime
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1984
- 1984-05-01 JP JP59086284A patent/JPS6041231A/en active Pending
- 1984-05-01 CA CA000453211A patent/CA1223800A/en not_active Expired
- 1984-05-02 EP EP84400874A patent/EP0125174A3/en not_active Withdrawn
Also Published As
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| EP0125174A3 (en) | 1987-01-14 |
| US4572765A (en) | 1986-02-25 |
| EP0125174A2 (en) | 1984-11-14 |
| JPS6041231A (en) | 1985-03-04 |
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