CA1221462A - Text comparator - Google Patents

Abstract

ABSTRACT
A text comparator includes word logic, delimiter logic, set logic, set combination logic, proximity logic, and programming logic. Delimiter logic serves to monitor characters transferred from a mass storage device and provides discrete signals depicting whether the character is a predefined delimiter character. Word logic serves to store data regarding predefined strings of characters and provides output word signals indicating when such predefined words have been located. Set logic receives delimiter signals and word signals and provides output signals when selected words are located in the same sentence, same paragraph, etc., as desired. Set combination logic serves to combine signals from the set logic in order to generate output signals in response to more complex search strategies than can be easily detected by the set logic. Proximity logic provides output signals indicating when predefined words detected by word logic 112, or predefined set of words detected by set logic 114, or a combination of this informa-tion, occurs within a predefined proximity. Programming logic serves to receive search strategy instructions from the user and provide the proper timing, addressing and data signals to the word logic, delimiter logic, set logic, set combination logic, and proximity logic to cause to be stored within these elements the information required to perform the desired search strategy.

Description

~;~2~4~;2 Background of the Invent on This application is a divisional of Canadian Patent Application, Serial Number ~80,692 filed May 3, 19~5 whlch, in turn, is a divisional of Canadian Patent Application Serial No. 420,092 filed January 24, 1983 and issued July 30, 1985 as Patent No. 1,191,263.
Field of the Invention This invention relates to a structure and method for searching computer data bases in order to locate and retrieve textual information.
Description of the Prior Art Prior art text comparators for searching a computer data base are known. Structures for carrying out such techniques (such structures are herein called "textual comparison systems") are used, for example, b~ Lockheed Dialog Information Retrieval Service, the United States Government "Flite" service, "Lexis", and others.
Such prior art textual comparison systems are software oriented in that a portion of the information stored in the computer (called a "data base") must be loaded into the computer working memory from a mass memory storage device (typically a magnetic disk). The portion of the data base within the working memory of the computer is scanned by the computer, as controlled by software instructions, in order to determine if any portion of the data base stored in the computer working memory matches the desired text. Typically the textual material comprising the data base is stored by using a set of standard ~;~2~46Z

l transfer of sequential portions of the data base from a

2 large storage media, such as a disk, to the computer memory,

3 and the computer must then utilize an itera~;ive process in order to determine whether the desLred text is contained 5 within that portion of the data base which has been 6 transferred to the computer memory. Because the computer 7 itself is performing the search, such prior art searching 8 techniques are rather slow, and consequently expensive due 9 to the large amount of computer time required to perform a lO search.

12 Another prior art comparator system is described in 13 United States Patent No. 4,152,762 issued May 1~ 1979 to 14 Bird et al. Bird et al describe a method and structure for text comparison which is rather complex and requires each 16 desired textual word or phrase to be stored in octal format l7 in one of a plurality of "key memories". In addition, the 18 Bird structure requires the use of additional memories, l9 including a "pointer memory" and a "hash memory", as well as a wide variety of other subcircuits. Thus, the Bird 21 structure is rather complex.

The present invention attacks the problem of text 26 comparison for tne purpose of retrieving textual information 27 from a large data base system from a different point of 28 view. In accordance with one embodiment of this invention, 29 information stored in a mass memory unit, such as a magnetic disk, as a plurality of bytes, each byte representing a 31 character, is input to a text comparison subcircuit which 32 includes a decoder means, decoded data memory, and one or 33 more logical operator sections. Each byte of inf`ormation 34 received from the dis~ is input to the decoder means and is immediately decoded, and a signal corresponding to the 36 character corresponding to the byte input to the decoder 37 means byte is generated. The system is capable of handling 38 up to P di~ferent characters, where P is a selected positive ., _ _, _ _ _ _ _ _ _ _ _ , . . .. . .... . .. . . . .. .. . .. ... .... .. . . .

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1 integer-3 Tlle decoded data mernory serves to store informatlon received rrom the decoder means pertaining to characters 5 represented by the bytes Or in~ormation received froM the 6 disk. The decoded data memory contains a plurality of P
7 serial in~parailel out shift registers, one shift register P
8 being uniquely associated with each one of the plurality of 9 P different characters forrning the data base stored in the storage device. Corresponding to the pth character (where p ll is an integer given by lSp<P) and contained within the 12 decoded data memory is a pth shift register uniquely 13 arranged to receive the signal from the decoder representing 14 the pth character. Upon receipt of a byte from the disk corresponding to a specific character, a first signal (e.g.
16 a binary zero) is applied to the serial input lead of the 17 shift register uniquely associated with the character de-18 coded by the decoder mean~s, and a second signal (e.g. a 14 binary one) is applied to the serial input lead of all shift registers associated with all other characters. A clock 21 signal is applied to each shirt register~of the decoded data 22 memory, thus shifting~the data on the input lead of each 23 shift register into the least significant bit of the shift 24 register, and shif~ting eacn bit previously stored in a shift register to the next most significant bit position within 26 the shift register. In this manner~, the-decoded data memory 27 will provide signals on the output leads of~each shift reg-28 ister indicative of the most recently received character, as 29 well as each of the preceding (K-1) characters (i.e. a "character string" comprising K characters) received from 31 the mass memory unit and decoded~, where K is the number of 32 bits contained in each shift register of the decoded data 33 memory. Thus, each bit stored within a shift register wiIl be a 34 binary one except ror the binary zero bits stored within a shift register corresponding to the location within the K bit 36 character string of a character corresponding to the shift 37 register. 0~ importance, only a single shift register within 38 the decoded data memory will store a binarr zero bit , .

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lZ;~1462 1 corresponding to each Or the K position~ within the K bit char-2 acter string. By examining the bit~ 5tored within each ~hift 3 regi~ter o~ the decoded data mernory, the o~laraoters cornpris-:

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lZ2i4~i2 l ing the K bit character strlng, anc~ t~leir relative position2 within the character string i5 determlned.

The output leads o~ the shi~t registers which provide 5 signals derilling t~le relative location of characters recently 6 received ~rom t~ne mass storage device and decoded by the de-7 coder means are connected to the input leads of a number of one 8 or more logical operator sections which include logical gates, 9 such as AND gates and ~0~ gates, in order to provide an output signal indicating that a desired textual phrase has been 11 located in the mass storage device.

13 The logical o?erator sections include word counters, para-14 graph counters, and other devices are employed as desired to provide special text comparison functions. The text comparison 16 sub-circuit, the decoded data memory, and the logical operator 17 sections o~ this invention are capable of operating at very high 18 speeds, equal to the data output spee~d of the mass memory unit, l9 thus providing a very high speed~textual comparison ope~ration.
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21 A second embodiment of a text comparator constructed in 22 accordance with this invention receives data stored in a mass 23 storage device. This embodiment includes word logic, delimiter 24 logic, set logic, set cornbination logic, proximity logic, and programming logic. The delimiter logic serves to monitor the 26 characters transferred froM~the mass storage device~and provides 27 a signal depicting whether the character~being transferred is a 28 predefined delimiter character and~,~if so, the type of delimiter 29 character. The word logic serves~ to store~data regarding pre-defined words (i.e.,~strin~s of charactersj~which are to be lo-31 cated and provides output signals i~ndica~ting when such prede-32 fined words have been located- The;set logic receives the de-33 limiter signals and word si~nals and provides output signals when 34 selected words are located in the same sentence, same paragraph, etc., as desired. The set combination logic serves to combine 36 the signals from t'ne set logic in order to generate output 37 signals in response to more complex search strategies then can be ~ ~ .

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lZ2~462 easily detected by the set logic. The proximity logic provides output signals indicating when predeElned words detected by the word logic, or predefined set of words, as detected by the set logic, or a combination of this information, occurs within a predefined proximity. For example, the proximity logic will determine if a first selected word occurs within N
(where N is a selected integer) words of a second preselected word.
In accordance with a broad aspect of the invention there is provided, in a textual comparison system, a word counter comprising a word counter shift register which is clocked upon receipt of a signal indicating the end of a word, wherein a first signal clears said shift register and provides a first input signal to said word counter shift register, and wherein input signals to said word counter shift register other than said first input signal are opposite said first input signal, whereby the location of said first input signal within said word counter shift register indicates the number of words decoded since the receipt of said first signal.
In accordance with another broad aspect of the invention there is provided, in a textual comparison system, a sentence counter comprising a sentence counter shift register which is clocked upon receipt of a signal indicating -the end of a sentence, wherein a first signal clears said shift register and provides a first input signal to said sentence counter shift register, and wherein input signals to said sentence counter shift register other than said first input signal are opposite said first input signal, whereby the location of said ~ZZ~4~

first input signal within said word counter shift register indicates the number of sentences decoded since the receipt oE said Eirst signal.
In accordance with another broad aspect of the invention there is provided, in a textual comparison system, a paragraph counter comprising a paragraph counter shlft register which is clocked upon receipt of a signal indicating the end of a paragraph, wherein a first signal clears said shift register and provides a first input signal to said paragraph counter shift register, and wherein input signals to said paragraph counter shift register other than said first input signal are opposite said first input signal, whereby the location of said first input signal within said paragraph counter shift register indicates the number of paragraphs decoded since the receipt of said first signal.
sRIEF DESCRIPTION OF THE D~AWINGS
Figure 1 i.s a block diagram of a textual comparison system constructed in accordance with this inventioni Figure 2 is a diagram of a decoder means utilized in accordance with this invention;
Figure 3 is a diagram showing the interrelation of Figures 3a and 3b;

- 5a -Figures 3a and 3b are diayrams of -the decoded data mem-ory eonstructed in aecordance with this invention;
Figure 4 is a diagram of one shift register of the de-' coded data memory of Figure 3;
Figures 5a through 5e are diagrams of specific embodiments of the logieal operator section of -this invention;
Figure 6a is a diagram o~ one embodiment of a word eount-er of this invention;

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l Figure 6b is a diaKram of one embodiment of a sentence 2 counter of this invention;

4 Figure ~c is a diagram o~ one embodiment of a paragraph

5 counter of this invention;

7 Figures 7a and 7b are diagrams of another embodiment of 8 the logical operator section of this invention;

Fig. 8 is a block diagrarn of a textual comparator ll construction in accordance with a second embodiment of this 12 invention;
13 Fig. 9 is a diagrarn depicting the relationship between l~ Figs. 9a, gb and 9c which form a schematic diagram of the delimiter logic 113 shown in Fig. 8;
16 Fig. 10 is a diagram depicting the relationship between 17 Figs. 10a-lOd which in turn form a schematic diagram of the set 18 logic 114 depicted in Fig. 8i ~
l9 Fig. 11 is a diagram which depicts the relationship between Figs. 11a and 11b which in turn form a schematic 21 diagram of the set combination logic 115 depicted in Fig. 8;
22 Fig. 12 is a diagram depicting the relationship between 23 Figs. 12a-12d which in turn form a schematic diagrarn of the 24 word logic 112 shown in Fig. 8; and Fig. 13 is a diagrarn depicting;the relationship between 26 Figs. 13a-13c which in turn form a~schematic diagram of the 27 proximity Iogic 117 shown in Fig. 8.

31 The following specification recites certain standard, 32 well-known, and generally available TTL components. These TTL
33 components are available from a number of suppliers, including 34 but not limited to those listed in the specification, and as will be appreciated by those of ordinary skill in th~e art, 36 thcse specified components can be used in accordance with the 37 teachings of this invention, regardless of the supplier. For 38 further reference, the Applicant cites the "National :
`

~Z21462 l Semiconductor TTL Data ~ook", l~ational Semiconductor 2 Corporation, 1976, the "Signetics 'rTL Logic Data Manual, 1982", 3 Signetics, 1982, and the "Signetics Low Po~er Schottky Pocket 4 Guide", Signetics, 1978.

6 FIRST EMBODIMENT
8 System Overview 9 Figure 1 shows a block diagram o~ a text comparator constructed in accordance with the first embodiment of this ll invention. Mass storase device 11 comprises a devlce suitable 12 for the storage of a large quantity of data.

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~ZZ~62 1 Such data is typically called a "da-ta base". The data 2 base might be, for example, teY~tual material such as 3 United States pa-tents, juclicial decisions fro~ various courts, or other information. Mass storage device ll typically comprises a magnetic disk, as is well known in 6 the computer arts, and the data base stored within mass

7 storage device ll is typically stored in ASCII format,

8 although this invention can be utilized in conjunction

9 with data bases stored in other than ASCII format (for example, EBCDIC).

12 Data stored in mass storage device ll is transferred 13 via bus lla to decoder 12. Typically, bus lla comprises a 14 plurality of electrical leads,~in order that a plurality of bits forming a single byte of information may be trans-16 ferred simultaneously from mass storage device ll to 17 decoder 12. The simultaneous~ transfer of a plurality of 18 bits forming a single byte is o~ften~referred to as "parallel 19 data output".
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21 Decoder ~12 receives each byte transferred from mass 22 storage device ll, and decodes ~that~byte into one of a 23 plurality of unique decoded data signals. Each such 24 decoded data signal represents a~unique one of the charac-ters which form the data base stored~ in mass storage 26 device ll. For example, such characters typically comprise 27 the numbers zero through nine,~ twenty-six capital letters, 28 twenty-six lower case letters, and~a variety of punctu-29 ation and special symbols such~a~s asterisk, period, comma, question mark, space, and the like. Inasmuch as ASCII is 31 one widely used method of coding such characters into a 32 plurality of bytes, this speciflcation will refer to ASCII
33 coding in order to explain the operation of one embodiment 34 of this invention. However, it is to be understood that this invention is equally useful in systems wherein coding 36 schemes other than ASCII is utilized. A cross reference 37 table listing each character and its ASCII equivalent is ~38 given in Table 1.

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1 The output ~rom decoder 12 is connected via bus 12a 2 to decoded data memory 13. Because ASCII comprises a 3 plurality of 96 characters, bus 12a in the preferred 4 embodiment comprises a plurality of 96 leads, one such lead being associated with a unique one of the ASCII
6 characters. However, it should be understood that as many 7 leads as required can be used depending on the number of 8 characters to be decoded and in general bus 12a comprises 9 a plurality of M leads, where M is a selected positive integer representing -the number of characters to be decoded.

12 Decoded data memory 13 stores the decoded data provided 13 by decoder 12 for a sequence of K characters stored in 14 mass storage device 11 where K is a positive integer which is fixed by the particular design of the decoded data 16 memory 13. Typically K ~will be either eight or sixteen, 17 although K may be any positive integer. Decoded memory 13 18 comprises a plurality of 96 shift registers, one shift 19 register for each ASCII character. K is equal to the number of bits which are stored within each shift register.
21 The data (i.e., a logical one or a logical zero) contained 22 in each of the K bits of the 96 shift registers of decoded 23 data memory 13 indicates which ASCII characters form each 24 character of the K byte character string ending in the most recently decoded character.

27 An output bus 13a, containing a number of leads equal 28 to K96 (K96 equals K multiplied by 96), connects each of 29 the K96 output leads of the 96 shift registers of decoded data memory 13 to logical operator section 14. Logical 31 operator section 14 comprises one or more logical gates 32 which perform a logical operation on the data stored in 33 the shift registers of decoded data memory 13. This 34 logical operation provides an output signal indicating when a desired textual phrase, string of characters, or 36 sets of strings of characters, has been located within the 37 data base stored in mass storage device 11. This output ~2Z~4~6Z
_9_ 1 signal from logical operator section 1~ is applied via bus 2 14a to central processing unit (CPU) 15. Thus, central 3 processing unit 15 is made aware that a desired te~tual 4 phrase has been located in mass storage device 11. CPU 15 then follows its se-t of programmed instructions, and 6 utilizes the desired textual phrase which has been located 7 in the data base. Typically, CPU 15 stores the address 8 location of the beginning of the desired textual phrase 9 which has been located in the data base, stores the record number of the record (i.e., patent number, etc.) in which 11 the desired textual phrase has been found, or performs 12 other desired tasks in response to the location and identi~
13 fication of the desired textual phrase within the data 14 base. It is to be understood that, once the desired textual phrase has been located within the data base 16 stored in mass storage device 11, and the CPU signalled by 17 logical operator section 14, the operation of CPU 15 is 18 generally the same as the operation of central processing 19 units in systems utilizing prior art text comparison techniques.

22 Decoder 12 23 Referring to Figure 2, the detailed operation of 24 decoder 12 will now be explained. The embodiment of decoder 12 shown in Figure 2 is designed for use with 26 systems utilizing ASCII coding. For systems utilizing 27 other than ASCII coding, the specific design of decoder 12 28 differs from that shown in Figure 2, but is easily provided 29 by one of ordinary skill in the art, in light of the teachings of this specification- In ASCII format, as 31 shown in Table 1, each character comprises eight binary 32 digits (bits) or two hexidecimal digits. Input bus lla 33 comprises eight leads, thus providing to decoder 12 in a 34 parallel output format the 8 bits forming a single ASCII
character stored in mass storage device 11 (Figure 1).
36 Input bus lla also comprises an additional lead 99, which 37 provides a valid data signal (VDA) which, when high (logical iZZ~462

-10-1 "1") indica-tes that valid da-ta is available on bus lla 2 from mass storage device :Ll. The four least significant 3 bi-ts (LSB) of the ASCII btye xeceived from bus lla are 4 applied to four bit buEfer B-1, thus providing on leads Do through D3 buffered signals representing the four least 6 significant bits of the ASCII byte. Similarly, the four 7 most significant bits (MSB) of the ASCII byte received on 8 bus lla are applied to four bit buffer B-2, thus providing 9 on leads D-7 through D-4 buffered signals representing the four most significant bits of the ASCII byte. Buffers B-l

11 and B-2 may comprise, for example, a 74125 device, such as

12 manufactured and sold by Texas Instruments.

13

14 The buffered four least significant bits (on leads Do through D3) are applied as input signals to demultiplexers 16 105-2 through 105-7 and the buffered four most significant 17 bits (on leads D-7 through D-4) are applied as input 18 signals to demultiplexer 103. Demultiplexers 103 and 19 105-2 through 105-7 are four bit to sixteen bit demulti-plexers such as the 74LS154 manufactured and sold by Texas 21 Instruments. Thus, each demultiplexer 103 and 105-2 22 through 105-7 provides a one of~sixteen bit demultiplexing 23 function, although only six of the sixteen output signals 24 from demultiplexer 103 (on leads R2 through R7) are used becausej as previously mentioned, ASCII comprises 96 26 characters,~and these 96 characters are uniquely defined 27 by the output leads of six separate four-to-sixteen bit 28 demultiplexers 105-2 through 105-7, as will be more fully 29 described below. Accordingly, as shown in Table 1, the four most significant bits of an ASCII byte range from a 31 binary 0001 (a decimal 1) to a binary 0111 (a decimal 7).

33 The output signal on each output lead of demulti-34 plexers 103 and 105-2 through 105-7 is normally high (logical one). Each demultiplexer has as many output 36 leads (16) as there are different binary input signals 37 (16) which can be applied to its four input leads. Each ..~

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1 output lead corresponds unique:Ly -to one possible input 2 signal to the demultiplexer. Ho~7ever, when a four bit 3 input signal (the four most signlficant bits on leads D-4 4 -through D-7 connected to demu:L-tiplexer 103, or the Eour least significant bits on leads Do through D3 applied to 6 demultiplexers 105-2 through 105-7) is input to a demulti-7 plexer, and that demultiplexer is enabled (to be more 8 fully described below), a logical zero is placed on the 9 output lead corresponding to the input signal applied to the demult.iplexer. For example, if a four bit binary 11 input signal 0101 is applied to a demultiplexer, and that 12 demultiplexer is enabled, the output lead 5 (corresponding 13 to a binary 0101) of the demultiplexer will be low, and 14 all other output leads of the demultiplexer-will be high.
A11 output leads of a disabled demultiplexer are high.

17 Demultiplexers 103 and 105-2 through 105-7 are enabled 18 by the appllcation of a low signal to their respective 19 enable terminals. This occurs only when valid data is present on bus lla from the mass storage device. As 21 previously described, a logical~one on valid data lead 99 22 indicates that valid data is present on bus lla. This 23 logical one signal is inverted by inverter 101a, and a 24 logical zero VDA signal is applied to NOR gate 102 and NOR
gates 104-2 through 104-7. Although NOR gates 102 and 26 104-2 through 104-7 are shown external to demultiplexers 27 103 and 105-2 through 105-7, these NOR gates are an integral 28 part of the 74LS154 devices. The output lead of NOR gate 29 102 is connected to the enable input lead of demultiplexer 103, and the output leads of NOR gates 104-2 through 104-7 31 are connected to the enable input leads of demultiplexers 32 105-2 through 105-7, respectively. Thus, with a low VDA
33 signal on lead 99, indicating that valid data is not 34 present on input bus lla, the VDA signal from the output lead of inverter 101a will be high, thus causing the 36 output signal from NOR gates 102 (having its other input 37 lead connected to ground) to be low, thus disabling 1;~2~46Z

1 demultiplexer 103. With demul-tiplexer 103 disabled, leads 2 R2 through R7 will all be ~ligh; thtls disabling demulti-3 plexers 105-2 through 105-7.
On the other hand, with a logical high on VDA lead 6 99, indicating that valid data is present on input bus 9, 7 the VDA signal will be lo~l. Because one input lead of NOR
8 gate 102 is connected to ground (logical zero) and the 9 other input lead of NOR yate 102 is connected to VDA, a low VDA signal causes the output signal from NOR gate 102.
11 to go high, thus enabling demultiplexer 103. Demulti-12 plexer 103 then demultiple.Yes the four most significant 13 bits, thus providing a logical low on the unique output 14 lead R2 through R7 corresponding to the value of the four most significant bits ~D4 through D7). Output Ieads R2 16 through R7 of demultiplexer 103 are connected to one input 17 lead of NOR gates 104-2 through 104~7, respectively, with 18 the other input lead of NOR gates 104-2 through 104-7 19 being connected to VDA. With a logical low VDA signal applied to one lead of NOR gates 104-2 through 104-7 and a :21 logical low signal corresponding to the demultiplexed most 22 significant bits of a unique one of leads R2 through R7 23 applied to the other lead of one of -the NOR gates 104-2 24 through 104-7, a high signal:will be generated on the output lead of the NOR gate 104-2 through 104-7 correspond~
26 ing to the value of the most significant bits D4 through D7.
27 Thus, upon receipt of valid data (high VDA signal) a 28 selected one of demultiplexers 105~2 through 105-7 will be 29 enabled, and all other demultiplexers 105-2 through 105-7 30 will be disabled by the logical high signaI on the re-31 maining leads R2 through R6 For example, with a high VDA
32 signal, indicating receipt of valid data, and the four 33 most significant bits e~ual to 0010, demultiple,~er 103 is ~~
34 enabled and a low signal generated on lead R2, with leads 35 R3 through R7 remaining high. Demultiple.Yer 105-2 is 36 enabled by the low VDA signal and the low signal on lead 37 R2. DemultipleXers 105-3 through 105-7 remain disabled by 38 the high level signals on leads R3 through R7, respectively.

.
, lZ~1~62 1 The output signals on each ou-tput lead of -the disabled 2 demultiplexers 105 2 through 105-7 ~7ill be high, as previ-3 ously described. The slgnals on the output leads of the h enabled one of demultiplexers 105-2 through 105-7 will be high, except for the single output lead which corresponds 6 to the decoded least significant bits on leads Do through 7 D3 connected to the input leads of demultiplexers 105-2 8 through 105-7. In this manner, upon -the receipt of valid 9 data on bus lla, a single low signal is genera-ted on a single output lead of demultiplexers 105-2 through 105-7.
11 The lead which contains that low signal corresponds to the 12 character represented by the 8-bit ASCII byte received on 13 bus lla. For example, with a high VDA signal and an eight 14 bit byte equal to 01101101 received on bus lla, demulti-plexer 103 will be enabled, as previously described, and 16 the four most significant bits (0110) demultiplexed by 17 demultiplexer 103, thereby generating a logical low signal 18 on output lead R6. This will enable demultiplexer 105-6, 19 which in turn demultiplexes the four least significant bits (1101), thereby generating the signals on a logical 21 low on output lead 6D of demultiplexer 105-6, with all 22 other output Ieads of demultiplexer 105-6 remaining high.
23 Output lead 6D corresponds to the ASCII character m, 24 represented by 01101101. A high signal is present on leads R2, R3, R4, R5 and R7, thus disabling demultiplexers 26 104-2, 104-3, 104-4, 104-5, and 104-7, thereby providing 27 high signals on output leads 20 through 5F and 70 through 28 7F. For convenience, the output leads from demultiplexers 29 105-2 through 105-7 are numbered~with two digits. The first digit indicates which of the six demultiplexers 31 105-2 through 105-7 is connected to the lead, and the 32 second digit indicates the lead number (represented in 33 hexidecimal as 0 through F). Utilizing this notation, the 34 first digit also represents the four most significant bits of the data word received on bus lla, and the second digit 36 also represents the four least significant bits of the 37 data word received on bus lla.

,.

l'L-1 Inverters lOla through lOlj provide a time delayed 2 VDA' signal. By applying -the valid data signal (VDA) on 3 lead 99 to the input lead of inverter lOla, a time delayed 4 valid data signal (VDA') is generated by inverte~ lOlj on S node 101. The VDA' signal is delayed from the VDA signal 6 by approximately 100 nanoseconds. The VDA' signal is used 7 to enable the decoded data memory 13 (Figure 1) to receive 8 data from output leads 20 through 7F of decoder 12, but 9 provides a time delay sufficient to allow the proper operation of decoder 12 prior -to the receipt of decoded 11 data by decoded data memory 13. Each inverter lOla through 12 lOlj may comprise, for example, one of -the six inverters 13 comprising a 7404 Hex inverter, such as is manufactured 14 and sold by Texas Instruments.

16 Decoded Data MemorY 13 17 Referring to Figures 3a and 3b, the operation of 18 decoded data memory 13 will now be explained. Upon the 19 receipt of a high VDA' signal (corresponding to valid data on input bus lla of decoder 12j on node 101 of decoded 21 data memory 13, buffer 201 provides high clock signals 22 CLK-2 through CLK-7. Buffer 201 may comprise, for example, 23 a 74365 device manufactured and sold by Signetics.

Decoded data memory 13 comprises a plurality of shift 26 registers such as shift register SR20. For purposes of 27 clarity, the plurality of 96 shift registers are not indi-28 vidually labelled; only shift register SR2~ is so labelled.
29 However, the array of shift registers of decoded data memory 13 of Figures 3a and 3b are arranged in a matrix 31 comprising six rows (row 2 through row 7) and sixteen 32 columns (column 0 through column F)- Thus, shift register 33 SR20 is the shift register located at the intersection of 34 row 2 and column 0. In a similar manner, the shift register located at the intersection of row n and column m will be 36 referred to as shift register SRnm in this specification.

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-15-1 Eactl shift reg:ister SRnm (~1here n and m are posi-tive 2 integers given by l~-n<=N and l~m~M) is connected to a 3 uni~ue one nm of leads 20 through 7F ~ich corresponds to 4 that shift register. Thus, shift register SR20 is con-nected to lead 20 and shift register SRnm is connected to6 lead nm. Leads 20, nm and ~ in turn are connected to the 7 decoder 12 of Figure 2. In this fashion, each shift 8 register of the decoded data memory 13 is connected to a 9 unique output lead of decoder 12 (Figure 2), thereby causing each shift register of decoded data me~ory 13 to 11 correspond to a unique one o~ the 96 ASCII characters.
12 For convenience, the ASCII character associated with each 13 shift register is indicated above the shift register.
~14 Thus, shift register SR20, connected to lead 2~, corres-ponds to a blank (b) which is~coded in ASCII as a hexi-

16 decimal "20", as shown in Table 1. In a similar manner,

17 each of the 96 shift registers of decoded data memory 13

18 corresponds to a unique ASCII character. As previously

19 mentioned, each shift reglster SRnm is capable of storing K bits, thus allowing decoded data memory 13 to store K
21 decoded characters and their relative posi-tion ~ithin the 22 string of K characters.

24 Clock signals CLK-2 through CLK-7 are connected to each shift register~within row;2~ thro~lgh row 7, respectively.
26 Upon the receipt of a high VDA' signal, CLK-2 thLough 27 CLK-7 go high. The low to high transition of clock signals 28 CLK-2 through CLK-7 enables all shift registers of rows 2 29 through 7, respectively, of decoded data memory 13.
Enabling each shift register causes the~ signal on the 31 signal lead connected to that shift register to be stored 32 in the least significant bit of the shift register, and 33 all other data previously stored shifted to the next most 34 significant bit. Thus, for example, if a logical zero is present on signal lead 2~, and a high VDA' signal is 36 received, CLK-2 will go high, thus causing the logical 37 zero on lead 20 to be stored in the least significant bit ~2Z~462 of shift register SR2~. All other da-ta previously stored 2 in shift register SR2~ ~ill be shifted to thc neV.t mos-t 3 significant bit, with the previously s-tored rnos~ signi-4 ficant bit being lost.

6 The plurality of shift registers comprislng decoded 7 data memory 13 may comprise, for example, eight bit serial 8 in, parallel out shift registers, such as 74164 devices 9 manufactured and sold by Signetics. Alternatively, each 0 shift register SR20 through SR7F may comprise a plurality of 74164 devices serially connected in order to increase 12 the number of bits which are stored within each of the 96 13 shift registers forming decoded memory 13.

Of importance, only a single logical zero will be 16 present on signal leads 2~-7F at any time. Thus, the 17 unique one of the 96 shift registers which corresponds to 18 the most recently decoded byte from mass storage device 11 19 will store a least significant bit equal to a logical zero, while all other shift registers will store a least 21 significant bit e~ual to a losical one. Thus, for example, 22 if a blank was the most recently decoded ASCII character, 23 decoded data memory 13 will indicate this fact by the 24 presence of a logical zero as the least significant bit of shift register 20, with the least significant bits of all 26 other shift registers SRnm being e~ual to a logical one.
27 In a similar fasion, the previously decoded character will 28 ~e indicated by the presence o~ a logical zero as the next 29 to least significant bit stored in the shift register corresponding to the previously decoded character. Thus 31 if an "!" was the previously decoded character, the next 32 to least significant bit stored within shift register SR21 33 (corresponding to the exclamation point) will be a logical 34 zero, and the next to least significant bit stored within all other shift registers will be a logical one. In this 36 manner, each of the most recently decoded K characters are 37 indicated by the location of logical zeros within the shift zz~

1 register of decoded data memory 13, where K is the nur~er 2 of bits stored in each shift register.

4 An exa~ple of the ability of decoded data rnemory 13 to store a character string which is decoded b~ decoder 12 6 (Figure 1) will now be given. Initially all bits contained 7 within each of the 96 shift registers of decoded data 8 memory 13, comprise logical ones. This may be accomplished, 9 for example, by providing a low VDA signal, thus disabling demultiplexers 105-2 through 105-7 (Figure 2), and thereby 11 providing logical one signals on leads 20 through 7F, and 12 providing a series of K low to high transitions on terminal 13 101, thus shifting a series of K logical one signals into 14 each K bit shift register (SR20 through SR7F~ of decoded data memory 13. These low to high transitions on terminal 16 101 are easily provided with well known circuitry (not I7 shown)-19 If the word "Work" is to be decoded by decoder 12, the 8 bits corresponding to the hexadecimal ASCII code 57 ~1 for a "W" will be output from mass storage device 11 to 22 input bus lla of decoder 12 (Fig. 2). A valid data signal 23 (high VDA) will also be made available on bus lla. Demulti-24 plexer 103 will be enabled, and a logical low signal generated on lead R5 corresponding to the most significant 26 bits of the ASCII code for W. The logical low on lead R5, 27 and the low VDA signal will enable demultiplexer 105-5.
28 Demultiplexer 105-5 then demultiplexes the least signifi-29 cant bits, and provides a logical low on output lead 57.
All remaining output leads of demultiplexers 105-2 through 31 105-7 remain high at this time. The output signals on 32 demuItiplexers 105-2 through 105-7 are then (after the 33 time delay provided by inverters lOla through lOlj) shifted ~~
34 into the least si~nificant bit positions of their cor-responding shift registers of decoded data memory 13 ,.

12%1~6Z

(Figure 3). Thus, the least signific~nt bit of shift reyister SR57 will s-tore a logical zero, and the least sign:i.Eicant bits oE
all remaining shi~t registers will store a logical one. The shift register SR57 will store the bits 1110, and all other shift registers will store the bits 1111, if shift registers SR20 through SR7F comprise four bit shift registers.
The letter "o" (hexadecimal 6F) is then output from mass storage device 11 to decoder 12 (Figure 2). Demultiplexer 103 decodes the four most significant bits D4 through D7 and provides a logical low signal on output lead R6. The low signal on lead R6, together with the low VDA signal, enables demultiplexer 105-6.
Demultiplexer 105-6 then decodes the four least significant bits Do through D3, and provides a logical low signal on output lead 6F. All signals on all remaining output leads of demultiplexer5 105-2 through 105-7 are logical ones at this time. The signals on the output leads of demultiplexers 105-2 through 105-7 are then shifted into the least significant bit of their associated shift registers of decoded data memory 13 (Figure 3). At this time, shift register SR6F corresponding to the character "o" will store the bits 1110, indicating that a "o" has been the most recently decoded character. Similarly, shift reglster SR57 will store the bits 1101, indicatlng that the character "W" was the previously decoded character. All other shift registers of decoded data memory 13 will store the bits 1111 indicating that their associated characters are not one of the last four charac-ters decoded.
The character "r" (hexadecimal 72) is no~ output from mass storage device 11 to decoder 12 (Figure 2). Demultiplexer 103 decodes the most significant bits of the character "r", and - 18a -provides a loyical zero signal on output lead R7. Dernultiplexer 105-7 is thus enabled, and provides a loyical zero sicJnal on output lead 72, ~7ith -the signals on all other output leads ~0 through 7F beiny : ~ ~

~2~ L62 1 logical ones. The signals on the ou-tput leads of demulti-2 plexers 105-2 through 105-7 are -then shifted into decoder 3 data memory 13 (Figure 3). Shift register SR72 will store the bits 1110, shift register SR6F will store the bits 1101, shift register SR57 will store the bits 1011, and 6 all remaining shift registers will store the bit 1111, 7 indicating that the character string "Wor" has been decoded.

9 The ASCII character "k" (hexadecimal 6B) is then 0 output from mass storage device 11 to decoder 12 (Figure 2).
Demultiplexer 103 decodes the most significant bits of the 2 ASCII character, thus providing a logical zero signal on lead R6. The logical zero signal on lead R6 enables de-1~ multiplexer 105-6. Demultiplexer 105-6 demultiplexes the least significant bits of the ASCII character, thereby 16 providing a logical zero signal on output lead 6B, with 17 logical ones being present on all other output leads 20 18 through 7F. The data on the output leads of demultiplexer 19 105-2 through 105-7 is then shifted into decoded data memory 13 (Figure 3a)~. At this time, shift register SR6B
21 will store the bits~lllO, shift register SR72 will store 22 the bits 1101, shift register 6F will store the bits 1011, 23 and shift register SR57 will store the bits 0111, indi-24 cating that the character string "Work" has been decoded.
////

30 j 3 3 // j/

38 j ,~

-` ~L22~46Z

-20 2 TAB:LE 1 ASCIT. ASCII
4 ASCII Code ASCII Code Code ~}lexi- Code (~lexi-6 Character(Binary) decimal) Character (Binary) decimal) 7 blank 00100000 20 P 01010000 50 ' 00100001 21 (~ 01010001 51 8 ~ 00100010 22 R 01010010 52 9 # 00100011 23 S 01010011 53 $ 00100100 24 r OlOlOlOO 54 % 00100101 25 U 01010101 55 11 & 00100110 26 V 01010110 56 ' 00100111 27 W 01010111 57 12 ( 00101000 28 ~ 01011000 58 13 ) 00101001 29 Y 01011001 59 `:' 00101010 2A Z 01011010 5A
14 ~ 00101011 2B [ 01011011 5B
' 00101100 2C \ 01011100 5C
- 00101101 2D ] 01011101 5D
16 . 00101110 2E -1 or ,\ 01011110 5E

0 00110000 3~ ` 01100000 6 18 1 ~00110001 31 a 01100001 61 19 2 00110010 32 b 01100010 62 3 . 00110011 33 c 01100011 63 4 00110100 34 cl 01100100 ~4

21 5 00110101 35 e 01100101 65 6 00110110 36 ~ 01100110 66

22 7 00110111 37 g OllOOll]. 67

23 8 00111000 38 h 01101000 68 9 00111001 39 i 01101001 69

24 : 00111010 3A j 01101010 6A
; 00111011 3B k 01101011 6B
< OOlIllOO 3C 1 01101100 6C
26 = 00111101 3D m 01101101 6D
27 : 00111110 3E n 01101110 6E
? 00111111 3F o 01101111 6F
28 @ 01000000 4~ p 01110000 70 29 A 01000001 41 q 01110001 71 B 01000010 42 r 01110010 72 C 01000011 43 s 01110011 73 31 D 01000100 44 t 01110100 74 E 01000101 45 u 01110101 75 32 F 01000110 46 ~ v 01110110 76 33 & 01000111 47 w 01110111 77 H 01001000 : 48 x 01111000 78 34 I 01001001 49 y 01111001 79 J 01001010 4A z 01111010 7A
K 01001011 4B ~ 01111011 7B
36 L 01001100 4C ' 01111100 7C
37 0lOOllOl 4D } 01111101 7D
N~ 01001110 4E ~ 01111110 7E
38 0 01001111 4F DEI, 01111111 7F

. ~
. :
.

~221~6Z

1 A detailed view of the output leads of tlle shift registers of decoded data memory 13 ls sho~n in Figure '~.
Shift register SRnm, corresponding to the shift register 4 at the intersection of row n and column m, has a pluralit~
of K output leads for examining -the IC hits stored within 6 shift register SRnm. Thus, the least significant bit 7 stored within shift register SRnm is available on lead 8 nml, the next to the least significant bit is available on 9 lead nm2, and the most significant bit is available on lead nmK.

12 Logical O~erator Section 14 13 Logical operator section 14 comprises one or more 14 logical gates which may be hard wired to decoded data memory 13, or alternatively programmably connected under 16 computer control, as described later. One embodiment of 17 logical operator section 14 (Figure 1) is shown in Figure 18 5a. Here, NOR gate 761a is connected so as to provide a 19 logical one signal on output lead 762a when the character string "Work" has been located in mass storage device 11 21 (Figure 1). When the character string "Work" has been 22 received, the fourth least significant bi-t of shift register 23 SR57 (as provided on lead 574), the third least significant 24 bit of shift register SR6F ~as provided on lead 6F3), the second least significant bit of shift register SR72 (as 26 provided on lead 722), and the least significant bit of 27 shift register SR6B (as provided on lead 6B1), will all be 28 equal to logical zeros. Thus, upon receipt of the character 29 string "Work", the output signal on lead 762a of NOR gate 761 (having its input leads connected to leads 574, 6F3, 31 722 and 6B1) will be a logical one, in contrast to the 32 logical low signal present on lead 762a at all other 33 times.

Because the character string "Work" will be detected 3~ by NOR gate 761a upon decoding of the first four letters 37 of the word "Working" as well as for the word 'IWork'', when " '' .

~Z14~2 1 seeking -to locate a character string e~uivalent to the 2 word "Work", and not any variations thexeof, the logical 3 operator section 14 (Figure 1) is programmed to locate the 4 character string "Work~l' (where b is a blank charac-ter).
This is depicted in Figure Sb, ~lhere NOR gate 761b re~uires 6 the fifth least significant bit of shift register SR57 (on 7 lead 575), the fourth least significant bit of shift 8 register SR6F (on lead 6F4), the third least significant 9 bit of shift register SR72 (on lead 723), the second least significant bit of shift register SR6B (on lead 6B2), and 11 the least significant bit of shift register SR20 (on lead 12 201) to all be logical zeros in order for the signal on 13 lead 762a to be a logical one, indicating receipt of the 14 character string "Work~".
16 By the appropriate connection of additional gates, 17 logical operator section 14 may perform other search 18 functions. For example, if it is desired to locate within 19 mass storage device 11 all occurrences of either the word "Workb" or "workb", the circuit of Figure 5c will serve as 21 logical operator section 14. Here, the input leads of ~D
22 gate 760 are connected to leads 575 (from shift register 23 57 corresponding to the capital letter "W") and 775 (from 24 shift register 77 corresponding to the lower case letter "w"). Thus, a logical low on either lead 575 or lead 775 26 will provide a logical low signal on lead 760-1, which in 27 turn is connected to an input lead of NOR gate 761C. The 28 remaining input leads of NOR gate 761C are connected to 29 leads 6F4, 723, 6B2, and 101, as in the embodiment of Figure 5b. In this manner, a logical high output signal 31 is provided on lead 762C when either of the desired words 32 "Workb" or "workb" are located.

34 In many data base systems, additional symbols are used to indicated the end of a word (EOW), the end of a 36 sentence (EOS), the end of a paragraph (EOP), and the end 37 of a document (EOD). These additional symbols may comprise =

.

~ZZ14GZ

1 eight bit bytes which do not for~ one of the 96 ASCII
~ characters (i.e~ comprise ~ through 0F or 8~ through 8F).
3 Alternatively, these additional symbols may comprlse one 4 or more ASCII characters. For example, the end of sentence signal (EOS~ may comprise a period followed by t~,70 blanks.
6 Additional shift registers are utilized to serve as word 7 counters, sentence counters, and paragraph counters.

9 An example of a word counter, which indica~es which word within a sentence is being decoded, is shown in 11 Figure 6a. Shift register SR-EOW may comprise a 74164 12 8-bit seriai-in, parallel-out shift register, as has been 13 previously described for the shift registers of decoded 14 data memory 13. Alternatively, a plurality of 8-bit shift registers may be connected serially, thus providing shift 16 register SR-EOW which is capable of storing greater than 8 17 bits. As shown in Figure 6a, shift register SR-EOW is 18 provided a clock signal by the end of word (EOW) signal.
1~ Thus, shift register SR-EOW is clocked upon receipt of an EOW signaI, thereby shifting data on input lead 876a into 21 shift register SR-EOW and shifting data stored in the 22 shift register to the next most significant bit. Input 23 lead 876a is connected to the output lead of SR flip flop 24 999 (which may comprise a 74LS279 device manufactured by Signetlcs). On receipt of a high EOS signal, indicating 26 the end of a sentence, a logical low EOS signal is generated 27 by inverter 998 (e.g. a 7404~device) and applied to the 28 clear input lead of shift register SR-EOw, thus clearing 29 shift register SR-EOW ~i.e. shift re~ister SR-EOW stores all zeroes when clear). This low EOS signal also causes 31 flip flop 999 to provide a high output signal on lead 32 876a. Upon the receipt a high EOW signal, indicating the 33 end of a word, the high output signal on lead 876a is ~-34 clocked into the least significant bit of shift register SR-EOW. Also, upon receipt of a high EOW signal, inverter 36 997 provides a low R signal to reset flip flop 999, thus 37 causing flip flop 999 to provide a low output signal.

.
~' 12;;~ i2 -2'~-1 This low output signal is input to shift register SR-EOW
2 by the operation of subsequent EOW signals applied to the 3 clock input lead of shift register SR-EOW, ~hereb~ shi~ting 4 the low Q signal on the output lead of flip flop 999 into S the least significant bit of shift register SR EOW, and 6 shifting the data stored in each bit of shift register SR-EOW to the next significant bit. Thus, the signal initially stored within the least significant bit of shift 9 register SR-EOW in response to a high EOS signal is shifted to the left (i.e. the ne.~t most signi~icant bit) upon 11 receipt of each EOW signal. In this manner, the signal 12 on leads EOW-l through EOW-;, where j is the number of 13 bits stored within shift register SR-EOW, indicate which 14 word within the sentence is being decoded. Thus, for example, if a logical one is present on lead EOW-l, the 16 first word in the sentence is being decoded. Similarly, 17 where a logical one is present on lead EOW-2, the second 18 word of the sentence is being decoded. Of importance, 19 only a single logical one will be present on leads EOW-l through EoW-j. This is accomplished by applying a high 21 signal to the "clear" input lead of shift register SR-EOW
22 upon receipt of a high EOS signal, thus resetting all bits 23 stored in shift register SR-EO~ to logical zeros ir~nediately 24 prior to the storage of a logical one in the least signifi-2S cant bit of shift register SR-EOW when a high EOS (End of 26 Sentence) signaI is applied to input lead 876.

28 A sentence counter is shown in Figure 6b. The sentence 29 counter, comprising shift register SR-EOS having output leads EOS-1 through EoS-j, operates in a similar manner as the word 31 counter of Figure 6a. ~owever, RS flip flop 989 has its input 32 lead connected to the EOP (End of Paragraph) signal, thereby 33 clearing shift register SR-EOS and setting flip flop 989 --34 high upon receipt of each EOP signal. Upon ihe receipt of a high EOS signal, shift register SR-EOS is clocked in a 36 similar manner as SR-EO~ (Figure 6a), thereby storing a 37 logical one in the least significant bit of shift register ~Z2~4~62

-25- .
1 SR-EOS upon receipt of the first sentence of each paragraph, 2 and clocking this logical one to the ne~t siynificant bit 3 upon receipt of each sentence. Thus, the presence of a 4 logical one on a unique one of leads of EOS 1 through EOS-j indicates which sentence in a paragraph is being 6 decoded.

8 A paragraph counter is shown in Figure 6c. The paragraph counter, comprising shift register SR-EOP having output leads EOP~l through EOP-;, operates in a similar manner as the word counter of Figure 6a and the sentence counter of Figure 6b. However, the EOP signal provides a 13 clock signal to the paragraph counter SR-EOP. The input 4 lead 876c of the paragraph counter is connected to the output lead of RS flip flop 979, which is set by the EOD
16 (End of Document~signal. The clear input lead is activated 17 upon receipt of a high EOD signal. In this manner, the 18 logical one appearing on a unique one of output leads ~9 EOP-l through EOP-; indicates which paragraph within the document is being decoded.

22 Utilizing the word counter~, sentence counter, para-23 graph counter, and decoded data memory 13, complex full-text 24 searching may be accomplished. For example, if it is desired to locate a document stored within mass storage

26 device 11 in which the word "Workb" appears in the third

27 ~ord of the fourth sentence of the second paragraph, the

28 circuit of Figure 5d is used. The~circuit of Figure 5d

29 comprises AND gate 901 having one input lead connected to output lead 762b of the circuit of Figure Sb. Thus, a 31 logical high signal will be input to AND gate 901 on lead 32 762b when the character string "Workb" is decoded. Simi-33 larly, a logical high signal will be input to AND gate 901 34 when the third least significant bit of the word counter is a logical one, indicating that the third word is being 36 decoded. This high signal will be available on lead 37 EOW-3. In a similar manner, when the fourth sentence of 3~

-~ZZlq.6Z

the paragraph is being decoded, a logical high ~,1ill be applied at an iIlpUt signal -to ~ gate 901 on lead EOS-~, 3 and when the second paragraph o~ a document is being decoded, a high input signal will he applied to AND gate 901 on lead EOP-2. Thus, a logical high signal will be 6 present on output lead 901-1 only when the word l'Workb" is 7 decoded as the third word of the fourth sentence of the second paragraph of a document.

In accordance with this invention, full te~t searching 11 is accomplished to locate documents in which a plurality of 12 desired words occur within the same sentence. For example, 13 one embodiment of a logical operator section 14 which may 14 be utilized to locate text which includes the word "batb"
and "ballb" in the same sentence is shown in Figure 5e.
16 NOR gate 976 has its input leads connected to leads 624, 17 613, 741 and 201 of decoded data memory 13, thus providing 18 a logical high output signal on lead 976-1 when the word 19 "batb" has been decoded. Similarly, NOR gate 977 has its input leads connected to leads 625, 614, 6C3, 6C2 and 2~1 21 of decoded data memory 13, thus providing a logical high 22 on output lead 977-1 when the word "ballb" is decoded.
23 Lead 976-1 is connected to the S input of SR flip-flop 978, 24 thus providing a logical high on the Q1 output lead 978-1 when the word "batb" has been decoded. Similarly, lead 26 977-1 is connected to the S input;lead of SR flip-flop 979, 27 thus providing a high sir3nal on the Q2 output lead 979-1 28 when the word "ballb" has been decoded. ~Flip-flops 978 29 and 979 are reset by a low EOs signal, which is applied to the R input leads of the flip-flops. Thus, at the end 31 of each sentence, flip-flops 978 and 979 are reset (Q
32 and Q2 reset to logical zeroj, thus indicating that the 33 words "batb" and "ballb" have not been decoded within the ~-34 ne~t sentence. The output leads 978-1 and 979-1 from the flip-flops are connected to the input of ~D gate 980, 36 thus providing a logical high on output lead 980-1 when 37 the words "batb" and "ballb" have been decoded within the 1 same sentence (i.e. Q1 output lead of flip flop 978 and Q2 2 output lead of flip flop 979 both high). By utllizing the 3 end of paragraph (EOP) or the end of docllment (EOD) signal 4 in place of the end of sen-tence (EOS) signal in the logical operator section depicted in Figure 5e, documen-ts may be 6 located in which the words "batb" and "ballb" are located 7 within the same paragraph, or document, respectively.

9 It is often desired to find the location ~1i-thin the data base where a first desired word appears within a 11 selected number of words of a second desired word. For 12 example, it may be desirable to locate instances where the ~3 word "ball" appears within four words of the word "bat", 14 in order to locate portions of the data base referring to baseball, while not locating portions of -the data base 16 referring to any other type of ball (e.g. golf ball, etc.) 17 and any other type of bat (e.g. flying mammals). One 18 embodiment of logical operator section 14 which may ac-19 complish this task of locating portions of the data base wherein the word "bat" appears within four words of the 21 word "ball" is shown in the schematic diagrams of Figures 22 7a and 7b.

24 Logical operator section 14 of Figure 7a includes NOR
gate 976 and NOR gate 977, which are connected in the same 26 manner as NOR gates 976 and 977, respectively, of Figure 27 5e. Accordingly, a high output signal from NOR gate 976 28 indicates that the word "batb" has just been located.
29 Similarly, a low output signal from NOR gate 977 indicates that the word "ballb" has just been located. Inverters 31 831 and 832 invert the output signal from NOR gates 976 32 and 977, respectivel~. Thus, upo~ detection of the word 33 "batb", the output signal from inverter 831 is low, thus 34 setting SR flip flop 833 to have a high Q output signal.
Similarly, upon detection of -the word~"ballb", the output 36 signal from inverter 832 is low, thus setting SR flip flop 37 834 such that its Q output signal is high. The Q output ~2;~ 162 1 signals from SR flip flops 833 and 834 a.re clocked into 2 the least significant bit of shift registers 834 and 836, 3 respectively, upon receipt of a low ~W slgnal which is 4 applied to the cloc]s input leads of shift registers 835 and 836. SR flip flops 833 and 834 are required in order 6 to preserve the signal indicating that the desired words 7 have been decoded, until the receipt of the EOW signal 8 which clocks that data into shift registers 835 and 836, 9 respectively. If SR flip flops 833 and 834 ~ere not used, the signal indicating that the desired words had been 11 detected would be lost prior to being clocJced into shift 12 registers 835 and 836, respectively. Of importance, when 13 the EOW signal comprises a blank character (which appears 14 at the end of every word), and -the desired word being detected includes the blank character and the end of the 16 word (e.g. "batb" and "ballb") shift registers 833 and 83~
17 (and thus inverters 831 and 832) are not required, ~ecause 18 the EOW signal appears simultaneously with the high outpu~
19 signal f~om either NOR gate 976 or NOR gate 977 indicating that the desired word has been decoded.

22 Upon detection of the word "batb" and receip~ of the 23 EOW signal, a logical one is clocked into the least signi-24 ficant bit of shift register 835. After the data from flip flops 833 and 834 have been clocJced into shift regi-26 sters 835 and 836, respectively, upon the receipt of an 27 EOW signal, a low signal is applied to terminal 841 which 28 is connected to the reset (R) input leads of flip flops 29 833 and 834, thus resetting the Q output signals of flip flops 833 and 834 low. This reset signal applied to 31 terminal 841 may comprise, for example, a signal EGW' 32 which is derived from but delayed by approximately 75 33 microseconds from the EOW signal, thus resetting flip 34 flops 833 and 834 after the data appearing on their Q

output leads have been clocked into shif-t registers 83s 36 and 836, respectively, upon receipt of a low~EOW signal.
37 At the beginning of a search, a logical low signal is . ~

~Z;~62 l applied in a well known manner to node 840a which is ~ connected to the reset (R) input leads oE shift registers 3 835 and 836, -thus resetting each bit within shi~t ~egisters 4 835 and 836 to logical zeros. Upon each subsequent EO~,~
signal, the clata in shift registers 835 and 836 is shifted 6 to the next most significant bit, with output data from SR
7 flip flops 833 and 834 being input to the least significant 8 bits of shift registers 835 and 836, respectively. Ac-9 cordingly, the signals appearing on output leads T1 through Tj of shift register 835 indicate which one or ones of the 11 previous j words decoded was equal to "batb", and the 12 signals on the output leads Pl through Pj of shift register 13 836 indicates which one of the previous j words decoded 14 was equal to "ballb". In -this example, it is desired to locate occurrences of the word "batb" within four words of 16 the word "ballb". Accordingly, the four least significant 17 output leads of shift registers 835 and 836 are connected 18 to the input leads of NOR gate 837 and 838, respectivelv.
19 Thus, NOR gate 837 generates a low output signal when the word "batb" is one of the four most recently decoded 21 words, and similarly, NOR gate 838 provides a low output 22 signal when the word "ballb" has been one of the four most 23 recently decoded words. The output leads of NOR gates 837 24 and 838 are connected to the input leads of NOR gate 83g, thus providing a high output signal from NOR gate 839 26 which is available on node 840 when both the words "batb"
27 and "ballb" have been decoded within four words of each 28 other.

The shift registers 835 and 836 are reset in a number 31 of desired ways. First, as previously described, on 32 beginning a search, shift registers 835 and 836 are cleared.
33 Shift registers 835 and 836 are also cleared upon receipt 34 of a high output signal from NOR gate 839, thus indicating that the desired words have been decoded within four words 36 of each other. This reset procedure is designed to prevent 37 erroneous multiple high signals on the output lead of NOR

~2Z~ 2

-30-1 gate ~39 under certain circums-tances ~7hen -the desired 2 words have been decoded. For example, if the desired 3 words are adjacent to each other, and shift registers 83-~
4 and 836 are not reset upon -their first detection, ~IOR gatc 839 will provide a high output signal when the desi.red 6 words are the two most recently decoded words, the second 7 and third most recently decoded words, and the third and 8 fourth most recently decoded words, thus providing three 9 signals for the same occurrence of the two desired words.
Thus, by reset-ting shift registers 835 and 836 upon receipt 11 of a high output signal from NOR gate 839, such erroneous 12 multiple signals will be prevented. Finally, shift regi-13 sters 835 and 836 may, if desired, be reset upon receipt 14 of an EOS signal, thus requiring the desired words to appear in the same sentence. Alternatively, shift registers 835 16 and 836 may be reset by the EOP signal or the EOD signal, 17 thus requiring the desired words to be located within the 18 same paragraph, or the same document, respectively.

Figure 7b shows NOR gate 870 having its input leads 21 connected to~ the EOS signal, the output signal from NOR
22 gate 839 appearing on terminal 840, and a signal labelled 23 as "begin search", which is high when a search is to 24 begin. Accordingly, NOR gate 870 will provide a low output signal which is connected to terminate 840a of 26 Figure 7a to reset shift registers 835 and 836 at the 27 beginning of each ~search, at the end of each sentence, and 28 upon detection of the desired words and their desired 29 relationship by receipt of a high signal on terminal 840.

31 Those of ordinary skill in the art, in light of the

32 teachings of this invention, are also able to construct a

33 logical operation section 14 may also be constructed which

34 will detect the occurrence of a first desired word within a fixed number of sentences of a second desired word.
36 Logical operator section 14 of Figure 7a may be used for 37 this purpose with but a few modifications. For example, , ~ ~zz~4~Z

1 shift registers 835 and 836 wil:L, in this ins-tance, recei~e 2 their clock signals from the EOS signal, and flip flops 833 and 834 will be reset by a delayed ~,OS' signal applied 4 to terminal 841. Furthermore, the NAND gate 870 o~ Flgure 7b will receive as its input signals the EOP signal. in 6 place of the EOS signal, if it is desired that the two 7 words appear within the same paragraph. Alternati~ely, 8 the EOS siynal applied to NOR gate 870 of Figure 7b is 9 replaced by the EOD signal, when it is desired that the two desired words appear in the same document.

12 Furthermore, it is to be understood that the decoder 13 12 and decoded data memory 13 (Figure 1) can be used with 14 logical operator section 14 other than those specific embodiments provided in this specification. Similarly, 16 the logical operator section 14 need not be used with the 17 specific embodiments of decoder 12 and decoded data memory 18 13 provided in this specification.

The logical operator section 14 (Figure lj can comprise 21 hardwired logical gates which serve to search for desired 22 character strings. Alternatively, logical operator 23 section 14 may comprise a large number of logical gates, 24 including AND gates, OR gates, NOR gates, flip-flops, and the like, which may:be programmably connected in order to 26 provide the desired character search, in order to be 27 highly flexible in performing searches. The use of cross-28 point switch arrays, and particularly such arrays imple-29 mented as integrated circuits, will be useful in the construction of logical operator section 14. One such 25631 by 256 cross-point switching array is described in an 32 article entitled l'Cross-Point Array IC Handles 2S6 Voice 33 and Data Channels", written by Lloyd Reaume and appearing 34 in Electronics Magazine, October 6, 1981, pages 133-135.
Such a cross-point switch array is useful for connecting 36 the plurality of output leads from the shift registers of 37 decoded da-ta memory 13 contained within bus 13a, the EOW, 3~

lZ;~462 1 EOS, EOP, and EOD signals, as well as providing inter-2 connections between the logical gates of logical opera-tors 3 section 14. U-tilizi.ng a sultable compu-ter program, the ~ operation of such cross point switch arrays within logical operators section 14 may be accomplished as a resul-t of 6 simple commands describing the desired search. The computer 7 is programmed to receive -the commands and operate the 8 cross-poin-t switch array in such a manner as to provide 9 proper connection between -the leads ~1ithin bus 13a, the EOW, EOS, EOP and EOD leads, and the logical gates within 11 logical operator section 14.

13 As previously described, upon the decoding of the 14 desired character string, logical operator sec~ion 14 generates a signal on bus 14a, which is connected to 16 central processing unit (CPU) 15 (Figure 1). CPU 15 then 17 operates as programmed, for example, to store -the document 18 number containing the desired character string, print the 19 sentence containing the desired character string, and the like.

24 SYstem Overview A second embodiment of a text comparator constructed 26 in accordance with this invention is depicted in the block 27 diagram of Fig~. 8. Text comparator ~0 includes mass 28 storage device 111 which, as previously described in 29 conjunction with~ the first embodiment of this invention, stores a large amount of textual data, often referred to 31 as the "data base." Data stored in mass storage device 32 111 is transferred via bus llla and made available to word 33 logic 112, delimiter logic 113, set logic 114, set combi-34 nation logic 115, proximity logic 117, and programming logic 116, as is fully described below. Delimiter logic 36 113 serves to monitor the characters transferred from mass 37 storage device 111 on bus llla and provides discrete ,.

.

~2Z~6Z

1 signals depic-ting whether the character being transferred 2 ls a predefined del.imi-ter character. Such delimiter 3 characters include, for example, special characters or 4 groups of characters denoting the end of a word (EOW), end of a paragraph (EOP), end of a sentence (EOS), end of a 6 document (EOD), end of a chapter (EOC), and the end of a 7 title (EOT). The delimiter signals provided by delimiter logic 113 are required in order to allow the text comparator 9 80 to determine, for example, when -two specified words occur within the same sentence or within the same paragraph, 11 as is fully described below.

13 Word logic 112 serves to store data regarding pre-14 defined words (i.e., strings of characters) which are to be located within the text stored in mass storage device 16 111. Word logic lI2 then pEovides output word signals on 17 bus 112a indicating when such predefined words have been 18 located in the character string being transferred from 19 mass storage device 111 via bus llla. These word signals are transferred via bus 112a to set loglc 114 and proxim'ity 21 logic 117.

23 Set logic 114 receives the delimiter signals from 24 delimiter logic 113 via bus 113a and word signals from word logic 112 via bus 112a and determines when selected 26 words are located in the same sentence, same paragraph, ~7 etc., as desired, and provides output signals on bus 114a 28 indicating when predefined words or strings of characters 29 have been so located.
31 The output signals from set logic 114 are applied to 32 set combination logic 115, which serves to combine the 33 signals from set logic 114 in order to genera-te output 34 signals on output bus 115a indicating when the te~tual information transferred from~mass storage device 111 on 36 bus llla meets the desired search strategy selected by the 37 user-~ZZ~462 1 Proximity logic 117 receives input signals from buses 2 llla, 112a, 113a, and ll~a and combines this information 3 in order to provide output signals indica-ting ~7hen pre-4 defined words detec-ted by word logic 112, or predefined S set of words, as detected by set logic 114, or a combina-6 tion of this information, occurs wi-thin a predefined 7 proximity. For example, proximity logic 117 will determine 8 if a first selected word occurs within N (where N is a 9 selected integer) words of a second preselected word.
ll Programming logic 116 serves to receive search strategy 12 instructions from the user and in response thereto provide 13 the proper timing, addressing, and data signals via bus 14 llla to word logic 112, delimiter logic 113, set logic 114, se-t combination logic 115, and proximity logic 117 to 16 cause to be stored within these elements the information 17 required to perform the desired search strategy.

19 While for ease and understanding word logic 112, delimiter logic 113, set logic ll~j set combination logic 21 115, and proximity logic 117 will now be described in ~22 separate subsections of this specification, it is to be 23 understood that each~of these elements is, if required, 24 programmed by programming logic 116 prior to the execution of a user defined tex~tual search strategy.

27 Delimiter Loqic 113 28 Fig. 9 depicts the relationship between Figs. 9a 29 through 9c which in turn form a schematic diagram of one embodiment of delimiter logic 113. Delimiter logic 113 31 provides on its output leads 9-6a, 9-7a, 9-8a, 9-lOa, 32 9-12a, and 9-14a, delimiter signals indicating, for example, 33 the end of a word, end of a p~aragraph, end of a document, 34 etc. These output leads 9-6a, 9-7a, 9-8a, 9-lOa, 9-12a and 9-14a form bus 113a of Fig. 8.

\ ~2z~46Z

-35-In many textual data bases, the end of a ~70rd (EOr~7) is 2 indicated by a non-blank character followed by a blank.
3 This is preferred over the -technique used by some te.Ytual 4 data bases where the end of a word ls indicated simpl~ b~
S a blank character, because at the end of a sen-tence and at 6 the end of a paragraph numerous blanks may occur in sequence, 7 providing a corresponding plurality of undesired end of 8 word signals. Similarly, an end of a sentence is often 9 indicated by a period followed by two blanks, and an end of paragraph is indicated by a period follo~ed by three 11 blanks.

13 The portion of the delimiter logic 113 shown in Fig.
14 9a serves to detect the occurrence of a blank, a non-blank character, and a period, and also combines these three 16 characters in order to provide EOW, EOS and EGP signals on 17 output leads 9-6a through 9-8a, respectively. The eight 18 bit data word comprising bits DO through D7 is latched 19 into latch 9-1 upon receipt of a clock signal (CLK) which is provide~d by mass storage device 111 on bus llla to 21 indicate that a valid data word is present on bus llla.
22 Latch 9-1 comprises, for example, a 74373 device manufac-23 tured by National Semiconductor Corporation (hereinafter 24 referred to as "National"). Latch 9-1 serves to store data received on bus llla and provide this data to the 26 remainder of delimiter logic 113 until the next data word 27 has been set onto bus llla. Thus latch 9-1 provides bits 28 DO through D7 on leads 9-la through 9-lh. Each bit DO
29 through D7 is uniquely applied to one input lead of exclu-sive OR gates 9-2al through 9-2a8, and are also uniquely 31 applied to one input lead of exclusive OR gates 9-2bl 32 through 9-2b8. The remaining input leads of exclusive OR
33 gates 9-2al through 9-2a8 are connected either to a logical --34 zero signal (typically zero volts) or a logical one signal (typically 5 volts) in order to program exclusive OR gates

36 9-2al through 9-2a8 so as to detect when a blank character

37 is transmitted on bus llla. Similarly, the remai~ning

38 ~ZZ1462 1 input leads of exclusive OR yates 9-2bl through 9-2b8 are 2 connected either to a logical ~ero signal or a logicaL one 3 signal in order to program exclusive OR gates 9-2bl througi 4 9-2b8 so as to detect when a period is trans~ltted on bus llla.
7 Referring to table 1, it is seen that in ~SCII, a 8 blank is a hexadecimal 20 ~binary 00100000). Accordingl~, 9 the program leads of exclusive OR gates 9-2al through 9-2a8 (i.e., those leads not connected to data bi-ts ~0 11 through D7 provided by leads 9-la through 9-lh, respectivel~) 12 are programmed to the binary signal corresponding to the 13 inverse of the binary signal representing a blank. Thus, 14 the program leads of exclusive OR gates 9-2al through 9-2a8 are programmed to binary 11011111, respectively. In 16 this manner, when a blank signal is transmitted on bus 17 llla and stored in latch 9-l, the D0 through D7 signals 18 applied to each exclusive OR gate 9-2al through 9-2aa are 19 opposite the program signal applied to these exclusive OR
gates, and each exclusive OR gate 9-2al through 9-2a8 21 provides a logical one output signal on its output lead.

23 The output signals from exclusive OR yates 9-2al 24 through 9-2a8 are applied to the input leads of Nt~ND gate 9-3a. Thus, when a blank character is transmitted on bus 26 llla, each input signal to NAND gate 9-3a is a logical 27 one, and the blank output signal from NAND gate 9-3a is a 28 logical zero, indicating that a blank character has been 29 transmitted.
31 Conversely, when a nonblank character is transmitted 32 on bus llla and stored in latch 9-1, at least one exclusive 33 OR gate 9-2al through 9-2a8 receives a data signal D0 34 through D7 ~hich is identical to the programming signal applied to that exclusive OR gate, and the output signal 36 from that exclusive OR gate is a logical 7ero. Thus, the 37 blank ou~tput signal from NAND gate 9-3a is a logical one, 38 indicating that a nonblank character has been transmitted.

L46%

The output signal from NAND gate 9-3a is ~pplied to 2 the D inpu-t lead of D type ~ip-flop 9-~La. The Q output 3 lead of ~lip-flop 9-~a is connected to the D input lead of 4 D-type ~lip-flop 9-4b, whose Q output lead is in turn connected to the D input lead of D-type flip-flop 9-4c.
6 Flip-flops 9-5a through 9-5d thereby providing signals 7 indicating whether each of the last three characters 8 transmitted was a blank or a nonblank character. D-type 9 flip-flops 9-~a through 9-4c comprise, for example, one flip-flop of a 74175 quad D-~ype flip-flop manufactured by 1 National. Flip flops 9-4a through 9-4c each receive their clock signals from the Valid Data signal provided by mass 13 storage device lll (Fig. 8~ indicating that valid data is 14 available on bus llla.
16 Again referring to table 1, it is seen that in ASCII, 17 a period is a hexadecimal 2E ~binary 00101110j. Accordingly, ~8 the program leads of exclusive OR gates 9-2bl through 19 9-2b8 (i.e., those leads not connected to data bits DO
through D7 provided by leads 9-la through 9-lh, respectively) 21 are programmed to the binary signal corresponding to the 22 inverse of the binary signal representing a period. Thus, 23 the program leads of exclusive OR gates 9-2bl through 24 9-2b8 are programmed to binary 11010001, respectively. In this manner, when a period signal is transmitted on bus 26 llla and stored in latch 9-l, the DO through D7 signals 27 applied to each exclusive OR gate 9-2bl through 9-2b8 are 28 opposite the program signal applied to these exclusive OR
29 gates, and each exclusive OR gate 9-2bl through 9-2b8 30 provides a logical one output signal on its output lead.

32 The output signals from exclusive OR gates 9-2bl 33 through 9-2b8 are applied to the input leads of NAND gate 34 9-3b. Thus, when a period character is transmitted on bus llla, each input signal to NAND gate 9-3b is a logical one, 36 and the . output signal from NAND gate 9-3b is a logical 37 zero, indicating that the period has been transmitted.

.

- 1~2~4~

1 Conversely, ~7hen a nonperiod character is transmitted 2 on bus llla and stored in latch 9-1, at least one exclusive 3 OR gate 9-2bl through 9-2b8 receives a data signal DO
~ thro~1gh D7 which is identical to the programming signal S applied to that exclusive OR gate, and the output signal 6 from that exclusive OR gate is a logical zero. Thus, the 7 . output signal from NAND gate 9-3b is a logical one, 8 indicating that a non-period character has been transmitted.
The output signal from NAND gate 9-3b is applied to 11 the D input lead of D type flip-flop 9-5a. The Q output 12 lead of flip-flop 9-5a is connected to the D input lead of 13 D-type flip-flop 9-5b, whose Q output lead is in turn 14 connected to the D input lead of D-type flip-flop 9-5c, whose Q output lead is in turn connected to the D lnput 16 lead of D-type flip-flop 9-5d. Flip-flops 9-5a through 17 9-5d, D-type flip-flops 9-5a through 9-5d comprise, for 18 example, one flip-flop of a 74175 quad D-type flip-flop 19 manufactured by National. Flip-flops 9-5a through 9-5d, each receive their clock signals from the Valid Data 21 signal provided by mass storage device 111 (Fig. 8) indlcat-22 ing that valid data is available on bus llla.

24 Because the end of a word is indicated by a nonblank character followed by a blank character, one input lead of 26 NAND gate 9-6 is connected to the Q output lead of flip-flop 27 9-4b and one input lead of NAND gate 9-6 is connected to 28 the Q oupu~ lead of flip-flop 9-4a. Thus, when the charac-29 ter most recently transmitted on bus llla is a blank, the 30 Q output signal from flip flop 9-4a is a logical one. ~
31 Similarly, when the preceding character transmitted on bus 32 llla is a nonblank character, the Q out~ut signal from 33 flip-flop 9-4b is a logical one. With both input leads of 34 NAND gate 9-6 receiving logical one signals, the EOW
output signal generated by NAND gate 9-6 and available on 36 output lead 9-6a is a logical zero, indicating that the 37 end of a word has been detected. At all other times, .,.~

12Z14~Z

-39-1 either the Q output lead of Elip flop 9-~a will provide a 2 logical ~ero signal (indicating that the character most 3 recently transmitted on bus llla is a nonblank character) 4 or the Q output lead from flip flop 9-4b will provide a logical zero signal, indicating that the previously received 6 character was not a nonblank character, or both, thereby 7 causing NAND gate 9-6 to generate a logical one EOW signal.

9 Similarly, because the end of a sentence is indicated by a period followed by two blanks, NAND gate 9-7, which 11 generates a EOS signal on its output lead 9-7a, has one of 12 its three input leads connected to each of the Q output 13 leads of flip-flops 9-4a, 9-4b, and 9-5c. In this manner, 14 when the two most recently received characters are blanks, flip-flops 9-4a a~d 9-4b provide logical one Q output 16 signals, and when the character preceding these two blank 17 characters is a period, flip-flop 9-5c provides a logical 18 one O output signal, thereby causing NAND gate 9-7 to 19 generate a logical zero EOS signal on output lead 9-7a.
21 In a similar manner, the end of a paragrah is indi-22 cated by a period followed by three blanks. Thus, NAND
23 gate 9-8 has one of its input leads connected to each of 24 the Q output leads of flip~flops 9-4a, 9-4b, 9-4c, and 9-5d. In this manner, when the three most recently received 26 characters are all blanks, flip flops 9-4a through 9-4c 27 will provide logical one Q output signals to three input 28 leads of NAND gate 9-8. When the character preceding 29 these three blanks is a period, flip flop 9-5d will provide a logical one~ Q output signal to the remaining input lead 31 of NAND gate 9-8, thereby causing NAND gate 9-8 to generate 3~ a logical zero EOP signal on output lead 9-8a. Conversely, 33 when the four characters most recently transmitted on bus 34 llla are not a period followed by three blanks, at least one Q output signal from flip-flops 9-4a, 9-4b, 9-4c, and 36 9-5b will be a logical zero, thereby causing NAND gate 9-8 37 to generate a logical one EOP signal on output lead 9-8a .' ' ~':
:~

3LZZ~2

-40 1 indicating tha-t the end of a paragraph has no-t been detected.

3 Because the EOW, EOS and EOP signals are rather 4 universally indica-ted by a non-blank character ~ollowed by a blank, a period followed by two blanks, and by a period 6 followed by three blanks, respectively, it is preferable 7 to utilize arrays of exclusive OR ga-tes 9-2a and 9-2b, 8 each exclusive OR gate having a programming lead hard 9 wired to a logical zero or logical one potential, in order to detect the end of a word, end of a sentence, and end of 11 a paragraph. However, the EOD, EOC, and EOT signals 12 oftentimes stored within mass memory device 111 utilizing 13 a variety of special characters, depending on the database 14 used. For example, one system might store an EOD signal in mass memory device 111 as a hexadecimal FF, while 16 another system might store an EOD signal in mass storage 17 device 111 as a hexadecimal FA. Accordingly, it is desir-18 able to provide delimiter logic 113 with the ability to be 19 programmed in a manner that will allow delimiter logic 113 to detect the presence of the EOD, EOC and EOT signals, 21 regardless of how those signals are stored in the mass 22 storage device 111 of the particular system being used.

24 The remainder of the delimiter logic 113 shown in Fig. 9 is capable of being programmed to detect any three 26 desired characters stored within mass storage device lll.
27 In this embodiment, these three characters detected by the 28 circuit of Fig. 9 are the characters which are used to 29 indicate the end of a document (EOD), the end of a chapter (EOC) and the end of a title (EOT)- The prosramming of 31 delimiter logic 113 occurs prior to the transfer of data 32 from mass storage device lll to bus llla for comparison.
33 Prior to such transfer, programming logic 116 (Fig. 8) 34 provides signals on bus llla which serves to pre-program delimiter logic 113 as to the characters stored in mass 36 storage device 111 which serve as the EOD, EOC and EOT
37 delimiters. For example, programming logic 116 will first -lZ2~62

-41-l cause latch 9-9 (which comprises, ~or example a 7~374 2 device manufactured by Na-tional) to store the inverse of 3 the binary signal correspondiny to the EOD delimiter 4 character stored in mass storage device 111. Thus, for S example, if the EOD delimiter characters stored in mass 6 storage device 111 is a hexadecimal EF (binary 11111111) 7 its inverse (binary 00000000) is stored in latch 9-9.
8 This storage is performed by programming logic 116 providing on bus llla data bits D0 -through D7 equal to 00000000 and a suitable clock signal CLK to cause this data to be 11 stored in latch 9-1. Programming logic 116 also provides 12 an address signal of 000 on address ]eads A0 through A2, 13 respectively, of bus llla. The address signal 000 is 14 applied to the address input leads of decoder 9-1~ (which comprises, for example, a 74138 manufactured by National~.
16 Programming logic 116 also provides appropriate chip 17 enable signals E1 through E3 to decoder 9-1~, thereby 18 enabling decoder 9-18. In response to these input signals, 19 decoder 9-18 provides a positive going clock signal CLK 9-0 which is applied to latch 9-9. This positive going clock 21 signal CLK 9-0 causes the data present on leads 9-la 22 through 9-lh (i.e., the data stored in latch 9-l by pro-23 gramming logic 116) to be stored within latch 9-9. This 24 data is stored in latch 9-9 until programming logic 116 stores another eight bit word in latch 9-9. Generally, 26 because a given data base will not change the delimiter 27 character such as EOD, this data need b~ loaded into 28 latch 9-9 only once upon installation of the equipment.
29 However, in order to insure reliable operation of the delimiter logic 113, it may be desirable to periodically 31 reload latch 9-9 with a binary 0~0000000 in order to insure 32 that the proper data is stored in latch 9-9 despite any 33 incipient failures which would cause -the data stored 34 within latch 9-9 to deviate from its intended value.

36 During the operation of the text comparator, character 37 data is transferred from mass storage device lll (Fig. 8) ~ z2~46~
-~2-1 to bus llla and, in addition to being compared by exclusive 2 OR gate arrays 9-2a and 9-2b, is simultaneousl~ compared 3 with the data s-tored in latch 9-9 by excluslve OR gate 4 array 9-2c to determine whether an EOD character has been transmitted on bus llla. Thus, when an EOD c~laracter (hex 6 FF) is transmitted on bus llla, a logical one signal ~
7 be applied to one input lead of each exclusive OR gate 8 9-2cl through 9-2c8 of exclusive OR gate array 9-2c. The 9 data stored within latch 9-9 is continuously applied to the other input leads of exclusive OR gates 9-2cl -through 11 9-2c8. Thus, when an EOD character is -transmitted on bus 12 llla, the data signals D0 through D7 applied to one input 13 lead of exclusive OR gates 9-2cl through 9-2c8 will be the 14 inverse of the data which is applied b~ latch 9-9 to the other input lead of exclusive OR gates 9-2cl through 16 9-2c8, thereby causing each exclusive OR gate 9-2cl through 17 9-2c8 to provide a logical one signal on its output lead.
18 These output signals are in turn applied to the input 19 leads of NAND gate 9-10, thus causing NAND gate 9-10 -to 2~ provide a logical zero EOD signal on output lead 9-lOa, 21 indicating that an EOD character is present on bus llla.
22 Conversely, if a character other than an EOD character is 23 transferred on bus llla, at least one exclusive OR gate 24 9-2cl through 9~2c8 receives a data signal D0 through D7 which is identical to the data which that exclusive OR
26 gate receives from latch 9-9, and the ou-tput signal from 27 that exclusive OR gate is a logical zero, thus causing the 28 EOD signal from NAND gate 9-10 to be a logical one, indi-29 cating that an EOD character has not been transferred on bus llla.

32 In a similar manner, latch 9-11, exclusive OR array 33 9-2d, and NAND gate 9-12 provide an EOC signal on terminal 34 9-12a which indicates whether an end of chapter (EOC) character has been transferred on bus llla. Thus, for 36 example, if an EOC character is hexadecimal FE (binary 37 11111110), prior to the textual comparison process, pro-. ~

~ Zz~ 9~6z 1 gramming logic 116 provides a data signal D7 throuyh D0 2 equal to 00000001, and causes -this signal to be stored in 3 latch 9-ll by providing an A2 through A0 address signal o 4 001 which, together with appropriate enabling signals E1 through E3, in turn is applied to decoder 9-18, which in 6 turn provides a positive going CLK 9-1 signal which is 7 applied to latch 9-11. In this manner, when textual data 8 is transferred from mass storage device 111 (Fig. 8) to 9 bus llla, each textual character is compared by exclusive OR gate array 9-2d with the data stored in latch 9-11, and 11 an EOC signal is made available on output terminal 9-12a 12 indicating whether an EOC character has been transmitted 13 on bus llla.

In a similar manner, latch 9-13, exclusive OR array 16 9-2e, and NAND gate 9-14 provide an EOT signal on terminal 17 9-14a which indicates whether an end of chapter (EOT) cha-18 racter has been transferred on bus llla. Thus, for example, l9 if an EO~ character is hexadecimal FD (binary 11111101), prior to the textual comparison process, program~ing logic 21 116 provides a data signal D7 through DO equal to 00000010, 22 and causes this signal to be stored in latch 9-13 by provid-~3 ing an A2 through A0 address signal of 010 ~hich, together 24 with appropriate enabling signals E1 through E3, in turn is applied to decoder 9-18~, which in turn provides a positive 26 going CLK 9-2 signal which is applied to latch 9-13. I~
27 this manner, when textual data is transferred from mass 28 storage device lll (Fig. 8) to bus llla, each textual cha-29 racter is compared by exclusive OR gate array 9-2e with the data stored in latch 9-13 and an EOT signal is made avail-31 able on output terminal 9-14a indicating whether an EOT
32 character has been transmitted on bus llla.

34 Naturally, for data base systems which utilize spec characters to indicate EOW, EOS, and EOP, circuitry anal-36 ogous to latch 9-9, exclusive OR gate array 9-2c, and NAND
37 gate 9-l~ may be used in a similar manner as these circuit ~2Z~L62 1 elements are used to detect an EOD character. ~urthermore, 2 the programming leads of excluslve OR gate arrays 9-2a and 3 9-2b need not be hard wired to logical zero or logical one 4 signals, but rather could be ~lired -to output signals S available from a memory device, if desired. Still Eurther, 6 one or more of latches 9-9, 9-11, and 9-13 can be replaced 7 by hard wiring the programming input leads of exclusive OR
8 gate arrays 9-2c, 9-2d, and 9-2e, respectively, to appro-9 priate logical zero and logical one signals, although, as previously described, by utilizing la-tches 9-9, 9-11, and 11 9-13, the delimiter logic 113 of Fig. 9 can be utilized 12 with any data kase, regardless of the specific character 13 which that data base uses as an EOD, EOC, and EOT character.

Word Loqic 112 16 Referring to Fig. 12, the operation of word logic 112 17 will now be described. Fig. 12 depicts a portion of word 18 logic 112 which is capable of detecting a predefined 19 string of up to eight characters. Al-though not shown in Fig. 12, word logic 112 includes a latch (such as a 74373 21 device manufactured by National) provided between mass 22 storage device 111 (Fig. 8) and bus llla, in order to 23 store data output from mass storage device 111 and provide 24 this data to the remainder of word logic 112 until the next data word has been made available by mass storage 26 device 111. Naturally, other embodiments of this invention 27 will become readily apparent to those of ordinary skill in 28 the art in light of the teachings of this specification 29 which will allow character strings of more than (or, if desired, less than eight characters to be detected. It is 31 also to be understood that word logic 112 typically com-32 prises a plurality of the type of circuits shown in Fig.
33 12, in order that a plurality of character strings may be 34 detected simultaneously. Thus, for example, in this embodiment word logic 112 contains a plurality of sixteen 36 circuits of the type shown in Fig. 12, and thus a plurality 37 of sixteen separate character strings, each character lZZ1~62 ~5-1 string comprising as many as eight characters, may be 2 detec-ted sirnultaneously as character da~a .is trans~erred 3 ~rom mass storage device 111 on bus 111a. Since each such 4 circuit contained within word logic 112 is iden~ical, the description of one such circui-t as shown in Fi~. 12 will 6 fully describe the operation of word logic 112.

By way of example, assume that it is desired to 9 locate each occurrence of the word "knife" within the character data stored in mass storage device 111 (Figure 11 ~). Because -this embodiment of word logic 112 is capable 12 of detecting up to sixteen character strings simulaneously, 13 "knife" will be referred to as word ~ or W~ to distinguish 14 from other words being detected. First, the circuit OI
Fig. 12 is programmed in order to be able to detect each 16 occurrence of the word "knife." To do this, programming 17 logic 116 (Fig. 8j sequentially stores within each character ~8 latch 17-0 through 17-7 a binary signal corresponding to 19 the inverse of the binary signal representing each letter of the word "knife." Thus, programming logic 116 provides 21 on bus llla~address signals A4 through A0 of 0000, together 22 with suitable enabling signals (not shown) to enable 23 decoder 16. These address signals are applied to decoder 24 16 which comprises, for example, a 74154 manufactured by National. In response to this 0000 address signal, decoder 26 16 provides a positive going chip enable 0 (CE0) signal, 27 which is applied to character latch 17-0, thus causing the 28 data bits D7 through D0 provided on bus llla by programming 29 logic 116 to be stored in latch 17-0. Because the letter 30 "k" is depicted in ASCII as a binary 01101011, programming 31 logic 116 provides a D0 through D7 signal on bus llla of 32 10010100, which is stored in character latch 17-0.

3~ Next, programming logic 116 provides an address signal A4 through A0 of 0001, which, together with suitable 36 enabling signals, cause decoder 116 to provide a positive 37 going CEl signal which is applied to character latch 17-1, ~L2Zl~L62 l thus sausing character latch 17-l -to store the D7 tilrough 2 D0 signal provided by programming logic 116. A-t this 3 time, programming logic 116 provides a D7 through D0 4 signal of 10010001, the inverse of the binar~ signal 01101110 which denotes the le-t-ter "n" in ASCII. In a 6 similar manner, programming logic 116 sequentially gener-7 a-tes address signals which, together with suitable enabling 8 signals, cause decoder 16 to provide positive going CE2 9 through CE7 signals, thereby causing data words provided by programming logic 116 -to be stored in character latches 11 17-2 through 17-7, respectively. Since the selected word 12 is "knife", the data which is stored in character latch 13 17-2 is a binary lO010110, corresponding to the inverse of 14 the binary representation of the ASCII letter "i". The data stored within character la-tch 17-3 is a binary lO011001, 16 (the inverse of the letter "f"), and the da-ta stored 17 within character latch 17-4 is a binary 10011010 (the 18 inverse of the letter "e"). Because the word "knife"
19 contains only five letters, it is unimportant what is stored in character latches 17-5 through 17-7, as the 21 presence or absence of the characters detected by character 22 latches 17-5 through 17-7 and their associated components 23 will be masked by NAND gates 22-5 through 22-7, respecti-~ely, 24 in order to have no effect on the WORD~ output signal provided on output lead 112a-0. Output lead 112a-00 26 comprises one of the sixteen leads (leads 112a-1 through 27 112a-15 not shown) forming bus 112a. Leads 112a-0 through 28 112a-15 provide word signals ~ E~ (W0) through WORD15 29 (W15), respectivelyr 31 The masking of unneeded characters is provided as 32 follows. After loading the re~uired data into latches 33 17-0 through 17-7, programming logic 116 sets onto bus 34 llla an eight bit data word which defines which characters are to be masked by NAND gates 22-0 through 22-7. This 36 eight bit mask word is stored in latch 20 (which may 37 comprise, for example, a 74374 manufactured by National) ~Z;Z1~6%

1 in response to the CE8 signal from decoder 16, ~lhich is 2 generated in response to appropriate signals from program-3 ming logic 116. Because "knife" contains only five charac-4 ters,~ the eight bit mask provided by programming loyic 116 and stored in latch 20 is a binary 00011111, indicating 6 that the three characters detected by character latches 17-5 through 17-7 and their associated components are to 8 be masked.
After the programming of the character latches 17-0 11 through 17-7 and the masking latch 20 of the WORD~ circuit 12 of Fig. 12, the character latches and masking latches of 13 the WORDl through W0RD15 circuits are programmed in a 14 similar manner in order to allow these WORDl through WORD15 circuits to detect additional words simultaneously 16 with the WORD0 circuit detecting occurrences of the word 17 "knife"-19 Mass storage device 111 then transfers its contents on a character-by-character basis to bus llla. Each data 21 bit D7 through DO of each character transferred onto bus 22 llla is applied to one input lead of a plurality of eight 23 exclusive OR gates, each such exclusive OR gate being 2~ associated with one character latch 17-0 through 17-7.
Thus, the DO bit is applied to one input lead of exclusive 26 OR gate 18-Oa assoeiated with character latch 17-0, one 27 input lead of exclusive OR gate 18-la associated with 28 eharaeter latch 17-1,... and one input lead of exclusive 29 OR gate 18-7a associated with character latch 17-7. The remaining input lead of each exclusive OR gate receives 31 the appropriate bit from its associated character latch 32 17-0 through 17-7. Thus, exclusive OR gate 18-Oa receives 33 the DO signal from bus llla and the least significant bit ~~
34 stored in character latch 17-0. Similarly, exclusive OR
gate 18-Ob receives the Dl signal from bus llla, and the .

~L22~ 6Z

-'~8-1 second leas-t significan-t bit s-tored in character latch 2 17-0, e-tc. Because character la-tch 17-0 stores the binar~
3 inverse of the Eirst character "k" to be detec-ted, when 4 the chrac-ter "k" is set onto bus ll:La, each exclusive OR
gate 18-Oa through 18-Oh receives complementary input 6 signals (i.e., one input signal is high, and the other 7 input signals is low), and thus the output signal from 8 each exclusive OR gate 18-Oa through 18-Oh is a logical 9 one, which are in turn applied to the input leads of NAND
gate 19-0, thus providing a logical zero k output signal 11 from NAND gate 19-0. Conversely, iE a character other 12 than a "k" is set onto bus llla, at least one exclusive OR
13 gate 18-Oa -through 18-Oh receives identical signals on its 14 input leads i.e. either both logical zero or both logical one), and thus that exclusive OR gate generates a logical 16 zero output signal which causes NAND gate 19-0 to provide 17 a logical one k output signal, indicating that the character 18 "k" has not been detected.

In a similar manner, the remaining character latches 21 17-1 through 17-4, and their associated exclusive OR gates 22 and NAND gates, provide logical zero n, i, f and e signals 23 on the output lead of NAND gates l9-l through 19-4 when 24 the characters "n", "i", "f", and "e", respectively, are detected. At all other times, the signals on the output 26 lead of NAND gates l9-1 through 19-4 are logical one.

28 The output signals from NAND gates 19-0 through 19-7 29 are applied to one input lead of masking NAND gates 22-0 through 22-7, respectively. Masking NAND gates 22-0 31 through 22-7 mask the detected character signals provided 32 by NAND gates 19-0 through 19-7 in accordance with the 33 masking word stored within masking latch 20- The least 34 significant bit stored in masking latch 20 is applied to the other input lead of NAND gate 22-0, the second least 36 significant bit stored within that masking latch 20 is 37 applied to the other input lead of NAND gate 22-1, etc., 3~

_,~9_ 1 and the most significant bi-t s-tored in masking Latc}l 23 s 2 applied -to the other input leacl o~ NAND gate 22-7 Beca~c;e 3 the three most significant bits stored in Inaskill(3 latc.l 20 4 are zeroes, and these logical zeroes are applied to one input lead of NAND gates 22-S -through 2 -7, NAND gates 6 22-5 through 22-7 always provide logical one signals on 7 their output leads. Thus, even though the output signals from NAND gates 19-5 through 19-7 are applied ~o one input 9 lead of NAND gates 22-5 through 22-7, respecti~tel~, these signals from NAND gates 19-5 through 19-7 have no effec~
11 on the output signals provided by NAND gates 19-5 througn 12 19-7. Conversely, because the five least significant bits 13 stored in masking latch 20 are logical ones, the output 14 signals provided by NAND gates 22-0 -through 22-4 will be the inverse of the signals provided by NAND gates 19-0 16 through 19-4, respectively. Thus, ~hen the character "k"
17 is set onto bus llla, NAND gate 1~-0 provides a logical 18 zero k signal to one input lead of NAND gate 22-0, which 19 in turn provides a logical one k output signal. In a 2~ similar manner, when the letter "n" is set onto bus llla, 21 NAND gate 22-1 provides a logical one n output signal;
22 when the character "i" is set onto bus llla, NAND gate 23 22-2 generates a logical one i output signal; when the 24 character "f" is set onto bus llla, NAND gate 22-4 generates a logical one f output signal; and when the character "e"
26 is set onto bus llla, NAND gate 22-5 generates a logical 27 one e output signal. As previously described, NAND gates 28 22-5 through 22-7, corresponding to the detection of 29 characters which are not of interest when searching for the character string "knife", always provide logical one 31 output signals.

33 The output signals from NAND gates 22-0 through 22-34 are applied to the input leads of shift registers 23-0 through 23-7, respectively. Shift register 23-0 is an 36 eight bit shift register, shift register 23-1 is a seven 37 bit shift register, shift register 23-2 is a six bit shitt ,, ~-z~

1 register, etc., and shift regis-ter 23-7 is a one bit shift 2 register. Shift regis-ters 23-0 through 23-7 are formed, 3 for example, by the appropriate connec-tion of a plurality 4 of 74174 hex D-type flip flops manufactured by National.
Shift registers 23-0 through 23-7 each receive a clocl~
6 signal on input lead 23-7a which is provided by mass 7 storage device 111 (Fig. 8) on bus llla, indicating that a 8 valid data character is present on bus llla. The signals 9 provided by NAND gates 22--0 through 22-7 are received by shift registers 23-0 through 23-7, and -the content of each 11 shift register 23-0 through 23-7 is shifted -to the next 12 most significant bit within that shift register upon 13 receipt of each clock signal on lead 23-7a. In this 14 manner, the output signals as provided by shift registers 23-0 through 23-7 depict the positional relationship of 16 the detected characters.

18 In order to provide a logical zero WOR~ signal 19 indicatin~ when the word "knife" is detected, and provide a logical one W ~ signal when the word "knife" is not 21 detected, shift registers 23-0 through 23-7 are used. In 22 this example, the character string "knife~ " is to be 23 detected, where each "~"indicates a "don't care" character.
24 To detect the charac-ter string "knife~o~", the most recently detected character must be a "don't care" character, the 26 second most recently detected character must also be a 27 "don't care" character, the third most recently detected 28 character must be a "don't care" character, the fourth 29 most recently detected character must be the letter "e", the fifth most recently detected character must be a "f", 31 the sixth most recently detected character mus-t be an "i", 32 the seventh most recently detected character must be an 33 "n", and the eighth most recently detected character must 34 be a "k". Accordingly, since the character "k" must be the eighth most recently detected character, the output 36 signal from NAND gate 22-0, indicating when the character 37 "k" has been detected, is applied to 8 bit shift register ~,.ZZ1~6Z
5l 1 ~3-o. Similarly, since -the letter "nl' mus-t be the seven-th 2 most recently detected character, the output signal from 3 NAND ga-te 22-1, which indicates when the le-t-ter l'n" has 4 been detected, is applied -to the inpu-t lead of seven bit shift register 23-l, etc. When the proper se~uence of 6 characters have been detected which spell "knifeoo~" the 7 output signal from each shift register 23-0 through 23-7 8 is a logical one, which in turn is applied -to the input 9 leads of NAND gate 23-?3, thus causing NAND gate 23-8 to provide a logical zero WORD0 signal on output lead 112a-0, ll thus indicating that "knife" has been detected. At all 12 o-ther times, at least one output signal from shift registers 13 23-0 through 23-7 is a logical zero, thus causing NAND
14 gate 23-8 to provide a logical one W~ signal on output lead 112a-0, thus indicating that "knife" has not been 16 detected.

18 It is apparent to those of ordinary skill in the art l9 in light of the teachings of this specification that, if desired, word logic 112 can be programmed such that pro-21 gramming latches 17-0 through 17-7 and their associated 22 components detect the character string "oooknife", rather 23 than "knifeooo" as described above. In -this even-t, the 24 masking word stored in masking latch 20 will be 11111000, indicating that the three characters detected by character 26 latches 17-0 through 17-3 and their associated components 27 are to be masked by NAND gates 22-0 through 22-3, respec-28 tively. In this embodiment, where the "don't care" charac-29 ters precede the characters to be detected, the ~ORD0 signal goes low upon receipt of the last character in the character 31 string being detected, rather than j characters later, where 32 j is the number of "don't care" characters in the character 33 string being detected (i.e., j=3 for ''oooknifes'~)~

It is also apparent to those of ordinary skill in the 36 art in light of the teachings of this specification that, 37 if desired, word logic 112 can be programmed such that the "

lZ;Z ~L6;~

1 programming la-tches 17-0 throuyh 17-7 and -their associated 2 componen-ts detect the character string "efin]saon". In 3 this even-t, the masking words stored in masking latch 20 4 will be 00000111, indicating that the three characters detected by character latches 17-5 through 17-7 and -their 6 associated components are to be masked by NAND gates 22-5 7 through 22-7, respectively. In this event, however, shift 8 register 23-0 is a one bit shift register, shift register 9 23-1 is a -two bit shift register, shift register 23-2 is a three bit shift register, e-tc., and shift register 23-7 is 11 an eight bit shift register.

13 It is also apparent to one of ordinary skill in the art 14 in light of the teachings of this specification that, if desired, word logic 112 can be programmed such that programming 16 latches 17-0 through 17-7 and -their associa-ted components 17 detect the characters string "oLoefink". In this event, the 18 masking word stored in masking latch 20 will be 11100000, 19 indicating tha-t the characters detected by character latches 17-0 through 17-2 and their associated components are to be 21 masked by NAND gates 22-0 through 22-2, respectively. In 22 this event, shift register 23-0 is a one bit shift register, 23 etc., and shift register 23-7 is an eight bit shift register.

If it is desired to detect the occurrence of either 26 upper case or lower case letters, the sixth least signifi-27 cant bit received from mass storage device 111 is held high 28 and the word latches 17-0 through 17-6 are loaded with data 29 to cause the detection of upper case letters forming the desired word. Alternatively, the sixth least significant 31 bit received from mass storage device 111 is held low, and 32 the word la-tches 17-0 through 17-6 are loaded with data to 33 cause the detection of lower case letters forming the 34 desired word. In either event, both upper and lower case letters will be detected by latches 17-0 through 17-6 and 36 their associated components, as the sixth least significant 37 bit, which distinguishes between upper and lower case, is ~Z~ Z

1 effec-tively masked. In anothe:r embodiment of this inven-2 tion, the OUtpllt signal Erom the sixth least significant 3 exclusive nor gates 18 Ob, 18-~b, . . . 16 6b, are held 4 high, thereby effectively masking -the six-th leas-t signifi-S cant bit and thus providing output signals when either 6 upper or lower case letters are detec-ted.

8 Set Logic 114 9 Figs. 10a through 10d form a schematic diagram of se-t logic 114. Although not shown in Figure 10, set logic 114 ll includes a latch (such as a 74373 device manufactured by 12 National) provided between mass storage device 111 (Figure 13 8) and bus lla, in order to store data output from mass 14 storage device 111 and provide this data to the remainder of set logic 114 until the next data word has been made 16 available by mass storage device 111. Set lagic 114 17 serves to determine when a set of selected words are 18 detected within the same sentence, paragraph, document, 19 etc., as defined by the user's search strategy. For example, that portion of set logic 114 shown in Fig. 10a 21 detects when a predefined set of words 0 through 3 (i.e., 22 a user defined set of' ~0 through W3 signals generated by 23 word logic 112 (shown in Figs. 8 and 12) are detected 24 within the same sentence or paragraph, etc. As previously ~5 described, the W0 through W3 signals are provided by word 26 decode logic 112 tFig. 12). Set logic 114 as shown in 27 Fig. 12 is capable of receiving sixteen word signals 28 (i.e., W0 through W15, although it is apparent to one of 29 ordinary skill in the art in light of the teachings of this specification that set logic 114 can be constructed 31 to operate on any desired number of words which are each 32 detected, for example, by a uni~ue one of an e~ual number 33 of circuits as shown in Fig. 12 which form word logic 112.
34 Furthermore, as will now be fully described, set logic 114 is capable of forming a plurality of sets, each set being 36 generated by a plurality of four words. It is readily 37 apparent to one of ordinary skill in the art in light of :~LZ2~6~

1 the teachings of this specification that set logic 11~ can 2 be constructed in order to form arly desired number of 3 sets, each set beiny ~enerated in response to any desired 4 number of words. Because the embodiment of se-t loyic 114 depicted in Fig. 10 is forrned of fol~r subs-tantially identi-6 cal subcircuits (one such subcircuit being substantially 7 shown in each of Figs. 10a through 10d), the following 8 description of the operation of the subcircuit of Fig. 10a 9 is sufficient to describe the operation of the entire set logic 114 depicted in Fig. 10a through 10d.

12 Referring to Fig. 10a, leads 9-la through 9-lh are 13 connected to bus llla to receive the data signals D0 14 through D7, respectively. The delimiter signals (EOT, EOC, FOD, EOP, EOS, and EOW) are received from delimiter 16 logic 113 (Figs. 8 and ~) on bus 113a. The ~0 through '~3 17 signals are received from appropriate portions of word 18 logic 112 (Figs. 8 and 12) and applied to the SET 3 input 19 leads of SR latches 10-7a through 10-7d, respectively.
Latches 10-7a through 10-7d serve to store data indicatins 21 when words 0 through 3, respectively, have been detected 22 by word logic 112. SR latches 10-7a through 10-7d each 23 comprise, for example, one of the four latches contained 24 ~ithin a DM7a279 device manufactured by National.
26 Multiplexer 10-3 selects the appropriate delimiter 27 signal or ground, as will be fully described later) and, 28 in response thereto, provides a RESETA signal which is 29 applied to the RESET (R) input leads of latches 10-7a through 10-7d, causing latches 10-7a through 10-7d to be 31 reset to store logical zeros when the RESETA signal is a 32 logical zero. Multiplexer 10-3 comprises, for example, a 33 74151 device manufactured by National. Latch 10-1 stores ~-34 information provided by programming logic 116 (Fig. 8) on 35 bus llla during the programming of the text comparator 36 prior to executing a textual search strategy. Latch 10-1 37 comprises, for example, a 74374 device manufactured by 38 National-~Z~62 1 Latch 10-8 (for example a 74374 device) serves to 2 store masklnc3 informa-tion which i~ provided by programming 3 logic 116 (Fig. 8) to la-tch 10-8 ~ia bus llla during -the 4 programming of the text comparator of this invention prior to the execu-tion of a user-defined textual comparison 6 search strategy. Logical AND circuitry 10-36 combines the 7 ~ through W3 signals in a logical AND and a logical N~ND
8 fashion and provides the SETlAND (S2AND) and the SET2.~iD
9 (SlAND) signals on leads 10-14a and 10-16a, respectivel~y.
Similarly, the logical OR circuitry 10-37 combines the r~;o 11 through W3 signals in a logical OR and a logical NOR
12 fashion and provides the SETlOR (SlOR) and the SETlOR
13 (SlOR) signals on leads 10-13a and 10-15a, respectively.
14 Logical AND circuitry 10-36 and logical OR circuitry 10-37, when masked by the masking data stored in masking 16 latch 10-8, provide output signals which indicate whether 17 the word O through 3 have been detected between two occur-18 rences of the signal selected by decoder 10-3, thereb~
19 providing output signals indicating whether words 0 through 3 have been detected in the same sentence, for example.

22 In order to program set logic 114, programming logic 23 116 (Fig. 8) first sets onto -the D0 through D7 data lines 24 of bus llla the information which is to be stored in latch 10-1. Programming logic 116 then provides the appropriate 26 A0 through A2 and E1 through E3 signals, thereby causing 27 multiplexer 9-18 (Fig. 9a) to generate a positive going 28 CLK10-1 signal, which is applied to latch 10-1, thereby 29 causing the D0 through D7 data on bus llla to be stored within latch 10-1. The three least significant bits 31 stored in latch 10-1 are applied to the address input 32 leads of multiplexer 10-3, and similarly -the next three 33 least significant bits stored in latch 10-1 are applied to 34 the address input leads of multiplexer 10-4. The three address signals applied to multiplexer 10-3 define which 36 delimiter signal ~or ground, if the input lead of multi-37 plexer 10-3 which is connected to ground, as shown, is . , :~Z2'~L~62 1 selected by mul-tiplexer 10-~ in response to the address 2 signals provided thereto by latch 10-1) are to gerlerate 3 the RES-ETA signal on -the output lead oE m-lltiplexer 10-3.
4 Ground is selected by multlplexor 10~3 in orcier to generate S a RESETA signal when desired to reset the con-tents, of 6 flip-flops 10-7a through 10-7d, for example on power-up of 7 the set logic 11~. Next, programming logic 116 (Fig. 8) 8 sets onto the D0 through D7 data leads of bus llla the 9 masking data which is to be stored in maslcing latch 10-~.
Programming logic 116 then sets onto bus llla the A0 11 through A2 and the El through E3 signals which cause 12 demultiplexer 9-18 (Fig. 9a) to generate a positive going 13 CLK10-2 signal, which in turn is applied to latch 10-8, 14 thereby causing the data on leads D0 through D7 of bus llla to be stored in latch 10-8. If required by the user 16 defined search strategy, programmlng logic 116 then repeats 17 these steps in order to program the remaining latches 18 10-2, 10-9, 10-10, and 10-11 of set logic 114.

Assume, for example, that it is desired to locate 21 within the textual information stored in mass storage 22 device 111 all instances where the word "knife" (WORD0) 23 occurs within the same sentence as the word "blood"
24 (WORD1). Programming logic 116 programs word logic 112 as previously described, to cause WORD0 -to be the word "knife"
26 and WORD1 to be the word "blood", thus causing a low W0 27 signal and a low Wl signal to be generated upon detection 28 of the words "knife" and "blood", respectively. Because 29 it is desired to locate these two words only within the same sentence, the latches 10-7a through 10-7d must be 31 reset upon receipt of the EOS delimiter signal. Accordingly 32 programming logic 116 stores within latch 10-1 three least 33 significant bits which, when applied to the address input 3~ leads of multiplexer 10-3, cause multiplexer 10-3 to select the EOS signal applied via bus 113a to generate the 36 RESETA signal. Furthermore, because only WORD0 and WORD1 37 are of interest in this particular search, programming 1 logic 116 causes -to be stored in masking latch 10-8 an 2 eight bit mask which will cause the W2 and W3 signals to 3 have no effect on the output signals genera-ted by the 4 logical AND logic circuitry 10-36.

6 Because in this example the ~70rds "knife" and "blood"
7 are to be combined a logical AND operation, the output 8 signals from logical OR circuitry 10-37 are not used, and 9 thus the value of the four most significant bits s-tored in masking latch 10-8 is unimportant. However, in order to 11 cause logical AND circuitry 10-36 -to provide SlAND and 12 SlAND output signals generated by the logical operation 13 Sl~ND = (~ AND Wl) the four least significant bits (D4 14 -through D0) provided by programming logic 116 and stored in latch 10-8 must be equal to 1100, respectively. In 16 -this manner, the least significant bit stored in masking 17 latch 10-8 is a logical zero, which is applied to one 18 input lead of NOR gate 10-12h. With a logical zero signal 19 applied to one input lead of NOR gate 10-12h, the other input lead of NOR gate 10-12h, which is connected to the o 21 output lead of flip flop 10-7a, controls -the output signal 22 from NOR gate 10-12h. Similarly, with the second least 23 significant bit being a logical zero, ~hich is applied to 24 one input lead of NOR gate 10-12g, the other input lead of NOR gate 10-12g, which is connected to the Q output lead 26 of flip flop 10-7b, causes NOR gate 10-12g to generate its 27 output signal in response to the W1 signal stored in flip 28 flop 10-7b. Because the third and fourth least significant 29 bits stored in masking latch 10-8 are logical ones and are each applied to one input lead of NOR gates 10-12f and 31 10-12e, respectively, NOR gates 10-12e and 10-12f always 32 provide logical zero output signals, indicating that the 33 W2 and W3 signals stores in latches 10-7c and 10-7d, 34 respectively (and thus WORD2 and WORD3) are unimportant and form no part of the logical operation performed by 36 logical AND circuitry 10-36.

~.

~2i~GZ

1 The ou-tput signals from NOR gates 10-12e through 2 10-12h are applied to the lnput leads of NOR gate 10-14.
3 Because the output signals from NOR ga-tes 10-12e and 4 10-12f are always a logical zero, the~ will have no effect on -the output signal generated by NOR gate 10-14. However, 6 only when the output signals generated by NOR gates 10-12g 7 and 10-12h are logical zeros, indicating that logical ones 8 are stored in both shift registers 10-7a and 10-7b (i.e., 9 logical zero W0 and Wl signals have been received and thus logical one W0 and W1 signals stored in flip flops 10-7a 11 and 10-7b, respectively, since the last RESETA signal) 12 will the SlAND output signal from NOR gate 10-14 be a 13 logical one, indicating that the words "knife" and "blood"
14 have both been located in a single sentence.

16 As previously described, the RESETA signal is, in 17 this example, generated by multiplexer 10-3 in response 18 to the EOS signal. Accordingly, the data stored in latches 19 10-7a and 10-7d is reset to logical zeros in response tG a logical zero RESETA signal. If after a logical zero 21 RESETA signal the word "knife" is detected, a logical zero 22 W0 signal is applied to the 3 input lead of flip-flop 23 10-7a, thus causing a logical one to be stored in flip 24 flop 10-7a. This generates a logical one Q output signal from flip-flop 10-7a which is applied to one input lead of 26 NOR gate 10-12h, thus causing NOR gate 10-12a to generate 27 a logical zero output signal. However, because the word 28 "blood" (WORDl) has not been detected, a logical zero is 29 still stored in shift register 10-7b, and shift register 10-7b provides a logical zero Q output signal which is 31 applied to one input lead of NOR gate ]0-12g. This, 32 to~ether with the logical zero input signal applied to its 33 other input lead from latch 10-8, causes NOR gate 10-12g 34 to provide a logical one output signal, thus causing NOR
gate 10-14 to generate a logical zero SETlAND output 36 signal, indicating that the words "knife" and "blood" have 37 not both detected in the same sentence. If an EOS signal Z2~2 _59_ 1 is now generated prior to the detection of the ~/ord "blood", 2 multiplexer 10-3 generates a logical zero I~ES~ siynal 3 and the shiEt registers 10-7a -through 10~7d are reset to ~t store logical zeros, -thereby preventillg an errorleous output signal from logical AND circuitry 10-36 sllould the 6 word "blood" be detected in a subse~uent sen-tence which 7 does not also contain the word "knife".

9 In a similar manner, if the search strategy requires the location of all occurrences of either the word "knife"
11 or "blood" in -the same sentence, the logical OR circuitry 12 10-37 is utilized. In this event, the four most significant 13 masking bits stored in masking latch 10-8 by programming 14 logic 116 are 0011. With the most significant bi-t from masking latch 10-8 being applied to one input lead of NAND
16 gate 10-12a, NAND gate 10-12a always genera-tes a logical 17 one output signal, and thus the W3 signal stored in shift 18 register 10 7d has no effect on the output signals generated 19 by OR logic circuitry 10 37. Similarly, because the second most signficant masking bit stored in masking latch 21 10-8 is applied to one input lead of NAND gate 10-12b, 22 NAND gate 10-12b always generates a logical one output 23 signal, and thus the W2 signal stored in shift register 24 10-7c has no effect on the output signal generated by logical OR circuitry 10-37. The third and fourth most 26 significant masking bits stored in masking latch 10-8 are 27 logical ones, and are applied to one input lead of NAND
28 gates 10-12c and 10-12d, respectively. These logical one 29 signals cause the output signals from NAND gates 10-12c and 10-12d to be generated in response to the W0 and Wl 31 signals stored in flip-flops 10-7a and 10-7b, respective 32 and applied to the other input lead of NAND gates 10-12d 33 and 10-12c, respectively. If the word "knife" is detected, 34 a logical zero W0 signal is generated by word logic 112, and thus a logical one W0 signal is stored in flip-flop 36 10-7a. This logical one W0 signal causes NAND gate 10-12d 37 to generate a logical zero output signal which causes NAND

.

~L221~6;2 1 gate 10-13 to generate a logical one SlOR slgnal on output 2 lead 10-13a (and causes inverter 10-5 to generate ~l loylcal 3 zero SlOR signal on output lead 10-15a), thus indicatiny 4 that the word "knife" has been detected. Similarly, if S the word "blood" is detected, a logical zero Wl signal is 6 generated by word logic 112 and thus a logical one Wl 7 signal is stored in flip flop ~0-7b. This logical one W1 8 signal causes NAND gate 10-12c to generate a logical zero 9 output signal, which in turn causes NAND ga-te 10-13 to generate a logical one SlOR signal on ou-tput lead 10-13a 11 (and causes inverter 10-15 to generate a logical zero SlOR
12 signal on output lead 10-lSa), thus indicating that the 13 word "blood" has been detected. If nei-ther the word 14 "knife" or the word "blood" is detected, flip flops 10-7a through 10-7d will each store a logical zero signal, NAND
16 gates 10-12a through 10-12d each generate logical one 17 output signals, N~ND gate 10-13 generates a logical zero 18 SlOR signal, and inverter 10-15 generates a logical one 19 SlOR signal), thus indicating that neither "knife" or "blood" has been detected.

22 Set Combination Logic 115 24 Set combination logic 115 serves to combine the set signals provided by set logic 114 (Figure 10) in accordance 26 with a user defined search strategy. Although not shown 27 in Figure 11, set combination logic 115 includes a latch ~8 (such as a 74373 device manufactured by National) provided 29 between mass storage device 111 (Fig. 8) and bus llla, in order to store data output from mass storage device 111 31 and provide this data to the remainder of set combination 32 logic 115 until the next data word has been made available 33 by mass storage device 111. Set combination logic 115 34 includes latches 11-2 and 11-3 (which comprise, for example 74374 devices manufactured by National) which store set 36 combination words provided by programming logic 116 in 37 response to the user defined search strategy. Latches 11-2 ~221~2 1 and 11-3 store thls information in response to the CLK11-6 2 and CLK11-7 signals, respectively, genera-ted by decoder 3 9-17 (Fig. 9), as previously described). Set combina-tion 4 logic 115 also includes RS Elip-flops ll-la thro-lc3h ll-lh 5 which comprise, for example, 74279 devices manufactured by 6 National. Shift registers ll-la through 11-lh store the 7 SOOR, SIAND through S30R, ~ D signals provided by set 8 logic 114 (Figure 10). Flip-flops 11-la through 11 lh are 9 reset by reset signal lla provided by programming logic 116 (Fig. 8) when a search strategy is begun.

12 Latch 11-2 stores the masking word provided by pro-13 gramming logic 116, in order to cause NAND gates 11-2a 14 through 11-2h and their associated components to combine the set signals stored in flip flops 11-la through 11-lh 16 in a logical OR function. For example, if it is desired 17 to combine the SOOR and SOAND signals, programming logic 18 116 (Figure 8) causes latch 11-2 to store D7 through D0 19 signals of 00000011, where the logical ones indicate which set signals are to be combined in the logical OR function.
21 Thus, latch 11-2 provides logical zero signals to one 22 input lead of NAN~ gates 11-2a through 11-2f, thereby 23 causing the output signals from these NAND gates 11-2a 24 through 11-2f to be logical ones. Latch 11 2 also provides logical one signals to one input lead of NAND gates 11-2g 26 and 11-2h. The other input leads of NAND gates 11-2g and 27 11-2h are connected to the Q output leads of flip flops 28 ll-la and 11-lb, respectively. Prior to the SUOR and 29 SOAND signals going low, the Q output signals from flip-flops 30 ll-la and 11-lb are logical zero, thus causing the output 31 signals from 11-2g and 11-2h to be logical ones. This 32 causes the output signal from NAND gate 11-3 to be logical 33 zero, and the output signal from inverter 11-4 to be 34 logical one. Thus, only when a logical zero S00R signal 35 or ~D signal has been generated by set logic llds (Fig.
36 10), will the Q output signal from flip-flops 11-la or 37 ll-lb be a logical one, thereby causing the output signal 38 from NAND gates 11-2g and 11-2h to be a logical zero.

~22~L62 1 With one input signal to NAND ga-te 11-3 a logical zero, 2 the output signal from NAND yate 11-3 is a logical one, 3 indicating that the logical OR combination of the set 4 siynals de~ined by the masking word stored in latch 11-2 has been met. This logical one signal from NAND gate 6 11-3 causes the outpu-t signal from inverter 11-~ be a 7 logical zero, thereby causing -the output signal from NAND
8 gate 11-9 to be a logical one.
g In a similar manner, latch 11-3 stores a masking word 11 provided by programming,logic 116 in order to combine the 12 set signals applied to flip flops ll-la through 11-lh to 13 be combined in a logical AND fashion. Thus, if it is 14 desired to combine the SOOR signal with the S0AND signal in a logical AND function, latch 11-3 is programmed by 16 programming logic 116 (Fig. 8) to store D7 through D0 17 signals 11111100. With logical ones applied to one input 18 lead of NOR gates 11-5a through 11-5f, the output signals 19 from these NOR gates are logical zeroes. With logisal zero signals applied by latch 11-3 to one input lead of ~1 NOR gates 11-5g and 11-5h, the output signals from NOR
22 gates 11-5g and 11-5h will be logical zero only when both 23 the SOOR and S0P~ signals have been logical zero, thus 24 causing logical one Q signals to be provided by both flip-flops 11-la and 11-lb, respectively. With the output 26 signal from both NOR gates 11-5g or 11-5h logical zeros, 27 the output signal from NOR gates 11-7 is logical one, and 28 t,he output signal from NAND gate 11-8 is a logical zero, 2~ indicating that both S00R and S0AND has been low. This causes the output signal from NAND gate 11-9 to be a 31 logical one.

33 Thus, a logical one on the output lead of N.~ND gate --34 11~9 indicates that ei,ther the logical OR function provided 35 by latch 11-2 and its associated componentS or the logica 36 AND function provided by latch 11-3 and its associated 37 components, has been met. This logical one output signal 38 from NAND gate 11-9 is available on lead 115a-1 to provide ~2~ 2 1 an interrupt signal to a central proce.ssin~ unit (CPU, not 2 shown) if desired. This Lnterrupt ~signal can be inverted by an 3 inverter tnot shown) if desired. Tllis logical one output 4 signal from NAND gate 11-9 also provLdes a clock signal to 5 latch 11-10 ancl which compri:,es, ~or exarnple a 74373 device 6 manufactured by National), thus causing the Q output signals 7 from flip flops ll-la throug~l ll-lh to be stored in latch 8 11-10. Terminal ll-lOa re^eives an output enable signal from 9 the central processing unit, thereby causing the bits stored in latch 11-10 which indicate the statug of the set signals 11 received and stored within flip-flops ll-la through ll-lh, to 12 be set onto bus 111 a for use by the central processing unit, if 13 desired.

Proximity Logic 117 17 Referring to Figure 13, the operation of proximity logic 18 117 will now be described. Proximity logic 117 includes a 19 latch (such as a 74373 device manufactured by National) provided between mass storage device 111 (Figure 8) and bus 21 111a, in order to store data output from mass storage device 22 111 and provide this data to the remainder of proximity logic 23 117 until the next data word has been made available by mass 24 storage device llla. Proximity logic 117 serves to detect when a first selected word (detected by word logic 112 of 26 Fig. 12) or set (detected by set logic 114 of Fig. 10) is 27 located within a specific distance or proximity of a second 28 selected word or set. For example, proximity logic 117 can 29 be programmed to detect when a first word "knife" (detected by word logic 112 as, ror exarnple, word zero) is located 31 within n words of a second selected word "blood" (detected by 32 word logic 112 as, for example, word four), wherein n is a 33 selected integer ranging from -7 to 7. Naturally, it is 3~ apparent to those of ordinary skill in the art in light of the teachin~s of this specification that alternati~e 36 embodimentS of proximity logic 117 can be constructed which 37 will allow selection from a greater number of words or sets, ~LZ~462 -6~-1 and where the range of proximi-ties can be an~ desired number, 2 including numbers greater -than 7. Furthermore, proximi-ty 3 logic 117 allows detec-tion of words or sets ~ thin a plural-4 ity o~ n delimiter characters. Thus, proximity logic 117 is capable, for example, of de-tecting when a first selected 6 word or se-t is located within n sen-tences, paragraphs, 7 documents, e-tc., of a second selected word or set.

9 The operation of the embodiment o~ proximi-ty logic 117 shown in Figure 13 is as follows. Proximity logic 117 11 includes latches 13-2 and 13-5 which are programmed by pro-12 gramming logic 116 to store address bits which in turn are 13 applied to decoders 13-3 and 13-4, respectively, which 14 cause decoders 13-3 and 13-4 to select which delimiter signal will provide clock signals CL~ 13-l and CL~ 13-2, 16 respectively. Latches 13-2 and 13-5 comprise, for example, 17 74374 devices manufactured by National. La-tch 13-2 is pro-18 grammed by programming logic 116 setting onto bus llla the 19 desired word to be stored, and appropriate address signals which cause decoder 16 (Figure 12) to genera-te a CE9 signal.
21 Latch 13-5 is then programmed by programming logic 116 22 setting onto bus llla the desired bits to be stored within 23 latch 13-5, and appropriate address signals ~3 through A0 to 24 cause decoder 16 to generate a CE11 signal. Latch CElO
(also a 74374 device) is then programmed in a similar manner 26 to provide address signals to decoders 13-8 and 13-9, which 27 in turn each select one of a plurality of word and set 28 signals for use by proximity logic 117, as will be more 29 fully understood with reference to the following discussion.
31 The data stored within latch 13-2 also provides three 32 address bits to decoder 13-6, which causes decoder 13-6 to 33 select the appropriate word or set signal to be applied to 34 the input lead of shift register 13-ll. In a similar fashion, latch 13-10, which is programmed by programming 36 logic 116 when accessed by a CElO signal generated by 37 decoder 16 (Figure 12), provides address signals to decoders 38 13-8 and 13-9 which selects the appropriate set and word . . .

~Z21'~

1 signals for input to shift registers 13~L5 arld 13-17. ~wo 2 bits from la-tch 13-2 and one bit from latch 13-lO ser~;e as 3 address inpu-t signals -to decoder 13-7, t:hereby se:Lect .q 4 the appropxiate word and se-t signals for input to shi t register 13-13. La-tches 13-2, 13-5, and 13-10 cornDrise, 6 for example, 74374 devices manufactured by National.
7 Decoders 13-3, 13-4, 13-6, 13-7, 13-8, and 13-9 cornprise, 8 for example 74151 devices manufactured bv National.

The operation of shift register 13-11, latch 13-i2, 11 and their related components is identical to the operation 12 Of shift register 13-13 and latch 13-14, shift register 13 13-15 and latch 13-16, and shift register 13-17 and latch 14 13-18, and their related components, and thus only the operation of shift register 13-11 and latch 13-12 and 16 their associa-ted components will be described here. Shif !
17 registers 13-11, 13-13, 13-15 and 13-17 comprise, for 18 example 74164 serial in-parallel out shift registers 19 manufactured by National. La-tches 13-12, 13-14, 13-16, and 13-18 comprise, for example, 74374 devices manufactured 21 by National. Latch 13-12 is programmed by programming 22 logic 116 in response to a CE12 signal generated by decoder 23 16 (Figure 12) in response to the appropriate A3 through 24 A0 signals provided by programming logic 116. Latch 13-12 stores an eight bi-t proximity word which defines the 26 desired proximity of the words or sets being searched.
27 Shift register 13-11 stores signals representing the 28 relative position of the set or word selec-ted by decoder 29 151. The bits stored in latch 13-12 indicate which posi-tions within shift register 13-11 are of interest in the 31 search strategy. For example, if it is desired to find 32 word zero within two words of word seven (i.e., "undirected~
33 proximity), programming logic 116 programs latch 13-2 to 34 cause decoder 13-6 to select the W0 signal, and decoder 13-7 to select the W7 signal. Furthermore, programming 36 logic 116 programs latch 13-12 to store 00000111, and 37 latch 13-14 to store 00000111. Programming logic 116 38 programs latch 13-2 to cause decoder 13-3 to select the 12;~ iZ

signal as the CLK13-1 sigrlal, thus causing -the W0 and 2 W7 slgnals selected by decoders 13-6 and 13-7, respectively, 3 to be shifted into shlft registers 13~11 and 13-13, r.espec-tively, on each EOW signal.

6 With -the four most significant bits of la-tch 13-12 7 logical zeroes, NAND gates 13-19a through 13-19e are 8 disabled, thereby providing logical one outpu-t signals 9 regardless of the contents of -the five most significant bits of shift register 13-ll. However, because the -three ll leas-t significant bi-ts s-tored in latch 13-12 are logical 12 ones, the output signals from NAND gates 13-19f through 13 13-19h are the logical inverse of the three least signifi-14 cant bits of shift register 13-11. Thus, if a logical one is stored in any of the three least significant bits of 16 shift register 13-11, the output signal from the associated 17 NAND gate 13-19f through 13-19h is a logical zero, thus 18 causing NAND gate 13-23 to generate a logical one output 19 signal. Thus, when both word zero and word seven appear within the last three words decoded (i.e., word zero is 21 within two words of word 7), the output signal from NAND
22 gates 13-23 and 13-24 are both logical ones, and thus the 23 output signal from NAND gate 13-27a is a logical zero, 24 indicating that word zero and word seven have been located within two words of each other.

27 In a similar manner, NAND gates 13-27b through 13-27h 28 provide output signals based on the appropriate logical 29 combinations of the output signals from NAND gates 13-23 through 13-26. Latch 13-5 also provides three address 31 signals to decoder 13-28 (which comprises, for e~ample, a 32 74151 device as manufactured by National) which in turn 33 selects the output signals from one of NAND gates 13-27a 34 through 13-27h to provide an interrupt signal on terminal 13-50. This interrupt signal is used to indicate to a 36 central processing unit (not shown) that the text comparator 37 of this invention has detected the occurrence of the 38 desired words or sets of words defined by the search ~2~

1 stra-tegy, as deEined by the Outp~lt s:ignal from the NAND
2 gate 13-27a through 13-27h ~hich has been selected b~
3 decoder ]3-28.

In one embodiment of this invention, pro,~imity logic 6 117 also includes latch 13-29, which comprises, for e,cample 7 a 74374 device as manufactured by National. Latch 13-29 8 stores the output signals provided by NA~D gates 13-27a 9 through 13-27h, and thereby allows the cen-tral processing unit (not shown) to determine the value of the signals 11 provided by NAND gates 13-27a through l3-27h at any desired 12 time. In one embodiment of this invention, one eight bit 13 word representing the output signals from ~IAND gates 14 13-27a through 13-27h is stored in latch 13-29, ~nd is made available to a central processing unit (not shown) on 16 bus llla.

18 Proximity logic 117 is also capable of detecting a 19 so-called "directed" proximity of words or sets of words.
In this event, the eight bit proximity word stored in 21 latches 13-12, 13-l~, 13-16, and 13-18 will contain only a 22 single logical one bi-t, thereby causing proxi~ity logic 23 117 to provide an output signal indicatiny when a first 24 word or set is located within a precise proximity of a second selected word or set. Thus, for example, proximity 26 logic 117 can be programmed to detect the occurrence of 27 word zero in a location which is exactlY n words after the 28 occurrence of word seven, for example, where n is an 29 integer ranging from -7 to +7. Thus, if it is desired to locate the occurrence of word 0 which is precisely four 31 words after word 7, decoder 13-6 selects word 0, decoder 32 13-7 selects word 7, latch 13-12 stores 00000001, latch 33 13-13 stores 00010000, and decoder 13-28 selects the 34 output signal from NAND gate 13-27a, thus providing an interrupt signal on output lead 13-50 when word 0 is 36 located exactly four words after word 7.

12~ z 1 Al-ternatively, if it is desired -to locate the occur-2 rence of word 0 which is precisely four words before ~ord 3 7, decoder 13-6 selected ~ord 0, decoder 13--7 selects word 4 7, latch 13-12 stores 00010000, latch 13-~3 stores 00000001, S and decoder 13-2~3 selects the output signal from NAND gate 6 13-27a, thus providing an interrupt signal on ou-tput lead 7 13-50 when word 0 is located exactly four words before 8 word 7.
Furthermore, if it is desired -to loca-te the occurrence 11 of word 0 which is within four words before word 7 (:i.e., 12 word 0 is the first, second, third or fourth ~ord before 13 word 7), decoder 13-6 selects ~10rd 0, decoder 13-7 selects 14 word 7, latch 13-12 stores 0011110, latch 13-13 stores 00000001, and decoder 13-28 selects the output signal from 16 NAND gate 13-27a, thus providing an interrupt signal on 17 output lead 13-50 when ~10rd 0 is located ~7ithin four words 18 before word 7.

It is also unders-tood to one of ordinary skill in the 21 art in light of the teachings of this specification, that 22 proximity loyic 117 can be constructed to detect the 23 occurrence of grea-ter combinations of ~ords and sets, 24 merely by expanding the number of latches, decoders, and shift registers, and logic gates 13-27a through 13-27h, in 26 order to detect more complex search strategies.

28 While this specification has explained the operation 29 of this invention in conjunction ~ith several specific embodiments, it is to be understood that this specifi-31 cation is not to operate as a limitation on the scope of 32 the invention. Many other embodiments of this invention 33 will become apparent to those skilled in the art in ligh-t 34 of the teachings of this invention.

Claims (9)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In a textual comparison system, a word counter comprising a word counter shift register which is clocked upon receipt of a signal indicating the end of a word, wherein a first signal clears said shift register and provides a first input signal to said word counter shift register, and wherein input signals to said word counter shift register other than said first input signal are opposite said first input signal, whereby the location of said first input signal within said word counter shift register indicates the number of words decoded since the receipt of said first signal.

2. Structure as in Claim 1 wherein said first signal is an end-of-sentence signal and the location of said first input signal within said word counter shift register indicates the number of words decoded in the present sentence being decoded.

3. Structure as in Claim 1 wherein said first signal is an end-of-paragraph signal and the location of said first input signal within said word counter shift register indicates the number of words decoded in the present paragraph being decoded.

4. Structure as in Claim 1 wherein said first signal is an end-of-document signal and the location of said first input signal within said word counter shift register indicates the number of words decoded in the present document being decoded.

5. In a textual comparison system, a sentence counter comprising a sentence counter shift register which is clocked upon receipt of a signal indicating the end of a sentence, wherein a first signal clears said shift register and provides a first input signal to said sentence counter shift register, and wherein input signals to said sentence counter shift register other than said first input signal are opposite said first input signal, whereby the location of said first input signal within said word counter shift register indicates the number of sentences decoded since the receipt of said first signal.

6. Structure as in Claim 5 wherein said first signal is an end-of-paragraph signal and the location of said first input signal within said sentence counter shift register indicates the number of sentences decoded in the present paragraph being decoded.

7. Structure as in Claim 5 wherein said first signal is an end-of-document signal and the location of said first input signal within said sentence counter shift register indicates the number of sentences decoded in the present document being decoded.

8. In a textual comparison system, a paragraph counter comprising a paragraph counter shift register which is clocked upon receipt of a signal indicating the end of a paragraph, wherein a first signal clears said shift register and provides a first input signal to said paragraph counter shift register, and wherein input signals to said paragraph counter shift register other than said first input signal are opposite said first input signal, whereby the location of said first input signal within said paragraph counter shift register indicates the number of paragraphs decoded since the receipt of said first signal.

9. Structure as in Claim 8 wherein said first signal is an end-of-paragraph signal and the location of said first input signal within said paragraph counter shift register indicates the number of paragraphs decoded in the present paragraph being decoded.