CA1215434A - Bias current reference circuit having a substantially zero temperature coefficient - Google Patents
Bias current reference circuit having a substantially zero temperature coefficientInfo
- Publication number
- CA1215434A CA1215434A CA000469022A CA469022A CA1215434A CA 1215434 A CA1215434 A CA 1215434A CA 000469022 A CA000469022 A CA 000469022A CA 469022 A CA469022 A CA 469022A CA 1215434 A CA1215434 A CA 1215434A
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- Canada
- Prior art keywords
- current
- bias
- coupled
- voltage
- mos transistor
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
Abstract
A BIAS CURRENT REFERENCE CIRCUIT HAVING A SUBSTANTIALLY
ZERO TEMPERATURE COEFFICIENT
Abstract A bias current reference circuit having a reference voltage portion and a reference current portion for providing a bias current which is established by a .DELTA.?BE of two bipolar transistors. Two resistors of differing temperature coefficient are used in the reference current portion and have a weighted summed temperature coefficient which substantially equals the temperature coefficient of the .DELTA.?BE voltage. As a result, the temperature coefficient of the circuit is near zero.
ZERO TEMPERATURE COEFFICIENT
Abstract A bias current reference circuit having a reference voltage portion and a reference current portion for providing a bias current which is established by a .DELTA.?BE of two bipolar transistors. Two resistors of differing temperature coefficient are used in the reference current portion and have a weighted summed temperature coefficient which substantially equals the temperature coefficient of the .DELTA.?BE voltage. As a result, the temperature coefficient of the circuit is near zero.
Description
` ~Z~54~L
A BIAS CURRENT REFERENCE CIRCUIT HAVING A SUBSTANTIALLY
ZERO TEMPERATURE COEFFICIENT
Technical Field This invention relates generally to reference circuits and, more particularly, to a circuit for provlding a current bias source having a near zero temperature coefficient at a predetermined temperature.
10, Background Art A common voltage reference from which bias currents are established is the ~VBE of two transistors as taught by Roger Whatley in United States Patent No. ~,450,367 assigned to the assignee hereof entitled " ~VBE Bias Current Reference Circuit". As noted by Whatley, the ~VBE voltage has a known positive temperature coefEicient. A resistor which is utilized to provide a reference current also has a known positive temperature coefficient. Although a ~VBE bias current reference circuit exhibits a lower temperature coefficient than a VBE bias current reference circuit, the temperature coefficient of the ~VBE cixcuit is determined by the temperature coefficient of resistors and is nonzero.
Summary of the Invention It is an object of the present invention to provide an improved bias current reference circuit.
Another object of the present invention is to provide an improved bias current reference circuit having a substantially zero temperature coefficient.
In carrying out the above and other objects of the 3L2:~54~
present invention, there is provided, in one form, a bias current reference circuit which has a substantially zero temperature coefficient. A reference voltage portion comprising a first bipolar transistor provides a reference voltage which is proportional to a bias current. A
reference current portion is coupled to the reference voltage portion and comprises a second bipolar transistor and first and second resistors having first and second predetermined temperature coefficients, respectively. The difference in the base to emitter voltages, ~VBE, has a third predetermined temperature coefficient. The reference current portion provides a reference current which is proportional to ~VBE and the resistance of the first and second resistors. A weighted sum of the first and second temperature coefficients is made substantially equal to the third temperature coefficient.
A bias voltage portion is coupled to the reference current portion and provides a bias voltage proportional to the reference current to both a bias current portion and an output portion. The output portion provides an output bias current in response to an attached load.
The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the following drawings.
Brief Description of tne Drawing The single Figure illustrates in schematic form a bias current reference circuit in accordance with the present invention.
Detailed Description of the Present Invention Shown in the single Figure is a bias current .
~543 reference circuit 10 generally comprising a reference voltage portion 11, a reference current portion 12, a bias voltage portion 13, a bias current portion 1~ and an output portion 15. Although specific N-channel and P-channel MOS transistors and bipolar transistors are illustrated, it should be apparent that bias current reference circuit 10 could be implemented by completely reversing the processing techniques (e.g. P-channel to N-channel) or by using other types of transistors.
Reference voltage portion 11 comprises a bipolar NPN
transistor 16 having a collector and a base connected together at a terminal for receiving a first supply voltage VDD. In a preferred form, supply voltage VDD is positive. An emitter of transistor 16 is connected to a source of a P-channel transistor 17.
Transistor 17 is diode-configured by connecting its gate to a drain thereof.
Reference current portion 12 comprises a bipolar NPN
transistor having a collector and a base connected togther at the terminal for receiving supply voltage VDD. An emltter of transistor 20 is connected to a first terminal of a resistor 21. A second terminal of resistor 21 is connected to a first terminal of a resistor 22. A second terminal of resistor 22 is connected to a source of a P-channel transistor 24. A gate of transistor 24 is connected to the gate of transistor 17.
Bias voltage portion 13 comprises an N-channel transistor 26 having a drain connected to a drain of transistor 24. A gate of transistor 26 is connected to the drain of transistor 26 for providing an output bias current. A source of transistor 26 is connected to a second supply voltage Vss. In a preferred form, supply voltage Vss is the most negative supply voltage.
Bias current portion 14 comprises an N-channel 5~
transistor 28 having a drain connected to the drain of transistor 17. A gate of transistor 28 is connected to the ga~e of transistor 26. A source of transistor 28 is connected to supply voltage Vss.
Output portion 15 comprises an N-channel transistor
A BIAS CURRENT REFERENCE CIRCUIT HAVING A SUBSTANTIALLY
ZERO TEMPERATURE COEFFICIENT
Technical Field This invention relates generally to reference circuits and, more particularly, to a circuit for provlding a current bias source having a near zero temperature coefficient at a predetermined temperature.
10, Background Art A common voltage reference from which bias currents are established is the ~VBE of two transistors as taught by Roger Whatley in United States Patent No. ~,450,367 assigned to the assignee hereof entitled " ~VBE Bias Current Reference Circuit". As noted by Whatley, the ~VBE voltage has a known positive temperature coefEicient. A resistor which is utilized to provide a reference current also has a known positive temperature coefficient. Although a ~VBE bias current reference circuit exhibits a lower temperature coefficient than a VBE bias current reference circuit, the temperature coefficient of the ~VBE cixcuit is determined by the temperature coefficient of resistors and is nonzero.
Summary of the Invention It is an object of the present invention to provide an improved bias current reference circuit.
Another object of the present invention is to provide an improved bias current reference circuit having a substantially zero temperature coefficient.
In carrying out the above and other objects of the 3L2:~54~
present invention, there is provided, in one form, a bias current reference circuit which has a substantially zero temperature coefficient. A reference voltage portion comprising a first bipolar transistor provides a reference voltage which is proportional to a bias current. A
reference current portion is coupled to the reference voltage portion and comprises a second bipolar transistor and first and second resistors having first and second predetermined temperature coefficients, respectively. The difference in the base to emitter voltages, ~VBE, has a third predetermined temperature coefficient. The reference current portion provides a reference current which is proportional to ~VBE and the resistance of the first and second resistors. A weighted sum of the first and second temperature coefficients is made substantially equal to the third temperature coefficient.
A bias voltage portion is coupled to the reference current portion and provides a bias voltage proportional to the reference current to both a bias current portion and an output portion. The output portion provides an output bias current in response to an attached load.
The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the following drawings.
Brief Description of tne Drawing The single Figure illustrates in schematic form a bias current reference circuit in accordance with the present invention.
Detailed Description of the Present Invention Shown in the single Figure is a bias current .
~543 reference circuit 10 generally comprising a reference voltage portion 11, a reference current portion 12, a bias voltage portion 13, a bias current portion 1~ and an output portion 15. Although specific N-channel and P-channel MOS transistors and bipolar transistors are illustrated, it should be apparent that bias current reference circuit 10 could be implemented by completely reversing the processing techniques (e.g. P-channel to N-channel) or by using other types of transistors.
Reference voltage portion 11 comprises a bipolar NPN
transistor 16 having a collector and a base connected together at a terminal for receiving a first supply voltage VDD. In a preferred form, supply voltage VDD is positive. An emitter of transistor 16 is connected to a source of a P-channel transistor 17.
Transistor 17 is diode-configured by connecting its gate to a drain thereof.
Reference current portion 12 comprises a bipolar NPN
transistor having a collector and a base connected togther at the terminal for receiving supply voltage VDD. An emltter of transistor 20 is connected to a first terminal of a resistor 21. A second terminal of resistor 21 is connected to a first terminal of a resistor 22. A second terminal of resistor 22 is connected to a source of a P-channel transistor 24. A gate of transistor 24 is connected to the gate of transistor 17.
Bias voltage portion 13 comprises an N-channel transistor 26 having a drain connected to a drain of transistor 24. A gate of transistor 26 is connected to the drain of transistor 26 for providing an output bias current. A source of transistor 26 is connected to a second supply voltage Vss. In a preferred form, supply voltage Vss is the most negative supply voltage.
Bias current portion 14 comprises an N-channel 5~
transistor 28 having a drain connected to the drain of transistor 17. A gate of transistor 28 is connected to the ga~e of transistor 26. A source of transistor 28 is connected to supply voltage Vss.
Output portion 15 comprises an N-channel transistor
2~ having a gate connected to the drains of transistors 24 and 26. A source of transistGr 29 is connected to supply voltage Vss and a drain of transistor 29 provides an output terminal 30. An output load 31 has a first terminal coupled to outpu~ terminal 30 and a second terminal connected to supply voltage VDD.
In operation, transistor 16 develops a first VBE
voltage across its base-to-emitter electrodes, and transistor 20 develops a second VBE voltage across its current electrodes. A ~VB~ voltage is developed across resistors 21 and 22 which provides a reference bias current, say I1, through transistors 24 and 26.
Transistor 24 is constructed with a channel width to channel length ratio such that transistors 17 and 24 have the same channel .current density. Therefore, the gate-source voltage of transistor 24 is substantially equal to the gate-source voltage of transistor 17.
Applying Kirchoff's voltage law to the loop comprising transistors 16, 17, 20 and 24 and resistors 21 and 22, results in the equation:
VBE16 - VgE20 ~ ~VBE
where VBE16 and VBE20 represent the base to emitter voltages of transistors 16 and 20, respectively, and avBE is the d.ifference in the base--to-emitter voltages whlch will be reflected across resistors 21 and 22. Transistor 26 provides a bias voltage equal to its gate-to-source voltage, VGs, and proportional to the 35 reference current I1. Transistors 26 and 28 are ratioed 4;3'~
to mirror a proportional current through transistor 2~.
Similarly, transistors 26 and 29 are ratioed so that transistor 26 mirrors a current proportional to the reference current through transistor 29. Transistor 29 provides an output current when coupled to an external load such as load 31.
The illustrated embodiment differs from prior art circuits in that the resistance used in reference current portion 12 is implemented as two distinct or separate resistors having differing temperature coefficients to provide a bias current reference circuit having a substantially zero temperature coefficient. The bias current I1 can be expressed as:
I1 = (~\VBE) / (R21 + R22) where it can be readily shown that V3E=[(kT)/(q)]xln[I16/I2o)x(A2o/A16)]
where, k = Boltzman's constant;
T = temperature in degrees Centigrade;
q = electrical. charge in Coulombs;
I16 = the current in Amperes through transistor 16;
I20 = the current in Amperes through transistor 20;
A20 = the emitter junction area of transistor 20; and A16 = the emitter junction area of transistor 16.
The conventionally known temperature coefficient of AVBE is approximately +3400 ppm/-C. In order for bias current I1 to have a zero temperature coefficient, the following equation must be satisfied:
d/dT (I1) = 0.
From the above equations/ it can be readily shown that the temperature coefficient of bias current I1 equals the ratio of the combined temperature coefficient of resistors 21 and 22 and ~VBE at a predetermined temperature.
Therefore, if the combined temperature coefficient of resistors 21 and 22 is approximately +3400 ppm/~C, a 5~3'~
substantially zero temperature coefficient results. This combined temperature coefficient should also be positive rather than having both positive and negative temperature coefficients since the temperature coefficient of I1 is a ratio. Unfortunately, a single resistive component having a temperature coefficient of +3400 ppm/~C is typically not fabricated in any conventional electronic process. However, there are numerous processes such as MOS in which resistive components having positive temperature coefficients of much greater and much less than ~3400 ppm/C are both fabricated on the same integrated circuit. Therefore, a resistor having a composite temperature coefficient of approximately +3400 ppm/GC can be fabricated by taking a weighted sum value of resistors 21 and 22 wherein resistor 21 may have a temperature coefficient greater than +3~00 ppm/~C and resistor 22 may have a temperature coefficient less than -~3400 ppm/C. Resistors 21 and 22 are size ratioed with respect to aach other so that the effective temperature coefficient is +3400 ppm/CC, a temperature coefficient normally not available in conventional MOS processes. In a preferred form, resistors 21 and 22 are fabricated as P-and P+ resistors, respectively. By using P- and P+
resistors, an ohmic contact which does not require metalization may be fabricated between the two composite resistors. Metal contacts have a very inaccurate and variable impedance associated therewith and the avoidance of metal contacts is desirable for precise ternperature coefficient accuracy. Within some CMOS processes, resistor 21 may be fabricated as a P- resistor from a tub diffusion and resistor 22 may be fabricated as a P~
resistor from a source-drain diffusion. Within any CMOS
process, when semiconductor tubs are very lightly doped, resistors having high temperature coefficients result.
Therefore, resistor 21 may be fabricated having a known high ~5~
temperature coefficient for predetermined dimensions.
Since resistor 22 is a P~ resistor which is very heavily doped, a low temperature coefficient in the range of 1000-1500 ppm/iC results. By using P- and P~ resistors, less space is required than other types of equal valued resistors because of the high sheet rho of P-. Increased absolute accuracy is obtained due to the smaller initial tolerance of P+ than P-.
Additionally, P+ or N~ poly resistors having different temperature coefficients may be used to provide a bias current reference circuit having a near zero temperature coefficient. Although specific types of reæistors have been discussed, other types of resistors may be used. The method of the invention is to use a first resistor having a temperature coefficient greater than a ~VBE temperature coefficient and a second resistor having a temperature coefficient less than a ~VBE temperature coefficient. The first and second resistors are then ratioed to provide a composite resistor equal to the ~VgE temperature coefficient.
By now it should be understood that a bias current reference circuit having a near zero temperature coefficient has been provided. By ratioing two resistors having known different temperature coefficients, an effective resistance with a desired temperature coefficient required to provide a near zero circuit temperature coefficient results. Therefore, a bias current reference circuit having minimal temperature dependence is provi~ed without increasing circuit complexity.
While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above.
. 5~
Accordingly/ it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.
In operation, transistor 16 develops a first VBE
voltage across its base-to-emitter electrodes, and transistor 20 develops a second VBE voltage across its current electrodes. A ~VB~ voltage is developed across resistors 21 and 22 which provides a reference bias current, say I1, through transistors 24 and 26.
Transistor 24 is constructed with a channel width to channel length ratio such that transistors 17 and 24 have the same channel .current density. Therefore, the gate-source voltage of transistor 24 is substantially equal to the gate-source voltage of transistor 17.
Applying Kirchoff's voltage law to the loop comprising transistors 16, 17, 20 and 24 and resistors 21 and 22, results in the equation:
VBE16 - VgE20 ~ ~VBE
where VBE16 and VBE20 represent the base to emitter voltages of transistors 16 and 20, respectively, and avBE is the d.ifference in the base--to-emitter voltages whlch will be reflected across resistors 21 and 22. Transistor 26 provides a bias voltage equal to its gate-to-source voltage, VGs, and proportional to the 35 reference current I1. Transistors 26 and 28 are ratioed 4;3'~
to mirror a proportional current through transistor 2~.
Similarly, transistors 26 and 29 are ratioed so that transistor 26 mirrors a current proportional to the reference current through transistor 29. Transistor 29 provides an output current when coupled to an external load such as load 31.
The illustrated embodiment differs from prior art circuits in that the resistance used in reference current portion 12 is implemented as two distinct or separate resistors having differing temperature coefficients to provide a bias current reference circuit having a substantially zero temperature coefficient. The bias current I1 can be expressed as:
I1 = (~\VBE) / (R21 + R22) where it can be readily shown that V3E=[(kT)/(q)]xln[I16/I2o)x(A2o/A16)]
where, k = Boltzman's constant;
T = temperature in degrees Centigrade;
q = electrical. charge in Coulombs;
I16 = the current in Amperes through transistor 16;
I20 = the current in Amperes through transistor 20;
A20 = the emitter junction area of transistor 20; and A16 = the emitter junction area of transistor 16.
The conventionally known temperature coefficient of AVBE is approximately +3400 ppm/-C. In order for bias current I1 to have a zero temperature coefficient, the following equation must be satisfied:
d/dT (I1) = 0.
From the above equations/ it can be readily shown that the temperature coefficient of bias current I1 equals the ratio of the combined temperature coefficient of resistors 21 and 22 and ~VBE at a predetermined temperature.
Therefore, if the combined temperature coefficient of resistors 21 and 22 is approximately +3400 ppm/~C, a 5~3'~
substantially zero temperature coefficient results. This combined temperature coefficient should also be positive rather than having both positive and negative temperature coefficients since the temperature coefficient of I1 is a ratio. Unfortunately, a single resistive component having a temperature coefficient of +3400 ppm/~C is typically not fabricated in any conventional electronic process. However, there are numerous processes such as MOS in which resistive components having positive temperature coefficients of much greater and much less than ~3400 ppm/C are both fabricated on the same integrated circuit. Therefore, a resistor having a composite temperature coefficient of approximately +3400 ppm/GC can be fabricated by taking a weighted sum value of resistors 21 and 22 wherein resistor 21 may have a temperature coefficient greater than +3~00 ppm/~C and resistor 22 may have a temperature coefficient less than -~3400 ppm/C. Resistors 21 and 22 are size ratioed with respect to aach other so that the effective temperature coefficient is +3400 ppm/CC, a temperature coefficient normally not available in conventional MOS processes. In a preferred form, resistors 21 and 22 are fabricated as P-and P+ resistors, respectively. By using P- and P+
resistors, an ohmic contact which does not require metalization may be fabricated between the two composite resistors. Metal contacts have a very inaccurate and variable impedance associated therewith and the avoidance of metal contacts is desirable for precise ternperature coefficient accuracy. Within some CMOS processes, resistor 21 may be fabricated as a P- resistor from a tub diffusion and resistor 22 may be fabricated as a P~
resistor from a source-drain diffusion. Within any CMOS
process, when semiconductor tubs are very lightly doped, resistors having high temperature coefficients result.
Therefore, resistor 21 may be fabricated having a known high ~5~
temperature coefficient for predetermined dimensions.
Since resistor 22 is a P~ resistor which is very heavily doped, a low temperature coefficient in the range of 1000-1500 ppm/iC results. By using P- and P~ resistors, less space is required than other types of equal valued resistors because of the high sheet rho of P-. Increased absolute accuracy is obtained due to the smaller initial tolerance of P+ than P-.
Additionally, P+ or N~ poly resistors having different temperature coefficients may be used to provide a bias current reference circuit having a near zero temperature coefficient. Although specific types of reæistors have been discussed, other types of resistors may be used. The method of the invention is to use a first resistor having a temperature coefficient greater than a ~VBE temperature coefficient and a second resistor having a temperature coefficient less than a ~VBE temperature coefficient. The first and second resistors are then ratioed to provide a composite resistor equal to the ~VgE temperature coefficient.
By now it should be understood that a bias current reference circuit having a near zero temperature coefficient has been provided. By ratioing two resistors having known different temperature coefficients, an effective resistance with a desired temperature coefficient required to provide a near zero circuit temperature coefficient results. Therefore, a bias current reference circuit having minimal temperature dependence is provi~ed without increasing circuit complexity.
While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above.
. 5~
Accordingly/ it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.
Claims (13)
1. A bias current reference circuit for providing an output current having a substantially zero temperature coefficient to an output terminal for selectively receiving a load, comprising:
reference voltage means comprising a first bipolar transistor, for providing a reference voltage proportional to a bias current;
reference current means coupled in parallel to the reference voltage means and comprising a second bipolar transistor coupled in series with a first and a second resistor having first and second predetermined temperature coefficients, respectively, the reference current means providing a reference current which is proportional to the difference in base to emitter voltages, .DELTA.VBE, of said first and second bipolar transistors having a predetermined third temperature coefficient and proportional to the resistance of said first and second resistors, wherein a weighted sum of the first and second temperature coefficients substantially equals the third temperature coefficient;
bias voltage means coupled to the reference current means, for providing a bias voltage proportional to the reference current; and bias current means having a control input coupled to the bias voltage means and coupled to the reference voltage means, for providing the bias current proportional to the bias voltage for said reference voltage means.
reference voltage means comprising a first bipolar transistor, for providing a reference voltage proportional to a bias current;
reference current means coupled in parallel to the reference voltage means and comprising a second bipolar transistor coupled in series with a first and a second resistor having first and second predetermined temperature coefficients, respectively, the reference current means providing a reference current which is proportional to the difference in base to emitter voltages, .DELTA.VBE, of said first and second bipolar transistors having a predetermined third temperature coefficient and proportional to the resistance of said first and second resistors, wherein a weighted sum of the first and second temperature coefficients substantially equals the third temperature coefficient;
bias voltage means coupled to the reference current means, for providing a bias voltage proportional to the reference current; and bias current means having a control input coupled to the bias voltage means and coupled to the reference voltage means, for providing the bias current proportional to the bias voltage for said reference voltage means.
2. The bias current reference circuit of claim 1 wherein the second bipolar transistor is diode-connected having both a first current electrode and a control electrode connected to a terminal for receiving a first supply voltage, and a second current electrode connectecd to the first resistor.
3. The bias current reference circuit of claim 2 wherein the first bipolar transistor is diode-connected and coupled in series with a diode-connected first MOS transistor of a first conductivity type, the first MOS transistor developing the reference voltage at a control electrode thereof.
4. The bias current reference circuit of claim 3 wherein said bias current means comprise a second MOS transistor of a second conductivity type having a first current electrode coupled to a first current electrode of the first MOS
transistor, a second current electrode coupled to a second supply voltage, and a control electrode coupled to the bias voltage means.
transistor, a second current electrode coupled to a second supply voltage, and a control electrode coupled to the bias voltage means.
5. The bias current reference circuit of claim 4 wherein said bias voltage means comprise a third MOS transistor of the second conductivity type having both a first current electrode and a control electrode coupled to both the reference current means and the control electrode of the second MOS transistor, and a second current electrode coupled to the second supply voltage.
6. The bias current reference circuit of claim 5 wherein said reference current means further comprise:
a fourth MOS transistor of the first conductivity type having a first current electrode coupled to said second resistor, a control electrode coupled to the control electrode of the first MOS transistor, and a second current electrode coupled to the first current electrode of the third MOS transistor.
a fourth MOS transistor of the first conductivity type having a first current electrode coupled to said second resistor, a control electrode coupled to the control electrode of the first MOS transistor, and a second current electrode coupled to the first current electrode of the third MOS transistor.
7. The bias current reference circuit of claim 1 further comprising:
second bias current means coupled to the bias voltage means for providing an output bias current at an output terminal.
second bias current means coupled to the bias voltage means for providing an output bias current at an output terminal.
8. The bias current reference circuit of 7 wherein said second bias current means comprise an MOS transistor having a first current electrode coupled to the output terminal, a control electrode coupled to the bias voltage means, and a second current electrode coupled to a supply voltage terminal.
9. A method of providing a bias current reference having a substantially zero temperature coefficient, comprising the steps of:
providing a reference voltage utilizing a first bipolar transistor, said reference voltage being proportional to a bias current;
providing a reference current utilizing a second bipolar transistor and first and second resistors having first and second predetermined temperature coefficients, respectively, said reference current being proportional to the difference in base to emitter voltages, .DELTA.VBE, of the first and second bipolar transistors, said a .DELTA.VBE voltage having a third predetermined temperature coefficient; and ratioing the first and second temperature coefficients with said third temperature coefficient so that a weighted sum of the first and second temperature coefficients substantially equals the third temperature coefficient.
providing a reference voltage utilizing a first bipolar transistor, said reference voltage being proportional to a bias current;
providing a reference current utilizing a second bipolar transistor and first and second resistors having first and second predetermined temperature coefficients, respectively, said reference current being proportional to the difference in base to emitter voltages, .DELTA.VBE, of the first and second bipolar transistors, said a .DELTA.VBE voltage having a third predetermined temperature coefficient; and ratioing the first and second temperature coefficients with said third temperature coefficient so that a weighted sum of the first and second temperature coefficients substantially equals the third temperature coefficient.
10. A bias current reference circuit which is substantially temperature insensitive, comprising:
a first bipolar transistor having a first current electrode coupled to both a control electrode thereof and a first supply voltage terminal, said first bipolar transistor having a first VBE
voltage;
a first MOS transistor of a first conductivity type having a first current electrode coupled to a second current electrode of the first bipolar transistor, and a control electrode coupled to a second current electrode;
a second bipolar transistor having both a first current electrode and a control electrode coupled to the first supply voltage terminal, and a second current electrode, said second bipolar transistor having a second VBE voltage;
a first resistor with a first predetermined temperature coefficient having a first terminal coupled to the second current electrode of the seocnd bipolar transistor, and a second terminal;
a second resistor with a second predetermined temperature coefficient having a first terminal coupled to the second terminal of the first resistor, and a second terminal;
a second MOS transistor of the first conductivity type having physical dimensions which are ratioed with the first MOS transistor and having a first current electrode coupled to the second terminal of the second resistor and a control electrode coupled to the control electrode of the first MOS transistor, wherein a voltage proportional to the difference between the first and second VBE voltages having a third predetermined temperature coefficient is developed across the first and second resistors;
bias voltage means coupled between a second current electrode of the second MOS transistor and a second supply voltage terminal, for providing a bias voltage;
first bias current means coupled between a second current electrode of the first MOS transistor and the second supply voltage terminal and to the bias voltage means, for providing a bias current to both the first bipolar transistor and the first MOS
transistor which is proportional to the bias voltage; and second bias currant means coupled between an output terminal and the second supply voltage terminal and to the bias voltage means, for providing an output current reference which is proportional to the bias voltage;
wherein a weighted sum of the first and second temperature coefficients substantially equals the third temperature coefficient to provide a bias current reference with substantially zero temperature coefficient.
a first bipolar transistor having a first current electrode coupled to both a control electrode thereof and a first supply voltage terminal, said first bipolar transistor having a first VBE
voltage;
a first MOS transistor of a first conductivity type having a first current electrode coupled to a second current electrode of the first bipolar transistor, and a control electrode coupled to a second current electrode;
a second bipolar transistor having both a first current electrode and a control electrode coupled to the first supply voltage terminal, and a second current electrode, said second bipolar transistor having a second VBE voltage;
a first resistor with a first predetermined temperature coefficient having a first terminal coupled to the second current electrode of the seocnd bipolar transistor, and a second terminal;
a second resistor with a second predetermined temperature coefficient having a first terminal coupled to the second terminal of the first resistor, and a second terminal;
a second MOS transistor of the first conductivity type having physical dimensions which are ratioed with the first MOS transistor and having a first current electrode coupled to the second terminal of the second resistor and a control electrode coupled to the control electrode of the first MOS transistor, wherein a voltage proportional to the difference between the first and second VBE voltages having a third predetermined temperature coefficient is developed across the first and second resistors;
bias voltage means coupled between a second current electrode of the second MOS transistor and a second supply voltage terminal, for providing a bias voltage;
first bias current means coupled between a second current electrode of the first MOS transistor and the second supply voltage terminal and to the bias voltage means, for providing a bias current to both the first bipolar transistor and the first MOS
transistor which is proportional to the bias voltage; and second bias currant means coupled between an output terminal and the second supply voltage terminal and to the bias voltage means, for providing an output current reference which is proportional to the bias voltage;
wherein a weighted sum of the first and second temperature coefficients substantially equals the third temperature coefficient to provide a bias current reference with substantially zero temperature coefficient.
11. The bias current reference circuit of claim 10 wherein said bias voltage means comprise:
a third MOS transistor of a second conductivity type having both a first current electrode and a control electrode coupled to both the second current electrode of the second MOS transistor and to the first and second bias current means, and a second current electrode coupled to the second supply voltage terminal.
a third MOS transistor of a second conductivity type having both a first current electrode and a control electrode coupled to both the second current electrode of the second MOS transistor and to the first and second bias current means, and a second current electrode coupled to the second supply voltage terminal.
12. The bias current reference circuit of claim 11 wherein said first bias current means comprise:
a fourth MOS transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the first MOS
transistor, a control electrode coupled to the control electrode of the third MOS transistor, and a second current electrode coupled to the second supply voltage terminal.
a fourth MOS transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the first MOS
transistor, a control electrode coupled to the control electrode of the third MOS transistor, and a second current electrode coupled to the second supply voltage terminal.
13. The bias current reference circuit of claim 12 wherein said second bias current means comprise:
a fifth MOS transistor of the second conductivity type having a first current electrode coupled to the output terminal, a control electrode coupled to the control electrodes of the third and fourth MOS
transistors, and a second current electrode coupled to the second supply voltage terminal.
a fifth MOS transistor of the second conductivity type having a first current electrode coupled to the output terminal, a control electrode coupled to the control electrodes of the third and fourth MOS
transistors, and a second current electrode coupled to the second supply voltage terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US56953584A | 1984-01-09 | 1984-01-09 | |
| US569,535 | 1984-01-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1215434A true CA1215434A (en) | 1986-12-16 |
Family
ID=24275840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000469022A Expired CA1215434A (en) | 1984-01-09 | 1984-11-30 | Bias current reference circuit having a substantially zero temperature coefficient |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS60159919A (en) |
| KR (1) | KR850005746A (en) |
| CA (1) | CA1215434A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4792748A (en) * | 1987-11-17 | 1988-12-20 | Burr-Brown Corporation | Two-terminal temperature-compensated current source circuit |
| EP1347570A1 (en) * | 2002-03-20 | 2003-09-24 | Motorola, Inc. | Temperature-stable bias circuit for an integrated circuit field-effect transistor |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2772069B2 (en) * | 1989-10-26 | 1998-07-02 | 沖電気工業株式会社 | Constant current circuit |
| JP4677735B2 (en) * | 2004-04-27 | 2011-04-27 | 富士電機システムズ株式会社 | Constant current source circuit |
| JP2006109349A (en) * | 2004-10-08 | 2006-04-20 | Ricoh Co Ltd | Constant current circuit and system power unit using the constant current circuit |
| JP2009225282A (en) * | 2008-03-18 | 2009-10-01 | Seiko Npc Corp | Constant current circuit |
-
1984
- 1984-11-30 CA CA000469022A patent/CA1215434A/en not_active Expired
- 1984-12-29 JP JP59281893A patent/JPS60159919A/en active Pending
-
1985
- 1985-01-08 KR KR1019850000053A patent/KR850005746A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4792748A (en) * | 1987-11-17 | 1988-12-20 | Burr-Brown Corporation | Two-terminal temperature-compensated current source circuit |
| EP1347570A1 (en) * | 2002-03-20 | 2003-09-24 | Motorola, Inc. | Temperature-stable bias circuit for an integrated circuit field-effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR850005746A (en) | 1985-08-28 |
| JPS60159919A (en) | 1985-08-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |