CA1210336A - Electronic stereo reverberation device with doubler - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

An electronic reverberation system for providing reverberations to signals in the audio frequency range. The system includes a reverberation circuit for receiving a main input audio signal and providing audio output signals having different delay components including at least first and second audio reverberation output signals. A doubling circuit receives the main input audio signal and provides an output signal whose pitch varies from the pitch of the inputted signal. Two out-put mixers are also provided. Each of the output mixers respectively receives the first and second audio reverberation output signals. The output mixers also receive the output signals from the doubling circuit and the main input audio signal. The output mixers combine the signals inputted thereto to provide two audio signals having different audio characteristics.

Description

~2~ 336 This application is a division of application Serial No. 437,063 filed September 20, 1983.
This invention is directed to devices which alter electrical audio signals, and more particularly to devices for introducing reverberation into such signals.

BACKGROUND OF THE I~VENTI ON
There are many prior art devices available for electrically introducing reverberation e~fects into audio output signals. Many of these devices are susceptible to mechanical jarring, and produce 'IBoing'' type sGunds when subject to such jarring or mechanical vibration or are elec-trically noisy. At least one prior axt reverb unit incor-porates a multiple output bucket brigate device, i.e. analog shift register. However, for certain applications this device does not provide sufficient reverberatlon effects to the inputted signal, and is limited in the type and quality of the reverb that it provides.
SUMM~RY OF THE _NVENTION
An object of the invention is to add reverberation to the electrical audio signals so tha-t the resultant signal has superior reverberation characteristics.
In accordance with the invention an electronic reverberation system for providing r~verberation to signals in the audio frequency range consists of a reverberation circuit for receiving a main input audio signal and pro-viding audio output signals having different delay components including at least first and second audio reverberation output signals. A doubling circuit receives the main input audio signal and provides an output signal whose pitch varies from the pitch of the inputted signal. Two output mixers, each of which respectively receives the first and second ~i~

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audio reverberation output signals, the Olltput mixers also receiving the output signals from the doubling circuit and the main input audio signal, the output mixers combining the signals inputted thereto to provide two audio signals having different audio characteristics.
In accordance with an embodiment of the invention for providing reverberation, a timed turn on gate receives a main audio signal and gates this signal to an analog shift register only after this signal exceeds a certain signal level for a certain time period. The analog shift register provides delayed output signals at a plurality of staggered delay taps.
Two summing devices each receive output signals from different combinations of delay taps, and sum the signals respectively inputted thereto to provide two different output signals having diferent reverb characteristics or delay components.
Also, by providing a timed turn on gatè in front of the analog shift register, much unwanted noise of short duration is re-moved and therefore an output signal having high quality reverberation is obtained.

2~ In another ~orm of the invention for providing re-verberation to an electrical audio signal, an analog shift xegister receives a main audio signal and provides dela~ed outputs at a plurality of staggered delay taps. An output delay circuit receives an output signal from one of the stag-gered delayed taps, preferably the last in the series, and -33~

delays the received signal a time period substantially different from the delay time period between any two of the adjacent staggered delay taps. Two summing devices receive output signals from differen~ combinations of the delay taps, and one of the summing devices receives the output from the output delay circuit. 8y summing the signals inputted thereto, the summing devices provide tw~ different channels of audio outpu~ signals having different delay components. The output delay circui~ following the anal~g shift register provides additional reverberation c~mponents to the resultant output signal, which is different from the sound obtained by using a single analog shift reqister.
Numerous other advantages and features of the present invention will become readily apparent from ~he following detailed description of the invention and one embodiment thereof, from the claims and from the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fiyure 1 is an overall block diagram of the electronic reverberation device according to the invention;
Figure 2 is an electrical schematic diagram of the timed turn on gate of Figure l;
~ igure 3 is an electrical schematic diagram of the synthetic doubling circuit stage of Figure l; and Figure 4 is an electric schematic diagram of the the analog shift register or bucket brigade stage, the delay output circuit, and the output amplifiers and mixers of Figure 0~

DETAILED D~SCRIPTION OF TH:E: PREFERRED EMBODIMENT

. While this inven~ion is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in de~ail one specific embodiment with the understanding that the present disclosure.is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the embodiment illustrated.
Referring to Figure 1, a reverberation device in accordance with the invention comprises a doubling circuit 18, a timed ~urn on gate 19, a bucket brigade device 20 with delay taps and including its associated input buffer amp and filter circuit, an output delay circuit 21, an output summin~
and amplifier circuit 22, and an output amplifier and mixing circuit 23. The device operates in one of three modes to provide doubling alone, reverb alone, or both doubling and reverb, as controlled ~y switch SW 201~
Turning now to ~igure 2, the operation of the timed turn on gate 19 will now be described. ~he timed turn on ga~e 19 receives a main audio signal which is fed i~to ampli-~ier IC lO~B. Amplifier IC 102B, in conjunction with ampli-ier IC lOSA and associated resistors ~ 133 through R 140, capacitors C 118 through C 120 and diodes D 106 through D 110, will effect switching of FET transitor Q ~02 (to gate the main audlo signal to IC lOSB) 40 milliseconds after a main audio signal of sufficient magnitude is present on the main signal line. The main audio signal that is gated comes through resistor R 141.

; 25391 When ~he input signal is low the resistance across the FET will be low and the signal will be attenuated to a very low amount, essentially ~ff. When .the signal to the FET is high, the F~T will turn on and open its gate to let the main audio signal pass virtually unattenuated as long as a certain amount of voltage is maintained at the gate of the FET. The value of capacitor C 120, in conjunction with re-sistor R 138, determines the turn on time which is about ~o milliseconds. As soon as a si~nal of sufficient magnitude appears at the input of IC 102B, the signal at the output of IC 102B begins charging capacitor C 120. When C 120 is charged to a sufficient amount, the signal is passed to IC 105A. Therefore, adequate turn on voltage does not get to the FET gate uneil 40 ~illiseconds after the sign~l is present at the input of op amp IC 102B.
Capacitor C 120, in conjunction with R 139, sets the release time of the timed turn on gate which ~s a few milliseconds. Thus, if the signal voltage suddenly drops, the voltage across the capacitor C 12C will not disappear immediately, but will bleed off gradually throu~h resistor 139. Therefore, the FET will not clamp down shut. suddenly but instead will slowly turn of~ so ~hat the sound into the reverb does not end abruptly.
By providin~ a timed turn on gate some unwanted noise spikes of short duration, e.g. a few milliseconds, are prevented from being reverberated. Another benefie of the eurn orl gate ~s that very loud ~ttach portions of certain musical s~gnals are pre~ented from e~terin~ and overlo~ding the re~rerberator.

Without a timed turn on gate according .to the invention, the spikes would pass to the main re~erb unit and would result in numerous discrete echoes. One way to reduce the effect of spikes might be to provide ~ large number of ~..2~ 33~

del~y taps, i.e. about 100 taps. ~owever, this wDuld be quite costly. Therefore, by providing a timed turn on gate according to the invention, spikes will be eliminated even in reverb units having a small number of stages. If a note is played and then another note is played immediately there-after, the gate is already opened so a spike would get through, b~t tbe spike would not be noticed because program material would mask it.
The doubling circuit 18 essentially functions to simulate a second instrument which is slightly off key and slightly out of time with an initial instrument. This is done by cyclicly varying the pitch of the initial instrument signal back and forth about its nominal pitch. ~or example, if the nominal pitch of the initial instrument signal is an F note then the doubler will output a sharp F note for a while and then a flat F note for a while followed by a sharp note again and so on~
Cyclic pitch variation can be achieved by inputting the initial instrument signal into an analoy delay device and then varyin~ the clock ~requency of the clock which drives the delay device. If the analog delay device is a bucket brigadel the bucket brigade receives an initial instrument signal and shifts the signal within the ~rigade from bucket to bucket at speed determined by the frequency of the clock which drives the bucket brigade. By varying the frequency of the clock siqnal the pitch of the signals passed by the buckets can be varied~ By reducing the clock freq~ency the pitCh Wi~ wer. To hold the pitch at the reduced pitch le~el, one must keep reducing the clock speed at the same

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rate of change. H~wever if this is continued the resultant delay ~f the bucket brigade will be delayed further and further until eventually the output would be minu~es behind its input. In order ~o provide a pitch differential while still keeping the overall delay to a ab~ut 15 to 20 milli-seconds~ the pitch is increased and then reduced ~nd so on in a cyclical manner. Of course the delay will vary within the range of about 15 to 20 milliseconds.
The doubling circuit 18 comprises essentially two circuit portions: an analog delay portion 18A and a delay cl~ck portion 18B.
The anal~g delay pc)rtion 1BA comprises a bucket brigade device IC ~10 which has a~ input buffer amp IC lO~A, and an output buffer amp IC 106B, each having associated resistors and capacitors as shown. The bucket brigsde IC
llO ~t its pins 2 and 6 receiYes a series of clock pulses of opposite phase from lC 109. lC 108 and 109 creste ~ hl~h freque~cy cloc~ whose frequency varies about a nomlnal rate.
ln order to create a slow variation 1~ thls clock rate~
a low frequency osclllator co~prlsln~ lC 107 A ~nd B, along wlth sssociated resistors and capacitors, pro~ides ~ triangle wAvefor~ 3ignal of ~requency abou~ .5 H2 to pin 3 of IC 109. ln response to this eriangle wave form, IC 10~ and 109 ~ill produce clock pulses of slowly ~arying frequencyO The bucket brigade will respond to these clock pulses ~o cyclicly Yary the pitch of its output signal to either slde of the pitch of ies input signal. ~he output of the d~ubling ~ircuit -7- :

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will thus simulate a second instrument slîghtly off key and out of time with an instrument wh~se signal is inputted to the doubling circuit.
As shown in Figure 4, the output from th~ timed turn un gate 19 and ~he doubling circuit 18 is provided to terminals of switch SW ~01. Switch 201 is an eight terminal three position slide switch having an upper sliding member which engages tw~ adjacent terminals at a time, and a lower sliding member which also engages two terminals at a time and moves in conjunction with the upper sliding member. The sliding members are moved by manual switch actuating element.
When the switch actuator is on the extreme left, the rever~
beration portion of the preferred embQdiment provides a doubling output but no reverb output to the output mixers.
When the switch actuator is in the middle position, the rever beration portion of the preferred embodiment will provide both a doubling component and a r~verberation component to the output mixers. When the switch actuator is on the extreme right, the circuit will provide a reverberation signal but no doubling component to the output mixers., As shown in Figure 1, the reverberation unit c~m-prises a bucke~ brigade delay device (an analog delay device) 20 wbich receives an input signal from a musical instrument or the like at the left as shown in the figure. The bucket brigade device has 6 output taps labeled 1 through 6 in Figure 1. A signal appearing at the input 20-1 of the bucket brigade will appear at the first output delay tap about 20 milliseconds a~ter it is inputted. The delay between ad~ncent 33~

t~ps ls unequal. ~or ex~mple, the inputted sign~l wlll ~pe~r ~t the second output del~y tap ~bout 12 ~1llisecc~nds after it ~ppeass at the first output, which 1~ about 32 mllllseconds ~fter lt ~ppears st the ~nput ~0^1.
The ~nputted signal wlll appeAr st del~y Laps 3 - 6 in sequence w~th lrregul~r delay~ bet~ee~ e~ch tap. Fln~lly, the slgnal wlll ~ppear ~he ~tput of thc la~t del~y t~p ~bout 150 mllllsecond~ ~ftor lt l~
inputted on the 20-1.

The output of the last delay tap is inputted to an output delay circuit 21 at an input line 21-1. The output delay circuit will produce the inputted signal to its output 21-2 about 50 milliseconds after it appears at its input 21-1.
The outputs of the bucket brigade are connected to ~ summing circuit 22 comprising right and left summers 22A
and 22B, respectively. Right summer receives alternate out-puts from the bucket brigade 20, i.e. delay ~aps 1, 3 and 5, while the left summer receives different ~lternate outputs from the bucket brigade 20, i.e. delay taps 2, 4 and 6. The righ~ summer will also receive the output from the output de~ay circuit 21. However, this ou~put at line 20-1 from output delay circuit 21 will not be provided to the left summer. In this manner, not only will the righ~ summer receive different combinations of outputs from bucket brigade 20 than the ri~ht summer, but the left fiummer will receive an additional delay output, i.e. the output from output delay circuit 21. There~ore, the outputs 22-1 and 22-2 of the su~mers 22A and 22B will haYe different delay components.
Ihe result o~ dding these ~wo sep~r~te groups of irregularly _9_ spa~ed delay c~p~n~nts Is to create ~wo hlghly complex f~equency responses, ~lth many pe~ks and ~lley~ whlch ~re n~t corr~l~ted to e~ch ~thRr. When these t~o dlferent slgn~ls e~e fed to sep~r~te sound tr~nsducers or ~
stereo ~mpllfier 2nd ~peaker syst~ for e.g., the sounds produced by the tw~ ~u~er~ wlll cTe~te ~ 9ter~0 ~ e.
Referring again to Figure 4, when switch 201 is in either the middle or extreme right position, the bucket brigade circuit 20 will receive a signal at the inpu~ of its buffer amplifier and filter circuit portion 20~. The buffer amplifier and filter circuit portion comprises two integrated circuits IC 203A and IC 203B, and associated resistors and capacitors, and provides an amplified and filtered signal to pin 1~ of the bucket brigade device IC
~06. The integrated circuit IC 206 is an analog shift register having 6 output delay taps at pins 4-9 thereof~
Integrated circuit IC 208 is an analog shift register clock generator/driver which drives both integrated circuits IC 206 and IC 207~ The period of the switching of the timer is dependent upon the circuit values of resistors R 254~ R 255 and capacitor C 228. The bucket brigade IC 206 receives an input signal at pin 12 and provides this signal at different delay periods to the output delay ~aps (pins 4-9~. The delay between ad~acent delay taps is lrre~ular, ln the r~n~
of 10 to 30 ~ ¢conds, A ~ign~ outputted ~It the l~t delny tap (p~n

4) abou~ 150 milliseconds af~er it is received a~ inpu~ pin 12 of IC 206. The output of the last delay tap (pin 4) is provided to pin 3 of an additional output delay integrated circuit chip I~ 207, ~hich is also an analog shift register like IC 206, but with ~ewer stages. The IC 207~ at pins 7 -10- . !

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and 8, provides a delayed output about so milliseconds after it receives an input at pin 3.
The output of output delay taps 4-9 of bucket brigade IC 2D6 and delay taps 7 and B of IC 207 are fed into a resistor summing network comprising resistors R 245 throuqh ~ 251. As seen in Figure 4, the outputs of alternate pins 4, 6 and 8 are summed on the lower outpu~ line 206L
~left channel), whereas the outputs of alternate pins 5, 7 and 9 are summed on the upper output line 206R kight channel).
~ur~her, ~he ~utput of the additional outpu$ delay chip IC
207 is fed only to the upper output line 206R. ~he output of the upper output line 206R (right channel3 is fed to the input of a right output amplifier and filter comprising inte-grated circuits IC 204A and IC 204B, associated resistors R 225 through R 230, and capacitors C 216 through C 220.
The output of this righ~ output amplifier and filter appearing at pin 7 of IC 204B is connected to a resis~or R ~04 at the input of output amplifier and mixing circuit 23.
Similarly, the output line 206L of the lower line of summing re-~istors (left channel) is fed to the left output amplifier and filter circuit comprising IC 205A and IC 205B, associated resistors R 231 through R 236, and capaci~ors C 221 through C 225. The output of the left output amplifier and filter circuit appears at pin 7 of IC 205B and is connec-ted to resistor ~ 209 a~ ~he input sf output amplifier and mixing circuit 23.
The output amplifier and mixing circuit 23 comprises essentially two different, but substan$ially identical, output .

amplifier and mixing circuits 23A and 23B. The upper output amplifier and mixing circuit 23A comprises four input summing resistors R 20~ through R 205 and an ampli~ier mixer IC 202A.
In like manner, the lower output amplifier and mixing circuit 23B comprise~ four input summing resistors R 206 through R 209 and an amplifier mixer IC 202B.
The main siynal from ~he controlled distortion and tone alteration portion of the circuit always appears at ~he left side of input summing resistors R 20~ and R 206. When switch SW 201 is in the middle or right positisn, reverbera-tion signals will appear at the left side of input summing resistors R 204 and R 209. A doubling si~nal will appear at the left side of input summing resistors R 203 and R 207 wben switch SW 201 is in eitheE the left or middle position, but not when SW 201 is in the right position. ~owever, when SW 201 is in the riyht position, the main audio signal will appear at the left side of resistors R 20~ and R 207 in place o the doubling circui~ si~nal to compensate for the absence o the doubling circuit signal. In this way, the signal level to each mixer provided by the combination of the main audio si~nal and the double~ is maintained relatively constant.
An auxiliary input signal can be inputted to connect~r CN
203 if desired and will then appear at the right side of input summing resistors R 205 and R 208.
Switch SW 202 in the output amplifier and mixing circuit 23 provides a means to selectively attenuate the mixed signals in both channels before they pass through ampli-~iers IC 202A and IC 202B. Switch SW 202 is a three p~si~ion, eight terminal slide switch substantially identical in struc-~2~33~;

ture and operation to switch SW 201. When the switch contacts are in the extreme right position, 0 db attenuation is achieved. When the switch is in the middle po~ition, 4 db attenuation is obtained, and when the switch is in the left position 8 db of attenuation is achieved.
The output of output amplifier and mixing circuit 23 provides two separate channels of output signals having different signal characteristics. The signals are provided to connector CN 202 which is a stereo output connector, and to terminals 1 and 2 of c~nnector CN 201, also a stere~ out-put connector. The signals from these two separate channels can be provided to a s~und transducer, a stereo amplifier and speaker sys~em, a mixing console or sound recording device.
Table 1 attached hereto lists the values of the circuit components described herein. However, it is to be understood that the invention is not limited to the precise circuit values or even the specific embodiment described above, and no limitation with respect tv the specific apparatus illustrated herein is intended or should be lnferred. It can be appreciated that numerous variations and modifications may be effected without departing from the ~rue spirit and scope of the novel concept of the invention.
It is of course intended to cover ~y the appended claims all such modifications as fall within the scope of the claims9 -13- !

3~6 TABLE I

R 134 1 M . R 159 39 K

R 137 4 . 7 K R 162 220 K
R 138 1 M R 163 6 ~, 8 K

R 140 10 M R 165 2 . 7 K

R 144 12~ K R 204 390 R
R 145 lSD K R 205 33 ~

R 148 6 . 8 K R 208 33 R

R 150 2.2 R R 210 2~2 K
R 151 100 g R 211 2 . 2 K
R 152 100 K R 212 ~ R
R 153 4 . 7 K R 213 1 K
R 154 4 . 7 ~ R 214 2 . 7 K
R 155 56 X R 215 2 . 7 K
R 156 56 R ~ 216 1() R 157 27 R R 217 :L0 K

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TABLE X ~ con t ' d ~

R 224 33 K . R 251 150 K
R 225 100 K R 252 5.6 K
R 226 33 K R 253 5.6 R

R 231 100 R C 118 .01 uf R 232 33 K C 119 .05 uf R 233 47 R C 120 .05 uf R 234 56 K C 121 3.3 uf R 235 100 K C 122 Ç2 pf R 236 33 K C 123 1500 pf R 237 56 K C 124 2700 pf R 238 56 K C 125 22 uf R 239 56 ~ C 126 3.3 uf R 2~0 56 K C 127 .0033 uf R 241 56 K C 128 .001 uf R 242 56 K C 129 .115 uf R 243 100 K C 130 .01 uf R 244 100 K C 131 1~ pf - ~L2~L~336 T~BLE I (cont'd) C 132 3O3 uf C 226 3.3 uf C 201 22 uf C 227 3.3 uf C 202 22 u~ C 22~ 220 pf C 203 .1 uf D 106 - -C 204 .1 uf D 111 IN 9114 C 205 220 uf D 112 LED
C 206 220 ~f D 113 LED
(VB = 2.2) C 207 .OS uf D 201 In 9114 C 208 .05 u~ IC 102 TL 072 C 209 .1 uf IC 105 TL 072 C 211 220 pf IC 106 TL 072 C 212 220 pf IC 107 TL 072 C 213 2700 pf IC 108 IC 7555 C 214 2700 pf IC 109 CD 4013B
C 215 2700 pf IC 110 MN 3007 C 216 220 pf IC 201 LM 386 C 217 220 pf I~ 202 LM 386 C 218 2700 p~ IC 20~ TL 072 C 219 2700 pf IC 204 TL 072 C 22~ 2700 pf IC 205 TL 072 C 221 220 pf IC 20`~ MN 3011 C 222 220 pf IC 207 MN 3007 C 223 2700 pf IC 208 MN 3101 C 224 27~0 pf C ~25 2700 pf , .

Claims (12)

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:-

1. An electronic reverberation system for providing reverberation to signals in the audio frequency range, comprising:
a reverberation circuit for receiving a main input audio signal and providing audio output signals having differ-ent delay components including at least first and second audio reverberation output signals;
a doubling circuit for receiving the main input audio signal and for providing an output signal whose pitch varies from the pitch of said inputted signal; and two output mixers, each of which respectively re-ceives the first and second audio reverberation output signals and wherein the output mixers also receive the output signals from said doubling circuit and the main input audio signal, and wherein the output mixers combine the signals inputted thereto to provide two audio signals having different audio characteristics.

2. The electronic reverberation system of claim 1 including manual switch means having multiple positions including a first circuit interconnecting position in which the output from the doubling circuit is connected to the mixers and the outputs from the reverberation circuit are disconnected from the mixers.

3. The electronic reverberation system of claim 2 wherein the manual switch means has a second circuit inter-connecting position in which the output from the doubling circuit and the outputs from the reverberation circuit are both connected to the mixers.

4. The electronic reverberation system of claim 3 wherein the manual switch means has a third circuit inter-connecting position in which the output from the doubling circuit is disconnected from the mixers and the outputs from the reverberation circuit are connected to the mixers.

5. The electronic reverberation system of claim 4 in which said reverberation circuit comprises a timed input delay gate for gating to its output only those audio signals inputted thereto which appear longer than a certain time period, an analog shift register for receiving the gated output signals from said delay gate and for providing staggered delayed outputs at a plurality of delay taps, and at least two summing devices which receive output signals from different combinations of delay taps from said analog shift register delay and which sum the signals inputted thereto to provide audio output signals having different delay components.

6. The electronic reverberation system of claim 5 wherein said manual switch means is slide switch having three positions in which adjacent terminals are successively interconnected.

7. The electronic reverberation system of claim 1 wherein said reverberation circuit further includes:
a timed input delay circuit including an input terminal for receiving the audio signal, an output terminal, and a gate means for gating from the input to the output terminal thereof, only those audio signals which have a duration longer than a predetermined time interval;
a delay means for receiving the gated output signals from said timed input delay circuit for providing at least two different delayed output signals;
and an output means which receives the delayed output signals from said delay means and which provides audio output signals having different delay components; and wherein said delay means comprises an analog shift register fox receiving the gated output signals from said delay circuit and for providing staggered delayed outputs at a plurality of delay taps;
and wherein said output means comprises at least two summing devices which receive output signals from differ-ent combinations of delay taps from said analog shift register delay and which sum the signals inputted thereto to provide audio output signals having different delay components;
and wherein said gate means comprises a charge-discharge circuit, a semiconductor control device, output circuit means, means coupling the input terminal to the charge-discharge circuit, means coupling the charge-discharge circuit to the semiconductor control device, means coupling the semiconductor control device to the output circuit means, means for coupling the audio input signal at the input terminal also to the output circuit means, means coupling the output circuit means to the output terminal, said charge-discharge circuit adapted to provide a time delay during which the semiconductor control device is operated to block the main audio signal at the output circuit means for a predetermined time interval.

8. The electronic reverberation system of claim 7 including manual switch means having multiple positions including a first circuit interconnecting position in which the output from the doubling circuit is connected to the mixers and the outputs from the reverberation circuit are disconnected from the mixers.

9. The electronic reverberation system of claim 8 wherein the manual switch means has a second circuit inter-connecting position in which the output from the doubling circuit and the outputs from the reverberation circuit are both connected to the mixers.

10. The electronic reverberation system of claim 9 wherein the manual switch means has a third circuit inter-connecting position in which the output from the doubling circuit is disconnected from the mixers and the outputs from the reverberation circuit are connected to the mixers.

11. The electronic reverberation system of claim 10 in which said reverberation circuit comprises a timed input delay gate for gating to its output only those audio signals inputted thereto which appear longer than a certain time period, an analog shift register for receiving the gated output signals from said delay gate and for providing staggered delayed outputs at a plurality of delay taps, and at least two summing devices which receive output signals from different combinations of delay taps from said analog shift register delay and which sum the signals inputted thereto to provide audio output signals having different delay components.

12. The electronic reverberation system of claim 11 wherein said manual switch means is slide switch having three positions in which adjacent terminals are successively interconnected.