CA1207917A - Semiconductor package - Google Patents

Abstract

ABSTRACT
A chip carrier 90 and a process Or assembling a chip carrier are disclosed. The carrier used for mounting a chip comprises a copper or copper base alloy component 92 having a thin interface layer 93 on a surface thereof. The surface and the interface layer have an indentation formed therein for receiving the chip 102. A metallic circuit pattern 98 for electrical connection to the chip is bonded to the interface layer and insulated from the copper or copper base alloy by the interface layer. A seal 104 is provided for enclosing the chip to the indentation.
Another embodiment of the invention includes a circuit board structure comprising a circuit board device 24 having a first coefficient of thermal expansion. A
chip carrier 90 is provided having a second coefficient thermal expansion of substantially the same value as the first coefficient of thermal expansion. The chip carrier has electrical leads 100 soldered to the circuit board whereby thermal cycling of the circuit board structure does not substantially stress the bond between the solder, leads and circuit board. Other embodiments of the present invention include both leadless and leaded hermetic semi-conductor packages and innovative relationships between the packages and printed circuit boards.

Description

IMPROVED SEMICONDVCTOR PACKAGE
While the invention is sub~ect to a wide range of applications, it is especially suited for use in printed circuit board applications and will be particularly described in that connection.
The printed circuit industry produces most printed circuits by adhering one or more layers of copper foil to organic materials such as glass fiber reinforced epoxy, phenolic laminated papera polyester films, poly~mide films, etc. Although widely used, these structures have certain deficiencies. Firstly, their maximum operating temperature is restricted by the maximum temperature tolerance of the organic substrate used. Secondly, a substantial mismatch usually exists between the coefficient of thermal expansion of the organic substrate and that of the copper foil, that of the solder compositions normally used to attach components to the circuitry and that of ~ the components themselves. The coefficient of thermal ; 20 expansion of the organic materials is normally substantially greater than that of the copper foil, the solder or the components being attached to the circuit. This mismatch results in substantial "thermal stresses" whenever the finished product is thermally cycled. These stresses create a variety of failure modes, such as tensile failure of the copper foil, failure of the solder attachment of components to the circuit and tensile failure of the components themselves.
~o alleviate some of the problems associated with thermal stress, the industry uses two distinct types of metal core boards. One is an epoxy or other organic insulation over the metal core (either steel or aluminum), and the other is porcelain enameled steel.

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The ~ost popular is the metal core-org~nic type.
Typically, t~e ~etal core, such as .050" thlck alumlnum, ls drilled with oversized ~oles. As t~e core is coated with epoxy, the holes are filled with the epoxy. Copper foil is then bonded to one or both sur~aces of the core.
The holes are redrilled to a desired size and a liner of the epoxy Cor other organic) is left in each hole. The finished metal core board compares to and may be processed as a standard plastic board. This may lnclude electroless deposition of copper in the holes to provide current paths from top to bottom, etc. Better heat disslpation is provided by the metal core board s compared to the gla~s ~iber rein~orced epoxy type boards w~th rather poor thermal conductivity.
The second type of board~ porcelain cnameled steel, is considered either a metal core board or a metal clad board depending on the terminology. First, porcelain en~mel (essentlally a glas~y material) is applied to a sheet o~ steel. A circuit pattern ls screen prlnted on the sur*ace o~ the porcelaln enamel with one of the thick film ~conductive ink~" and the board is refired to create a continuous pattern of metallic conductive elements. Through-holes cannot be used due to problems with short circuiting and, thereforeg multi-layer boards are not manu~actured in this manner. The porcelaln Cglass) is rather thick and its thermal conductivity is relatively poor; in fact, it is even poorer than the thermal conductivity of plastics used in plastic boards or as a coatlng in metal core boards described above. It follows that the heat di~sipation characteristics of the porcelain board are poor.
Conductive ink technology usually requires multiple applications o~ the conductive ink to build a conductor pattern which is thick enough to carry a desired electric current, The multiple screening and ~iring operations used in applying the conductive ink tend to be relatively complicated and expensi~e.

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~ resently, there is an increase in t~e circuit denstt~ o~ prlnted clrcuit boards. This creates a need ~or narrower and more closely spaced "wlres"
or llnes on the printed circuit board. The minlmum line width ~enerated by the state o~ the art conducti~e ink technology is limited by the ~rinting process for applying the conductive ink. Also, the ~inal conducti~e lnk (generally either copper- or sll~er-) porcelain-steel product ~requently has problems relating to the metallized pattern. The pattern may have a substantially different Chigher) coe~ficlent oX thermal expansion than the steel substrate. Thl~ causes a substantial shear force at the circuit-porcelaln interface and substantial ris~
of fa~lure during thermal cycling.
Many of the abo~e-mentloned considerations regarding clad metal ~re described ~n a paper entltled "Clad Metal Circuit Board Substrates ~or Direct Mou~ting o~ Ceramlc C~ip Carriers" b~ Dance and Wallace and presented at the Flrst Annual Con~erence of the International Electronics Packaging Society, CleYeland, Ohio, 1981. Also, an article entitled "Use of Metal Core Substrates for Leadless Chip Carrier Inter-connection" by Lassen ln lectronlc Packaging ~ld Production, March 1981, pages 98T104, discusses ~he latest technology ln metal core substrates.
Presently, copper foil is adhered to an organic printed circuit substrate by electrodeposition o~
9'coral copper:' to the ~oll sur~ace. The result ~s a rough sur~ace wlth re-entrance cavities to receiYe the surface layer o~ ~he organ~c substrate andfor the organic adhesive to form a "locked" mechanical bond.
Since the sur~ace layer is a conductiYe metal structure (copper) embedded in the organic material, considerable care must be exercised to remove any residual coral copper treatment ~rom the spaces .

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between the final pr~nted circuit llnes. This a~olds unwanted current passlng between lines, bridging of solder across the spaces between lines, etc. I~
prlncipal, removal o~ residual coral copper treatment ~ro~ areas requires additional etching beyond that required to remove the base foil itsel~. Thls e~cessi~e etching leads to additional undercutting and partial destruction o~ the circuit pattern. Thus, the ~anufac~urer o~ conYentional copper ~oil-organic circuit boards must str~ke a balznce between enough etching to reliably remo~e the coral copper treatment while min~mizing excesslve etching to prevent und~r-cutting of the circuit pattern~
~he increased complexi~y of circultry for inter-connecting ~ariou~ deYice~ mounted upon a printedcirc~it board o~ten re~uires that both sur~aces o~ the board contain conductive patterns. Some of the inter-connectlons are pro~ided by the circuit pattern on the o~verse face of the board (the surface to whlch the components are mounted), while other interconnections are proYided upon the reverse side Or the board. The interconnection between the obverse and reverse sides of the board may be pro~ided by solder fllled through-holes. Con~entlonal two sided copper ~o~l-organic boards of this general conflguration are widely used.
~owe~er, in state o~ the ~rt porcelain en~meled steel sub~trate boards, two sided boards are not practical since the solid and continuous steel substrate creates a continuous path ~or electrical conduction .rom one through hole to another.
In certai~ applicatlons, the circuit requirements include a double sided or multi-layered board in ~h~ch thermal exposure or other ~actors prevent the use of a copper ~oil-organic board. An alternative i 5 a metal circuit pattern on both sides of a suitable cer2~ic, non-conductive substrate with interconnection bet-~een 5- lZ~ 13056-MB

the two c~rcuits by conducti~e through-holes, Thls techn~e ~s used on speclalized printed circuit boards and upon substrates for h~rid packages.
As ~ntegrated clrcuits ~ecome larger ~more '~ ind~ dual f'unctlons on a single silicon chip ), and ~here s a corresponding lncrease in the number of leads for interconnection, the principal ~eans o~
integrated circult interconnectlon, the dual-in-line CD~P~ package becomes impract~cal. A DIP lncludes a 10 . lead frame with the leads emergin from the pac~age and ~ormed ~nto "pins". As its name indicates, the DXP
pac~age ~as two rows-of pins~ ane on either side of the ~ackage. The pins are inserted and soldered into holes in a printed circuit board. Characteristically; the pins are spaced apart on .100" centers. A relati~ely simple de~ice requiring a 20 lead package, 10 on a side, will be approximately 1" long. A 40 lead DIP
pac~age is about 2" long and a 64 lead DIP package, about the largest now made, ls approximately 3.2'~ long.
For reasons relating to geome~ry~ as the packages become longer with more pins, they become wider.
Typically, the width o~ the completed package is approximately one-thlrd its length. For both mechan-ic~l and electronic reasons, DIP packages with more than 64 leads are consldered impractical to manu~actu~e.
However, large-scale integrated circu~ts often require ~ore lnterconnections than pro~ided by DIP packages.
EYen with smaller integrated circuits, the cir~uits are spaced together on the printed circuit board as closely as possible. Obviously, the package size limits the closeness a~ the spacing. Therefore, the semiconductor industry has a growing interest in "chip carriers".
Ch~p carriers deal with the problems of largs-scale circuits reauiring more interconnections than provided ~y a DIP package as well as reduction of -6~ 1:3056-MB

package size for ~ ntermediate sized integrate~ clrcuit~
to lncrea~e component density on the printed circuit ~oard. The term chip carrier, in its broadest sense, relates to packages, both ceramic and plastic. The configuration of a chlp carrier may be essentially square and leads emerge from wi hln the package on all four sides. Furthermore, typical center-to-center spacing of leads on a chlp carrier ls .050~. Thus~ a 64 ~ead de~lce haYlng a "footprint" o~ roughly 3.25~' x 1.1" in a DIP package has a "~ootprint" of approximately 0.8" ~ 0.8~ ln a chip carrier package. More impor-tantly, the area covered by the chip carrier would be appro~imakely 18~ of that covered by the DIP package.
At this time, chip carrier packages with 128 and more leads are ~eing pro~uced.
The principal constraint in establishin~ .100" as the normal spac~ng between leads on the DIP package is the insertion of the lead pins into holes on the prlnted circuit board. Allowing ~or the hole, a pad area around the hole for solder adhesion and spzcing between the holes to electric lly isolate them from each other, lt becomes difficult to crowd them much closer together.
Typicall~, the coefficient o~ thermal expansion of the DIP package is di~erent from khat of the prlnted clrcuit board. Th~ extent to which board and packa~e dimensions change with ~arying temperature can be accommodated by de~lectlon of the leads, i.e. between the printed circuit board and the package~ Effect-i~ely, the leads become spring members whichaccommodake the differences ln coefficient of expansion.
State of the art chip carriers haYing .050" leads are not normally mounted by insertion of the leads into holes ln the printed circuit boards. Instead, most chip carriers use a surface mounting technique ln which _7_ 13056-MB

the lead ~orms a pad mounted ~lush to the printed circult board and ls soldered ln place. The metalllzed pads on the exter~or surface o~ the chip package are integral wlth t~e package and expand and contract with the packase. There ls no accommodation for deflection o~ leads due to changes ln boa~d and package dimensions, as in the case o~ DIP packages, during thermal cycling. As a result, the solder bond between the pad and ~he board is sub~ected to substantlal stresses. The stresses increase as the tota~. package slze becomes larger and/or the board's operation is ln an expanded temperature range. Repeated stressing o~
th~ sold~r ~ond leads to ~atlgue failure.
As ~lth DIP packages, chip carrier pac~ages may use a plastic package or may require a hermetic packag~. With the DIP package, essentially the same external configuration is employed ~or a hermetic (Ceramic Dual-In-Line ~ackage) or a plastic package.
In both configurations, the flexible leads accommadate ~or differential thermal expansion.
~ he "standard" glass cloth reinforced epoxy board material has a coe~ficient of thermal expansion o~ 15.8 x 10-6/C. Ceramic chip carriers usually made ~rom an aluminum oxide ceramic have a coefficient of thermal expanslon of 6.4 x 10~6/5C. If thermal conductlvity is particul.arly important, they made be made from ber-yllium oxide also having a coefficient o~ thermal expansion of 6.4 x 10-6/aC. In either event, there is a substantial mismatch in coef~icient o~ thermal expansion between the board and the chip carrier.
There~ore, substantial stresses are ~mposed on the solder bond when sub~ected to significant thermal cycling.
One solution has been to surface m?unt the c~ip carrier to a ~etall~zed pattern on 2n aluminum oxide ceramic substr~te. The substrate has the s~me ~ '7~

coef~icient Or thermal expansion as the chlp carrier.
P~ns may be brazed to the alumina substrate and plugged into holes ln tne printed clrcuit board. Although this sort of con~iguration a~oids problems assoclated with 5 mismatch ~n coe~~icie~t of thermal e-xpansion, it also has the e~ect o~ sacrificlng much of the space saving adYantage of the chlp carrier.
~ description o~ the latest technology with respect to chip carrlers is presented in an art~ cle ent~tled "Chlp-Carriers, Pin-Grid Arrays Chan~e the PC-Board Landscape" by Jerry Lyman, Electronics, December 29, 1981, pages 65-75. Another article entltled 'IChip C.rrler~: Coming Force in Packaging" by Er~ckson, in Electron ~ ductlon3 ~arch 1981, pages 64~80 dlscusses the construction and other details concer~ing chip c2rriers.
~ .~. Patent No. 3,546,3~3 to Pryor et al. dis-closes a composite metal product for use as a seal to gl2sses and ceramics which has properties of a low coef~-cient o~ expansion, appro~imatlng that Or the appropriate glasses and ceramics, good ther~al conductivlt~, and fine grain slze in the annealed conditlon.
U.S. Patent ~os. 3,546,363; 3,618,203; 3,676,292;
25 3 ,726, 9~7; 3, 82~, 627; 3, 826, 629; 3, 837, 8~5; 3, 852, 148;
Pnd 4,149,910 disclose glass or ceramic to metal com~osites or seals wherein the ~lass or ceramic ls bonded to a base alloy h~ving a thin film of refractory oxide on its surface.

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~ 75~7 It is a problem underlying the present invention to provide a semiconductor package by itself or mounted on a circuit board which can accommodate substantial thermal cycling.
It is an advantage of the present invention to provide a semiconductor package by itself or mounted on a circuit board which obviates one or more of the limit-ations and disadvantages of the described prior arrange-ments.
It is a further advantage of the present inven-tion to provide a semiconductor package by itself or mounted on a circuit board which substantially reduces the formation of stresses between the chip carrier and the circuit board due to thermal cycling.
It is a still further advantage of the present invention to provide a semiconductor package by itself or mounted on a circuit board which is relatively inexpensive to manufacture~
It is a further advantage of the present invention to provide a semiconductor package by itself or mounted on a circuit board having improved heat dissipation.
In accordance with a particular embodiment of the invention, there is provided a chip carrier adapted for mounting a chip. ~he carrier includes a first metal or metal base alloy component having a first surface and a metallic circuit for electrical connection to the chip.
A glass component bonds the metallic circuit to the alloy component, and means are provided for sealing the chip within the chip carrier.
From a different aspect, and in accordance with the invention, there is provided a process of assembling a chip carrier adapted for mounting a chip.
The process includes th2 steps of providing a first metal or metal base alloy component and providing ~2~7~ 7 a metallic circuit for electrical connection to the chip. A glass component is provided for bonding the metallic circuit to the alloy component so that the metallic circuit is insulated from the first component and the chip is sealed within the chip carrier.
The invention and further developments of the inventlon are now elucldated by means of preferred embodiments shown in the drawings, Figure 1 is a cross sectlon of a prior art printed circuit board;
Figure 2 is a cross section of a metal core prior art printed c~rcuit ~oard, Figure 3 is a cross section of a printed circuit board ha~ing a glass component bonded between the refractory oxide coating of two copper alloys in accordance with the present invention;
Figure 4 is a printed circuit board having high thermal conductivlty substrates bonded to copper alloy components;
Fig~re 5 is a cross-sectional vlew of a printed circui~ board with a fused interface layer between two substrates;
Figure 6 is a printed circuit board having clrcuits on opposite surfaces and interconnections therebetween;
Figure 7 is a cross-sectional ~iew of a printed circuit board havlng circuits on opposlte surfaces and a metal grid therebetween;
Figure 8 ~5 a top view of a metal grid used for rein~orcement of a printed circuit board, Flgure 9 is a vlew through 9-9 of Fig~re 8;
Figure lO is a side view of a multi-layer printed circuit board in accordance with the present invention;
Flgure 11 .is a side Yie~ of a leadless chip carrier in accordance with the present inventlon;

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Figure 12 is a view through 11-ll of Figure 10;
Figure 13 ls a slde ~iew o~ a leadless chlp carrier mounted upo~ a prlnted circuit board 1 accordance with the present invention.
Figure 14 is a cross-sectional view of a hermetic package with leads;
Figure 15 is a cross-sectional ~iew of a hermetic package with a skirted substrate;
Flgure 16 is a cross-sectional view of a hermetic package with a skirted substrate with cooling f~ns;
Figure 17 ls a cross sectional view of a hermetic package with a sklrted substrate contacting a heat sink in a printed clrcuit board;
Figure 18 is a cross-sectional view of a hermekic packa~e with a drop center substrate contacting a heat sink in a printed circuit board;
Figure l9 is a cross-sectional ~iew of a leadless chip carrier having a skirted substrate;
Figure 20 is a cross sectional view of an in~er~ed leadless chip carrier having a substrate bonded to the lead ~rame; and Figure 21 i~ a cross-sectlonal view of a chip carrier having a thick substrate $n contact with a heat sink in a printed circuit board.
~s shown in Figure l, prlor art printed circuits 10 are produced by adhering one or more layers of copper ~oil 12 to organic material 14 such as glass fi~er reinforced epo~y, phenolic laminated paper, etc.
These structures have several deficiencies including restricted maximum operating temperature due to the organic substrate and substantial mismatch between the coefficient of thermal expansion of the organic substrate and that of the copper foil, the solder compositions to attach components ~o the circuitry and the c~mponents themselves. Substantial thermal stresses, resulting from the mismakch, create failure '7~
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~odes such as tensile failure of the copper foil3 fall~re of the solder attachment of components to the circult and tensile ~ailure of the components themsel~es.
There is some use of metal core boards 16 found in Figure 2. Typically, these include a metal core 18, a copper foil and an epoxy insulating layer 20 bonded to both layer 20 and foll 22. This type of ~oard provides better heat dissipation than the normal glass ~lber reinforced epoxy boards but still has the restricted maximum operating temperature related to the organic substrate. Also9 substantial mismatch between the coe~ficient of thermal expansion of the organic su~strate and the copper foil causes the types of problems associated witn conventional printed circuits a~ shown in Figure 1~
The present inventlon overcomes these problems by providing a composlte or printed circuit board 24 as shown in Figure 3. The composite may include a first metal or me~al base alloy component 26 having a thin interface layer 28 on at least a fi:rst ~

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~IL;2~'7~'7 surface 30 thereof and a second thin interface layer 34 on at least surface 36 of a metal or metal base alloy component 32. A glass component 38 is bonded to the first and second thin interface layers 28 and 34 to insulate the component 26 from the second component 32.
The preferred alloy for use in the embodi-ments of the present invention is a copper base alloy containing from 2 to 12% aluminum and the balance copper. Preferably, the alloy contains from 2 to l~/o aluminum, O.001 to 3% silicon, and if desired, a grain refining element selected frorn the group consisting of iron up to 4.5%, chromium up to 1%, zirconium up to 0.5%, cobalt up to 1% and mixtures of these grain refining elements and the balance copper~ In particular, CDA alloy C6381 containing 2.5 to 3.1% aluminum, 1.5 to 2 1% silicon, and the balance copper is useful as a substrate for this invention. Impurities may be present which do not prevent bonding in a desired environment.
l~e alloys useful with this invention and, especially alloy C6381 are described in U. S. Patent ~os. 3,341,369 and 3,475,227 to Caule et al which disclose copper base alloys and processes for pre-paring them.

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The present invention is not restricted to applications of alloy C6381 but includes the broad field of metal or alloys which have the ability to form continuous inter~ace layers on their sur~ace.
Several examples of other metal alloys such as nickel base and iron base alloys are disclosed in U. S~
Patent Nos. 3,698,964, 3,730,779 and 3,810,754.
Alloy C6381 is particularly suitable for this inven-tion because it is a commercial alloy which forms such films when heated~ The copper or copper base alloy component may also include composite metals in which the refractory oxide forming metal or alloy is clad upon another metal by any conventional technique. This other metal may be another copper alloy or any other metal whose bulk properties are desired for a specific application.
The present invention uses any suitable solder glass or ceramic component 38 preferably having a coefficient of thermal expansion/contraction which closely matches the metal components. The glass is bonded to the thin interface layers 28 and 34 and functions to adhere the metal components together and electrically insulate them from each other~ When the glass and the copper alloy substrates preferably have the same or closely matched coefficients of thermal expansion, thermal stresses in the system may he essentially eliminated and the problems associated with thermal stress in the finished product alleviated.
However, the specific character of the interface layer present on the preferred alloys C638 or C6381 allows bonding to so~der glasses with significantly 7~3 ~

lower expansion/contraction coefficients than that of the alloy. It has been demonstrated that mechanically sound bond~ can be achieved between C638 and CV432 (contraction coefficlent of 127 x 10 7C~.
Table I lists various exemplary solder glasses wh~ch are adapted for use in accordance with this in~ention.
TABLE I
Coefficient of Thermal i0 Solder Glass or Ceramic_Ty~e Ex~ansion, in.Jin./C
Ferro Corp.l No. RN-3066-H 167 x 10-7 Ferro Corp.l No. RN-3066-S 160 x 10-7 Owens Illinois2 No. EJ3 160 x 10-7 Owens Illlnois2 No. CV432 127 x 10-7 lProprietary composition manufactured by Ferro Corporation, Cleveland, Ohlo.
2Proprietary composition manufactured by Owens Illinois Corporation, Toledo, Ohio.
Re~erring a~ain to the embodiment as illustrated in Figure 3, a foil layer 32 is bonded to a thicker supportl~e layer 26 by means of glass 38. The foil 32 may be subsequentially treated with a "reslst" pattern and etched to produce a printed circuit. The result is a wrought copper alloy circuit pattern bonded to and insulated from a wrouæht copper alloy supportive substrate 26 by a layer of glass 38 whlch serves as both an adhesi~e and an insulating material. This configuratlon has a number of advantages over the prior technique of printing circuitry upon the surface of porcelain with conductive ink. Firstly, in the prior conduckive ink technology, multiple layers of the conductiYe ink are applied to provide an adequate conductive pattern for the requlred electric current.

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HoweYer, the circuit foil 32 may be of any desired thickness and replaces the multiple screening and f~ring operatlons by a single firing operation and a single etching operation. Secondly, recent increases in circuit density of printed circuit boards create a need for narrower and more closely spaced printed "~lres" or lines. The prior conductive ink technology is l$mited to the minimum line width generated by the printing process. The present invention, howeverg e~ches copper foil and provides narrow lines and spaces as in conventional etched copper Yoil, organic substrate circuits. Thlrdly, the metallized pattern formed on the conductive ink-porcelain-steel circuit . .

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board has a substantial:~y hlgher coef~icient o~ thermal expans~on than the steel substrate. Thermal cycling deYelops substantial shear forces at the circuit-porcela~n interrace creatlng substantlal risk o~
failure. The em~odiment of Figure 3 substantlally eliminat~s these shear forces because the ccefficient of t~ermal expansion of the circuit f.oil and-the metal su~strate may be substantially the same.
W~ere greater conductivlty than that inherent in the metal or all~ys producing bondable alumlna and slllca films is desired, a c~mposlte copper alloy foil incorporatin~ a higher conduct~.vlty layer, as shown in Figure ~, may replace the solid alloy 32 as in the preYious embodiment.
The embodiment o~ Figure 4 includes bondable copper allo~ substrate 40 and circuit foll 46 haYing ; interface layers 41 and 43, respectively. A
glass or ceramic 44 is bo~ded between the interface layer 43 on circuit foil 46 and the interface layer 41 on the coppe~ base alloy 40. Substrate 40 is bonded, as a composit~, to a copper or high conductivity copper alloy thicke~ component 42. The latter pro~ides for superior thermal dissipation Yrom the board zs compared to both conventional copper foil-organic boards and 25 porcelain on steel boards. Also, foll 46 may be bonded as a composlte to a copper or high conductivity copper alloy component 47 for superi~r electrical or thermal conductivity. It ls also within the scope of the present invention to provide only one of the cQmponents 42 or 47 as required. It is also within tne scope of the present lnvention to modify any Or the descr~bed embod~ments by bonding the comDonent, as a compos~te, to a metal layer having deslred physical properfies.
The embodiment as shown ln ~gllre 5 orovldes coppe~ alloy substrates 48 and 49 each Lorming an interface layer. These interface layers are t7 .

~used together into layer 50 and disp2nse with the provision o~ glass. T~e uni~ied interface layer ~0 bot~ adheres the metal substrates 48 and 49 and insulates them from each other. It is within the scope of the invention to substitute the glass in the embod-iments of the p.resent lnvention with fused interface layers as deslred.
The comple~ity of the circuitry for in~ercon-nectlng the various de~ices mounted upon a printed lO.circu~t board o~ten requires that both surf2ces of the board contain conductlYe patterns. Details of prior art ~wo sided circuit boards are described in the back-ground of the in~ention.
A two sided circu~t board configuration 55, as sho~n in Figure 63 has two relatiYely thick layers o~
copper ~ase alloy co~ponents 50 and 52, each haY1ng a thin interface layer 51 and 53, respectively, on at least one surface. The components ~re bonded : together and insulated from one another by a glass or .
ceramic 54 which is fused to the interface layers 51 and 53r A circ~lit pattern i~ ~ormed on each Or the components 50 and 52 by a conYention21 technique. The thlckness Or each metal component is established in accordance with the desired stiXfness o~ the finished board. The cireuit patterns on each side Or the board 55 must be carefully designed to provide reasonable stiffness and t~ aYold planes of weakness. Such planes might de~elop if an area of considerable size without any circuitry on one side o~ the board coincides witn a similar area on the reYerse side of the bond.
Through-holes 56 may be provided ln the circu~t board by any conventional technique such as drilling or punching. T~e through-holes may be ormed into a conductiYe pakh by any suitable means such as electro-less deposition of copper on their walls. If desire~, .

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the through-holes can then be ~1~1ed with a conductive ma~er~al such as solder.
Another embodiment of a two sided metal glass printed circuit board 57, as shown in Figure 7, includes two copper alloy substrates 58 2nd 60, each having a thin interface layer 62 and 64, respectlYely, bonded on at least one surface~ A glass component 65 is fused to the layers 62 and 64. A grid 66, preferably metal, is bonded ln the glass 65 and insulated from the alloy substrates 58 and 60. The recesses 68 o~ the grid may be fllled with glass ~5 or any ot~er sultable inorganic filler. Through-holes 69 are ~ormed in the board as described above. The result is a board with the same design flexibility as con-Yentional ~oil-organic boards but with the advantage o~
su~stantial ellmination of thermal stresses. The metal grid both stif~ens the board 57 and permits a plurality of through-holes 69 to pass through openings 68 of the gr d. The through-holes must not contact the metal ! ~ 20 grid to avoid short clrcuits.
The metal grid is pre~erably made of a copper alloy having a thin interface layer on both surfaces. It is, however, within the scope of the present invention to use any ~esired materl21 to con-25 struct the grid. The grid may be formed with any desired configuratlon, and a typical one ~s shown in ~l~ure 8. A series o~ recesses 68 are stamped in a metal sheet 67. Subseauently, the bottom 71 of therecesses are pierced lea~ing a p ttern o~ interlocking "V" bars, as shown in Figure 8, for reinforcement.
The need ~or still grezter circuit complexity than : provided by a two sided circuit board leads to multi-layer circuit boards ~ith three or more layers Or copper foil. Using the concepts described here,nabove, a multi-layer board composed of alternate l~yers of copper alloy foil ha~ing a ~hin interface layer -20- ~ 3~ ~ 13056-MB

on each sur~ace in contact with the glass insulator is described. As shown in Flgure 10, copper ~oll com-ponents 70, 71 and 72 ha~e thelr interface layers 733 74 and 75, respectively, bonded to glass 76.
The ~oil components may e~ch be provided with circu~try as in t~e embodiments described above~ Also, the components may be bonded as compos~tes to other metals with desired phy~ieal properties as descrlbed above.
It is ~hought that the thicker multl-layer boards ~ill 10 be sufflciently rigid. Where additional rigidlty is re~uired, grid reinforcement as described and illu-strated in Figure 7 may be added. Also, throu~h-holes 17.78 and 79 between the circuits, as described abave, may be pro~ided as necessary. Note that the through-holes may be between any numher of circuits.
Since the power consumption of most board mounted ; electronic components is quite modest, the heat generated during the$r operation is comparably small.
: However~ as packaging density becomes greaterj more elaborate means for coollng must be provide~. Thepresent inven~ion proYide3 ~or cooling of the multi layer printed circult boardsj as shown in Figure 10, by bonding high ~hermal conductivity layers Or copper alloy to the circuit foil, as in Fi~ure 4. This layer o~ copper alloy functions to conduct heat from the board. It is within the scope of the in~ention to pro~ide one or more layers of conductive material 80 : wlth~n the multi-layer board. Materlal 80 may be a solid strip of high thermal conductlvity material such as copper or copper alloy. It~ may be desirable to use a copper alloy having an interface layer for i~proved bonding to the gl2ss 76. Nzturally, any through-holes may require insulation Yrom the strip 80..
The onductive ma~erial 80 may comprise one or more - 35 tubular members embedded i~ the glass to provide coolant ~assaes. Again, it is preferable that ~he ~2~7~

copper tubing haYe a thin interface layer on its surface to bond to the glass.
Another important aspect of the present in~ention resides ln the provision of a leadless ceramic chip carrier which can be directly mounted to the surface of a printed circuit board. This chlp carrier substan-tially ellminates excessiYe stress~ng of the solder bond to the circuit board which generally occurs during thermal cycling of the chip carrier-printed circuit board systems as descri~ed hereinabo~e. Referring to ~igures 11 and 12, there is illustrated a leadless chip carrier~ ga whereln a coppPr alloy 92 with a thin interface layer 93, such as A1203, provided on one sur~ace thereo~ is su~stltuted for the prior art alumina or beryllia ceramic~ A glass 94 may be ~used onto the interface layer as described abo~e. I~ is~ -however, within the scope of the invention to u3e only the interface layer. As can be seen in Figure 11, the copper alloy 92 may be shaped with a slight indentation 96, exaggerated in the ~rawing to better clarify the concept. I~ is within the scope o~ the present inventlon to form khe indentation in ~ny desired configuratiorl. A metal foil 98, ?~hich may be formed o~
the same material as 92, ha~ing an interface l~ye~ ~9~ i~ bonded to the glass 94 or interface layer 93 and etched ~n any conventlonal manner to provide electrical leads lO0. A chip ~02 is prefera~ly a~tached to the glass 94 by any conventional technique and lead wlres connected between the circuitry on the chip and the lead 100.
- The chip may be sealed ~ithin the lndentatlon 96 by seYeral ~echniques. ~refera~ly, the sealing deY~'ce 97 may be a cover plate 104 compr~s~ng a copper ~r cop~er base alloy ha~ing a thin interface layer the~eon. ~lass ~5 ls ~used onto at least the ecges the cover 97. This gl 2S5 can be bonded to either . .

'7~

the interface layer 99 on the component 98 or to the glass 94 as required~ The result is to hermetlcally seal the chip 102 in the leadless chip carrler 90.
~nother embodlment pro~ides the seal by filling the indentatlon 96 with an epoxy. The epoxy will bond to the leads and the glass an~ provide an adequate but not necessarily hermetlc seal.
Rererrinæ to Figure 13, the leadless chip carrier 90 is af~ixed to a typical printed circuit board 110.
This boar~ has copper foil 112 and 114 separ~ted by glass cloth rein~orced epoxy 116. A circuit is pro~ided on the roil 112. The leadless chip carrier may ~e applied directly onto the circuitry of strlp 112 by solder pads 118 between the lead 100 and the foil 112 in a conYentlonal manner.
Alloy C6381, the preferred material of alloy components 92 and 98 Or the chlp c2rrier, has a coe~icient of thermal e~pànsion of 17.1 ~ 10-6~C.
.-.This is only 8.2% different from the coeff~cient of .
thermal expansion of conventional glass cloth rein-~orced epo~y which ls 15.8 ~ 10 6/oC. This is a vast impro~ëment over chip carriers formed of alum~na cer~mic which have a coefflcient of thermal e~pansion o~ 6.4 ~ 10~6~Cg l~e. aDproximately 144p greater than the thermal expznsion o~ the alumina cer~m~c. The result 1~ a signiflcant decrease in the formation ~f stress between the solder, leads and circuit ooard due to thermal cycling.
As the number of individual functions incorporated ~ . 30 upon a single silicon chip becomes lar~erJ the ^omount : o~ heat generated requlring dissipation inc~eases accordin~lyO Also, as the number of functions become ~reater, they are packed more closely together on the chip wh~ch further magnilies the problem of heat.
d~ssipabion. It is a further adY2ntage o~ the present invention th2t the thermal conductivity of alloy C6381is , ~37~33~7 2~ Btu/ft2/ft/hr/F. This is 131% greater than the thermal conductivity of alumina oxide (typically used for chip carriers) which is 10.4 Btu/ft2/ft/hr/F.
Also, the thermal resistance imposed between the chip and the exterior means of heat dissipation is reduced because of the thinner sections of the tougher material such as 6381 which are able to replace the thicker, more fragile and brittle materials such as alumina ceramics.
It should be noted that in certain applications, beryllia with a thermal conductivity of 100 Btu/ft2/ft/hr/F is used as a substrate for better heat dissipation despite - its extremely high cost.
Referring again to Figure 11, the copper alloy component 92 with a refractory oxide layer may be clad upon copper or any high conductivity alloy 113. Assum-ing that the composite metal is approximately 10%
alloy C6381 clad upon 90% alloy C151, the overall thermal conductivity is 196 Btu/ft2/ft/hr/F. This i5 18. 8% better than the thermal conductivity of alumina and 63% better than that provided by beryllia. In addi-tion, there is the additional advantage of a thinner chipless carrier as compared to a thicker alumina carrier.
The surface mounted hermetic chip carrier as des-; cribed above and illustrated in Figure 12 will resolve most of the normal problems associated with the effect of thermal cycling on a chip carrier that is surface mounted to a conventional glass cloth reinforced epoxy printed circuit board. However in some cases, a closer match of coefficient of thermal expansion may be re-quired and/or greater heat dissipation capability may be necessary. In these cases, a metal board configura-tion of the types described hereinabove and illustrated ; in Figures 2-7 and 10 may be substituted for the con-ventional printed circuit board.
In one embodiment, reduced mismatch of thermal expansion and greater heat dissipation can be achieved ;

~ .
, ~

~ 7~

hy mounting a ch~p carrier o~ the type lllustrated in Figures 11 and 12 on a prlor art printed circuit board as shown in Figure 2 ~here the core is copper or a high conducti~ity copper alloy. ~n alloy may be desirable 5 i f greater strength ls required than may be provided w~th pure copper. A suitable plastic lnsulating layer 20 is appropriately ~onded to the copper or copper allo~ core and in turn, the printed circult ~oil 22 ls bonded to the insulating layer. The plastic must be 10 suitable ~or bondlng wlth adhesives, ha~e suitable dielectrlc characteristics and t~e a~ility to withstand processing temperakures such as soldering. The thermally conductive plastlcs may be partlcularly useful for the plastlc layer. These plastics typically 15 contain metal powders to improYe their thermal conduc-ti~ity while mainta~nlng dielectric properties since the metal powders are not in a continuous phase. Since the plastic is only thlck enough to proYide the necessary dielectrlc proper~ies, resistance to heat ~ransfer from the chlp carrier to the high conductivity copper or copper alloy core is minim$zed. It can be appreciated that th~ coef~icient of thermal expansion o~ the metal board i5 essentially the s~me as that of the glass coated chip carrier and, there~ore, stresses induced by thermal cycling of the system are substan-tially eliminaked. This configuration is lim~ted by the temperature capability of the plastlc or plastic$
and the temperature resistance of the adhesiYes whlch are used in con~unction with the plastics.
To impro~e the m~ximum temperature capability of the leadless chip carrler and printed circuit board combination, a prlnted circuit board as illustrated in Figure 3 may be used in con~unction with the leadless chip carr~er 90 shown ln Figure 11. In this config-uration, the metal cor~ consists of copper or a high conductiYity copper alloy 2~ to which is clad ~lloy C6381 or an alternative glass bondable cop~er alloy.
In turn, a printed circuit ~oil 32 consisting o~ a glass bondable copper alloy such as C6381 is bonded to the glass 38. The alloy bonded to the C6381 may be selected ~rom copper or high conductivlty cooper alloys so as to improve the electrlcal conductiYity in the c~rcuit or to provide optimum solderab~lity ch~racter-istics. The system is completely inor~anic and will wi~hstand temperatures much hi~her than systems with organic materials and further 2voids various modes o~
de~radation to which organic materials are susceptible.
An additi~e circuit may be substi~uted for photo-etched fo~l 48 ln Figure ~. T~e circuit may be generated upon a ~lass coating 2pplied to the 15 inter:~ace layer on alloy C6381 or o ther glass bonda~le alloy core materi?l 49 using convent~onal techniques employed in generating additive circuitsO
For exzmple, the ~dditive circuit may be a pattern printed~upon ~he surface of the glass with co~.ducti~-e ink 2nd ~ired into place^ It is also within the scooe of the present invention for the alumina ~ilm which ~ay be iormed by heating the alloy to be used as the dieleckric layer separating the metal co.e from the additi~e circuit.
'~ereas an interface layer has been described as being formed by separately 'ne~ing the metal or ~lloy, i~ ~ay be formed in any manner such as durin~ the ~rocess of bonding the metal~or alloy to the gl2sS, ceramic or 2nother interface layer.
Whereas the chip carrier nas been descrioed 2S
eadless, i~ ls also w~hin the scooe of the p.esent invention to substitute a ch~p carrier with le2ds.
Referring to Figure 14, there is ~llustrated an e~odiment of the present invention which is similar to the embodiment of Figure 11. An added peripheral skirt 152 preferably extends from opposite sides of the ~ Z(~79~ ~

substrate 154 at an~ desired angle. Although the skirt is prefera~ly provided only along two sides of the substrate, lt is also within the scope of the present ln~ention to extend the skirt from all four sides.
Skirt 152 imparts additional strength and stiffness to the substrate 154. The stiffening effect of the skirt may permlt a substantial reduction in the thickness of the substrate and thereby provide a source of cost reduction. The skirt also enhances the thermal dissipation of the substrate by providing additional heat transfer surface to augment conductive heat transfer to the atmosphere. The cover lld 1~6, lead frame 158 and the substrate 154 are formed of metal or metal alloys having an interface layer on their surface as disclosed above. Accordingly, although not illustrated, the interface layers are provided between the sealing glass 160 and the metal components~
The embodiment as illustrated in Figure 15 is an in~erted package in which the substrate 170 becomes a , 20 plug which is glass bonded to a lead frame 172. A
; co~er 174, forming with a cavity 1~5, is glass bonded to the lead ~rame 172 as described in the Yarious embodiments set out above. During the assembly of this package, the chip 176 is mounted upon the plug 170, the plug is ~oined to the lead frame, and the inter-connection of the wires 178 between the chip and the tlps 180 of the lead frame is preferably completed be~ore the cover is glass bonded to the lead frame.
Th~s hermetically sealed inYerted package permits the outer sur~ace 181 of substrate 170 to contact the metal foil on the surface of a printed circuit board and thus disslpate heat ~enerated by the chip through the printed circuit board. The metal or metal alloys used ln this embodiment have interface layers on surfaces for bonding to other components.

~ Z~7~ 7 Another embodi~ent of the present invention is illustrated in Figure 16. The illustrated semiconductor package 189 is substantially the same as the embodiment shown in Figure 15 except that the substrate 190 is relatively thick. This embod~ment is most advanta-geously used with a conventional printed circuit board 192 includlng a copper foil 194, a heat sink 196 and an organic filler 198. A section 200 is removed from the clrcuit board to permit the plug 190 to be affixed to the heat sink 196. The plug may be attached to the heat sink by any conventional manner such as, for example$ soldering. The contact between the plug and the heat sink or ground plate 196 in the printed clrcuit board provides for improved heat dissipation from the semiconductor package 189.
Figure 17 illustrates a hermetically sealed casing 210 ha~ing a lead frame extending from the casing for packaging an electrical component 212. The casing includes a substrate 214, a lead frame 216 and a cover 218. The materials used to construct the substrate lead frame or cover are preferably alloys with interface surfaces of the type described here-inabove. Also, the materials may be composites of alloys having an interface surface and other metals or alloys with desired physlcal qualities.
The components are bonded together using a glass in the manner described in the embodiment of Flgure 11.
The embodiment of Figure 18 is a hermetically sealed package 230 which is similar to the package 210 3 of Figure 17. Package 230 has an additional per~pheral skirt 232 which extends from opposing sides of substrate 234. Although the skirt is preferably only pro~ided on two opposing sides of the substrate 2~4, it is also within the terms of the present invention to form the substrate on all sides of the substrate.
The skirt imparts additional streng~h and stiffness to ~ z~t7~ ~

the substrate 234. The stiffenlng effect of the skirt ma~ permit a ~ubstantial reductlon in the thickness of the substrate 9 i.e. as compared to the substrate 214 of Figure 17, and thereby provide a source of cost reductlon. The skirt 232 also enhances the thermal dissipation of the substrate by provlding additional heat transfer surface to augment convective heat transfer to the environment.
Referring to Figure 19, there is shown an embodiment o~ a hermetically sealed package 240 which is substantlally identical with the package 230 except for additional cooling fins 242. These fins may be added to the bottom s~urface of the substrate 244 by Joining a strip of preferably high thermal conductivity alloy such as alloy 151 in any conventional manner such as soldering. Although the fins 242 are illustrated as being formed from a strip of material bent into a substantially U-shaped conflguratlon, it is also within the scope of the present invention to provide any number of these cooling fins formed from any number of strips of material and each being o~ any desirable s ~ ed configuration.
Figure 20 illu trates another embodiment of the present in~ention wherein a he~metically sealed package 250,su~stantlally identical with the package 230 as shown in Fig~re 18,is ~oined to a conventional printed circuit board 252 having a buried heat sink/ground plate 254 proYided therein~ The ground plate 254 may be made o~ any material which preferably has a high thermal and electrical conductivity. At least two holes 255 and 257 are provided to permit the skirt 270 to contact the ground plate 254. The printed circuit board 252 includes through-holes 256 and 258 which may ~e plated with a materlal such as copper and which receive the ends of 260 and 262 of lead frame 264. The ends may be soldered in the through-holes and electrically connect outer foil layers 266 and 268.

~ 7~ ~

The skirt 270 is preferably ~oined by any desirable means, s~ch as solder, to the heat slnk/ground plate 254 to enhance the heat dlssipation from the package 250.
Figure 21 illustrates another embodiment o~ a hermetically sealed semiconductor package 280 with leads ln accordance with the present inventlon. A
dropped center substrate 282 is provided by any means such as deep drawing the materlal of the substrate. A
lead frame 283 is glass bonded to the $nner sur~ace o~
the subs~rate. A substantially flat co~er 284 may be hermetically sealed to the lead frame 283 whereby an enclosure 285 is formed to protect the chip 286. The chip is preferably affixed to a flat inner surface 287 of the bottom surface 289 of substrate 282. An open section 288 of the printed circuit board 290 receives the dropped center substrate. The bottom 289 o~ the substrate may be ~oined directly to a heat sink/ground plate 292 which is burled within the printed circuit board. The coef~icient of thermal expansion of the substrate may be chosen to closely match that of the heat sink/~round plate which is preferably made o~ a good thermal conductor such as copper. Thus, difflcultles which might arise out of a mismatch of the coe~ficient o~ thermal expansion and in particular due to the large ~oining area 289 are substantially eliminated.
Referr~ng agaln to Figure 21, a layer of molsture or contaminant absorbing material 300 may be placed upon the internal surface 301 of the lid 284 so as to scavenge water vapor and/or other contaminants ~hich may diffuse into the package. This layer may consist of materials such as silica gel, activated carbon, etc., or mi~tures of such materials. The material may be affixed by any conventional manner such as by an adhesiYe or placing the material in a container and a~fixing the container to the surface. Although this option is illustrated in Figure 21, it may also be applied to any of the other embodiments of the inven-tion as provided herein. Also, the absorbing material may be affixed to any inner surface as desired.
Although the disclosure has thus far des-cribed embodiments using interface layers, it will be apparent to one skilled in the art that such layers are not necessary to meet the objectives of the invention. For example, a preferred em~odiment of the invention does not have any interface layer be-tween the glass component and each of the metal or alloy component. Another preferred embodiment of the invention comprises at least one such interface layer made of a material other than refractory oxide, e.g.
made of any oxide such as copper oxide.
It is apparent that there has been provided in accordance with this invention a composite, a semi-conductor package, and a system of mounting the semi-conductor package with the composite which satisfies the objects, means, and advantages set forth herein-above. While the invention has been described in combination with the embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accord-ingly, it is intended to embrace all such alternatives, modifications, and variations as fall within the spirit and broad scope of the appended claims.

Claims (12)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:-

1. A leadless chip carrier adapted for mounting a chip comprising:
a copper base alloy substrate having an inden-tation adapted to receive the chip;
a copper base alloy circuit foil adapted to be electrically connected to said chip;
a glass or ceramic bonding component having a coefficient of thermal expansion of at least about 160 x 10-7 in/in/°C for bonding said circuit foil to said substrate, said coefficient of thermal expansion of said bonding component being closely matched to the coefficient of thermal expansion of said substrate and circuit foil; and means covering said indentation and bonded to said circuit foil being adapted to seal said chip within the indentation of said chip carrier.

2. A leadless chip carrier as in claim 1 wherein the copper base alloy of said copper base alloy sub-strate and said copper base alloy circuit foil has a coefficient of thermal expansion of about 171 x 10-7 in/in/°C and comprises an effective amount of up to about 12% aluminum to form a refractory oxide and the balance essentially copper.

3. A leadless chip carrier as in claim 2 wherein said means covering said indentation comprises:
epoxy type material disposed within said indentation adapted to seal said chip within said chip carrier.

4. A leadless chip carrier as in claim 2 wherein said means covering said indentation comprises:

a copper base alloy cover having a coefficient of thermal expansion of about 171 x 10-7 in/in/°C, said cover having a refractory oxide layer at least along its outer edge, said cover being bonded at least along its outer edge to said circuit foil with the bonding com-ponent whereby said chip carrier is adapted to seal said chip within the indentation of said chip carrier.

5. A leadless chip carrier as in claim 2 wherein said copper base alloy substrate and said copper base alloy foil each have a refractory oxide layer on at least one surface for enhancing the bond to said first bonding component.

6. A leadless chip carrier as in claim 2 wherein said substrate includes a high conductivity clad for increasing the thermal conductivity of said substrate.

7. A semiconductor package adapted for an integrated circuit chip, comprising:
a metal or metal alloy substrate member;
a metal or metal alloy cover member;
a metal or metal alloy lead frame disposed between said substrate member and said cover member, said lead frame extending outwardly from said package and adapted to be electrically connected to said chip;
a glass or ceramic component bonding said lead frame between said substrate member and said cover member to electrically insulate said lead frame from said cover member and said substrate member whereby said chip is substantially hermetically sealed within said package; and skirt means extending outwardly from at least two opposite edges of said substrate member and trans-versely out of the plane of the substrate member and beyond said substrate member for strengthening said substrate member and providing heat transfer from said semiconductor package.

8. The semiconductor package as in claim 7 further including:
a printed circuit board having first and second metal or metal alloy layers;
means for bonding said layers together;
a heat sink plate embedded in said bonding means;
at least one cavity extending through one of said layers to said heat sink plate; and said semiconductor package being joined to said printed circuit board so that said skirt means contacts said heat sink plate to enhance the heat dissipation from the semiconductor package.

9. A semiconductor package adapted for an inte-grated circuit chip, comprising:
a metal or metal alloy substrate member;
a metal or metal alloy cover member disposed adjacent said substrate member;
a metal or metal alloy lead frame disposed between said substrate member and said cover member, said lead frame extending outwardly from said package and being adapted to be electrically connected to said chip; and a glass or ceramic component having a co-efficient of thermal expansion of at least about 127 x 10-7 in/in/°C bonding said lead frame between said substrate member and said cover member and electrically insulating said lead frame from said cover member and said substrate member so that said chip is substantially hermetically sealed within said package.

10. A chip carrier for mounting a chip comprising:
a metal or metal alloy substrate member having an indentation therein adapted to support the chip;
a metal or metal alloy lead frame disposed on an inner surface of said substrate member and extending from the edges of said substrate member to within said indentation;
a metal or metal alloy cover member having its outer edge in contact with said lead frame to enclose said chip within said indentation;
a glass or ceramic component bonding the lead frame between the edges of said cover member and said substrate member whereby said chip is substantially hermetically sealed in said package; and skirt means extending outwardly from at least opposite edges of said substrate member and transversely out of the plane of the substrate member and beyond said substrate member for strengthening said substrate member and providing heat transfer from said chip carrier.

11. A semiconductor package adapted for an inte-grated circuit chip, comprising:
a metal or metal alloy substrate member adapted for mounting the chip thereon;
a metal or metal alloy lead frame extending outward and coplanar with the edges of said substrate member and adapted to be electrically connected to said chip;
a metal or metal alloy cover member having an indentation therein to receive said chip, said cover member being partially disposed against a portion of said lead frame extending coplanar with said sub-strate; and a glass or ceramic component bonding the edges of said substrate member to said lead frame and said cover member to said lead frame for electrically insul-ating said lead frame from said cover and said substrate member and for substantially hermetically sealing said chip within said package.

12. The semiconductor package as in claim 11 further including:
said substrate having a portion extending out-ward from said package;
a printed circuit board having first and second metal or metal alloy layers;
means for bonding said first and second layers together;
a cavity in said circuit board extending through one of said layers to the other of said layers;
and said semiconductor package being disposed in relation to said circuit board so that said lead frame is in contact with said one of said layers and said portion of said substrate member which extends from said package is disposed within said cavity and in contact with said other of said layers.