CA1207057A - Synchronizing signal recovery circuit for radiotelephones - Google Patents
Synchronizing signal recovery circuit for radiotelephonesInfo
- Publication number
- CA1207057A CA1207057A CA000433763A CA433763A CA1207057A CA 1207057 A CA1207057 A CA 1207057A CA 000433763 A CA000433763 A CA 000433763A CA 433763 A CA433763 A CA 433763A CA 1207057 A CA1207057 A CA 1207057A
- Authority
- CA
- Canada
- Prior art keywords
- inhibiting
- synchronizing signal
- signal recovery
- recovery circuit
- generating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
ABSTRACT
An improved circuit for synchronizing signal recovery particularly suitable for mobile radiotelephone operation is disclosed. The initializing circuit of the phase-locked loop in the data receiver is inhibited for a predetermined duration upon triggering of a "window mode"
by either of a rising or falling pulse-edge in a sequence of "ones" or "zeros" in the received data. The window mode masks the invalid transitions in such sequences and prevents retriggering by such transitions.
An improved circuit for synchronizing signal recovery particularly suitable for mobile radiotelephone operation is disclosed. The initializing circuit of the phase-locked loop in the data receiver is inhibited for a predetermined duration upon triggering of a "window mode"
by either of a rising or falling pulse-edge in a sequence of "ones" or "zeros" in the received data. The window mode masks the invalid transitions in such sequences and prevents retriggering by such transitions.
Description
AN IMPROVED SYNCHRONIZING SIGNAL RECOVERY
CIRCUIT FOR RADIOTELEPHONES
FIELD OF THE INVENTION
The present invention relates to circuits for timing signal recovery, and in particular to an improved circuit for such signal recovery in the presence of noise and other corrupting transmission impairments. More particularly still it relates to mobile radiotelephone receivers.
BACKGROUND OF THE INVENTION
United States patent No. 4,029,900 granted June 14, 1977 to E.J. Addeo discusses at length the problems associated with reception in mobile radiotelephone systems.
Circuits for recovery of digital synchronizing signals - are disclosed therein that constitute significant improve-ments over the prior art in particular, synchronizing characters in a data stream are detected and the resulting character indicating signals are utilized in conjunction with a stable bit clock signal to generate word synchron-i,zing signals only after at least two bit rate clock pulses and synchronizing character indicators have been detected in coincidence. Furthermore, the circuits employ the well known digital phase-locked loop (DPLL) that is initialized upon the detection of a data message intro-ductory character and that thereafter locks in response to an approximate bit rate timing signal derived from the data signal bit stream. This digital phase-locked loop _ 1 - q~
0~(~57 produces a stable bit rate clock for use by the words synchronizing circuits. In the latter circuits, a timing chain counts down the stable bit clock to provide words synchronizing rate pulses which are used or output word synchronizing signals. The timing chain is forced to an initial count state by a first coincidence o~ a synchronizing character with a stable bit clock pulse and produces a word synchronizing rate pulse at one word synchronizing interval after such coincidence. If the latter pulse coincides with another synchronizing character indicating pulse and a bit clock pulse, the forcing of the timing chain to an initial count state is inhibited until such time as the loss of at least a predetermined number of plural successive synchronizing characters indictors is detected.
SUMMARY OF THE INVENTION
The present invention endeavors to improve the operation of the above mentioned recovery circuits by providing an improved receiver circuit capable of two modes of operation during synchronization signal aquis-ition. In addition to the flywheel mode of operation the present circuit provides a "window mode". During sequences of logic "zeros" or "ones" in the incoming data, 12(~71~57 invalid transitions are masked by the window mode circuit in order to eliminate the 180 phase ambiguity once a rising or falling data pulse-edge has been detected.
In addition, a flywheel mode control circuit is utilized which activates a flywheel masking window, similar to the window mode, once a signal is received from the external CPU of the system indicating word synchron-ization.
These-improvements result in yet faster synchron-ization signal aquisition by the receiver and in improved system stability.
Thus, according to the present invention, there is provided an improved synchronizing signal recovery circuit in a receiver for data signals having a pre-determined word rate, a predetermined bit rate, and a predetermined synchronizing character rate, comprising:
generating means for aquiring a stable clock f-rom said data signals at said bit rate, initializing means responsive to said data signals for intializing said generating means; and first inhibiting means for inhibiting said intializing means from reintializing said generating means for a predetermined duration upon being triggered by one of rising and fulling pulse-edges in said data signals of the present invention.
~` :L2(~7~:!57 In a narrow aspect of the present invention, the improved circuit further comprises:
- indicating means for indicating recognition -of a synchronizing character, and second inhibitlng means responsive to said first inhibiting means and to said indicating means for in-hibiting said generating means fr~m recommencing aquis-ition of said stable clock.
More narrowly, the generating means is a digital phase-locked loop.
More narrowly still, the digital phase-locked loop has a phase detector input responsive to the second inhibiting means.
In a preferred embodiment of the present invention, the first inhibiting means comprising first and second monostable circults, each inhibiting the.other once trig-gered, one responsive to rising and the other to falling pulse-edges, and both having their outputs OR-ed to generate an inhibiting signal for said predetermined dur-ation upon either of them being triggered by one of saidpulse-edges.
12~7~57 BRIEF DESCRIPTION OF THE DRAWINGS ~
The preferred embodiment of the present invention will now be described in conjunction with the accompanying drawings in which:
Figure 1 is a general block schematic showing major component blocks of a data receiver in a mobile radiotelephone system; and Figure 2 is a schematic of a window mode circuit according to the present invention for use in the data receiver of figure 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
With reference to figure 1 of the drawings a brief description of the general block schematic of a data receiver is given. Terminal 10 receives the DATA
I~ from a mobile radio circuit (not shown), which data is in a format known as the Manchester Code. A timing generator 11, as well as an initializer circuit 12, receives the Manchester Data. A digital phase-locked loop (DPLL) 13, which is supplied by a stable clock at 2.56
CIRCUIT FOR RADIOTELEPHONES
FIELD OF THE INVENTION
The present invention relates to circuits for timing signal recovery, and in particular to an improved circuit for such signal recovery in the presence of noise and other corrupting transmission impairments. More particularly still it relates to mobile radiotelephone receivers.
BACKGROUND OF THE INVENTION
United States patent No. 4,029,900 granted June 14, 1977 to E.J. Addeo discusses at length the problems associated with reception in mobile radiotelephone systems.
Circuits for recovery of digital synchronizing signals - are disclosed therein that constitute significant improve-ments over the prior art in particular, synchronizing characters in a data stream are detected and the resulting character indicating signals are utilized in conjunction with a stable bit clock signal to generate word synchron-i,zing signals only after at least two bit rate clock pulses and synchronizing character indicators have been detected in coincidence. Furthermore, the circuits employ the well known digital phase-locked loop (DPLL) that is initialized upon the detection of a data message intro-ductory character and that thereafter locks in response to an approximate bit rate timing signal derived from the data signal bit stream. This digital phase-locked loop _ 1 - q~
0~(~57 produces a stable bit rate clock for use by the words synchronizing circuits. In the latter circuits, a timing chain counts down the stable bit clock to provide words synchronizing rate pulses which are used or output word synchronizing signals. The timing chain is forced to an initial count state by a first coincidence o~ a synchronizing character with a stable bit clock pulse and produces a word synchronizing rate pulse at one word synchronizing interval after such coincidence. If the latter pulse coincides with another synchronizing character indicating pulse and a bit clock pulse, the forcing of the timing chain to an initial count state is inhibited until such time as the loss of at least a predetermined number of plural successive synchronizing characters indictors is detected.
SUMMARY OF THE INVENTION
The present invention endeavors to improve the operation of the above mentioned recovery circuits by providing an improved receiver circuit capable of two modes of operation during synchronization signal aquis-ition. In addition to the flywheel mode of operation the present circuit provides a "window mode". During sequences of logic "zeros" or "ones" in the incoming data, 12(~71~57 invalid transitions are masked by the window mode circuit in order to eliminate the 180 phase ambiguity once a rising or falling data pulse-edge has been detected.
In addition, a flywheel mode control circuit is utilized which activates a flywheel masking window, similar to the window mode, once a signal is received from the external CPU of the system indicating word synchron-ization.
These-improvements result in yet faster synchron-ization signal aquisition by the receiver and in improved system stability.
Thus, according to the present invention, there is provided an improved synchronizing signal recovery circuit in a receiver for data signals having a pre-determined word rate, a predetermined bit rate, and a predetermined synchronizing character rate, comprising:
generating means for aquiring a stable clock f-rom said data signals at said bit rate, initializing means responsive to said data signals for intializing said generating means; and first inhibiting means for inhibiting said intializing means from reintializing said generating means for a predetermined duration upon being triggered by one of rising and fulling pulse-edges in said data signals of the present invention.
~` :L2(~7~:!57 In a narrow aspect of the present invention, the improved circuit further comprises:
- indicating means for indicating recognition -of a synchronizing character, and second inhibitlng means responsive to said first inhibiting means and to said indicating means for in-hibiting said generating means fr~m recommencing aquis-ition of said stable clock.
More narrowly, the generating means is a digital phase-locked loop.
More narrowly still, the digital phase-locked loop has a phase detector input responsive to the second inhibiting means.
In a preferred embodiment of the present invention, the first inhibiting means comprising first and second monostable circults, each inhibiting the.other once trig-gered, one responsive to rising and the other to falling pulse-edges, and both having their outputs OR-ed to generate an inhibiting signal for said predetermined dur-ation upon either of them being triggered by one of saidpulse-edges.
12~7~57 BRIEF DESCRIPTION OF THE DRAWINGS ~
The preferred embodiment of the present invention will now be described in conjunction with the accompanying drawings in which:
Figure 1 is a general block schematic showing major component blocks of a data receiver in a mobile radiotelephone system; and Figure 2 is a schematic of a window mode circuit according to the present invention for use in the data receiver of figure 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
With reference to figure 1 of the drawings a brief description of the general block schematic of a data receiver is given. Terminal 10 receives the DATA
I~ from a mobile radio circuit (not shown), which data is in a format known as the Manchester Code. A timing generator 11, as well as an initializer circuit 12, receives the Manchester Data. A digital phase-locked loop (DPLL) 13, which is supplied by a stable clock at 2.56
2~ MHz from an oscillator 14, locks onto the exact frequency o the data clock generated in the timing generator 11 until relnitialized by the initializer circuit 12. The output of the DPLL 13 clocks data supplied to a data filler 15 by the timing generator 11 (which is a version of the :~L207(~57 input Manchester Data) to yield a non-return-to-zero (NRZ) version of the Manchester Data which is filtered and-output at a DATA O~T terminal 16. In addition, the output of the DPLL 13 is also output of a CLOCK O~T
terminal 17 to supply other circuits with a stable clock at the data rate.
In mobile radiotelephones Manchester Data is normally transmitted at the clock rate of 10 KHz, which is, therefore, the frequency at which the DPLL 13 operates.
The DPLL 13 is initialized by the initializer circuit 12 in order to speed-up the phase-locked aquisition time as a data burst is received.
Data encoded in Manchester format represents an NRZ binary or logic "one" by a transition from zero-to-one in the centre of the bit cell. An NRZ "zero" is represented by a transition from one-to-zero in the centre of the bit cell.
The "window mode" of operation is provided by . . .
the circuit shown in figure 2. After the DATA IN is limited by limiter 20 it is applied to a window generator 21 which comprises two monostable circuits 22 and 23, each having its ~ output connected to the clear terminal CD
of the other and its Q output connected-an OR-gate 24, ~ ~~ the output of which constitutes the output of the window generator 21. The limited data rom the limiter 20 is 12071:?S7~
applied to the mono-flop 22 input which responds to pos-itive or rising pulse-edge transitions, and is also applied to the mono-flop 23 input which responds to negative or falling pulse-edge transitions. Accordingly, once a pulse sequence has started by either of the mono-flops 22 or 23 by having been triggered by a rising or falling pulse-edge, respectively, the operation of the other mono-flop is inhibited for the duration of the monostable pulse width, which in the present case is selected to be 75 microseconds, given that transitions occur every 100 MS at the used 10 KHz data rate. Thus a 75 MS window is created which eliminates the 180 ambiguity by masking out all invalid transitions present during a sequence of "zeros" or "ones" in the in-coming Manchester data. Thus the initializer circuit 12 is periodically inhibited from reinitializing the DPLL 13 except once every 100 MS.
In the "fly-wheel mode" it is also desirable to prevent noise pulses from generating a false transition during all "ones" or all "zero's" in the data, which would cause the regenerated clock to slip out of phase. For this purpose a fly-wheel control is provided which causes a 50 microsecond masking window to be inserted which prevents the generation of a false trigger sequence of the DPLL 13.
The 50 MS window is inserted on command from the system 1207Q5~
microprocessor (not shown) indicating the occur~nce of word synchronization. This is all carried out by the - remainder of the circuit in figure 2. The output of the OR-gate 24 is applied to a flip-flop 25 which generates a narrow (250 nanosecond) initilization pulse everytime a valid Manchester data transition occurs during "zero"
and "one" sequences. The initiali~e pulse is applied to the initializer circuit 12 as a gating pulse to reset the DPLL 13, but also to a 50 microsecond monostable circuit 26. The flip-flop 25 has its D-input controlled by an OR-gate 27 which relays the mocroprocessor command WORD
SYNC and the -90 clock of the system. The monostable 26 has its Q and Q outputs applied to the DPLL is phase-detector inputs to clear it only if there is no WORD
SYNC signal present from the microprocessor.
terminal 17 to supply other circuits with a stable clock at the data rate.
In mobile radiotelephones Manchester Data is normally transmitted at the clock rate of 10 KHz, which is, therefore, the frequency at which the DPLL 13 operates.
The DPLL 13 is initialized by the initializer circuit 12 in order to speed-up the phase-locked aquisition time as a data burst is received.
Data encoded in Manchester format represents an NRZ binary or logic "one" by a transition from zero-to-one in the centre of the bit cell. An NRZ "zero" is represented by a transition from one-to-zero in the centre of the bit cell.
The "window mode" of operation is provided by . . .
the circuit shown in figure 2. After the DATA IN is limited by limiter 20 it is applied to a window generator 21 which comprises two monostable circuits 22 and 23, each having its ~ output connected to the clear terminal CD
of the other and its Q output connected-an OR-gate 24, ~ ~~ the output of which constitutes the output of the window generator 21. The limited data rom the limiter 20 is 12071:?S7~
applied to the mono-flop 22 input which responds to pos-itive or rising pulse-edge transitions, and is also applied to the mono-flop 23 input which responds to negative or falling pulse-edge transitions. Accordingly, once a pulse sequence has started by either of the mono-flops 22 or 23 by having been triggered by a rising or falling pulse-edge, respectively, the operation of the other mono-flop is inhibited for the duration of the monostable pulse width, which in the present case is selected to be 75 microseconds, given that transitions occur every 100 MS at the used 10 KHz data rate. Thus a 75 MS window is created which eliminates the 180 ambiguity by masking out all invalid transitions present during a sequence of "zeros" or "ones" in the in-coming Manchester data. Thus the initializer circuit 12 is periodically inhibited from reinitializing the DPLL 13 except once every 100 MS.
In the "fly-wheel mode" it is also desirable to prevent noise pulses from generating a false transition during all "ones" or all "zero's" in the data, which would cause the regenerated clock to slip out of phase. For this purpose a fly-wheel control is provided which causes a 50 microsecond masking window to be inserted which prevents the generation of a false trigger sequence of the DPLL 13.
The 50 MS window is inserted on command from the system 1207Q5~
microprocessor (not shown) indicating the occur~nce of word synchronization. This is all carried out by the - remainder of the circuit in figure 2. The output of the OR-gate 24 is applied to a flip-flop 25 which generates a narrow (250 nanosecond) initilization pulse everytime a valid Manchester data transition occurs during "zero"
and "one" sequences. The initiali~e pulse is applied to the initializer circuit 12 as a gating pulse to reset the DPLL 13, but also to a 50 microsecond monostable circuit 26. The flip-flop 25 has its D-input controlled by an OR-gate 27 which relays the mocroprocessor command WORD
SYNC and the -90 clock of the system. The monostable 26 has its Q and Q outputs applied to the DPLL is phase-detector inputs to clear it only if there is no WORD
SYNC signal present from the microprocessor.
Claims (6)
EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED
AS FOLLOWS:
1. An improved synchronizing signal recovery circuit in a receiver for data signals having a predetermined word rate, a predetermined bit rate, and a predetermined synchronizing character rate, comprising:
generating means for aquiring a stable clock from said data signals at said bit rate;
initializing means responsive to said data signals for initializing said generating means; and first inhibiting means for ingibiting said initial-izing means from reinitializing said generating means for a predetermined duration upon being triggered by one of rising and falling pulse-edges in said data signals.
generating means for aquiring a stable clock from said data signals at said bit rate;
initializing means responsive to said data signals for initializing said generating means; and first inhibiting means for ingibiting said initial-izing means from reinitializing said generating means for a predetermined duration upon being triggered by one of rising and falling pulse-edges in said data signals.
2. The improved synchronizing signal recovery circuit defined in claim 1, further comprising:
indicating means for indicating recognition of a synchronizing character; and second inhibiting means responsive to said first inhibiting means and to said indicating means for inhibiting said generating means from recommencing aquisition of said stable clock.
indicating means for indicating recognition of a synchronizing character; and second inhibiting means responsive to said first inhibiting means and to said indicating means for inhibiting said generating means from recommencing aquisition of said stable clock.
3. The improved synchronizing signal recovery circuit as defined in claims 1 or 2, said generating means being a digital phase-locked loop.
4. The improved synchronizing signal recovery circuit as defined in claim 2, said generating menas being a digital phase-locked loop having a phase detector input responsive to said second inhibiting means.
5. The improved synchronizing signal recovery circuit as defined in claims 1, 2 or 4, said first in-hibiting means comprising first and second monostable circuits, each inhibiting the other once triggered, one responsive to rising and the other to falling pulse-edges, and both having their outputs OR-ed to generate an inhibiting signal for said predetermined duration upon either of them being triggered by one of said pulse-edges.
6. The improved synchronizing signal recovery circuit as defined in claims l, 2 or 4, said second in-hibiting means being a monostable circuit for generating a pair of opposite polarity pulses for a preselected duration upon being triggered.
.
.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000433763A CA1207057A (en) | 1983-08-03 | 1983-08-03 | Synchronizing signal recovery circuit for radiotelephones |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000433763A CA1207057A (en) | 1983-08-03 | 1983-08-03 | Synchronizing signal recovery circuit for radiotelephones |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1207057A true CA1207057A (en) | 1986-07-02 |
Family
ID=4125787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000433763A Expired CA1207057A (en) | 1983-08-03 | 1983-08-03 | Synchronizing signal recovery circuit for radiotelephones |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1207057A (en) |
-
1983
- 1983-08-03 CA CA000433763A patent/CA1207057A/en not_active Expired
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| MKEX | Expiry |