CA1203638A - Method of batch manufacture of microwave diodes with incorporated encapsulation and diodes obtained by said method - Google Patents
Method of batch manufacture of microwave diodes with incorporated encapsulation and diodes obtained by said methodInfo
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- CA1203638A CA1203638A CA000420415A CA420415A CA1203638A CA 1203638 A CA1203638 A CA 1203638A CA 000420415 A CA000420415 A CA 000420415A CA 420415 A CA420415 A CA 420415A CA 1203638 A CA1203638 A CA 1203638A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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Abstract
A METHOD OF BATCH MANUFACTURE OF MICROWAVE
DIODES WITH INCORPORATED ENCAPSULATION
AND DIODES OBTAINED BY SAID METHOD
A B S T R A C T
In a method of batch manufacture of junction-type semiconductor devices such as diodes, the junction is limited to its active portion and inserted in a dielectric material which serves as a support, thereby dispensing with the need for a casing.
DIODES WITH INCORPORATED ENCAPSULATION
AND DIODES OBTAINED BY SAID METHOD
A B S T R A C T
In a method of batch manufacture of junction-type semiconductor devices such as diodes, the junction is limited to its active portion and inserted in a dielectric material which serves as a support, thereby dispensing with the need for a casing.
Description
~2~3~3~3 This invention relates to a method of batch manufacture of devices having two me~allized faces such as diodes, for example. These devices are produced in the form of elements in which provision is made for incorporated encapsulation and do not require the use of casings. They are particularly suitable for Gunn diodes or avalanche diodes. The ease with which the geometrical dimensions of these diodes can be controlled makes it possible to employ them to advantage in solid-state milli-meter-wave sources by carrying out a radial impedance conversion.
When the utilization frequency of Gunn diodes and especially avalanche diodes and Schottky diodes which are employed as oscillators for transmission or as mixers for reception of millimeter waves increases to a value above 30 GHz, the self-capacitance and self-inductance of con-ventional casings become more and more troublesome. It has therefore been sought to i~prove the casing, especially above 50 GHz, but the different solutions proposed have not proved wholly satisfactory. There can in fact be found in the prior art designs which have the advantage but also the disadvantage of being practically pretuned to one frequency and are therefore not optimized when it is desired to have a fairly wide frequency-tuning band.
Other solutions carry a heavy cost penal-ty or are not readily conducive to mass production. Whereas an
When the utilization frequency of Gunn diodes and especially avalanche diodes and Schottky diodes which are employed as oscillators for transmission or as mixers for reception of millimeter waves increases to a value above 30 GHz, the self-capacitance and self-inductance of con-ventional casings become more and more troublesome. It has therefore been sought to i~prove the casing, especially above 50 GHz, but the different solutions proposed have not proved wholly satisfactory. There can in fact be found in the prior art designs which have the advantage but also the disadvantage of being practically pretuned to one frequency and are therefore not optimized when it is desired to have a fairly wide frequency-tuning band.
Other solutions carry a heavy cost penal-ty or are not readily conducive to mass production. Whereas an
-2- ~$
elementary chip may be produced by batch-cutting ~rom a wafer, the very delicate addition of good encapsulation is in fact a unitary process. The present invention pro-poses a remedy for these problems by means of a particular method of manufacturen The invention is directed to a method for the batch manufacture of a semiconductor device comprising a multilayer semiconducting pastille placed between two connecting leads, the different steps of the method being as follows :
a) epitaxial growth from a semiconductor substrate of an assembiy of layers for providing the struc~ure of said pastille, b) delimitation of said pastille by etching said assembly so as to form an annular cup having a depth greater than that of the assembly, c) filling of said annular cup with dielectric material.
A further distinctive feature of the invention lies in the fact that it also involves the following steps :
d) etching of the substrate on the face opposite to the assembly in order to form a central cup, the bottom wall of which is constituted by said pastille, the rim of which is constituted by said opposit face and the side walls of which are delimited by the dieleckric material, e) formation of the connecting leads aforesaid by means of ~2~
a metal overlay on both faces of the complex structure obtained in the preceding step, f) detachment of the device by cutting performed outside the central cup~
The invention is further directed to a semi-conductor device comprising a support having a first and a second metallized face, a semiconducting pastille in-cluded in said support and adjacent to said first face, and an annular cup formed around sald pastille from said first face. The depth of said annular cup is at least equal to the thickness of said pastille and is filled with dielectric material. Said device essentially comprises in addition a central cup which is formed from said second face and the bottom wall of which joins said pastille, the rim of said central cup being formed by a portion of said second face.
Other features of the invention will be more apparent upon consideration of the following description and accompanying drawings, wherein :
- Figs. l to 7 illustrate the successive steps of the batch process in accordance with the invention ;
- Fig. 8 is a top view of a diode produced by means of the process in accordance with the invention ;
- Fig~ 9 is another top view oE a diode produced by means of the process in accordance with the invention ;
- Figs. lO to 12 show alternative forms of diodes ~a~_ ~3Gi~
produced by the batch process ;
- Figs. 13 and 14 are original steps of the batch process.
The fabrication of silicon avalanche diodes by means of the method of manufacture in accordance with the invention will now be described by way of example. In particular, this type of diode can be employed in modules for millimeter waves (at operating frequencies of the order of 100 GHz) by reason of the high accessibility of their geometrical components.
In order to form the junction, a series of layers of different conductivity types which will subse-quently form a semiconducting structure are formed by epitaxial growth on a monocrystalline silicone wafer having high resistivity. The cross-sectional area of the wafer will be designated as S~ the thickness of said wafer will be designated as W, its resistivity will be designated as p and its dielectric constant will be designated as ~.
The wafer can be compared with a resistor connected in parallel with a capacitor. The behavior of the wafer will become more similar to that of a dielectric as the current which flows through said wafer and which is subjected to a voltage having an angular frequency ~ between its two faces is obtained much more by capacitive effect than by the resistive effect of the electrical diagram equivalent to the wafer. This condition is satisfied if p .
1~3638 A wafer having high resistivity is therefore employed at the outset. This wafer will be designated as ~ if the small quantity of impurities included in the semiconducto is n-type, and will be designated as ~ if said impurities are p-type. If the impurity residue is zero, then the material would in that case be designated as I (intrinsic).
Fig. 1 is a sectional view of part of the wafer.
This view shows the original waer 1 whi~h is not doped or which may be only lightly doped, in contrast to the usual methods of fabrication in which the initial substrate was usually n doped. The thickness of this wafer is approximately 100 microns for technical reasons which will be explained hereinafter. Its resistivity is of the order of 4000 Q.cm or more. The first layer developed on the wafer is the n doped layer 2 having a resistivity of 0.003 Q.cm and a thickness of approximately 5 to 10 microns.
There then follow an n-type layer 3 (thickness of 0.35 micron, doping of 2 x 1017 atoms/cm3), a p~type layer 4 (a thickness of 0.35 micron, doping of 2 x 1017 atoms/cm ), and a p -type layer 5 ~thickness of 0.3 micron, doping of 5 x 10 9 atoms/cm3). This is therefore an avalanche diode having a double drift region.
The second step of the method relates to de-limitation of future diodes. This step consists in carry-ing ou-t a chemical mesa etching whieh progresses from the epitaxial growth layers down to the substrate 1 in order to ~3~38 form grooves 6 having the shape of annular cups which delimit the future diodes. The junctions will therefore appear in the Eorm of pastilles. For reasons of enhanced simplicity, the complete assembly of epitaxial layers is designated by the single reference numeral 7. At this stage, the wafer has the appearance illustrated in the cross section of Fig. 2. The groove which surrounds each diode can be circular. In this case, the elements fabricated for operating frequencies of the order of 94 GHz have approximately the following geometrical charac-teristics : -- diameter of the junction : 30 microns - external diameter of the groove : 400 microns - depth of groove : 30 microns.
With due regard to theoretical considerations relating to the use of this type of diode in modules for millimetex waves, the groove has been formed in accordance with a special profile as shown in cross-section in Fig. 2.
This profile has been obtained by chemical etching carried out in two stages. For example/ the wafer was etched by means of a first mask until the depth corresponding to the annular shoulder 8 was reached. Etching of the wafer was then resumed with a second mask having a smaller surface area in order to obtain the profile which is illus-trated.
In Fig. 2, in which the cross-section has been taken along a diameter of the groove 6, it is observed that the depth ~2~3~
of the annular shoulder 8 is appro~imately equ~l to the total thickness of the epitaxial layers.
In the following step, the walls o~ the grooves are preferably covered with a thin-film barrier layer 9 composed of a material which affords resistance to the chemical agent to be subsequently employed during an etching stage. By way of example, use can be made of silicon nitride Si3N4 or silica SiO2 which affords resistance to a chemical silicon-etching agent such as a mixture of nitric acid and hydrofluoric acidO The grooves are then filled with dielectric material. This material can advantageously consist of molten glass which has fairly good dîelectric properties at the frequencies con-sidered as well as good mechanical properties. Furthermore, this dielectric must be capable of withstanding the high temperatures encountered in avalanche diodes (up to 300C).
It is also worthy of note that the external diameter of the groove is of the order of magnitude of one half-wavelength (in the dielectric considered) of the electric signals employed in this type of device. The glass is supplied in a measured quantity such that its surface is flat or slightly concave. Fig. 3 is a sectional view of a fragment of the wafer 1. It is noted that the barrier layer 9 covers the walls of the groove which has been filled with molten glass 10. In this example of applica-tion of the method, the quantity of glass has been measured ~2~363~3 so as to produce a slightly concave surface. This makes it possible to weld the diode upside-down without any need for a substantial thickness of metallization and welding.
Inverted welding is a practical requirement in the case of avalanche diodes.
It comes within the scope of the invention to make use of dielectrics other than glass, such as poly-merizable materials, for example.
A wafer thickness greater than 100 microns has been intentionally chosen in order to permit correct formation of-grooves having a maximum depth of approx-imately 30 microns and to fill them with dielectric material. The choice of an original wafer of smaller thickness could give rise to problems as a result of mechanicaL stresses.
The step shown in Fig. 4 consists in grinding the wafer on the intrinsic side in order to reduce this latter to the desired thickness if necessary and to minimize the losses which could be introduced by an excessive thickness of silicon in spite of its high resistivity. It is even possible to continue the operation until initial grinding of the glass. In the case illus-trated in Fig. 4, the value chosen for the dimension ~2 is much smaller than the value El The following operation consists in chemical etching of the waEer regions located internally with _9_ respect to the annular grooves by making use of a masking technique. This etching operation is continued down to the first epitaxial layer which is adjacent -to the sub-strate 1 while eVen removing a part of this n+ region.
Checking of the thickness of the junction may be performed by means of an in~rared transparency test. This etching operation is preferably performed in reactive plasma by reason of the possible anisotropy of the etching. Fig. 5 shows the result obtained on comple-tion of this etching process. The type of masking adopted has made it possible to retain a portion of the substrate beneath the groove and to form a central cup. The bottom of said central cup is therefore constituted by the semiconducting pastille and its rim is constituted by part of that face of the substrate from which the etching operation has been performed. The barrier layer 9 has prevented any possible attack of the glass by the chemical agent. The junction thus obtained is limited to its active portion and inserted in a support having controlled dimensions.
The step shown in Fig. 6 consists in metallizing the faces providing access to the junction in order to form the connecting leads. It i5 an advantage to extend the metallizations on each face of the wafer by cathodic sputtering, for example. One advantageous method consists in first depositing a platinum layer on each face of the junction and in forming platinum silicide by heat treatment ~ f~ g~
at a temperature of approximately 400C followed by successive deposits of titanium, platinum and gold on all or part of the faces of the wafer.
This series of titanium-platinum-gold deposits is represented in Fig. 6 by the layers 13 and 14. When an avalanche diode is used in continuous operation, that portion of the junction which heats up to the greatest extent is the top portion if consideration is given to Fig~ 6, that is to say the portion which is close to the metallization layers 11 and 13. This accordingly gives rise to the problem of removal of the heat given off by the junction during operation. The design or the diode in accordance with the invention has the advantage of pro-viding the maximum clearance on that side of the junction which heats its support -to the greatest extent, especialLy if the dielectric 10 has a slightly concave free surface.
For better heat removal r avalanche diodes are usually bonded by inverted welding, that is to say to the metalli~ation layer 13 (of Ti-Pt-Au). The contact 13 is accordingly formed by an electrolytic growth of gold which provides a thermal and mechanical buffer between the brazing material and the diode. In -the case of inverted welding or bonding to diamond II A (which is a crystallo-gra~hic variety of the diamond marketed by the South African company known as Drucker and the thermal conduct-ivity of which is distinctly higher than tha-t of copper), P36~
it will be possible to limit the thickness of the gold layer to 2 microns, for example, and to operate by thermo-compression in order to ensure maximum heat removal by the diamond. If the diode is intended to be utilized in the pulsed regime, the heat generated during use of the diode is distributed in a practically uniform manner on each face of the junction and it is an advantage in this case to provide a gold layer of greater thickness for the contact 14.
The step shown in Fig. 7 consists in separating the diodes by cutting, for example by the chemical etching process. Fig. 7 illustrates a diode which has thus been obtained. This diode is characterized by its geometrical dimensions such as it~ external diameter, for examplel which are important in many applica-tions. The chemical etching process employed for separating the diodes can proEitably serve to eliminate part of the frame of intrinsic material such as the portion A, for example, or even all of this material. The cutting operation can also contribute to the removal of part of the dielectric material 10 . The region 15 formed of epitaxial layers will preferabl~v be kept when it is desired to carry out inverted welding. Said region 15 is located in the same plane as the junction and serves to provide good surface flatness of the device at the time o-f welding.
The fact of allowing the intrinsic frame to 31!~
remain entirely as shown in Fig. 7 is liable to introduce losses at the utilization frequencies. In consequence, the method described is particularly advantageous from the point o~ view of cost price since the diode obtained by batch fabrication does not entail any need for a casing~
The above-mentioned fr~me may be compared with a resistor R and a capacitor C which are connected in parallel with the junction. In the case of the diode given by way of example of application r it iS nevertheless demonstrated that the current within the parasitic resistor R is approximately 2500 times lower than the current within -the capacitor C at a frequency of 94 GHz.
The diode cut-outs can be of circular shape. In this case, each diode appears in the form of a small disk as shown in FigO 8 which is a top view of a diode from which the metallization layers 11 and 13 have been removed.
There can be seen in this figure the junction 7 at the center of the dielectric 10 which is in turn sur-ro~mded by an annulus 15 formed by residues of the epitaxial layers.
It is within the scope of the invention to give a square or rectangular shape to the junction, the surfaces of said junction which are in contact with the metalliza-tion layers being provided in the form of elongated rectangles which tend to reduce the thermal resistance between the junction and the metallic contacts. Fig. 9 is ~2~3~
a top view of a design of this type from which the metallization layers have been removed in order to gain acces~ ~o the junction. It has been found pre~erable in this case to give the assembly a shape which is also rectangular although this is not an essential requirement.
The cutting operation may be performed with a saw or, if so desired, by chemical etching which should preferably be highlv anisotropic. ~he figure shows the junction 16 sur-rounded by a dielectric 17 which can consist of glass as lo in thé preceding embodiment and by a frame 18 having the same composition as the junction 16.
By virtue of the hollow shape of the metalliza-tion layer 14, a contact can nevertheless be readily established between a connecting lead and this face of the diode simply by applying a rod within the utilization cavity.
In order to limit any possible current leakage, an insulating layer 19 can be deposited locally prior to metallization by means of a lift-off technique, for eXample on the zone 15 as shown in Fig. 10. Fig. 11 shows the same avalanche diode as the diode which was described earlier and from which the original substrate 1 has been completely removed, with the result that the diode can accordingly have any desired resistiYity.
~nother type of cut-out has resulted in the device shown in Fig. 12 which retains a portion 26 of the
elementary chip may be produced by batch-cutting ~rom a wafer, the very delicate addition of good encapsulation is in fact a unitary process. The present invention pro-poses a remedy for these problems by means of a particular method of manufacturen The invention is directed to a method for the batch manufacture of a semiconductor device comprising a multilayer semiconducting pastille placed between two connecting leads, the different steps of the method being as follows :
a) epitaxial growth from a semiconductor substrate of an assembiy of layers for providing the struc~ure of said pastille, b) delimitation of said pastille by etching said assembly so as to form an annular cup having a depth greater than that of the assembly, c) filling of said annular cup with dielectric material.
A further distinctive feature of the invention lies in the fact that it also involves the following steps :
d) etching of the substrate on the face opposite to the assembly in order to form a central cup, the bottom wall of which is constituted by said pastille, the rim of which is constituted by said opposit face and the side walls of which are delimited by the dieleckric material, e) formation of the connecting leads aforesaid by means of ~2~
a metal overlay on both faces of the complex structure obtained in the preceding step, f) detachment of the device by cutting performed outside the central cup~
The invention is further directed to a semi-conductor device comprising a support having a first and a second metallized face, a semiconducting pastille in-cluded in said support and adjacent to said first face, and an annular cup formed around sald pastille from said first face. The depth of said annular cup is at least equal to the thickness of said pastille and is filled with dielectric material. Said device essentially comprises in addition a central cup which is formed from said second face and the bottom wall of which joins said pastille, the rim of said central cup being formed by a portion of said second face.
Other features of the invention will be more apparent upon consideration of the following description and accompanying drawings, wherein :
- Figs. l to 7 illustrate the successive steps of the batch process in accordance with the invention ;
- Fig. 8 is a top view of a diode produced by means of the process in accordance with the invention ;
- Fig~ 9 is another top view oE a diode produced by means of the process in accordance with the invention ;
- Figs. lO to 12 show alternative forms of diodes ~a~_ ~3Gi~
produced by the batch process ;
- Figs. 13 and 14 are original steps of the batch process.
The fabrication of silicon avalanche diodes by means of the method of manufacture in accordance with the invention will now be described by way of example. In particular, this type of diode can be employed in modules for millimeter waves (at operating frequencies of the order of 100 GHz) by reason of the high accessibility of their geometrical components.
In order to form the junction, a series of layers of different conductivity types which will subse-quently form a semiconducting structure are formed by epitaxial growth on a monocrystalline silicone wafer having high resistivity. The cross-sectional area of the wafer will be designated as S~ the thickness of said wafer will be designated as W, its resistivity will be designated as p and its dielectric constant will be designated as ~.
The wafer can be compared with a resistor connected in parallel with a capacitor. The behavior of the wafer will become more similar to that of a dielectric as the current which flows through said wafer and which is subjected to a voltage having an angular frequency ~ between its two faces is obtained much more by capacitive effect than by the resistive effect of the electrical diagram equivalent to the wafer. This condition is satisfied if p .
1~3638 A wafer having high resistivity is therefore employed at the outset. This wafer will be designated as ~ if the small quantity of impurities included in the semiconducto is n-type, and will be designated as ~ if said impurities are p-type. If the impurity residue is zero, then the material would in that case be designated as I (intrinsic).
Fig. 1 is a sectional view of part of the wafer.
This view shows the original waer 1 whi~h is not doped or which may be only lightly doped, in contrast to the usual methods of fabrication in which the initial substrate was usually n doped. The thickness of this wafer is approximately 100 microns for technical reasons which will be explained hereinafter. Its resistivity is of the order of 4000 Q.cm or more. The first layer developed on the wafer is the n doped layer 2 having a resistivity of 0.003 Q.cm and a thickness of approximately 5 to 10 microns.
There then follow an n-type layer 3 (thickness of 0.35 micron, doping of 2 x 1017 atoms/cm3), a p~type layer 4 (a thickness of 0.35 micron, doping of 2 x 1017 atoms/cm ), and a p -type layer 5 ~thickness of 0.3 micron, doping of 5 x 10 9 atoms/cm3). This is therefore an avalanche diode having a double drift region.
The second step of the method relates to de-limitation of future diodes. This step consists in carry-ing ou-t a chemical mesa etching whieh progresses from the epitaxial growth layers down to the substrate 1 in order to ~3~38 form grooves 6 having the shape of annular cups which delimit the future diodes. The junctions will therefore appear in the Eorm of pastilles. For reasons of enhanced simplicity, the complete assembly of epitaxial layers is designated by the single reference numeral 7. At this stage, the wafer has the appearance illustrated in the cross section of Fig. 2. The groove which surrounds each diode can be circular. In this case, the elements fabricated for operating frequencies of the order of 94 GHz have approximately the following geometrical charac-teristics : -- diameter of the junction : 30 microns - external diameter of the groove : 400 microns - depth of groove : 30 microns.
With due regard to theoretical considerations relating to the use of this type of diode in modules for millimetex waves, the groove has been formed in accordance with a special profile as shown in cross-section in Fig. 2.
This profile has been obtained by chemical etching carried out in two stages. For example/ the wafer was etched by means of a first mask until the depth corresponding to the annular shoulder 8 was reached. Etching of the wafer was then resumed with a second mask having a smaller surface area in order to obtain the profile which is illus-trated.
In Fig. 2, in which the cross-section has been taken along a diameter of the groove 6, it is observed that the depth ~2~3~
of the annular shoulder 8 is appro~imately equ~l to the total thickness of the epitaxial layers.
In the following step, the walls o~ the grooves are preferably covered with a thin-film barrier layer 9 composed of a material which affords resistance to the chemical agent to be subsequently employed during an etching stage. By way of example, use can be made of silicon nitride Si3N4 or silica SiO2 which affords resistance to a chemical silicon-etching agent such as a mixture of nitric acid and hydrofluoric acidO The grooves are then filled with dielectric material. This material can advantageously consist of molten glass which has fairly good dîelectric properties at the frequencies con-sidered as well as good mechanical properties. Furthermore, this dielectric must be capable of withstanding the high temperatures encountered in avalanche diodes (up to 300C).
It is also worthy of note that the external diameter of the groove is of the order of magnitude of one half-wavelength (in the dielectric considered) of the electric signals employed in this type of device. The glass is supplied in a measured quantity such that its surface is flat or slightly concave. Fig. 3 is a sectional view of a fragment of the wafer 1. It is noted that the barrier layer 9 covers the walls of the groove which has been filled with molten glass 10. In this example of applica-tion of the method, the quantity of glass has been measured ~2~363~3 so as to produce a slightly concave surface. This makes it possible to weld the diode upside-down without any need for a substantial thickness of metallization and welding.
Inverted welding is a practical requirement in the case of avalanche diodes.
It comes within the scope of the invention to make use of dielectrics other than glass, such as poly-merizable materials, for example.
A wafer thickness greater than 100 microns has been intentionally chosen in order to permit correct formation of-grooves having a maximum depth of approx-imately 30 microns and to fill them with dielectric material. The choice of an original wafer of smaller thickness could give rise to problems as a result of mechanicaL stresses.
The step shown in Fig. 4 consists in grinding the wafer on the intrinsic side in order to reduce this latter to the desired thickness if necessary and to minimize the losses which could be introduced by an excessive thickness of silicon in spite of its high resistivity. It is even possible to continue the operation until initial grinding of the glass. In the case illus-trated in Fig. 4, the value chosen for the dimension ~2 is much smaller than the value El The following operation consists in chemical etching of the waEer regions located internally with _9_ respect to the annular grooves by making use of a masking technique. This etching operation is continued down to the first epitaxial layer which is adjacent -to the sub-strate 1 while eVen removing a part of this n+ region.
Checking of the thickness of the junction may be performed by means of an in~rared transparency test. This etching operation is preferably performed in reactive plasma by reason of the possible anisotropy of the etching. Fig. 5 shows the result obtained on comple-tion of this etching process. The type of masking adopted has made it possible to retain a portion of the substrate beneath the groove and to form a central cup. The bottom of said central cup is therefore constituted by the semiconducting pastille and its rim is constituted by part of that face of the substrate from which the etching operation has been performed. The barrier layer 9 has prevented any possible attack of the glass by the chemical agent. The junction thus obtained is limited to its active portion and inserted in a support having controlled dimensions.
The step shown in Fig. 6 consists in metallizing the faces providing access to the junction in order to form the connecting leads. It i5 an advantage to extend the metallizations on each face of the wafer by cathodic sputtering, for example. One advantageous method consists in first depositing a platinum layer on each face of the junction and in forming platinum silicide by heat treatment ~ f~ g~
at a temperature of approximately 400C followed by successive deposits of titanium, platinum and gold on all or part of the faces of the wafer.
This series of titanium-platinum-gold deposits is represented in Fig. 6 by the layers 13 and 14. When an avalanche diode is used in continuous operation, that portion of the junction which heats up to the greatest extent is the top portion if consideration is given to Fig~ 6, that is to say the portion which is close to the metallization layers 11 and 13. This accordingly gives rise to the problem of removal of the heat given off by the junction during operation. The design or the diode in accordance with the invention has the advantage of pro-viding the maximum clearance on that side of the junction which heats its support -to the greatest extent, especialLy if the dielectric 10 has a slightly concave free surface.
For better heat removal r avalanche diodes are usually bonded by inverted welding, that is to say to the metalli~ation layer 13 (of Ti-Pt-Au). The contact 13 is accordingly formed by an electrolytic growth of gold which provides a thermal and mechanical buffer between the brazing material and the diode. In -the case of inverted welding or bonding to diamond II A (which is a crystallo-gra~hic variety of the diamond marketed by the South African company known as Drucker and the thermal conduct-ivity of which is distinctly higher than tha-t of copper), P36~
it will be possible to limit the thickness of the gold layer to 2 microns, for example, and to operate by thermo-compression in order to ensure maximum heat removal by the diamond. If the diode is intended to be utilized in the pulsed regime, the heat generated during use of the diode is distributed in a practically uniform manner on each face of the junction and it is an advantage in this case to provide a gold layer of greater thickness for the contact 14.
The step shown in Fig. 7 consists in separating the diodes by cutting, for example by the chemical etching process. Fig. 7 illustrates a diode which has thus been obtained. This diode is characterized by its geometrical dimensions such as it~ external diameter, for examplel which are important in many applica-tions. The chemical etching process employed for separating the diodes can proEitably serve to eliminate part of the frame of intrinsic material such as the portion A, for example, or even all of this material. The cutting operation can also contribute to the removal of part of the dielectric material 10 . The region 15 formed of epitaxial layers will preferabl~v be kept when it is desired to carry out inverted welding. Said region 15 is located in the same plane as the junction and serves to provide good surface flatness of the device at the time o-f welding.
The fact of allowing the intrinsic frame to 31!~
remain entirely as shown in Fig. 7 is liable to introduce losses at the utilization frequencies. In consequence, the method described is particularly advantageous from the point o~ view of cost price since the diode obtained by batch fabrication does not entail any need for a casing~
The above-mentioned fr~me may be compared with a resistor R and a capacitor C which are connected in parallel with the junction. In the case of the diode given by way of example of application r it iS nevertheless demonstrated that the current within the parasitic resistor R is approximately 2500 times lower than the current within -the capacitor C at a frequency of 94 GHz.
The diode cut-outs can be of circular shape. In this case, each diode appears in the form of a small disk as shown in FigO 8 which is a top view of a diode from which the metallization layers 11 and 13 have been removed.
There can be seen in this figure the junction 7 at the center of the dielectric 10 which is in turn sur-ro~mded by an annulus 15 formed by residues of the epitaxial layers.
It is within the scope of the invention to give a square or rectangular shape to the junction, the surfaces of said junction which are in contact with the metalliza-tion layers being provided in the form of elongated rectangles which tend to reduce the thermal resistance between the junction and the metallic contacts. Fig. 9 is ~2~3~
a top view of a design of this type from which the metallization layers have been removed in order to gain acces~ ~o the junction. It has been found pre~erable in this case to give the assembly a shape which is also rectangular although this is not an essential requirement.
The cutting operation may be performed with a saw or, if so desired, by chemical etching which should preferably be highlv anisotropic. ~he figure shows the junction 16 sur-rounded by a dielectric 17 which can consist of glass as lo in thé preceding embodiment and by a frame 18 having the same composition as the junction 16.
By virtue of the hollow shape of the metalliza-tion layer 14, a contact can nevertheless be readily established between a connecting lead and this face of the diode simply by applying a rod within the utilization cavity.
In order to limit any possible current leakage, an insulating layer 19 can be deposited locally prior to metallization by means of a lift-off technique, for eXample on the zone 15 as shown in Fig. 10. Fig. 11 shows the same avalanche diode as the diode which was described earlier and from which the original substrate 1 has been completely removed, with the result that the diode can accordingly have any desired resistiYity.
~nother type of cut-out has resulted in the device shown in Fig. 12 which retains a portion 26 of the
3~
substrate 1. It is observed that there no longer remains any semiconducting material which interconnects the electrodes. In this case, if -the grooves are of sufficient depth, the material forming the substrate does not need to have very high resistivity. It must on the contrary have very low resistivity in order to avoid any introduction of lossesO
An alternative embodiment of the method of fabrication consists in depositing a barrier layer between the substrate and the epitaxial layers. In this case, in order to form, for example, an avalanche diode having a double drift region similar to the diode described earlier, the starting element can consist of an _ doped semi-conductor substrate having the shape of a disk approx-imately two inches in diameter and one hundred microns inthickness. The partial view of Fig. 13 shows the sub-strate 22 on which a barrier layer 20 has been deposited.
Said barrier layer can be formed of silicon oxide SiO2, of silicon nitride Si3N4 or by a mixture of these ~wo products.
There is then deposited in an epitaxial-growth reaction vessel a thick layer 21 approximately one hundred microns in thickness and consisting of polycrystalline silicon having high resistivity (p ~ 1). This high resistivity can be obtained for example by lightly doping the silicon with oxygen or nitrogen~ The conditions of growth of this layer are adjusted so as to ensure excellent surface 3~
flatness of the top face of the layer 22. Said layer 22 is then thinned-down by grinding and/or chemical etching to a thickness of approximately 5 to 10 microns. An n-doped layer 23, a p-doped layer 24 and a ~ -doped layer 25 are then developed by epitaxial growth on the layer ~2 The impurity concentrations and the thicknesses of the layers 22 to 25 are of the same order of magnitude as the corresponding layers of the avalanche diode described earlier. At this stage, the method of manufacture resumes the steps described earlier. The advantage of this variant is that chemical etching of the rear face or in other words etching of the substrate in the direction of the layer 22, stops at the barrier layer 20. Said barrier layer 20 has to be partly removed in order to establish a contact with the layer 22. This is achieved by selective chemical etching or rather by ion-beam machining which ensures better control of the etching process.
In the case of the vaxiant as in the case described earlier, the groove can have a depth either greater than or equal to the thickness of the semiconducting structure which forms the diode. If the thickness of the groove is greater than the thickness of the structure, the chemical etching which serves to cut said groove must be capable of partly removing the barrier layer 20 and attacking the substrate 21. This is illustrated in Fig. 14 which is a cross-section of the wafer duriny fabrication, ~2~163~
said cross-section being taken along a diameter of the groove~ There can be seen -the groove 28 provided with an annular shoulder 26, the semiconducting structure 27 and residues of the barrier layer 20. Another barrier layer 29 is then deposited on the walls of the groove. The intended ~unction of this layer is to protect the dielectric subse~uently employed for fillin~ the groove against chemical etching of ~he substrate 21 at the time o~ access to the layer 22. If the groove is given a depth e~ual to ~he thickness of the semiconducting structure 27, the layer 20 can serve to stop the chemical attack which is necessary in order to form the groove. Said layer 20 can then be partly removed by ion-beam machining in order to gain access to the layer 22.
The invention also applies to any diode which it may be desired to mount the right way up, that is, in the non~inverted position. The invention is also applicable to diodes fabricated from gallium arsenide, in particular to Gunn diodes, to mixer diodes and possibly also to varactor diodes. It is necessary in this case to employ the method in accordance with the invention in conjunction with the technology which is suited to gallium arsenide.
The method and the result achieved by the method in accordance with the invention offer appreciable advanta$es over the prior art. These advantages are as follows :
~17-?AI~
- a method of batch fabrication on a wafer, - the fact that there is no need for a casing, - the formati.on of an inverted weld under excellent conditions and good surface flatness of the device, - the possibility of giving various shapes to the junction, - accessibility to the aimensions of the component and in particular -to the annulus of dielectric material which surrounds the junction, thus permitting good radial impedance conversion in the case of modules for milli-meter waves.
substrate 1. It is observed that there no longer remains any semiconducting material which interconnects the electrodes. In this case, if -the grooves are of sufficient depth, the material forming the substrate does not need to have very high resistivity. It must on the contrary have very low resistivity in order to avoid any introduction of lossesO
An alternative embodiment of the method of fabrication consists in depositing a barrier layer between the substrate and the epitaxial layers. In this case, in order to form, for example, an avalanche diode having a double drift region similar to the diode described earlier, the starting element can consist of an _ doped semi-conductor substrate having the shape of a disk approx-imately two inches in diameter and one hundred microns inthickness. The partial view of Fig. 13 shows the sub-strate 22 on which a barrier layer 20 has been deposited.
Said barrier layer can be formed of silicon oxide SiO2, of silicon nitride Si3N4 or by a mixture of these ~wo products.
There is then deposited in an epitaxial-growth reaction vessel a thick layer 21 approximately one hundred microns in thickness and consisting of polycrystalline silicon having high resistivity (p ~ 1). This high resistivity can be obtained for example by lightly doping the silicon with oxygen or nitrogen~ The conditions of growth of this layer are adjusted so as to ensure excellent surface 3~
flatness of the top face of the layer 22. Said layer 22 is then thinned-down by grinding and/or chemical etching to a thickness of approximately 5 to 10 microns. An n-doped layer 23, a p-doped layer 24 and a ~ -doped layer 25 are then developed by epitaxial growth on the layer ~2 The impurity concentrations and the thicknesses of the layers 22 to 25 are of the same order of magnitude as the corresponding layers of the avalanche diode described earlier. At this stage, the method of manufacture resumes the steps described earlier. The advantage of this variant is that chemical etching of the rear face or in other words etching of the substrate in the direction of the layer 22, stops at the barrier layer 20. Said barrier layer 20 has to be partly removed in order to establish a contact with the layer 22. This is achieved by selective chemical etching or rather by ion-beam machining which ensures better control of the etching process.
In the case of the vaxiant as in the case described earlier, the groove can have a depth either greater than or equal to the thickness of the semiconducting structure which forms the diode. If the thickness of the groove is greater than the thickness of the structure, the chemical etching which serves to cut said groove must be capable of partly removing the barrier layer 20 and attacking the substrate 21. This is illustrated in Fig. 14 which is a cross-section of the wafer duriny fabrication, ~2~163~
said cross-section being taken along a diameter of the groove~ There can be seen -the groove 28 provided with an annular shoulder 26, the semiconducting structure 27 and residues of the barrier layer 20. Another barrier layer 29 is then deposited on the walls of the groove. The intended ~unction of this layer is to protect the dielectric subse~uently employed for fillin~ the groove against chemical etching of ~he substrate 21 at the time o~ access to the layer 22. If the groove is given a depth e~ual to ~he thickness of the semiconducting structure 27, the layer 20 can serve to stop the chemical attack which is necessary in order to form the groove. Said layer 20 can then be partly removed by ion-beam machining in order to gain access to the layer 22.
The invention also applies to any diode which it may be desired to mount the right way up, that is, in the non~inverted position. The invention is also applicable to diodes fabricated from gallium arsenide, in particular to Gunn diodes, to mixer diodes and possibly also to varactor diodes. It is necessary in this case to employ the method in accordance with the invention in conjunction with the technology which is suited to gallium arsenide.
The method and the result achieved by the method in accordance with the invention offer appreciable advanta$es over the prior art. These advantages are as follows :
~17-?AI~
- a method of batch fabrication on a wafer, - the fact that there is no need for a casing, - the formati.on of an inverted weld under excellent conditions and good surface flatness of the device, - the possibility of giving various shapes to the junction, - accessibility to the aimensions of the component and in particular -to the annulus of dielectric material which surrounds the junction, thus permitting good radial impedance conversion in the case of modules for milli-meter waves.
Claims (14)
1. A method for batch manufacture of a semi-conductor device comprising a multilayer semiconducting pastille placed between two connecting leads, the different steps of the method being as follows :
a) epitaxial growth from a semiconductor substrate of an assembly of layers for providing the structure of said pastille, b) delimitation of said pastille by etching said assembly so as to form an annular cup having a depth greater than that of the assembly, c) filling of said annular cup with dielectric material, wherein said method further comprises the following steps :
d) etching of the substrate on the face opposite to the assembly in order to form a central cup, the bottom of which is constituted by said pastille, the rim of which is constituted by said opposite face and the side walls of which are delimited by the dielectric material, e) formation of the connecting leads aforesaid by means of a metal overlay on both faces of the complex structure obtained in the preceding step, f) detachment of the device by cutting performed outside the central cup.
a) epitaxial growth from a semiconductor substrate of an assembly of layers for providing the structure of said pastille, b) delimitation of said pastille by etching said assembly so as to form an annular cup having a depth greater than that of the assembly, c) filling of said annular cup with dielectric material, wherein said method further comprises the following steps :
d) etching of the substrate on the face opposite to the assembly in order to form a central cup, the bottom of which is constituted by said pastille, the rim of which is constituted by said opposite face and the side walls of which are delimited by the dielectric material, e) formation of the connecting leads aforesaid by means of a metal overlay on both faces of the complex structure obtained in the preceding step, f) detachment of the device by cutting performed outside the central cup.
2. A method of batch manufacture according to claim 1, wherein said semiconductor substrate has high resistivity at the utilization frequencies of the semiconductor devices.
3. A method of batch manufacture according to claim 1, wherein said method comprises a step which involves machining of the substrate face opposite to said structure in order to reduce the thickness of the sub-strate.
4. A method of batch manufacture according to claim 1, wherein the semiconductor substrate is constituted by a first layer which is intended to form part of said pastille and by a second high-resistivity layer, said two layers being separated by a barrier layer which is then selectively removed prior to formation of the connecting leads.
5. A method of batch manufacture according to claim 1, wherein the walls of said annular cup are covered with a barrier layer.
6. A method of batch manufacture according to claim 1, wherein said filling operation is carried out by deposition of glass in the molten state.
7. A method of batch manufacture according to claim 1, wherein said filling operation is regulated so as to ensure that the dielectric material has a concave surface.
8. A method of batch manufacture according to claim 1, wherein said detachment of the device is performed by chemical etching.
9. A method of batch manufacture according to claim 8, wherein said chemical etching also removes at least part of said semiconducting material which surrounds the dielectric material.
10. A method of batch manufacture according to claim 1, wherein said detachment of the device also serves to remove part of said dielectric material.
11. A semiconductor device comprising a support having a first and a second metallized face, a semiconduct-ing pastille included in said support and adjacent to said first face, an annular cup formed around said pastille from said first face, the depth of said annular cup being at least equal to the thickness of said pastille and being filled with dielectric material, wherein said device further comprises a central cup formed from said second face, the bottom of said central cup being joined to said pastille and the rim of said central cup being formed by a portion of said second face.
12. A semiconductor device according to claim 11, wherein said support comprises an annulus which surrounds said dielectric material, said annulus being of the same nature as said pastille and located in the same plane as said pastille.
13. A semiconductor device according to claim 11, wherein said support comprises a residual annulus of said substrate surrounding said dielectric material.
14. A semiconductor device according to claim 11, wherein an insulating layer separates said annulus which surrounds the dielectric material from the corresponding metallized face.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8201651A FR2520931B1 (en) | 1982-02-02 | 1982-02-02 | COLLECTIVE PROCESS FOR MANUFACTURING MICROWAVE DIODES WITH BUILT-IN ENCAPSULATION AND DIODES OBTAINED THEREBY |
| FR8201651 | 1982-02-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1203638A true CA1203638A (en) | 1986-04-22 |
Family
ID=9270586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000420415A Expired CA1203638A (en) | 1982-02-02 | 1983-01-28 | Method of batch manufacture of microwave diodes with incorporated encapsulation and diodes obtained by said method |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0085607A3 (en) |
| JP (1) | JPS58134486A (en) |
| CA (1) | CA1203638A (en) |
| FR (1) | FR2520931B1 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2559959B1 (en) * | 1984-02-21 | 1987-05-22 | Thomson Csf | MICROWAVE DIODE WITH EXTERNAL CONNECTIONS TAKEN BY BEAMS AND METHOD FOR PRODUCING THE SAME |
| FR2565030B1 (en) * | 1984-05-25 | 1986-08-22 | Thomson Csf | STRUCTURE OF METALLIZATIONS FOR RETRIEVING CONTACTS OF A SEMICONDUCTOR DEVICE AND DEVICE HAVING SUCH A STRUCTURE |
| GB8719309D0 (en) * | 1987-08-14 | 1987-09-23 | Marconi Electronic Devices | Diodes |
| DE4209983A1 (en) * | 1992-03-27 | 1993-09-30 | Daimler Benz Ag | Semiconductor component mfr. esp. IMPATT diode prodn. - producing component, housing and connection contacts in integrated construction from and on semiconductor substrate |
| EP0603971A3 (en) * | 1992-12-23 | 1995-06-28 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device with passivated side and semiconductor device with passivated side. |
| DE4317721C1 (en) * | 1993-05-27 | 1994-07-21 | Siemens Ag | Process for separating chips from a wafer |
| DE19856331B4 (en) * | 1998-12-07 | 2009-01-02 | Robert Bosch Gmbh | Method for encasing electronic components |
| US8182528B2 (en) | 2003-12-23 | 2012-05-22 | Sadra Medical, Inc. | Locking heart valve anchor |
| DE102007007159B4 (en) * | 2007-02-09 | 2009-09-03 | Technische Universität Darmstadt | Gunn diode |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4180422A (en) * | 1969-02-03 | 1979-12-25 | Raytheon Company | Method of making semiconductor diodes |
| GB2028583B (en) * | 1978-08-02 | 1983-01-06 | Aei Semiconductors Ltd | Electrical lead for a semiconductor device |
| GB2067354B (en) * | 1980-01-09 | 1984-04-18 | Aei Semiconductors Ltd | Mounting for a sc device |
-
1982
- 1982-02-02 FR FR8201651A patent/FR2520931B1/en not_active Expired
-
1983
- 1983-01-25 EP EP83400164A patent/EP0085607A3/en not_active Withdrawn
- 1983-01-28 CA CA000420415A patent/CA1203638A/en not_active Expired
- 1983-02-01 JP JP58015385A patent/JPS58134486A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2520931A1 (en) | 1983-08-05 |
| FR2520931B1 (en) | 1986-12-12 |
| EP0085607A3 (en) | 1983-08-24 |
| EP0085607A2 (en) | 1983-08-10 |
| JPS58134486A (en) | 1983-08-10 |
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