CA1203568A

CA1203568A - Method and apparatus for load shedding

Info

Publication number: CA1203568A
Application number: CA000444782A
Authority: CA
Inventors: G. Carl Schweer
Original assignee: 319226 ONTARIO Ltd D/B/A CARMA INDUSTRIES
Current assignee: 319226 ONTARIO Ltd D/B/A CARMA INDUSTRIES
Priority date: 1984-01-05
Filing date: 1984-01-05
Publication date: 1986-04-22

Abstract

ABSTRACT OF THE DISCLOSURE

The present invention relates to a method and apparatus of turning (load shedding) non-critical loads on and off over wide areas for the purpose of controlling peak demands in an electrical distribution system. An active tuned high pass filter is used to detect on-off signals and cause loads to be added or shedded particularly hot water heaters and plenum heaters.

Description

The present invention relates to a method and apparatus of turning (load shedding) non-critical loads on and off over wide areas for the purpose of controlling peak demands in an electrical distribution system.

Receivers Eor turning (load shedding) non-critical loads on and off over wide areas have been in use since the 1930's for the purpose of controlling peak demands. The present systems generally consist of a signal in]ector, a motor generator, both located at a power dis-tribution sub-station, and receivers located at the load (usually hot water heaters and plenum heaters) to be switched. When required, the signal injector superimposes a high frequency (720 ~z or 3KHz) on the 60Hz power line at an amplitude of approximately 2.5% of line voltage through suitable coupling means. The receivers respond to the high frequency signal by either switching on or off, depending on the duration of the signal. Typically, for hot water heaters, four to six seconds is a switch ON signal, while sixteen to twen-ty-four seconds is a switch OFF signal.

In the devices presently used, 720Hz is separated from 60Hz by some forrn of high pass filter. The separated 720Hz releases a tirner, usually of the resistor-capacitance type which, in turn, latches the relay contacts closed or open.

~203568 The presently used receivers suffer from a number of drawbacks. First, the lnput impedence is very low, usually from six to one-hundred ohms, and therefore the signal injector must supply a large amount of power. Secondly, the separation of 720Hz from 60Hz is usually by tuned circuits, and therefore bulky components are required which may have poor tolerances, possibly resulting in false operation. Thirdly, the timing means used is generally a resistor-capacitor method, and this suffers from poor tolerances and temperature variations. Fourthly, a long duration ON signal can cause a false trip to OFF.

Accordingly, it is an object of the present invention to provide an improved receiver for turning non-critical loads on and off over wide areas for the purpose of controlling peak demands.
It is a further object of the present invention to allow for the selection of at least two types of loads to be shedded, such as hot water heater loads and plenum heater loads without changing the type of signal injection equipment presently being used. The receiver of the present invention has a much higher input impedence, and thus eliminating the necessity for the signal injector to supply a large amount of power. In addition, the present invention contains a "T" filter and an active filter combination which does not require the same bulky components as had been used in prior-art receivers. Further, timing is accomplished in the present invention by a counting technique, a ripple coun-ter, and gating techniques, thus providing greater tolerances and less influence due to temperature variations than was possible in old receivers. In addition, the present invention employs a relay control in the form of an enabled latch, preventing false OFF operation, which is controlled by the timer.
The duration of the high frequency control signal allows for the selective shedding of one load.

The present invention provides a receiver for a load shedding system comprising:
(a) a power supply into which an input signal is sent;
(b) a means to attenuate the input signal;
(c) a passive high pass filter to annenuate low components of the input signal;
(d) an active tuned filter to pass a pre-determined high frequency component of the input signal;
(e) timing circuits to detect a pre-determined high frequency component and output a signal to a latch;
(f) a control relay energizing circuit which accepts an output signal from the latch and causes a load to be sheddecl or added.

1203S~;8 A preferred embodiment of the present invention will be described with the aid of the accompanying drawings. It is understood -that the accompanying drawings and the description of the preferred embodiment are not intended to limit the scope of the invention.

Figure 1 is a drawing showing a 60Hz sine wave, a 720Hz sine wave, and wave comprised of the sum of 60Hz and 720Hz;
Figure 2 is a block diagram of a preferred embodiment of the present invention;
Figure 3 shows a typical power distribution system for use in association with the present invention.
Reference is made to Figure 1. In Canada and in the United States of America, the typical frequency for line voltage is a 60Hz sine wave as shown in Figure 1. In present methods of load shedding, a signal injector generates a 720Hz sine wave, shown in Figure 1, at an amplitude of approximately 2.5% of the line voltage through a suitable coupling means. The resulting signal comprising 720Hz superimposed on 60Hz is shown in Figure 1.
At the present time, this signal is sent to receivers which are attached to ].oads to be shedded during times of peak demand.
Typically, for hot water heaters, a signal of sixteen to twenty-four seconds will cause -the receiver to switch OFF the load. After the peak demand period is over, a signal of four to six seconds would be sent to switch ON the load again.

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Reference is made to Figure 3 which shows a typical power distribution system. The sub-station is shown at 20, where the 720Hz signal is injected through transformer T2. Only the secondary of transformer Tl is shown in the drawing. Typically, Phases A, B and C would be distributed to about 25 transformers T3, and typically, approximately 10 households would be services by transformer T3. Secondary 10 from transformer T3 is distributed to homes and receivers, and is generally 220 volts.

Reference is made to Figure 2, the block diagram of a receiver of a preferred embodiment of the presen-t invention. The input at voltage divider and power supply 10 comes from the secondary of transformer T3 in Figure 3. This input signal may or may not contain the 720Hz signal superimposed on the 60Hz line frequency. Generally, the 720Hz signal is either 1.5 volts AC or 3 volts AC, depending on whether the input is 120 volts AC at 60Hz or 2~0 volts AC at 60Hz. The output from the voltage divider and power supply 10, for the preferred embodiment of the present invention, is 5 volts DC and an attenuated AC signal to a level for safe operation of the electronic components. The alternating current output preferably will be less than 20 volts AC.

The output :Erom voltage divider and power supply 10 is input into passive filter 20, which is a high pass filter of 120~

preferably single "T" configuration, which will greatly at-tenuate the 60Hz component, while passing the 720Hz component.
Preferably, filter 20 does not contain any active components, such as an amplifier.

The output Erom filter 20 is input into active tuned filter 30 which is tuned to 720Hz (plus or minus 30Hz) by the selection of capacitors and resistors configured around an operational amplifier. Only the 720Hz (plus or minus 30Hz) signal is passed and amplified. The bias is made adjustable to compensate for component tolerances.

The output from active filter 30 is input into converter 40 which serves a two-fold function. Converter 40 converts a 720Hz sine wave into a 720Hz square wave. This will enable proper operation of the cloc]c circuit of the counter 70. In addition, converter 40 will hold counter 70 in a reset mode when the 720Hz signal is not present.

One output from converter 40 is input into counter reset circuit 50. In counter reset circuit 50, when a 720Hz signal is not present, the output of converter 40 will remain at approximately 3.3 volts, allowing a capacitor to charge through a resistor to appro~imately 3.3 volts in ten milliseconds. However, when a 720Hz signal is present, the output of the converter 40 will drop to near zero volts 720 times per second. Thus, the previously mentioned capaeitor ean discharge through the same charging resistor, but in addition, can also discharge through a bloeking diode (which would now be forward biased) and another resistor o~ much lower value ensuring a discharge time of less than .7 milliseeonds (one half the period of 720Hz). In summary, the counter reset circuit 50 allows a counter reset capacitor to charge slowly and diseharge quickly depending on the input.

A second output from converter 40 is input into cloek gate 60. Clock gate 60 allows a 720Hz square wave to pass onto eounter 70 a cloek pulse as long as the output of AND gate 90 is at zero volts. An output from AND gate 90 is a seeond input into eloek gate 60. When the 2 inputs into eloek gate 60 are a 720Hz square wave from eonver-ter 40, and a zero volt signal from AND
gate 90, an output of eloek gate 60 will be a 5 volt positive square wave at 720Hz. However, if the input to eloek gate 60 from AND gate 90 is a 3 volt signal, the output of eloek gate 60 will be approximately 5 volts DC.

Counter 70 is a eonventional ripple counter, having one input from elock gate 60, and a second input from counter reset circuit 50. When the counter reset circuit output is at logic 1 voltage (3 volts), all outputs from counter circuit 70 are driven to zero and remain there regardless of clock gate output 60. When

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counter reset circuit 50 outputs logic zero voltage, the output from counter 70 will increment by 1 each time the output from clock gate 60 drops from logic 1 to logic 0.

AND gate 80 and AND gate 90 have input from counter 70.
The gates are made up of two diodes, and when both inputs 70 are a logical 1, the output from each AND gate will be a logical 1.
otherwise, the output from each .~ND gate will be a logic zero.

Latch circuit 100 has an input from AND gate 80 and AND
gate 90. I,atch 100 operates as a voltage comparator with regenerative (positive) feedback. The ouput from Latch 100 always follows the input that has the greater voltage. The output will be either a logic 1 (5 volts) or a logic zero (zero volts).

Timer 110 has its inputs from counter reset circuit 50, and outputs a signal to latch 100.

Timer 110 is provided to allow for selective load shedding. The load to be shedded is a function of the 720Hz shedding signal which is generated and input into voltage divider and power supply 10. In the preferred embodiment, selection can be made between 2 loads, a plenum heater control or a hot water hea-ter control without changing the type of signal injection equipment presently in use, although minor changes to the sequence ~03S~8 of the injection equipment operation will be required. Typical changes are: ~

ON OFF
Hot water heater 5 sec. 15 sec.
Plenum heater 1 sec. 3 sec.

The system can be set so that any signal greater than 4 seconds is ignored by the plenum heater, and any signal under 4 seconds has no effect on the hot water heater control. A 4 second plenum signal detector (not shown) and a plenum memory circuit (not shown) must be added to the plenum heater control unit.

! The plenum memory circui-t (not shown) retains the data of the previous signal. The timer 110 determines if the new signal is for the plenum heater or the hot water heater. If the signal is for the hot water heater, the plenum memory circuit will retain the previous siynal and not allow the plenum heater to switch states. However, if the signal is for the plenum heater, it will respond to the signal by switching states.

When the receiver of the present invention is first powered up~ the following conditions will prevail:

(1) AND gates 80 and g0 will be near zero volts. As a result, the output from Latch 100 will be approximately the supply _g_ 35~

voltage, 5 volts, so tht all units will go to the "ON" condition when primary power is applied.
(2) The Latch is now in the "latched" condition.

(3) Clock gate 60, counter 70, and AND gates 80 and 90 are "interlocked" in such a way that AND gate 80 and AND gate 90 can never be a logical one together, therefore, only one input of Latch 100 can receive a logic one at any given time. Counter 70 i5 a ripple counter, whose counting action is such that each succeeding stage can only change to a logic one, and when the previous stage drops to a logic one, while all other stages will be at loglc zero, after an additional 4,096 counts the second last stage will also be at logic one with all preceeding stages at logic zero. Now AND gate 90 has two logic one inputs, and its output will be logic one, which through clock gate 60 will prevent Eurthex counting, and thus avoiding a false latch (ON condition) from occurring.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A receiver for a load shedding system comprising:

(i) A power supply into which an input signal is sent;
(ii) Means to attenuate the input signal;
(iii) A passive high-pass filter to attenuate low frequency components of the input signal;
(iv) An active tuned filter to pass a predetermined high frequency component of the input signal;
(v) Timing circuits which detect a predetermined high frequency component and output a signal to a latch;
(vi) A control relay energizing circuit which accepts an output signal from the latch and causes a load to be shedded or added.

2. A receiver according to claim 1 wherein the means to attenuate the input signal is a voltage divider.

3. A receiver according to claim 2 wherein said timing circuits include a timing circuit to detect and determine the length of the predetermined high frequency circuit.

4. A receiver according to claim 3 wherein the control relay energizing circuit contains a memory circuit, which will be altered only when the predetermined high frequency signal is either greater than or less than a predetermined duration.