CA1200941A - Gain regulation circuit - Google Patents
Gain regulation circuitInfo
- Publication number
- CA1200941A CA1200941A CA000422784A CA422784A CA1200941A CA 1200941 A CA1200941 A CA 1200941A CA 000422784 A CA000422784 A CA 000422784A CA 422784 A CA422784 A CA 422784A CA 1200941 A CA1200941 A CA 1200941A
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- gain
- pairs
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- signal
- pair
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Abstract
GAIN REGULATION CIRCUIT
Abstract of the Disclosure A gain regulation circuit e.g. for a telephone subscriber's instrument, includes a plurality (2n + 1) of long tailed transistor pairs (TR51, TR52) one of which has a significantly higher gain than the remainder (2n). The circuit may be adjusted to a composite gain value between limits defined by the high and low gain pairs by providing a suitably weighted combination of these pairs. Typically this weighting is achieved by control currents (I1, I2, I3) fed into the tail circuits of the pairs.
Abstract of the Disclosure A gain regulation circuit e.g. for a telephone subscriber's instrument, includes a plurality (2n + 1) of long tailed transistor pairs (TR51, TR52) one of which has a significantly higher gain than the remainder (2n). The circuit may be adjusted to a composite gain value between limits defined by the high and low gain pairs by providing a suitably weighted combination of these pairs. Typically this weighting is achieved by control currents (I1, I2, I3) fed into the tail circuits of the pairs.
Description
P . F . B 1 o~r, 1 ey -7 GAIN R~GllLATION CIRCUIT
This invention relates to electronic amplifier circuits navinq a regulatable gain, and ir. particular to a gain regulation circuit for use in a telephone instrument anci whereby the gain of the instrumerit speech paths may ~e adjusted e.g. for matching the receiver gain to the line loop impedance.
An electronic telephone lnstrumen~ includes an amplifying speech path whereby speech signals are relaye~ from the instrument microphone to the line and fro~n ~he iine to the inStrument receiver. I~ ~.7ill be appreciated tha~ for optimum performance of the instrument the receiver and transniitter speech paths must each include some means of gain regulation to prevent overloading and to provide matchiny of the receiver gain ;:o the line impedarlce~ The line or loop impedance is in general proportional to the length of the subscriber loop between the instrumen~ and rhe exchange and can thus have any value wi~hin a clearly defined range. Because it is necessary to cater for a wide variation of loop length, it is essential that the receiver circuit of the subscriber's instrument incorporates provision for line length compensation. To compensate loop length variations many telephone administrations require the provision of receiver circuits that can be set to a gain figure anywhere between ~pper and lower preset limits.
Furthermore, in order to prevent overloading and consequent saturation of the transmitter output state to the line it is necessary to provide some form of gain control whereby a speecll si~lnal waveform Iriay be limi~ed in arplitude. This technique comlilo~ ;no~1n a ~,`' soft clippinq is described in co-pending Canadian patent application Serial No. 422,785 of P.F. Blomley, filed March 3, 19~3.
A particularly useful variable gain element is the transistor long tailed pair the gain of which can be determined by controlling the common emitter current of the pair. ~he use of a single long tailed pair is however somewhat restricted by its significantly non linear signal/gain characteristic which gives rise to distortion Eor all but very low signal levels. In some applications this distortion may be outside the limits speci~ied by the telephone administration.
The object of the present invention is to provide a gain regulation circuit whereby a smooth and continuous qain variation between predefined limits in response to a control signal may be effected.
According to the invention there is provided a signal amplifier element having a controllable gain and comprising two or more transistor long tailed pairs, wherein the transistors of said pairs are so constructed that the maxima of the signal/gain charac~eristics of said pairs are symmetrically disposed about the signal ~ero level, and wherein the signal/gain characteristic of all the pairs acting in combination includes a substantially constant region.
According to another object of the invention there is provided a gain regulator and signal amplifier circuit e g. for an electronic telephone subset, the circuit comprising a first long tailed pair of transistors having substantially identical characteristics, an~ 2n further lon~ tailed pairs of transistors, where n is an integer including unity, wherein corresponding transistors of the 2n further pairs have emitter areas in the ratio l a; a : l; where a lies between zero and unity, whereby the gain maxima oE the characteristics corresponding to the further long taile~ pair are symmetrically disposed about the signal zero so as to provide together a substantially constant gain region of sigllificantly lower gain than the gain maxima of the first long tailed pair, and wherein tl~e circuit includes control means ~ ereby weigllted cont~ibutions to the circuit gain characteristic may be provide~ from the balanced pair and from the 2n unbalanced pairs so as to provide a stage gain adjustable between limits defined by ~he gain of the ~alanced pair and the gain of the unbalanced pairs. ~le have found that by providing an emitter area mismatch between the transistors of a long tailed pair the maxima of the signal/gain characteristic is off-set from the signal zero by a voltage ~ such that V = ~ t log x q where k is Boltzman's constant, t is the absolute terperature, q is the electronic charge and x is the ratio of er~litter areas. By combining two or more suitably off-set long tailed pairs with a further balanced pair a composite characteristic ha~ing a gain smoothly adjustable between two defined gain limits is obtained. ~he term gain as ernployed herein is understood to include values of less than unity..
Embodiments of the invention will now be described with reference to the accompanying drawings in which -Fig. 1 illustrates the signal/gaincharacteristic of a conventional balancecl tr~nsistor long tailed pair;
Fig. 2 shows an amplifier element comprising two long tailed transistor pairs provided with emitter area inbalance;
Fig. 3 illustrates the signal/gain characteristic of the circuit of Fig. 2;
Fig. 4 illustrates the extension of the characteristic offset technique to three or more pairs;
Fig. 5 shows a telephone receiver gain regulatioll circuit embodying the techniques o~ Figs. l ... . . _ _ . . ... ... .. .
and 4;
and Fig. 6 illustra~es the gain characteristics of the circuit of Fig . 5 .
Referring to Fig. l, the signal/gain characteristic o a conventional transistor long tailed pair is sho~n.
As will be well known to those skilled in the art the gain g of a balanced, i.e. a symmetrical long tailed pair is defined by g = q I sech q Vin 4 kt 2 kt where q is the electronic charge, I is the tail current of the pair, k is Boltzman's constantl t iS the absolu e temperature and Vin is the instantaneous input signal level. As can be seen the characteristic has the ap~earance of a somewha~ distorted inverted ~ and it will thus be apparent that low distortion amplificatiol1 is achieved only for a small input signal voltage s~ins.
For small input signals the circuit has substantially unit gain.
In the circuit shown in Fig. 2 two long tailed pairs TR2l,TR24 and TR22,TR23 are employed. The transistors of the two pairs are designed such that their emitter areas are in the ratio l : a and a : l where a is a number between zero and unity. This offsets the gain maxima of the two pairs to opposite sides of the input signal zero level as shown in Fig. 3. The voltage separation V between the two maxima is given by the equation V = 2 kt lo9 a q where k is Boltzman's constant, t is the absolute temperature and q is the electronic charge. The resultant gain characteristic of the two pairs is shown by the dashed line in Fig. 3. ~1ith a suitable choice of the area ratio a, typically froml to l , the characteristic has a substan':ially constant region of ... . . , ... . . . . . _ _ _ _, .. ... . . . .
gain a, less than unity, extending V on either side o~ the signal zero. This considerably enhances the low distortion signal handling capability of the circuit as compared to a conventional single long tailed pair amplifier. In this cir-cuit, gain has been traded for signal handling capability.
The technique of Figures 1, 2 and 3 can be combined as shown in Fiyures 4 and 5. Figure 4 illustrates the gain charac-terlstics of a circuit comprising three long tailed pairs wherein the respective emitter area ratios of the pairs of transistors are 1 :a; 1 : 1 and a : 1. As can be seen from Figure 4 the circuit can be set in a high (unit) gain condi-tion wherein the balanced long tailed pair acts as the major amplifying element, or to a low ~a~ gain condition wherein the unbalanced long tailed pairs act as the major amplifying ele-ment. Weighted combinations of these two states can be emp-loyed to provide any gain value between these limits. In the same way the technique can be extended to the use of five, or in general (2n + 1), long tailed pairs, i.e. one balanced pair and 2n unbalanced pairs. It will of course be clear that in general that in any applica-tion the final design will be a trade ofE between lineari-ty and circuit complexi-ty. The ratio 1 : a is increased for each subsequent pair.
Al-though the -techniques have been described in terms oE discrete transistors it is, in many applica-tions, advan-tageous to replace the individual pairs of -transistors by a single pair of multi-emitter transistors, each pair of emitters corresponding -to one long tailed pair.
~ n application of the techniques described herein is shown in Fiyure 5 of the accompanying drawings which is a cir-~0 cuit diagram of a gain regulation circuit stage e.g. for thereceiver speech path of an electronic telephone subse-t. The circuit output is coupled to the line via a further linear amplifier stage (not shown). In order to comply with the design specifications of most telephone administrations, it is necessary -to provide some means of gain control to compensate for the range of different line loop lengths between the exchange and the subscribers. Typically, the gain must be variable between two limits which represent -the 'best case' and 'worst case' loop lengths. The gain must be continuously and smoothly variable between these limits. A circuit which satisfies these constraints is shown in Fi~ure 5.
Referring to Figure 5, the gain regulation circuit provides an accurately defined gain of any value between first and second predetermined levels. The circuit comprises first and second multi-emitter transistors TR51 and TR52 arranged in a multiple long-tailed pair configuration. Corresponding pairs of emitters ElA, E2A; ElB, E2~; ElC; E2C are coupled each to a corresponding current source I1, I2, I3 arranged in the 'tail circuit' of the pair. The transistor collector loads may be provided by forward biased diodes Dl and D2, which pro-vide temperature compensation of the circuit.
As is ]cnown to those skilled in the art, -the imped-ance R oE a diode is given by the expression;
R = kt qI
where ]c is Boltzman's constant, t is the absolute temperature, is the electronic charge and I is the current in absolute units. It will be noted that this impedance expression is the tempera-ture dependent term of the gain expression of equation (1) above.
Thus, by providing diode loads in the collector cir-cuits of -the long tailed pair transistors a very significan~
degree of temperature compensation is provided. This compen-sation is sufficient to provide substantially temperature in-dependent operation throughout the ambient temperature range specified by the various telephone administrations.
The transistors TR51 and TR52 are fabricated such that the first emitters ElA and E2A are of substantially equal area, i.e. -they are capable of carrying substantially equal currents.
The second pair of emitters Els, E2B have areas in the ratio 1 : a and the third pair ElC, E2C have areas in the ratio a : 1, where a is an arbitrary fraction between zero and unity. Such a structure has the property that, in the absence of an input signal, the currents flowing through the respective pairs of emitters are in the ratio 1 ~ a and a : 1.
The circuit has two gain limits (Figure 4) of unity and a and is adjustable to any value between these limits. The ratio 1 : _ is equal to the ratio of the receiver gain value limits specified for the receiver gain value limits specified by the telephone administration. This ensures that the over-all gain of the receiver channel can be set to any value within these limits.
In use, the arrangement may provide a gain regula-tion feedback loop for an amplifier whereby speech signals are ou-t-put to the line. The bases of the transistors TR51 and TR52 are connected respectively to the speech signal and to a fixed potential. The emitter circui-ts are fed, via a current ampli-Eier (not shown) with currents corresponding to the line vol-tage. It will be appreciated that this line voltage is inversely proportional -to the subscriber loop impedance. In use, the line impedance is determined from the line voltage and corres-ponding currents are then fed to the rail circuits oE the longtalled pairs to provide a corresponding gain value.
-7a~
The gain condition of the circuit is determined by the weighted contributions of the balanced and ~V~
.
unbalanced pairs in the composite output charac~eristic.
By increasing or decreasing currents Il, I2, I3 fed into the tail circuit of the transistor pairs the contribution of each pair can be correspondingly reduce~
or increa.sed. This provides a smooth transfer, as shown in Fig~ 6, frorl a unit gain condition ~herein the balanced pair provides the major contribution to the output sigllal to a low (a) gain condition ~here the unbalanced pairs handle the major portion of the signal and the contribution of the balallced ~air is reduced su~stantially to zero. By suitable control of the currents Il, I2, I3 the circuit may be set to any gain val~e bet~een these t~o limit conditions.
rhe arrangement is equivalent to a ~lurality or lonc-tailed pairs arranged in paralle], the no-signal balance currents of each pair being defined by the emitter area ratio of the pair.
Advantageously the arrangemenrs described herein may be fabricated in integrated circuit form.
This invention relates to electronic amplifier circuits navinq a regulatable gain, and ir. particular to a gain regulation circuit for use in a telephone instrument anci whereby the gain of the instrumerit speech paths may ~e adjusted e.g. for matching the receiver gain to the line loop impedance.
An electronic telephone lnstrumen~ includes an amplifying speech path whereby speech signals are relaye~ from the instrument microphone to the line and fro~n ~he iine to the inStrument receiver. I~ ~.7ill be appreciated tha~ for optimum performance of the instrument the receiver and transniitter speech paths must each include some means of gain regulation to prevent overloading and to provide matchiny of the receiver gain ;:o the line impedarlce~ The line or loop impedance is in general proportional to the length of the subscriber loop between the instrumen~ and rhe exchange and can thus have any value wi~hin a clearly defined range. Because it is necessary to cater for a wide variation of loop length, it is essential that the receiver circuit of the subscriber's instrument incorporates provision for line length compensation. To compensate loop length variations many telephone administrations require the provision of receiver circuits that can be set to a gain figure anywhere between ~pper and lower preset limits.
Furthermore, in order to prevent overloading and consequent saturation of the transmitter output state to the line it is necessary to provide some form of gain control whereby a speecll si~lnal waveform Iriay be limi~ed in arplitude. This technique comlilo~ ;no~1n a ~,`' soft clippinq is described in co-pending Canadian patent application Serial No. 422,785 of P.F. Blomley, filed March 3, 19~3.
A particularly useful variable gain element is the transistor long tailed pair the gain of which can be determined by controlling the common emitter current of the pair. ~he use of a single long tailed pair is however somewhat restricted by its significantly non linear signal/gain characteristic which gives rise to distortion Eor all but very low signal levels. In some applications this distortion may be outside the limits speci~ied by the telephone administration.
The object of the present invention is to provide a gain regulation circuit whereby a smooth and continuous qain variation between predefined limits in response to a control signal may be effected.
According to the invention there is provided a signal amplifier element having a controllable gain and comprising two or more transistor long tailed pairs, wherein the transistors of said pairs are so constructed that the maxima of the signal/gain charac~eristics of said pairs are symmetrically disposed about the signal ~ero level, and wherein the signal/gain characteristic of all the pairs acting in combination includes a substantially constant region.
According to another object of the invention there is provided a gain regulator and signal amplifier circuit e g. for an electronic telephone subset, the circuit comprising a first long tailed pair of transistors having substantially identical characteristics, an~ 2n further lon~ tailed pairs of transistors, where n is an integer including unity, wherein corresponding transistors of the 2n further pairs have emitter areas in the ratio l a; a : l; where a lies between zero and unity, whereby the gain maxima oE the characteristics corresponding to the further long taile~ pair are symmetrically disposed about the signal zero so as to provide together a substantially constant gain region of sigllificantly lower gain than the gain maxima of the first long tailed pair, and wherein tl~e circuit includes control means ~ ereby weigllted cont~ibutions to the circuit gain characteristic may be provide~ from the balanced pair and from the 2n unbalanced pairs so as to provide a stage gain adjustable between limits defined by ~he gain of the ~alanced pair and the gain of the unbalanced pairs. ~le have found that by providing an emitter area mismatch between the transistors of a long tailed pair the maxima of the signal/gain characteristic is off-set from the signal zero by a voltage ~ such that V = ~ t log x q where k is Boltzman's constant, t is the absolute terperature, q is the electronic charge and x is the ratio of er~litter areas. By combining two or more suitably off-set long tailed pairs with a further balanced pair a composite characteristic ha~ing a gain smoothly adjustable between two defined gain limits is obtained. ~he term gain as ernployed herein is understood to include values of less than unity..
Embodiments of the invention will now be described with reference to the accompanying drawings in which -Fig. 1 illustrates the signal/gaincharacteristic of a conventional balancecl tr~nsistor long tailed pair;
Fig. 2 shows an amplifier element comprising two long tailed transistor pairs provided with emitter area inbalance;
Fig. 3 illustrates the signal/gain characteristic of the circuit of Fig. 2;
Fig. 4 illustrates the extension of the characteristic offset technique to three or more pairs;
Fig. 5 shows a telephone receiver gain regulatioll circuit embodying the techniques o~ Figs. l ... . . _ _ . . ... ... .. .
and 4;
and Fig. 6 illustra~es the gain characteristics of the circuit of Fig . 5 .
Referring to Fig. l, the signal/gain characteristic o a conventional transistor long tailed pair is sho~n.
As will be well known to those skilled in the art the gain g of a balanced, i.e. a symmetrical long tailed pair is defined by g = q I sech q Vin 4 kt 2 kt where q is the electronic charge, I is the tail current of the pair, k is Boltzman's constantl t iS the absolu e temperature and Vin is the instantaneous input signal level. As can be seen the characteristic has the ap~earance of a somewha~ distorted inverted ~ and it will thus be apparent that low distortion amplificatiol1 is achieved only for a small input signal voltage s~ins.
For small input signals the circuit has substantially unit gain.
In the circuit shown in Fig. 2 two long tailed pairs TR2l,TR24 and TR22,TR23 are employed. The transistors of the two pairs are designed such that their emitter areas are in the ratio l : a and a : l where a is a number between zero and unity. This offsets the gain maxima of the two pairs to opposite sides of the input signal zero level as shown in Fig. 3. The voltage separation V between the two maxima is given by the equation V = 2 kt lo9 a q where k is Boltzman's constant, t is the absolute temperature and q is the electronic charge. The resultant gain characteristic of the two pairs is shown by the dashed line in Fig. 3. ~1ith a suitable choice of the area ratio a, typically froml to l , the characteristic has a substan':ially constant region of ... . . , ... . . . . . _ _ _ _, .. ... . . . .
gain a, less than unity, extending V on either side o~ the signal zero. This considerably enhances the low distortion signal handling capability of the circuit as compared to a conventional single long tailed pair amplifier. In this cir-cuit, gain has been traded for signal handling capability.
The technique of Figures 1, 2 and 3 can be combined as shown in Fiyures 4 and 5. Figure 4 illustrates the gain charac-terlstics of a circuit comprising three long tailed pairs wherein the respective emitter area ratios of the pairs of transistors are 1 :a; 1 : 1 and a : 1. As can be seen from Figure 4 the circuit can be set in a high (unit) gain condi-tion wherein the balanced long tailed pair acts as the major amplifying element, or to a low ~a~ gain condition wherein the unbalanced long tailed pairs act as the major amplifying ele-ment. Weighted combinations of these two states can be emp-loyed to provide any gain value between these limits. In the same way the technique can be extended to the use of five, or in general (2n + 1), long tailed pairs, i.e. one balanced pair and 2n unbalanced pairs. It will of course be clear that in general that in any applica-tion the final design will be a trade ofE between lineari-ty and circuit complexi-ty. The ratio 1 : a is increased for each subsequent pair.
Al-though the -techniques have been described in terms oE discrete transistors it is, in many applica-tions, advan-tageous to replace the individual pairs of -transistors by a single pair of multi-emitter transistors, each pair of emitters corresponding -to one long tailed pair.
~ n application of the techniques described herein is shown in Fiyure 5 of the accompanying drawings which is a cir-~0 cuit diagram of a gain regulation circuit stage e.g. for thereceiver speech path of an electronic telephone subse-t. The circuit output is coupled to the line via a further linear amplifier stage (not shown). In order to comply with the design specifications of most telephone administrations, it is necessary -to provide some means of gain control to compensate for the range of different line loop lengths between the exchange and the subscribers. Typically, the gain must be variable between two limits which represent -the 'best case' and 'worst case' loop lengths. The gain must be continuously and smoothly variable between these limits. A circuit which satisfies these constraints is shown in Fi~ure 5.
Referring to Figure 5, the gain regulation circuit provides an accurately defined gain of any value between first and second predetermined levels. The circuit comprises first and second multi-emitter transistors TR51 and TR52 arranged in a multiple long-tailed pair configuration. Corresponding pairs of emitters ElA, E2A; ElB, E2~; ElC; E2C are coupled each to a corresponding current source I1, I2, I3 arranged in the 'tail circuit' of the pair. The transistor collector loads may be provided by forward biased diodes Dl and D2, which pro-vide temperature compensation of the circuit.
As is ]cnown to those skilled in the art, -the imped-ance R oE a diode is given by the expression;
R = kt qI
where ]c is Boltzman's constant, t is the absolute temperature, is the electronic charge and I is the current in absolute units. It will be noted that this impedance expression is the tempera-ture dependent term of the gain expression of equation (1) above.
Thus, by providing diode loads in the collector cir-cuits of -the long tailed pair transistors a very significan~
degree of temperature compensation is provided. This compen-sation is sufficient to provide substantially temperature in-dependent operation throughout the ambient temperature range specified by the various telephone administrations.
The transistors TR51 and TR52 are fabricated such that the first emitters ElA and E2A are of substantially equal area, i.e. -they are capable of carrying substantially equal currents.
The second pair of emitters Els, E2B have areas in the ratio 1 : a and the third pair ElC, E2C have areas in the ratio a : 1, where a is an arbitrary fraction between zero and unity. Such a structure has the property that, in the absence of an input signal, the currents flowing through the respective pairs of emitters are in the ratio 1 ~ a and a : 1.
The circuit has two gain limits (Figure 4) of unity and a and is adjustable to any value between these limits. The ratio 1 : _ is equal to the ratio of the receiver gain value limits specified for the receiver gain value limits specified by the telephone administration. This ensures that the over-all gain of the receiver channel can be set to any value within these limits.
In use, the arrangement may provide a gain regula-tion feedback loop for an amplifier whereby speech signals are ou-t-put to the line. The bases of the transistors TR51 and TR52 are connected respectively to the speech signal and to a fixed potential. The emitter circui-ts are fed, via a current ampli-Eier (not shown) with currents corresponding to the line vol-tage. It will be appreciated that this line voltage is inversely proportional -to the subscriber loop impedance. In use, the line impedance is determined from the line voltage and corres-ponding currents are then fed to the rail circuits oE the longtalled pairs to provide a corresponding gain value.
-7a~
The gain condition of the circuit is determined by the weighted contributions of the balanced and ~V~
.
unbalanced pairs in the composite output charac~eristic.
By increasing or decreasing currents Il, I2, I3 fed into the tail circuit of the transistor pairs the contribution of each pair can be correspondingly reduce~
or increa.sed. This provides a smooth transfer, as shown in Fig~ 6, frorl a unit gain condition ~herein the balanced pair provides the major contribution to the output sigllal to a low (a) gain condition ~here the unbalanced pairs handle the major portion of the signal and the contribution of the balallced ~air is reduced su~stantially to zero. By suitable control of the currents Il, I2, I3 the circuit may be set to any gain val~e bet~een these t~o limit conditions.
rhe arrangement is equivalent to a ~lurality or lonc-tailed pairs arranged in paralle], the no-signal balance currents of each pair being defined by the emitter area ratio of the pair.
Advantageously the arrangemenrs described herein may be fabricated in integrated circuit form.
Claims (14)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A gain regulator and signal amplifier circuit e.g.
for an electronic telephone subset, the circuit comprising a first long tailed pair of transistors having substantially identical characteristics, and 2n further long tailed pairs of transistors, where n is an integer including unity, wherein corresponding transistors of the 2n further pairs have emitter areas in the ratio 1 : a; a : 1; where a lies between zero and unity, whereby the gain maxima of the characteristics corresponding to the further long tailed pair are symmetrically disposed about the signal zero so as to provide together a substantially constant gain region of significantly lower gain than the gain maxima of the first long tailed pair, and wherein the circuit includes control means whereby weighted contributions to the circuit gain characteristic may be provided from the balanced pair and from the 2n unbalanced pairs so as to provide a stage gain adjustable between limits defined by the gain of the balanced pair and the gain of the unbalanced pairs.
for an electronic telephone subset, the circuit comprising a first long tailed pair of transistors having substantially identical characteristics, and 2n further long tailed pairs of transistors, where n is an integer including unity, wherein corresponding transistors of the 2n further pairs have emitter areas in the ratio 1 : a; a : 1; where a lies between zero and unity, whereby the gain maxima of the characteristics corresponding to the further long tailed pair are symmetrically disposed about the signal zero so as to provide together a substantially constant gain region of significantly lower gain than the gain maxima of the first long tailed pair, and wherein the circuit includes control means whereby weighted contributions to the circuit gain characteristic may be provided from the balanced pair and from the 2n unbalanced pairs so as to provide a stage gain adjustable between limits defined by the gain of the balanced pair and the gain of the unbalanced pairs.
2. A circuit as claimed in claim 1, wherein said control means includes means for sensing a telephone line impedance and for generating control signals corresponding to said impedance.
3. A circuit as claimed in claim 1 or 2, wherein said control signals comprise currents fed into the emitters of said long tailed pairs.
4. A circuit as claimed in claim 1 or 2, wherein said long tailed pairs are provided by two multi-emitter transistors.
5. A circuit as claimed in claim 1 or 2, wherein each transistor collector is provided with a forward biased diode load whereby temperature compensation of the circuit is effected.
6. A signal amplifier element having a controllable gain and comprising two or more transistor long tailed pairs, wherein the maxima of the signal/gain characteristics of said pairs are symmetrically disposed about the signal zero level, and wherein the signal/gain characteristic of all the pairs acting in combination includes a substantially constant region.
7. A signal amplifier element as claimed in claim 6, wherein each transistor of at least two said pairs are provided with a respective emitter area mismatch whereby their gain maxima are displaced from the signal zero.
8. A signal amplifier element as claimed in claim 6 or 7, wherein the transistors has a collector load comprising a forward biased diode.
9. An integrated circuit incorporating a gain regulator and signal amplifier circuit as claimed in claim 1 or 2.
10. A telephone subset provided with a circuit as claimed in claim 1 or 2.
11. An integrated circuit incorporating one or more signal amplifier elements as claimed in claim 6 or 7.
12. A telephone subset provided with a signal amplifier element as claimed in claim 6 or 7.
13. A gain regulator and signal amplifier circuit for an electronic telephone subset, said circuit comprising a first long tailed pair of transistors having substantially identi-cal characteristics, and 2n further long tailed pairs of tran-sistors, where n is an integer including unity, wherein cor-responding transistors of said 2n further pairs have emitter areas in the ratio 1:a, a:1, where a lies between zero and unity, whereby gain maxima of gain characteristics correspon-ding to said 2n further pairs are symmetrically disposed about signal zero of a circuit gain characteristic so as to provide together said circuit gain characteristic having a substan-tially constant gain region of significantly lower gain than gain maxima of said first long tailed pair, and wherein said circuit further includes control means coupled to emitters of said first pair and said 2n further pairs whereby weighted contributions to said circuit gain characteristic may be pro-vided for said first long tailed pair and from said 2n further pairs so as to provide a stage gain adjustable between limits defined by the gain of said first pair and the gain of said 2n further pairs.
14. A signal amplifier having a controllable gain and comprising a plurality of transistor long tailed pairs having gain control means coupled to their emitters, wherein the maxima of the signal/gain characteristics of said pairs are symmet-rically disposed about the signal zero level of an overall amplifier signal/gain characteristic, and wherein said overall signal/gain characteristic includes a substantially constant region due to said plurality of pairs acting in combination.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8200070A GB2090845B (en) | 1981-01-05 | 1982-01-04 | Silicone adhesive formulations |
| GB82/00070 | 1982-03-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1200941A true CA1200941A (en) | 1986-02-18 |
Family
ID=10527413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000422784A Expired CA1200941A (en) | 1982-01-04 | 1983-03-03 | Gain regulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1200941A (en) |
-
1983
- 1983-03-03 CA CA000422784A patent/CA1200941A/en not_active Expired
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