CA1199966A - Power inverter - Google Patents

Abstract

ABSTRACT OF DISCLOSURE
A method and apparatus are provided for an improved power inverter circuit, including a separate starting inverter having an A.C. output applied across a load prior to energizing the main inverter, and driven by a series of repeating gating signals. On achieving a preselected load condition, the starting inverter is removed from the circuit and the main power inverter is energized.

Description

IMPROVED POWER INVERTER
Di~olo~ure The pre~en~: invenkion rela~es to he ar~ of ~nduc~ion heat-ing ~nd more particularly ~o an iL~roved power inver~er and me~h-od of vpera~ing th~ ~ame for u6e in an induction heating or ~imilar environmen'c .

The presen~ invention relates to an improved inverter and m~thod ~f operating the same. For ~he purpose of background in-fonnation, the following United S~ate~ Letters Paten~smay be referred to 3, 506, 907; 3, 599, 078; 3, 657, 634;
3,718,852; 3,725,770; 3,757,197; b"039,926; and 4,195,233.
Background oX I~vention l~e invention rela~ces ~o inver~ers in general and more par~
ticularly to an inverter for induction heating. Such an inverter ~upplies high frequency alternating current to ~he induc~ion heat-ing coil which forms a tank cireui~ that has varying electricalcharacterl~tics ~ccording to the mffterial and size of the work~
piece andthe ~emperature of the workpiece be~ng heated. The load in the induction he~ting ins~allation has an inductive component, a capacltl~Je component and a resistive component. Consequently, it is su~ceptible to frequency changes and presents a load th~t varies drastically. In recent years, ~here ha~ been a su~stan-tial am~unt of work devoted ~o the developmen~ of a hig~ power solid~tate power supply for driving ~n ~nductio~ heating load.
Such devices generally convert D.C. current to an alternating curren~ which flows through ~he load. One o the m~t common of ~hese devices i~ a solid-~ate inverter having a cons~ant current ~upplied rom a D.C. ~ource, which curren~ is alternately ~witched through ~he load in different direction~ by two distinct ~e~ of ~wltching devices, ~enerally SCR's. This type of solid-state device has been used in tandem with a power rectifier wh~ch con-Yerts available ~hree phase altern~ing current into D.C. current.
Thi5 D.C. current 1~ ~hen directed to the inverter which changes the d$rect current into a ~in~le phase ~lternat~ng current of a controllable high frequency. Frequency o the inverter 1~ con-trolled by the rate at which gating ~ignal~ ~re provlded to he ,. .

g~

SCR's. One form of such inverters is a parallel-com:pensa~ed in-verter which is at~ached to ~ cons~ant ::urrent ~ource and is well known in the induction heating art.
In order for ~che SCR' s to be . eomnsutated to the OFF condition, 5 it ls necessary to apply a reverse voltage arross the ind~vidual SCR's for a 'cime whieh i3 rcferred to as .the turn-off time of thQ SCR' ,c or ~ther ~witching devices . This ~witching time varies ac-~ording to ~he particular type of switchlng device used. A~ ~he fre~quency increa.~es, there is 12SS ~cime available for commutating 10 the individual switching device~ or SCR' s . Consequently, wlth high frequency inverl:ers of 1.0 KHertz and higher, relatively precise switching devi es are required. Such devi~es are ex-pensive. Indeed, comrnercial SCRs ean not exceed a preselected high frequency when a large margin of 6afe~y 15 pro~ided to assure 15 turn-off ~ime. Thus, as in~rert~rs of the type descrlbed above are used for high frequency heating" generally required in in-duction heRting, t:he SCR' s be~ome expensive ~nd there i5 a rel~-~ively low maximun~ frequency to be obtained without modiying ~che well lcnown inver~er circuits. For this reason, controlling ~he 20 ga~cinE; lpulses or gatinE~ signal~ for ~he SCR's has been ~che gub~ect of sub~tantial de~elopm~ntal work. Gating is generally controlled by monitor~ng the phase relatlonship of the vol~age and currPn~
through the load and then ad~u~ting thiæ relationship ~o that s1lf-ficient turn-off time is assured. This concept limits the versa-25 tility of ~che inver'cer, rlecessitates expensive SCR' 8, requiresan expensive chok~ t~ assure contiTIuous current flow and generally complicates the inver~er c~ rcuit it~Plf .
l~other disadvantage of power inverter~, which is especially serious when used for wide1y varying loads, is that such inverter 30 for supplyislg an :Lnduc~ion load is difficul to s~ar~c. It i6 u~ually impossible ~o start the inverter by merely pro~7iding ga~ng pul~e~ to the SCR's in the inverter in a manner similar to the staady s~ate cond~ tion. At star up, 1:here is no energy in che tuned load for commutatinK ~he thyri tors or SCR' ~ . This ~tarting 35 problem is further compounded when the load ls ~paced from ~he inverter so that subs~antial inductance is created by connect-ing leads between ~he inverter and the load. Becau~e of these difficulties, a substanflal amount of work has been devoted to providing an arrangement for ~tartlng a pow r inverter u~ed in 5 the lnduction heating art, Circuits have ~een ~ugge~ted for causing initlal current oscillation ~hrough the load during the starting cycle. Some circui~s involve ~witching of speci~l capacitors ~cross the lo~d. Circuit~ have been provided to initially charge the t~ned load to bulld up o~cillation~ ln the load before the gating of the inverter is star ed. S~nce this starting concept requires ma~ching of ~n auxiliary circuit with ~he characteristics of the load, such concept could not be used for a wide range of load conditions. The most ~idely adopted ~on-cept ls the provision of a sm~othing induc~or or reactor between the input D.C. ~upply and the thyristor~ or SCR's of ~he inverter.
A precharging current ls then direc~ed through the inverter into the tuned load to shock the load in~o oscillations when ~h~ SCX's are gated. This technique required a relatively large reactor between the rectifier and ~nverter whi h i~ expensive and ~ub-Rtantially adds to the ~ost of the deYice. In additlon, the characteristics of the load negated th~s eoncept ac an effect~ve means for allowing s~ar~-up of a power inverter of the type used in induction heating.
The Invention

2~ The disadvantages discussed above and others are overcome by the present lnven~ion which is directed to an improved ~nvert2r of the type ~hat can be opera~ed substantially above 1,000 ~ertz and can be used for widely varying loads, a~ experienced in lnduo-tion hea~ing.
In accordance with the pre~ent invention there ~5 provided an improvemen~ in a power inverter for converting a D.C. current into an altern~ting current having a frequency controlled by the rate a~ which a series of gatlng signal3 are created, this inverter include~ control means for selectively energizing the power inverter, a first branch to be connected acros~ a load, a second branch to be cormected ~cross the load, first switchirlg mearls ~or applying ~ vo:ltage of a first polarity across the load by the first branch, second ~witching means for ~pplylng a vol~age of a econd pt>larity across the load by the secund branch and means or 5 alte~ately operating ~he firs~ a~d ~econd switching means by ~che series of gating signals. The improvement i~ the provision of a 8 tarting inverter ~asTing a D. C . input and arl A. C . output with a frequency controlled by a ~eries of repeatin~ gating commands.
~n arrangemen~c or selectively applying the A. C. output of the 10 starting inverter across the lo~d 1~ provided so that means re-sponsive to the existence of a given condition across the load can be used for energizing the main power inverter and de-energiz-ing the auxlliary ~tartin~; inverter. In practice, a cons~ant curren~ source i~ directed to the inverter; ~cherefore, the swi~ch-15 ing device~ actually apply ~ fixed current in aleernate dire~-tions across the load; however, this switching-action has the effect of creat~ng a voltage acro~s ~he load as deflned in the general ~tatement of the present invention. By employing this invention, the ~eparate and distinct ~tarting inverter may be relatively inexpensive and ean ~e u~ed separately to activate the main inverter duri~g the initlal, or ~tart-up condition.
In accordance with thi~ a~peet of ~he ~nvention, the frequency of ~he gating eommands used in the ~tarting inverter are eon-trolled to produre generally unity power factor a~ross ~he load. Thus, ~he auxiliary starting inverter itself can be a ~eparate and distinct electrieal device having rela~ivPly ~mall componen~s lntended to drive the load at its resonan~ frequency.
A variety o arrangements could be incorporated or creating this unity power factor for the auxiliary inver~er; however9 ~n accord-ance with ano~her aspec~ of the inventlon, generally standard loadvolt~ge and load current ~ensing circuits, ~uch a~ tho~e shown in patent No. 3,718,852, are employed f~r adiusting the frequency o the starting inverter to the re~onant freq~ency of the load.
This ~ ac~omplished by shifting the time di~plaeement o e~ther the load curr~nt or load voltage by ~ubstantially 90. Then the twc) waves are multiplied toge~cher. This produces a signal which is generally zero at unity power factor. This produced signal is used to consrol 'chP frequency or the gatin% command in th2 ~tarting lnverter to adjust khe frequency o the ~ arting in-5 vert~r to the resonant frequency o:E the load. Thus, irrespectiveo the load conditions 9 the ~tarting inYerter operates at unity power actor. Ater unity power actor has beerl reached, the main inverter is turned on by adjusting the input reetiier or otherwise. This can be done by sensing the pealc v~lue of the 10 load voltage or by waiting for a 8elected time, which can be de-:Eined as the 6tarting cycle ~cime. Thus, af~cer the starting in-verter has actuated the load at a unity -power factor, the main inver~er i8 actuated. Nearly contemporaneously ~herewi~h, ~he starting inverter i~ disconnected from ~he load. As is well known, 15 the phsse ~rlgle of ~he rectifier can be adjusted to increa~e the current to the main inverter. The starting inverter is proportioned 80 that it i~ 2pproximately 5% of the nominal power generated by ~he main inverter during the heating opera~ion. Consequen~ly, the inverter is relatively small, can use ~nexpensive SCR's 2Q and need not be proportioned to have high power components.
In accordance with another aspect ~f the inven~ion, there is provided an improved inverter of the ~ype defined abo~e, w~ich in~erter ineludes means for providing cloeklng pulses wi~h a known frequency, means for sensing a wave transfer between ad-~acent segments of the line ~oltage at the start of a particularsegment, i.e. a zero crossing, means for counting the pul~e~ dur-in~ ~he particular ~egmen~ to produce a control coun~ for a successive ~e~ment, mean3 for subtrac~ing from the con~rol ~oun~
a selected number to produce a gating number for the ~uccessive segme~t of the voltage wave, me~ns for counting the pU15eS during ~he successlve wave segment un~il reaching the gating number and means for creating a gatlng pulse when the gating number is rea hed durin~ a succe~sive voltage wave 3egment. In aceordance with ~his ~spect of the inventioa, the firing position in a given oscilla-

3~ ~ion of the load vol~age is con~rolled by the immediately previousoscillation or segmen~. In practice, this is the adjacent previous - 6 ~

o cillation or wave segment. Thus, the gating of the main $nverter is ~cco~lished on a real time ba~is. The coneep~ can lbe per-ormed digitally. As indica~ed, only the load voltage wa~e i8 required ~o determine the gating ~ignal time for the SCR' ~ or 5 thyristors in the main inverter. Irhere i~ no need to monitor the load currerlt for the purpo~e of controlling power fac1:or to assist in maintaining proper turn off time for the ~rarious SCR'~. By using this gating or trigger concept, wi~h or without: ~che ~tartlng inverter concept, ~he choke or reac~or betwee}l the rectifi~r and 10 khe main inverter can be reduced in ~ize and cost. The inver'cer using thi~ trigger concept can operate even with ~ discontinuous current condition at the input of the inver~cers. This greatly ~implifies the ~peration of the inYer~er and prevents turn-off and damage to the lnverters cau~ed by discontinuDus eurrent opera-15 ~ion and harmonic~ whi~-h can create false zero-rrossing point~ for ~che load curren~ wave.
In accordance with the above a~pect of the invention, ~he gating pulses c~n be created in an analog circui~. Corlseqllently, ~his aspec~ of the lnvention carl be defined broadly as a cirruit 20 for creating repetitive gating signals for the ~witching devii ces of a D.C. ~co A.C. power inverter, which gating signals are created in timed rela~ionship with respect to ~che load volta~e wave havlng alternate positive and negati~Je ~egments and direc~ced across a load.
The circui~ ln ac~ordance with this broad aspec~ of the invention 25 includes means for establ:Lshin~ a reference tlme e~hen the voltage transfers between al~cernate wave ~egments and means for cre ting a gating Rignal a preselected time after this reference time. Thi~
can be done digita:Lly or in arl nalog fa~hion.
The primary obj ect of the present invention is the provision 30 of an ~mproved ~olid-~tate power inverter and method of oper2ting the ~ame, which lmproved inverter and me'chod can ~e used in in-duc~ion heatlng and can be operated over a wide variation o fre-quencie~ .
A fur~her ob~ ect of the pre~ent insrention 1~ the provi~ion 35 of an in~rerter and method, as de~ined abo~e, which lnverter and ~ 7 --method can be operated at high frequencies, exceedin~3 1. 0 to 10. 0 K HPrtz.
Still a further ob~ect of 'che pres~nt in~ention 1~ the provision of an inverter and method, ~s defined above, w~ich inverter and me~hod can use relat~vely inexperlslve thyristors or SCR' ~ and can use a relatively inexperlsive connecting choke or reactor between ~che ourrent s~plying rec~ifier and the in-verter it~elf.
Ano~her obJec~ o:t' the presen~ inverl~ion is the provision of an inverter and method, as defined above, whi h in~rer~er and method employ only the load voltage wave for controlllng ~he ~ir-ing or tri~gering ~im~ for gating ~he S~R' s or thyristors .
Still an~ther obj ec~ of the presen~l: inven~ion is the provision of an inverter and method, as de:E~ned above, whieh inverter and 1~ method can employ a small~r reac~or or cholce between the current supplying rectifier and the power in~erter.
Yet another obj ec~ of the invention is the provislon of an inverter and method, as defined above, which inverter and method employ a separate and distinct starting inverter starting the main power inverter.
Still another object of the present i~vention is the provi~ion of an inverter aIld method, as defined above, which lTIverter and method can be ~tarted by a relatively inexpensive circuit which is connected across the load itself tt) create unity pc~wer factor cur-rent flow in the load for the starting opera~cion.
Another ob~ect of the present invention is the provision of an inverter and method, as defined above, which inverter and method control~; trigger or gating times ~ased upon an immediately previous 3wing of the load voltage. This can be done digitally and allows for accurate corl~rQl of the ga~ing time based upon current operat-ing conditions of the inverter. Thc commu~ating time of the various SCR'~ can be assured without large buil~ in safety factors. A1BO~
it i8 not necessary to control ~he power fac or to assure the necessary commutatlng time even a'c high ~requen-~ies.
. ` 35 Ye~ a fur~her ob~ ect of the pre~ent invention is the provi~ion o~ a power inverter ~nd me~hod a~ defirled abotre, which power inverter and method can :function over a wide variatlon ~n power fac~cor and ev n during discontinuous current cond~tions.
These and o~her obj erts and advant~ge~ will become ap~
parent from ~he following descrlption taken together with ~he 5 drawings accompanying this dis closure .
Brief De~cr:iption of Dra~Jings In this disrlosure, ~che followinE~ drawings are incorpc>rated:
FIGURE 1 i~ a combined wiring ~nd block diagram illustratlng the preferred embodimeTIt of the present invention;
FIt~l~E lA is a series of wa~ve char~cs indicaking an operat;ng characteris~ic of the prPferred embodiment of the inventlon;
FIGURE 2 is a wiring diagr m showing in more detail certain features o the prefexred embodim2nt as sh~ iLn FIGU~ 1, FIGURE 3 is a graph illustra~cing, ~chematic~lly, ~he load 15 voltage during normal opera~ion of the preerred embodiment of the presen~ lnv~ntion with certain operatin~3 characteristics set forth irl graph form therebelow;
FIGU~ ~ is a graph similar to the graph ~ho~n in FIG~ 3 and having a chart of certain chara teristics used in an aspect of 20 the pre~nt inven~ion;
FIGURE S is a schematic block diagram showing operating characteristics of the aspec~ of the present inventi3n set for~h schematically in FIGURE 4;
FIG~RE 6 is a com~ined wiring diagram and block diagram ~how-ing component~ employed in practice to ac~ompli~h the aspect of~he inven~lon ~e~ for~h schema~ically in FIGURES 3-5;
FIGURE 6Ais ~ simplified version of ~he circuit used in practice and as shown ln FI~URE 6;
FIGURE 7 i~ a combined block diagram ~nd wiring diagram illustratin~ the arrangement employed in practice to discon~inue opera~ion of ~he starting inverter, as ~h~wn in FI~RES 1 and ~;
FIGUR~ 8 is a com~ined wiring and block diagram ~howing ~ decoding arrangement employed in practice ~o perform ~he 3~ steps s~t forth numerically in FIGURE 9;

FIGURE 10 is a wiring di~gram illustrating the circuit employed in practice to rontrol ~he power ac~or o~ the ~tar~-ing inverter during thsa s~arting cycle of ~che main powPr ln-verter as ~hown in FIGURE l;
FXt:lTRE lï is a logic diagram illustra~ing the arrangement for combining the output of the circuit shown in FIGURE 10 to produce gating pul8es; and, FIGURE 12 shows a seri s of pulse chart~ indicating the output of FIGURE 10 and the input of FI~URE 11 as used to con-trol the trigger or ga~cing commands in the star~ing inv~rter of one ~spect of the present inv . rltion .

Pre f erred Embodiment Referring now to FIGURES 1 and 2, wherein the showings are for ~he purpose of illu~rating the preerred embodimen~ of the invention only, and not for the purpo~e ~f limiting same, a parallelco~pensa~ed inverter 10 having outpu~s a,b are connected ~o a ~tandard phase controlled rect~fier 12. FIGU~E 1 is a de-tailed layout of the pre~ent învention ~ncluding certain operating components utilized in the preferred embodiment. FIGURE 2 is a ~lmilar overall view of the preferred embodimen~ sh~wing primarily the in~erconnection be~ween ~he various basic somponents a~ set forth in more detail in FI&URE l. Thes~ two figurcs are taken together to complete ~he description of the general layout of thP various components employed in the preferred e~bodiment. In both igures, a choke or smoothing reac~or 14 connec~s the constant current D.C. output of r~ctifier 12 ~o the input ~ide of the ~ome-w~at standard parallel-compensated inverter 10. Rectiier 12 has a normal three phase input Ll, L2 and L3 which can be connected or dlsconnected from the rectifier by an approprl.ate clrcui~
breaker or switch network 20, ~hown generally i~ FIG~E 2 ~nd designated as a component of rectifier 12 in FIGV~E 1. In practice, line reactors 22, 23 and 24 are employed between circuit bre~ker 20 and phase con~rolled bridge or rectifier 12 to con~rol the di/dt of the line current being rectified into a cons~an~ cur-rent D.C. source by bridge or rectifier 12. Ou~put lines a,b are connected across an induc~ion heating load 50 which i~ a parallel tuned circuit, or tank circuit, including lnductance, reactance, and capacitance, as schematically illus~ra~ed in FIGURE 1. A choke 52 is illustra~ed to represent the inductance in the leads to and from load 50. Thi5 inductance could be p~r tially comprised of the inductance of load transformer 60 whioh i8 u~ed in practice and Is ~chematically ~llus~rated in FIGURE
2. As ~o far explained, inver~er ~e~work A, ~hown in FIGURES 1 and 2, i~ constructed substantially in accordance wi~h standa~d practice. A ~ran~former 62 9 ~hown in FIGURE 2, connects a second rectifier 64, through a choke 66, to the input side of a starting inver~er 70, which uxiliary inverter forms one aspec~ of thc present invention. Inverter 70 has output leads c,d t~ be con nected acro~s the load. Starting inver~er 70 ~an b~ connected across the induction heating load by swi~ch SW6 during the start-20 ing cycle of maiIl inverter 10 in inverter network A. As can beseen in FIGURE 2, inverter 70 is relatively si~plified and includes only two SCR's 90, 92 and is proportioned to dr~ve load 50 at its resonant frequency. The components of inverter 70 can be pro-portioned for low power and current vperation. ~ain inverter 10 in-clude~ two separate branches, one o which is ~ontrolled by SCR's80, 82 and the other of which is controlled by SCR's 84, 86. The SCR's, as shown in FIGURE 2, include gates 80a, 82a, 84a, 86a, 90a, and 92a, respec~ively. A ga~ing s;gnal recelved by one of these ~ates renders the respecti~e SCR conduc~ive in accordance with standard pra~tice. Each of these SCR's has a turn of ~imP or comm~tatin~ by reverse voltage. Thi~ ~urn off time is being re-duced as technology involved in the construction of 5CR's advances.
At thls time, the eut of time for the more expen~ve precisic~
SCR's having rating necessary ~o carry the current needed for induction heating ~8 generally 9 12 microseconds. Thus, after 2 gatin~ nal ha~ been received by one of the 13a~e~, the SCR ' 5 can be turned off only by rever~e biasing the SCR for a period exceedin~5 9-12 ~croseconds :Eor more ~vphl3ticated 5CR' æ . Les~
2xpensive SCR' 8 u~ed for power inverters have e~en greater turn off tlme arld may require 50 to 100 microseconds o reverse volt-age for conmlutating. To operate main inverter ~ û, gating pul es Pl are received in unison a~ gates 80a and 82a. Thereafter, SCR' s 80, 82 are reverse biased to ommutate when ga~cing pul~e~ P2 Qre directed to gates 84a, 86a to activate or render conduetiYe SCR' ~
10 ~4, 86. By alterna~ing g ~cing ~ignals Pî, P2, an al l:ernating cur-rent is ereated at ~ransformer 60 ~Eor driving iIlduc~ion heai:lng load 50. Thig is ln accordance with ~tandard solid-stste and ~nduc~ion hea~ing technology.
In accordance with the present invention~ switch SW6 is c10sed 15 during init1a1 star~up of main ~nverter 10. When ~his occurs, gat-ing commsnds ar~ alterna ely received by gates 90a, 92a which causes an al~ernating current ~o 10w through 1ines c, t ~o transformer 60 for dr~ving load 50. Since lnver~er ~0 1s a ~ma11 inverter having a power rat1n% approximatel~ 5% of the power rat1ng for main inverter 20 10, inverter 70 1s easy ~o start and ean be positive1y driven to resonant frequency of 10ad 50. Thi~ provide~ ~ufficient energy in the loAd to rommutate inver~ers 80-86 ~o inl~iate operation of main inverter 10. Reactors 94, 96 are coupled ~oge~her and combine with capacitor~ 95, 97 ~o commu~ate ~he SGR's. A ~ing1e re~istor ~3 in 25 line C is a curxent li~itlng e1ement to prevent a ~hort circuit be-tween 1ines c,d. As previous1y mentioned, ~nverter 70 is low power and i8 adapted for the funct~on of driving 10ad S0 at its reRonan~
~requ~ncy. In practice, inverter 10 has a rating of 200 Kw and start ing inverter 70 i8 si2ed for approximate1y 5-15 Kw.
Reerring now to ~he detailed b1Ock diagram of ne~work A a~
shown in FIGURE 1, a ~tandard ph~se contro1 100 i~ employed for contro11ing the output of rectifier 12. Thi~ controller can be turned on by a signa1 in line 102 and can be turned off by a signa1 in 1ine 104. In this ma~ner, rectifier 1~ can be activat~d or de~
35 activa~ed. ~hen activated, constant current i~ applied to main inverter 10. Otherwise, no eurrent or very 1Ow current ~s ~pplied and inverter 10 does not operate. In prac~ice, 11nes 102, 104 - ~2 -are employed for operating circuit breaker 20, a3 illustrated in FIGURE 2. Another technique u~ed f~r controlling the output o rec~ifier 10 is a phase angle adjus~men~ device 1060 As ~he phase angle i5 changed, the amount of power dlrec~ed from rectifier 12 5 to inverter 10 can `be controlled. Thus, by rhanging th2 phase angle by a rontrol de~ice well known in the art, ~he power rom reetifier 12 can be progressively increased or decreased. This can be u~ed instead o circuit breaker 20 for ~c~ually eonnecting rectifier 12 to inverter 10. In practice, lnverter network A in-rludes a start sequence device 110 actuated by switch 112 which may be a manual switch or a transistor ~witch. Upon actuation of s~itch 112, output 114 of sequence device 110 i5 provided with an appropria~e ~tart pulse 116. This pul~e i~ employed for acti~a~-ing rectifier 12 by a pulse in line 102. Even ~hough activated, device 106 is a~ a sufficient phase angle to prevent immediate applira~i~n of power to inverter 10. Pulse 116 also initis~es bistable device or one shot device 120 wh~ch i~ used to immedlately csnnect leads c,d across load 50 so ~hat inverter 70 is enegized and directs its output across induction heating load 50. To do 20 this, relay coil 122 is energized to close swi~ch SW6 $n lines c,d, : as ~hown in FIGURE 2, or in line d as ~hown ~chematically in FIGURE
1. In prac~ice, both leads are eonne ted by swi~ch SW6 across in-duction heating load 50. Starting pulse 116 appears ~n line 130 which set~ flip-flops 132, 134. The first flip~flop activate~
25 . the gating circuit 190 for ~n~erter 70 and the second flip-flop ac~ivates a voltage controlled oscillator 200 to control the spacing of ~he gate commands to SCR's 90; 92. The current from rectifier 64 i5 al~ernated across load 50 in accordanee wi~h a rate whieh will render the load voltage and load curren~ in pha~e, i.e. at unity power factor.
To stop main inverter 10 of inverter network A, a stop sequence deviee 140 is controlled by an appropriate ~witch 142. Output line 144 recelves a 8topping pulse 146 to initiate the termlnation of opera~ion of inver~er 10. This ~topplng pul8e t~rns off - 35 rect~fier 12 ~hrough con~roller 1~0 by creating a puls2 in line 104.

In ~ like manner, pul~e 146 resets flip-flops 132, 134 ~o ~hat 'che ga~ing circuit 19~ of inv2rter 7û i8 deae~lvated a~ i~ the voltage on~crolled os i lla~cor 200 u~ed for ~pacinEs the ga~ g pulse~ to SCR' s 90 . 9~. In su~ary, ~equencer 110 r~ualte~ net-5 work A by irst conditionirlg rectifier 12 to ~upply constantcurren~ to inverter 10 and th~n by activating ~tar~ing lnverter 70 for ~carting main inverter 10 lrl a manner w~ich will be de~
scrihed in more de~ail. To stop opera~ion of inverter 10 in network A, sequencer 140 is ener~3ized by a 5y6tem schematically 10 repre8en~ed as a 8ingle pole switch 142. l~is deactlvates recti-fier 12 ~o deac~Livate înverter 10. If ~arting inverter 7û i8 being used to star~ the main inverter when switch 142 i~ closed, flip- flops 132, 134 are re~et ~o stop the operation of auxiliary inverter 70. If main in~erter 10 is operating in a steady-state lS condition, swi~cch SW6 is op2n~d by relea~ing coii 122 and ~he stop sequence is employed only to remove power from invertex 10. As wlll be explained later, i~ is po~sible ~o direct power from ree~i-fier 12 to inYerter 10 without u~ing th~ inverter for driving load 50 by dieabling the network used in creatlng gating pulses Pl 3 P2.
20 Thus, main inverter 10 can be activa~ed by selecti~ely controlling the outpu~ of rec~ifier 12 or by controlling ~he ga~ing pulse to the main inv2rter . In practice t bQth of these devices are employed for the purpose of controlling the actuation and deaetuation of ~ain inverter 10.
~n appropriate level detector 150, which in practice isan operational amplifier, compares the average load voltage from a detector 151 with a pre6elected volkage level or reference repre-~en~ed as X. When ~he average voltage across ~he load reache~ a preselected value, a si~nal is crea~ed ~ithin ou~put line 152.
30 This changes the logic on line 154 to clamp one-shot device or bistable device 120 to the OFF posi~ion. This opens swi~rh SW6.
At the ~ame ~ime, line 156 resets flip-1Ops 132, 134 t~ de-activate starting inverter 70 which has been released from load 50 by opening switch SW6. Thus, when the voltage acro~s 35 load 50 reaches a preselected level, inverter 70 is disconnec~ed ~ 14 -from the load and the st&r~i7lg inverter is deactivated by flip-10ps 132, 134. A corresponding ~ignal is created in output 160 of level de~ec~cor 150. Th~s crea~ces a logic in 162 wh~ch pro~re~sivelyincreases phase angle ad~ustment by devire 1û6 to 5 progressively apply more power from rec~ifier 12 to main irlverter lO. At the ~ame time, the lo~sic on line 160 ~rea~es a slgnal in line 164 to energize gating cirruit 170 or T~ain inverter 10. As previou~ly mentiorled, thl6 i8 optional ~nd the gating circuit may be energized by ~equencer 110 and need not wait for the opera~ion 10 of auxiliary inverter 70 before ~che gating ~ignals are available and ~wai~ing increaset power from rectifier 12. I~e option of turning on gating circuit 170 by sequencer llû i~ schema~cically illustrated by dashed line 172.
In many power inverters prlor to the present invention, the 15 load eurrent ~nd load voltage were detected and compared so tha~c ~his comparlson could be used to adju~t the load phase angle ~o a preselected power factor. Thi5 pre~ele~ted power factor was de-termined by the operat~ng frequency of ~he inverter and the ~u:rn off characteristics oiE the SCR' s or ~hyris~ors . The power factor w~ adjusted to a~sure that the SCR's were not ~u~ected to a forward bias beore ~hey were oommuta~ed. Standard detectors 180, 182 are used in network A to perform the function of detecting the w~ve form of the load current and load voltage, respectively. In the present in~ention ~he output o detector 182 is direc~ed to ~he input of gating circuit 170 to control the rate of the ~ating pulses.
In the past, both current and voltage were generally employed for this function. By using the inventlon,gating pulses can be created while sensing only the load voltage wave from detector 182. The output of de~ector 182 is also employed by detec~or 151 for ereat-lng the average voltage across load 50 fox use in energizing maininYer~er lQ after star~ing inverter 70 has performed l~s ~tarting unetion.
During the starting ~ycle, which can be relatively shor~
auxiliary inverter 70 drives load 50 while main invert2x 10 i~
no~ energized. Ts eontrol the gating pul~es to ga~es 90a, 92a, ga~ing circuit 190 9 Sl:10Wn ln ~ore det~il in FIGURES 10-12, is employed and is 60nstructed in ac~ordance wlth another a~:pect of the l~v2n~ion. Gating circuit lgO has a ir~t ~nput 192 w~ich i6 the output of flip-flop 132. When thls flip-flop lL8 5 ~et, a logic 1 appears in lnput line 192 for enabling the ga'ci:ng pulses in a manner ~et forth in the ne~cwor.k ~hown in FIGURE 11.
Anc~ther irlput 194 of circui~ 190 iR cc;nnected to ~he s)u~pu'c of voltage es7ntrol 08c~1:La~cor 200. The output of this oscilla'cor ls a var~able frPquency directed ~o line 194 to con~rol ~he 10 freguency of ~he ga~ing commands ~n ~o lines 201, only one of these lines is illustrated in FI~URE 1 and FIGU~ 11. The frequency of the ga~cing pul~es in lines 201 de~ermines the frequency of voltage acro~s leads c, d t which frequency is ad-justed to the r son~nt requency of load 50.
For the purpose of c~ntrolling ~che frequency in line 194 from o~cillat~r 200, the vol~cage in ~npu~ line 202 is controlled by the c~rcuit l:est shown in FIt;URE lQ and schematically lllus-trated in FIGURE 1. Th~ circuit includes a voltage input 210 which has a Pinusoidal wave ~hape, shown in the top graph of ~0 FIGURE lA. The current wave at input 212 has the wave ~hape generally ~hown in the ~econd graph of FIGURE lA. In accordance with the present invention, one of these wave shapes i~ shifted 90. In the illu~rated embodlment, the load voltage wa~e at input ~10 is shif ted 90 by an integra~r ~14 . The ou~put of 25 this ln~egrator ls mul~iplied by the current wave in line 212 ~y appropriate analog mul'ciplier 216. The ou~put of ll:hi8 D!U~
pller i8 directed to ampliier 220, having outpu~ 226 controlling line 202 snd an input 228 controlled by the analog leYel of the voltage from nrultiplier 216. As illustrated ln FIS:URE lA9 when ~he 30 load ~oltage and load current are in phase, the prodllct of the integral o thP. load sroltage and ~he load eurrent ls ~he wave shape ~hown in ~he bottom ~raph of FIGURE lA. Thi~ wave average~
zero. ~us, the average output in line 228 19 zer~ when the current and voltage of load 50 are ~n phase. At unl~y power ~acto~, ~he a~rera~e out~ut of mult~plier 216 i~ zero. Ampli~ier 220 has pots 222, 224 for oontrolling the volt~ge on llne ~26 ~o that the input to osclllator 200 has a preselected value when the output o multiplicr 216 ls ave2-aged ~o zero. Thi~ clrcuit is 8hOWrl in morP detail ln FIGURE 10. A further ampl~fier 218 ron-trols ~he vol~age in line 202 a~ a function of 1:he vol~cage in line 226. me output in llne 194 controls ~che frequenl~y of gat-ing pulses to 5CR ga~es 90a, 9~a to produce uni~cy power factor in operati~n of s~arting inverter 70.
Referring now more particularly to the detailed disclosure lQ of FIGIJRES 10-1~ wh:l ch is direc~c2d to gating of 5CR' ~ 90, 92 of awciliary in~r~rter 7~ for ~he purpo~e of maintaining unity power fac~or during the start~ng cycle . 8atin~ circui'c 190 includes a requency divider 24û haYing an ou~put 241 which cr~ates pul~es having a duration during ~hich one of ~he gates 9ûa, 92a is to be activated. The other output 243 controls a JK fllp-flop 247 80 th~t repeti~ re pulses ln outpu~c 243 crea~e series of 20.0 micro~econd pul~e& in line 244, 246, alternately. These pulses each define the initial portion of a gating command ~o the par-fietllar SCR'~ 90, 92, as illustra~ed in FIGUR~ 10. Th~ pulses ~n llne 241 and 244 for SCR 90 are illustrated in FIGURE 12. ~n oscillator i8 employed for crea~cing a ~arrier as shown in the bottom of FIGURE 12. Gat~ng nc~work 25û for one of the SCR's, l.e. SCR
90, is shown in FIGURE 11. This ne1:work include~ ~he carrier in-put 252 ~ogether with a pulse input 241 and a gate input 244.
l~e pulse inpu~ 241, carrler 252 is used for both SCR' ~ . Network ~50 is employed for SCR 90 because it recelves f:he gating pulse in line 244. OR gates 260, 262 have outputs whlch control NAND
gate 270, This NAND ~ate i8 enabled by a logic 1 in llne 192, as shown in FI~URE 1. When a pulse appears in line 241, NAND gate 27û
is enabled 80 ~hat the carrier pulses in line 252 can be direc~ed through $nverter 272 to gating line 201. 6~hen a ~i gnal appears ~n line 244, t'lliS produce~ a logic 1 ln line 201. ~hen thi~ gate signal di~appears after 20.0 micro~econds, pulse 241 main~ains ~
chairl of pulses from carrier 252. Thus, dur~rlg e~ch gating eommand, here i~ a 20.0 ~icroseconds constant ~ating signal and then a rapid .

,3 ~a~L3 ~;ueeession of carrier pulses to malntain conduction. Thi~ g,ating signal is diæc~nt~nued preparatory ~o t~ommuta~lng ln ~ccordance with standard practice.
The operation of 8~arting inverter 70 is appareIl~ from the previc3us description. In s~ry, inver~cer 70 i~ connec~ed across load 50 by closin~ BWi~Ch SW6. Ga~cing circuit 190 control~ pul~es ~o ga~as 90a, 92a 80 that the ~oltage acr~ load 50 is in phase with the curren~ wave aeross the load. Aleter this occurs, de-tec~or 15û energiæes main in~rer~er 10 and deen~rgizeæ ~tarting inverter 70 by opening ~witch SW6 and changing the lo~ic on line 192 and di~con~lnuiIlg the opera~ion of o~clllator 200. Wlth load 50 being energized by inverter 70, main inverter 10 has su:fficient energy ~o be operated in acc~rdance with sltandard steady-state conditions . Operat~ on o inverter 70 at the resonant frequency of load 50 simplifies the inverter and allows it to start rapidly and be constructed of relatively inexpenæive components. As a safety factor, lf ~he voltage from de~ector lSl is in~ufficien~
to actuate detector 150 for a preselerted ~ime, inverter 70 is disconnected by tlme delay device 283, shown in FIGURE 1. Thi~
device i8 ~nitiated upon receipt of a ~tar~ing pulse 116 by bi-atable device 120. Time delay device 280 deac~iv~tes st~rting in verter 70 af~er a preselec~ed ~ime, whieh ls greater ~han the expected starting cycle. This may be less ~han a few ~econds.
It ls possible ~o bypass detector 150 and energize maln inverter 10 by time delay de~ice 280. In ~hls manner, the ~tartlng in-verter would be ener~ized for a pre~elected time. Thereafter, main inverter 10 would be actua~ed and star~ing inver~er 70 would be deactuated. Thl8 iS an alternative arrangement ~hich would employ ~lme delay 280 which, in practice, is a safety device to assure that lnverter 70 doe~ not operate over pr~longed periods when the load 50 ha~ charac~eristics that will ~o~ allow ~nity power factor within the range of frequencies available from oscillator 200.
Referrin~ now to FIGURE 3, ~he concept employed in FIGURE 6 for controlling ~e time locat~on of gating pulses Pl, P or .~

the SCR' s in main inverter 10 ~s schematically B2t forth. Re-erring to the upper graph, the sinusoidal load 1voltage i s ~llustra~d as cunTe m. ThiB wave passes through zero at point~ n, o and q. These are zero crossing poin~cs or cur~Te m. Between zero crossirlg point~ n and o, 'chere is one ~egment of curve m. During th~ 3 segment, a gatlng pulse P2 occurs at a tlme ~paced from the end of the ~egmeni!c (point o~ a dist~nce greater than the charac~ceristic . urn of time of SCRI s 80~8~ .
lhe ob~ect of the invention is to create pulse P2 :for che first men~ior~ed 3egmen~ at a ~paclng tOFF ~1~ which is greater than the characteristis~ turn off time prev~ously men~cioned. Thus, pulse P2 occurs before z ro crossing point o a suficient time to allow commutating of SCR's 80, 82. DurinE~ the nex~ segment of curve m between zero crossings o and q, pul,ce Pl occurs before point q a distance ~OFF(2~. E ch of ~hese ~p~cing times or amounts is ~r~a~er than the characteristic eomnrutating time of the SCR' s which is set forth as R,t~s. To obtain minim~n sae ~pacing for pul~es Pl, P2, it ha~ been common practlce to monitor both the load current and the load vol~cage to set the power factor at a desired v2alue. In some in~tances, the phase relationship between the éwo wave shapes was measured and the rate of the gating pulses was tnod:J fied ~ccordi~g to the power f actor O ~us, the gating cir-cuit of the prior art has required a comparison of the load current and the load voltage. In accordance wi~h the present concept, only the load voltage i~ monitored by circult 170. To aecomplish this advantage in an analog ashion, the concept set forth in the lower graph~ sf FIÇ:URE 3 is used. By detectin~ ~he ~ero crosslng n of the load vol~age, a capacitor i~ charged along lia~e r. When this voltage reaches a reference voltagP V5, gating pulse or pulses P2 are cre~ted. This energizes ~ates 84a, 86a which causes a rever~e voltage to be applied acro~s SCR's 80, ~2. This reverse voltage is retained for a time detennined by the location of pulse P2. By ad~usting the ~lope o line rt the inter~ection between line r Emd the reference llne V8 can be ch~nged with respect 'co 35 zero cro~sing n. By dPtecting the zero cros~ing o, the capaeitor 3~

cBn be charged according to line r ' . The ~lope of ~his lirle can be controlled by the end voltage Vl of line 4. I~us, the voltage 'co which a capacitor is being charged along line r' can be co~-trolled by the pr~ious ~oltage Vl . The slope s: f line r i~ con-trolled by the immedia~ely prlor-~egment between zero cro ~lng n, c . This ct)ntrol cvncept is repea~ed time af~eT 'cime during steady-state oper~t~on of main inverter ~0. In each instanoe, the ~lope of line r' i con~rolled by the ultima~ce destination voltage V1 of prior line r. ~he turn off time and ~pacing be-tween a zero cgss~ing point and the ga~ing pulse can ~se accurately controlled based upon only ~he load vol~age wave form. The exist-ing frequency at any given time ontrol5 the poæit~ on of the gating pul~es. The bo~ctom graph of FIGIJRE 3 indicates t~a~ when ore SCR
i8 tu~ed on~ the carrler iæ supplied 1:o the gate ~n aecordance ~ith thP previous discussion of ~che ga~ing pulse for s~arting inverter 70.
The concept of employisLg a prior ~e~Pnt of wave m for reating the ~pecific locatlon of the nex~ gating pul~e, as se~
forth xchema'cically in FIGI~E 3, ~ 8 employed in g~ting circuit 170 as 6hown in FIGURE 6. In ~chis in~tance~ a digital concept is used 'co memorize the length of the prior voltage ~egm~nt and for controlling the next gating pulse ba~ed upon this me~orized length. The concep~ ls ~chema~irally illustra~ed in FIGURES 4 and 5. In FïGlJRE 4, previously mentioned load volt~ge curve or wa~le m hss zero cros~ings n, o, q, etc. Be~ween each o these zero cro~sings is a ~egmen~ whieh i one-half period 4f w~ve m.
The alternate po~itive and ~egative ~egmen~s of the load vol~age wave sn are designated w~th appropriate signs. In a~cordance with ~he digital i~plementation of the concept generally d~sclused in FIGURE 3, a co~ter count pulses during ~he po8i~ive egmen~
between zero crossings n, o. This crea~e~ a ntmlber n. The ga~ing pulse Pl i~ ~co occur before zero croæsing q during ~he nega~ e ~egment between zero cros~ings o, q . To do thi~, prev~ ously ~enerated co~ n is deoremented by a num~er v counts indlcative of a time tl wh~ ch counts are selected for an offset time greater than the ~urn off time of scr~l s ~0-86 . The g~ting pulse is created after a time corresponding with oounts n tl. This crea~es a ga~ing pulse Pl. Whil4 ~he ga~ing pulse Pl is being crea~ed, a further count is belng made in the nega~ive seg~en~ be~weeTI æero crossings o, q. l~ls produces a new num~er fro~ which ~he pre-8eleeted count is removed whieh count reduce~ the ~ime of counts created during ~he negativP se~nen~ ~o a rime spacing t2. The ~ime represented by the coullt difference or ~paclng exeeeds the characteristic 1:urn of f ~lm~ or commlltatlng time of the SCR' s .
~hus, during each ~egmen'c, a count of eveIlly spaced pulses is made. This count is memorized and ~hen is used for es~cablishing the instant for the next gating pulse. This can be done by sub-tracting a number of pul6es or counts from the stored eouIIt or otherwise crea~lng a ~atinE5 sigrlal when a preslected number of s~ored colmts have been made. Since the end spacing is mos~
critical, a subtractive concept is preferred bec~use of the ease of obtalnirlg the proper spacing before the crueial zero crossing of wave m.
Referring now to FIGURE 5, a gating circuit 170 ' empl oylng the concept set forth in FIGt~ 4 is illustrated. Irl thi~ net-work, ~ensor 300 sen~es the time during whlch wav~ m i8 :Ln a positive segment. A ~imilar ~ensor 304 determines when the load voltage 1B in a negative segment. Up/ down di~ital counters 310, 312 are employed for memorlzing the num~er of eoun~s during ~he posi~ive segment of wave m and the negative segment of wave m, respectively. A commcrl oscill~tor 314 creates a plurality of evenly spaced counting pulses in line~ 320, 32~ which count cou~ters 310, 312, respectlvely~ in the direction determ~ned by logic in lines 324, 326, respectively. When sensor 300 ~s detecting a positive ~egment, line 324 causes counter 310 to count in the increa8in~S or up directi on. In a like manner, when ~en~or 302 ~5 6ensiTlg a negative 8~gment, line 326 causes coun~er 312 to count in the up directl on . The rats o coun~ing is de~
termined by fixed oscillator 314. When counter~ 310, 312 are eounting up or incrementing, line~ 330, 332 each direct a loglo û

to the enabling terminal of comparator~ 340, 342, respec~i~rely.
This preven~s a comparison ~ignal during ~che up couT~ting mode of co~ers 310, 312 . Con~ara~ors 340 9 342 com~are the digital output of regis~ers 350, 352 with 'chQ digital output of coun~er3 310, 312, respec~cively. Ea h of these registers iB loaded ~ith the co~t representing ~he spacing from zero cro~sing ~co provide necessary ~ime at the end of a ~egmerl~ W ~llow cosl~Du~a~ing of one of the SCR'6 80-86. This count i8 loaded in parallel fashion by lines represented by a ~ingle line 360, 362, re~pee~ively. Of course, registers 35û, 352 could be combined since they wil:l re-c~ive the ~ame digital number rom load line 360, 362.
In opera~ion, counter 310 coun~s in a binary fashion ~che pulses or counts from osclllator 3:L4. Ihis upcounting is COTI-~rolled by logic in lin~ 324. When ~hi~ logic ~hif~s to a logic U indicat~ng a zero crossing at the end of a positive segment of wave m, a logic 1 appears a~ line 330. This enables comparator 340. At the same ~:lme9 line 324 causes counter 310 ~o co~u~t do~n or decrement in accordance with the rate of oscillator 314. When counter 310 reaches the number set in register 350, a pul~e is ereated ln compare llne 344. This resets counter 310 and holds the oounter in ~che reset condition. I~ also directs input ~:o a one shot device 370 for creating gating pU18eS. The~e gA'cing pulses are directed to main ~nverter 10 for E~ating the SCR's 80, 82.
As soon as sensor 390 ag~in de~ectR a positive se~ment of wave m~
the logic on line 324 shifts to a logic 0. This st~rts the up-counting o count~r 310 and removes enable logic from comparator 340 so tha~ the compare signal in line 344 disappears. Thi~ same operation is employed for creating pul8es in line 346 when there is 8 comparison between count in counker 312 and 'che ~pacing couni:
in register 35~. By using this circuit, a prior ~egrnent determlnes the locationin a timed relatior~ship for each gating pulse or ~lgnal.
This is a digi~al system 'co p~rform ~he analog conoept ~et forth in FIGURE 3.
In practice, gatlng circuit 170 1~ construc~d to perform ~he uIIction ~et forth in FIGURES 4 and ~ by ~he detailed circuitry shown in FIGURE 6. RPferring now specl:fically to FIGURE 6A, a simpll:Eied version of l:he circuit in FIGURE 6, a selector 400 determines whe~her or not ~ine volt~ge w~ve m i~ in a ne~Sa-tive or positive se~ment. Select~r 400 ~L8 shown in more d~tail S in FIGURE 6 as flip flops 400a, 400b. A decoder 402 produces a ~uceession of pulses in lirles 410, 412, 414 ~ the ~tart of ea~h ~egment to process ::oun'~ing informatiorl as described with respect to 'che scheme set orth ln FIGURE 5. Decoder 402 1~ ~hown as ~eparate units 402a, 402~ in FIGIJRE 6. As ~os:~n as a zero crossing has been made, a series of pulses occur ~equentially ln llnes 410, 412, 414, respectively. These pulse~ cc~ntrol proces3iag of eo~nt information erea~ced primarily by counter 420 driven ~by a crystal controlled o~cilla~cor 4~2. In thi~ instance, cou~er 420 co~ts only in a preseleeted direction which is, in practice, ~he up direc~ion.
A binary data transfer devlce 424 i~ ~onnected in the parallel data mode to a binary ~torage devlce 426. When a zero crs:~ssing is detected by eelector 400, a pulse occurs in llne 410. Thi8 re-sets device 426 by gate 427. In~nediately ther~al'ter, on the next pulse, data ~ransfer device 424 transfers the data from courlter 420 into the cleared stora~e device. In ~he meantin:le, the reset pulse in line 410 has been removed. Thereafter, a pulse in line 414 re-sets r-ounter 420 ~o count t~e next wave ~egment. l~us> at the be-ginnirlg of each segment, storage de~ice 426 is cleared and the count occurring durin~ the previou~ segment and appearing at the parallel outputs of co~ter 420 is transferred to storage de~rice 426. A
fiub~racting decoder 430 removes a pre~elec~ced number of counts from the stored count~ in device 42S by standard binary subtrac-tion 80 that con~arator 432 has a first inpu~ wh~ch ~5 ~ previous count CN minus tOFF which is compared with a current co~t indicated as CN~l. As soon ~s thPre has been a com~arlson by bi-nary comparator 432, a comparlson ~ nal i8 created in llne 442.
Thi8 activa~e~ the gating network 450 so that gatin~ pulses appear ln ~ine 452~ In FIGURE 6, ~o lines 452a, 452b are employed for creating the gsting puls~s Pl, P2 as ~et :Eorth generally in FIGURE
35 2. A previous COUIlt CL~;I during a s gment of load VOl~L8ge wave m mirlu~ a su~Eficient numbe1; of counts (Te~FF) is eompared with a current count CN+l from rounter 420 When this c~mparison i~
made, a gating pul~e i~ created.
Refesring now to FIGURE 6, gatiTIg cireui~c 170 as u~ed ln 5 pras::tice 1~ lllustrated. Ihe various component~ ~re labeled accoraing ~o ~cheir IC designation. l~e number6 employed in FIGURE 6A are carried forward lnto FIGI~E 6; Selector 400a has an input gate 500 which i~ disabled by :1 ogie on line 502 at the ini~cial portlon of the ga~ing ~ignal for a positive ~egmen~.
0 Thi~ preven~R overlap in false countillg by eireuit 170. Selector 40Qa i ~ a JK flip-flop haYing an output 504 co~nected ~co the reset ter~irlal of a binary coun~cex 510. Thi8 counter is c~urlted by a 1. 0 megahertz clock a~ i~6 clocking terminal. Countex 510 ha~
successive countin~ outputs 512, 514 ~nd 516 eas:h of which is connected to an inverter 520, 322, 524, r~spectively. In this manner, either ~nverted ~r non~inver~ed logic from 'che outputs of counter 510 can be emF loyed by decoder 402a. In practice gates 530, 532 and 534 are used 8S the decoder. The~e AND ga~es are enabled by the previously mentloned clock CK for synchroniza-20 tion. ~hen the reset pulse i8 removed from line 504 during actua-tion of flip-flop 400a, counter 510 ~tarts counting. Gate 530 creates a pul~e in line 410. Thereafter, ga~e 532 creates a pulse in line 412. Gate 534 ~hen creates a pulse in l~ne 414. These pulses have been previously de~cribed in connection wl~h the block diagram shown in ~IGURE 6A. Selector 400b ~s e~entially the ~ame as selector 400a except it creates pulses in lines 410a, 412a, 414a which are ORed with lines 410-414. Input ~;ate 500a is enabled or disabled by ~hP logic oa line 502a. This again i~ for the purpose of preventing overlap and assure ope3: ation of counter 510 30 in the proper sequerlce. Binary regis~er 55û contains the courlt to be ~ubtracted by uni~ 430 from the number stored in memorg~ device 426. In prac~ice, 'chl~ binary register i6 adjusted automatically by an analog tc> digital inYerter 552. As ~he average load voltage ~hanges, the am~unt of co~ts subtracted from ~he previou ly stored 35 count is varied. Although i~c can be done automatic lly, this _ 2b, _ function c~n be accomplished manually. After a comp~re ~lgnal has been created in line 442, ~his loglc i~ inverted by lnverter 560 to clock flip-flop 562 having an ou~put 564. A9 600rl ~LS there i6 a compa~ee signal, flip-flop 562 is elocked to creat2 a loE~ic 1 5 in line 564. After approacitnately 2û . O mioro~econds, a ~ ogic 1 in line 566 resets flip-flop 562 ~o that ~he logic in line 564 shifts back to a logir zero. Although variou~ arrangements could ~e provided for rese~c~ing fllp-flop 562, in prac~ice, inYerter 568 ls in~erpo6ed bet~een he outE3u~ of rourlter 570 and reset line 566. C:ounter 570 ~s counted in a binary fashion by pulses received from oscillator 422 wherl a logic 1 ~B applied to enabling terminal E. A plurality of ~witches for a Tletwo~k 572 en-ables various output terminals from counter 570. This network con-trols ~he logic on several inputs for M~ID ga~e 580. Output 582 of this gate is connec ed t~ inver~er 568 and enabling terminal E.
In operat:ion, a logic 1 in line 584 occurs when there ls a rese~c pulse vr eompare signal ln llne 442. Th~s rese~s counter 570 to shif all terminal~ ~o a logic 0. Thus, at least one input of gate 580 i~ a~c ~ logic 0. Thi8 produres a logic 1 in line 582 for en~bling eloek 570 to c~ . This shit~ reset line 566 'co a logic Q. Consequently, fllp-flop 562 ean be elocked when a count selec~ed by switch network 572 has been reached and a logic 0 ap-pears in line 582. This resets flip-flop 562 to shift ~he logie on line 564 to a logic 0. At the same time, term~nal E of counter 570 ~s disabled. By adjusting swi~eh network 572 the width of the pulse in line 564 ean be adjusted. Thi~ pul~e creates a ga~ing pulse in one oiE the line~ 452~, 452b. The particular line whlch receivPs the gating pul~e is de~ermined by a steering flip-flop 590 ~et by the logic in line 592 and rese~ by the logic in line 594. Thus, ~he decoders 402a or 402b being operated controls the bistable flip-floF
590. The output~ o flip-flop 590 are directed to AND gates 600, 602 havin~ ou~puts 592, 502a, respectively. Thus, 1ip-flop 59û
¢nable~ one o ~he gates 600, 602 to steer the pul6e in llne 564 to ~n appropriate output l~ne. I::arrier flip-flop ~10 is ltoggled ..

- 2s -aecording to the logic at the output of gates 600, 602. Thi~
controls the ga~es 620, 622 for directing a 30 KXertz cRrrier to the input ~ide of one of the ~ignal ore~ting OR ga~e~ 63~, 632. Tn ~his manner, flip-flop 590 activates one of the gates 630, 632. A~c first, a constant ~ulse of 20 micru6ecoTIds i8 cre ted at the outpu~: uf ~he ~eleo~ed gate 630, 632. Thereaf'cer, a ~eries of pul~es from divider 625 occur a~ the ou~put of ~he ~elec~ced gate. Thus, during ga~cing, a cons'caIl~ pulse is crea~ed ollowed by a ~eries of pul~es. On acti~ration of ~che other selector 400a, 400b~ flip-flop 590 is 'coggled ~co activate another une of the ga~es 630, 632. In this manner, gating pulses or signals are created in line~ 452a, 452b for ~he purpo~e of on-trolling ~he SCR sets in main oscillator 10.
Referring no~ to FIGUR~S 7-9, a ~cheme employed in the 15 preferred embodiment for son~rolling certain a~pec~s of inverter network A ls schema~lcally illu~cra~ed even 'chough they do not form a par~ of the presen~ in~ren~ion. Referring firs~ ~o FIGIJRE
~, a flip-flop 640 controls the binary co~mter 644 which has out-putg decoded ~co succes~ive ~teps by ~ decoder 646. Flip-flop 642 20 is employed for resetting flip-flop 640. In accordanee with this schematic layout, neither the ~tark bu~ton 112 or ~he ~top butt~n 142 i9 depressed, flip-flop 640 is se'L to enable courl~er 644. The counter then count~ pulses from oseillator 422 . o ~equence ~hrough steps Nos. 1-~ at the output of decoder 646. The steps are as ~5 set forth in the chart of FIGIJRE 9 . A~ first, 24. 0 volts i5 ap-plied to inverter network A. mereafter, the starti~g inverter 70 is ~ctivated by energizing bistabl2 device 120. The starting inverter goes to unity power factor. Then, maln gating circuit 170 is turned on by line 172. Th~n, ~tep No. 4 ~h~fts device 106 to a minimum phase angle ~o ~ha~ rectifier 12 ls at a m~nim~m ou~pu~.
This i~ awaiting the ~peratlon of the ~tarting inverter a~ prev-iou~ly de~cribed. Then, power regul~or of network A is released and then during 8~p No. 6 the clocking pul~e i8 direc~ed ~o 1ip-flop 642 to disable flip-1Op 640. Thl~ ~ops eo~nter 644 a~d holds decoder 646 at s~ep No. 6.' This i~ the start~ng ~equence ~ ~et - ~6 -forth generally ln ~he s~ax t ~equencer block 110 . To deactiYate network A, step~ ~o. 7 a~ad No. B ar~ proce6sed by closing swltch 142 . l'he phase angle on control 100 is redueed and ~e 2b.. 0 volts ~ource is removed. Thus, ~tep6 ~os. 1-6 are in ~he start 5 sequence and steps No~. 7 ~nd 8 are ~n ~he stop ~equence. Re-ferring now tu FIGURE 7~ flip-flop 700 :I_R employed when skart s~quencer 110 l~ at step ~o~ 3. As ~oon ~ level d~ector 150 detect~ a preselected level of OU~pll'c voltage, fl~p-flop 700 i8 ~et. Thi~ activ~teE9 ~D ga~e 702 which dl~conn~cts starting in-10 verte~c 7û and applie~ power to inver~er 10 by performing ~ep ~o.4 . If during thi~9 routine 9 8top 'button 142 iS energi zed, fLip flop 700 i8 reset to prevent advanoe into ~ep No. 4. This con-cept is schema~lc ~n nature and is illustra~ed only ~o ~how tha~
level deteetor 150 i~ employed in perorming step No. 4 after ~ep No. 3 has been performed.
Referring now ts FIGUR~ everal s~itohes S~l-SW5 are illustra~ed. These ~wi~ches are used in ~he preferred embodiment of the ~nve~tion fsr the purpose o ~rou~le shooting lnver~er ne~-work A. By ope~ing the~e various ~wltche6, cer~ln components an be di~eonnec~ed ~o determine whe~her or not ~heir part~oular fune-tion is cau~ing dlfficulty being experienced by network A. These ~arious swltches are illustrated for the purpose of completene s;
however9 ~hey are no~ nece~ary for the un~ers~anding ~nd operation of ~he preferred embodlment of the invention.

Claims (9)

The embodiments of the invention in which an exclusive property or privilege is claimed axe defined as follows:

1. A circuit for creating repetitive gating signals for the switching devices of a D.C. to A.C. power inverter, which signals are created in timed relationship with respect to the voltage wave having alternate positive and negative segments and directed across a load connected to said inverter, said switching devices having a known minimum commutating time, said circuit comprising: means for establishing a reference time when said voltage transfers between said alternate segments and means for creating a gating signal a preselected time after said reference time.

2. A circuit as defined in claim 1 wherein said preselected time is substantially the measured time between successive instances of voltage transfer minus a known time exceeding the known minimum commutating time of said switching devices.

3. A circuit as defined in claim 2 including means for sensing the time of a transfer between adjacent wave segments, means for creating a known value representing said preselected time, means for incrementing a control signal from said sensed time toward said known value and means for creating a gating signal when said control signal reaches said known value.

4. A circuit as defined in claim 3 wherein said known value is a voltage level and said control signal is a voltage signal and said incrementing means includes means for progressively increasing said control signal until it equals the voltage level of said known value.

5. A circuit as defined in claim 4 wherein said known value is controlled by prior segments of said voltage wave.

6. A circuit as defined in claim 1 including means for providing clocking pulses with a known frequency;
means for sensing a wave transfer initiating a selected segment; means for counting said pulses during said selected segment to produce a control count for a successive wave segment; means for substrating from said control count a selected number to produce a gating number for said successive segment representing a reference time; means for counting said pulses during said successive segment until reaching said gating number; and creating a gating pulse when said gating number is reached during said successive segment.

7. A circuit as defined in claim 6 including means for holding said gating pulse for a preselected number of said clocking pulses.

8. In an inverter for converting a D.C. current into alternating current having a frequency controlled by the rate at which a series of gating signals are created, said inverter including a first branch to be connected across a load, a second branch to be connected across said load, first switching means for applying a voltage of a first polarity across said load by said first branch, second switching means for applying a voltage of a second polarity across said load by said second branch and means for alternately operating said switching means by said series of gating signals whereby a voltage wave having alternating positive and negative segments is applied across said load, the improvement comprising: means for providing clocking pulses with a known frequency; means for sensing a wave transfer between adjacent segments at the start of a selected segment; means for counting said pulses during said selected segment to produce a control count for a successive wave segment; means for substrating from said control count a selected number to produce a gating number for said successive segment; means for counting said pulses during said successive segment until reaching said gating number; and means for creating a gating pulse when said gating number is reached during said successive segment.

9. An improvement as defined in claim 6 including means for holding said gating pulse for a preselected number of said clocking pulses.