CA1183914A - Response time bidirectional circuitry - Google Patents
Response time bidirectional circuitryInfo
- Publication number
- CA1183914A CA1183914A CA000417100A CA417100A CA1183914A CA 1183914 A CA1183914 A CA 1183914A CA 000417100 A CA000417100 A CA 000417100A CA 417100 A CA417100 A CA 417100A CA 1183914 A CA1183914 A CA 1183914A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/46—One-port networks
- H03H11/48—One-port networks simulating reactances
- H03H11/481—Simulating capacitances
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Abstract
IMPROVED RESPONSE TIME
BIDIRECTIONAL CIRCUITRY
Abstract Bidirectional circuitry, which includes two amplifiers, each having a capacitor connected between an input and an output terminal thereof, and two interrupt transistors, acts to provide amplification and/or level shifting of information between two transceivers while also reducing capacitive loading and thus enhancing response time.
BIDIRECTIONAL CIRCUITRY
Abstract Bidirectional circuitry, which includes two amplifiers, each having a capacitor connected between an input and an output terminal thereof, and two interrupt transistors, acts to provide amplification and/or level shifting of information between two transceivers while also reducing capacitive loading and thus enhancing response time.
Description
3 ~:~
IMPROVED RESPONSE TIME BIDIRECTIONAL CIRCUITRY
BACKGROUND OF THE INVENTION
This invention relates to circuitry for enhancing the speed of transfer of information from one source to another and specifically for providing a bilateral path between two transceivers with separate circuitry in each leg of the path which selectively acts to amplify/level shift and/or acts as a one termina:L negative capacitance generator which reduces capacitance loading and thus enhances response time.
Many of today's electronics systems use MOS
circuitry which selectively has to drive a relatively high capacitance line (bus). One avenue to try and enhance response time is to increase the physical size of all the MOS drive devices so as to increase the drive capability by lowering the resistance. This also increases the capacitance on the bus which degrades response time. A
point is reached at which i,ncreasing the size of the MOS
driver devices proportionally increases the capacitance on the bus such that there is little or no enhancement of response time.
The publication entitled Ap~lications of Operational Amplifier Third-Generation Techniques by .
Jerald Graeme (pp. 38-40), describes an amplifier which uses a capacitor coupled between an input terminal and the output terminal to cancel some of the parasitic capacitance associated with the input terminal of the amplifier. This serves to enhance the response time of the ampLifier but does little to enhance the response time through a heavily capacitively loaded data bus which may be coupled to the output of the ampliier.
A Canadian applicatlon Serial No. 417,099 filed December 6, 1982 in the name of R. M. Rolfe and M. Shoji, which is being fi:Led concurrently with the present appli-cation and in which there is a common assignee and one common inventor, discloses essentially a one terminal negative capacitance generator circuit which can be coupled to a data bus (conductor) and acts to reduce the loading capacitance thereon. This serves to enhance the response time of information sent through the conductor.
It is desirable in many instances to provide a bilateral path between two transceivers which includes amplification and/or level shiftincl circuitry and in which capacitive loading on electrical conduits (data buses) connecting the transceivers is reduced such that response time is enhanced.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention there is provided in combination first and second amplifiers each having a first input terminal and an output terminal; first and second capacitance means each having first and second texminals; the first and second terminals of the first capacitance means being coupled to the first input terminal and to the output terminal of the first amplifier, respectively; the first and second terminals of the second capacitance means being coupled to the first input terminal and to the output terminal of the second amplifier, respectively; the first input terminal of each of the first and second amplifiers being adapted to be coupled to a transmitter, a receiver, or a trans-ceiver; first and second switching devices each having a control terminal and first and second output terminals; a first electrical conduit (bus, data bus, conductor) having a capacitance associated therewith and being coupled by a first terminal thereof to the second output terminal of the first switching device and being coupled by a second terminal thereof to the first input terminal of the second amplifier; a second electrical conduit (bus, data bus, cond~lctor) having a capacitance associated therewith and being coupled by a first terminal to the second output terminal of the second switching device and being coupled - 2a -by a second terminal thereof to the first input terminal of the first amplifier; the output ~erminal of the first amplifier being coupled to the first output terminal of the first switching device; the output terminal of the second amplifier being coupled to the first output terminal of the first switching device; the gain of the first amplifier and the value of the first capacitance means being selected such that total load capacitance on the input terminal of the first amplifier is less than would be the case if the first capacitance means were not utilized; the gain of the second amplifier and the value of the second capacitance means being selected such that total load capacitance on the input terminal of the second amplifier is less than would be the case if the second capacitance means were not utilized; and the first and second switching devices being adapted to be coupled by the respective control terminals thereof to control means which selectively allows essentially only one of the switching means to be conductive at a given time.
One embodiment of the present invention is directed to bidirectional circuitry which couples two transceivers. The bidirectional circuitry essentially comprises two amplifiers, each of which has a separate capacitor coupled between amplifier input and output terminals and which may be denoted as an amplifier-capacitor combination, and two switching devices which each have a control terminal and first and second output terminals. The output terminal of the first amplifier is coupled through the output terminals of the first switching means to a first electrical conduit (bus or data bus) which is coupled to the second transceiver and to an input terminal of the second amplifier. The output terminal of the second amplifier is coupled through the output terminals of the second switching means to a second electrical condult (bus or data bus) which is coupled to - 2b -the first transceiver and to an input terminal of the first amplifier.
When it is desired to transmit information from the first transceiver to the second transceiver, the first switching is biased on and the second transceiver is biased off. Information passes from the first transceiver through the first amplifier~ the first switching device, the first bus, and to the second transceiver and to the input terminal of the second amplifierO The information cannot pass from the output terminal of the second amplifier since the second switching means is biased off. The first amplifier-capacitor combination acts to amplify and/or level shift the information and to reduce all load capacitance at the input terminal thereof Under these conditions the second amplifier-capacitor combination reduces load capacitance at the second transceiver by functioning essentially as a single terminal negative capacitance generator. The reduction of load capacitance serves to enhance the response time of information sent from the first to the second transceiver.
If it is desired to send information from the second to the first transceiver, then the second switching device is biased on and the first switching device is biased off. Information passes from the second transceiver through the second amplifier, the second switching device, the second bus and to the first transceiver and to the input of the first amplifier. Information cannot pass from the output terminal of the first amplifier since the first switching device is biased off~ The second amplifier-capacitor combination now acts to amplify and/or level shift the information and to reduce all load capacitance at the input terminal thereof. Under these conditions the first ampl;fier-capacitor combination reduces load capacitance at the first transceiver by functioning essentially as a single terminal negative capacitance generator. The reduction in load capacitance serves to enhance the response time of information sent from the second to the first transceiver.
It is thus clear that the first and second amplifier-capacitor combinations switch functions depending on the desired direction of the flow of information between the transceivers.
These and other novel features and advantages of the present lnvention are better understood from con~id*ration of the following detaLled description taken Ln conjunction with the accompanying drawing.
~t~
Brief Description of the Drawing The FIGURE il]ustrates an embodiment of the present invention.
Detailed Description Referring now to the FIGURE, there is illustrated a system 10 comprising a first transceiver Tl, a second transceiver T2, a first amplifier-capacitor combination illustrated within dashed line rectangle 12 and to be denoted as circuitry 12, a second amplifier~capacitor combination illustrated within dashed line rectangle 1~ and to be denoted as circuitry 14, switching device Ql having a control terminal 26 and first and second output terminals, a second switching device Q2 having a control terminal 38 and first and second output terminals, capacitors C3, C4, C5, C6 and C7 and electrical conduits Bus 1 and Bus 2O C3, C4, C5, C6 and C7 represent the total capacitive loading of all components and/or a sus on the terminal to which same is illustrated coupled.
System 10 is bidirectional in that analog or digital information may be transmitted from Tl to T2 or from T2 to Tl. Circuitry 12 and circuitry 14 provide amplification and/or level shifting and cause the capacitive loading between T1 and T2 to be reduced from what would exist if circuitry 12 and circuitry 1~ were not used. Thus the response time of signals transmitted between Tl and T2 is enhanced.
Circuitry 12 comprises a capacitance means which is illustrated as capacitor CFl, resistors Rl and R2, and an amplifier Al having a first plus input terminal~ a second minus input terminal, and an output terminal. The first plus input terminal of Al is coupled to a first terminal oE CFl, to an input/output terminal of Tl, to a Eirst terminal of C3, to a second output terminal of Q2 (which is illustrated as an MOS transistor) through Bus 2, and to Eirst system terminal 16. The output terminal of Al is coupled to a second terminal of CFl, a first output terminal of Ql (which is illustrated as an MOS transistor), to a first terminal of R2, to a first terminal of C4, and to a second system terminal 18. Rl is illustrated coupled by a first terminal to a second terminal of R2, to the second minus input terminal of Al and to a terminal 20. A
second terminal of Rl is coupled to a potential source VRef and to a terminal 22. Rl and R2 are used to set the gain of Al and are not always needed as some amplifiers may have preselected gains. The parasitic capacitance of the first plus input terminal of Al is not explicitly illustrated and labeled but is included as part of C3. Second terminals of C3 and C4 are coupled to a ground terminal Gnd 1 and to a terminal 24.
Circuitry 1~ comprises a capacitance means illustrated as a capacitor CF2, resistors R3 and R~, and an amplifier A2 having a first plus input terminal, a second minus input terminal, and an output terminal. The first plus input terminal of A2 is coupled to a first terminal of CF2, to an input/output terminal of T2, to a first terminal of C5, to a second output terminal of Ql through an electrical Bus 1, and to a third system terminal 28. The output terminal of A2 is coupled to a first terminal of C6, to a first output terminal of Q2, to a first terminal of R4, and to a fourth system terminal 30. A second terminal of R4 is coupled to the second minus input terminal of A2, to a first terminal of R3, and to a terminal 32. A second terminal of R3 is coupled to a potential source VRef2 and to a terminal 34. Second terminals of C5 and C6 are coupled to a ground terminal Gnd 2 and to a terminal 36.
R3 and R4 are used to set the gain of A2 and are not always needed as some amplifiers have preselected gains. The parasitic capacitance of A2 is not explicitly illustrated and labeled but is included as part of C5.
The control (gate) terminals of Tl and T2 are typically coupled to control circuitry (not illustrated) which provides sic~nals that allow essentially only one of Tl or T2 to conduct inEormation (signals) between the output terminals thereof while the other is held non-L~
-- 6 ~
conductive. A variety of well known control circuits canbe used to obtain this function.
System l~ operates as follows: Assuming it is desired to send information from Tl to T2, Ql is biased on by a control signal applied to gate terminal 26 and Q2 is biased off by a control signal applied to gate terminal 38.
A signal from Tl propagates through Al, Ql, Bus 1~ and is received at T2 and at the first plus input terminal of A2.
Circuitry 12 acts to amplify and/or level shift the information (signal) transmitted from Tl and reaches the first plus input terminal of ~1. It further acts to cause the load capacitance C3 to be reduced from the value that would result if Al were used but if CFl were not used.
Circuitry l~ acts as a single terminal negative capacitance generator which causes the effective value of C5 to be lower than would be the case if circuitry 14 were not coupled to terminal 28. The use of circuitry 14 as a single terminal negative capacitance is disclosed in the aforementioned Canadian application (R. M. Rolfe-M. Shoji 1-ll). No information propagates past output terminal 30 of A2 since Q2 is biased offO
If it is later desired to transmit (send) information from T2 to Tl, then Ql is biased off and Q2 is biased on. Circuitry 14 now acts to amplify and/or level shift the signal applied to the first plus input of A2. It further acts to cause the load capacitance C5 to be reduced from the value that would result if just A2 were used but if CF2 were not used. Circuitry 12 acts as a single terminal negative capacitance generator which causes the effective value of C3 to be lower than would be the case if circuitry 12 were not coupled to terminal 16. The use of circuitry 12 as a single terminal negative capacitance is disclosed in the a~orementioned Canadian Application ~ \
(R. M. Rolfe-M. Shoji l-ll). No information propagates past output terminal 18 of Al since Ql is biased off.
With Ql biased Oll and Q2 biased offl information can be trans~ni,tted from Tl through Al, Ql and Bus l and be received by T2 wlth the capacitance on terminal 16 being reduced by circuitry 12, the information being amplified and/or level shifted by A1, and the capacitance on terminal 28 being reduced by circuitry 14. With Q2 biased on and Ql biased off, inEormation can be transmitted from T2 through A2, Q2, and Bus 2 and be received by T2 with the capacitance on terminal 28 being reduced by circuitry 14, the information being amplified and/or level shifted by A2, and the capacitance on terminal 16 being reduced by circuitry 12. The reduction in the capacitive loadin~ on terminals 16 and 28 serves to enhance the response time of information transferred between Tl and T2.
In many useful cases the response time of amplifiers Al and A2 should be approximately two times or greater less than that of the enhanced response time expected and the gain of Al and A2 should be approximately two or greater. The response time of information received at Tl is proportional to the ratio of CFl to C3 and the response time of information received at T2 is proportional to the ratio of CF2 to C5. As these ratios of capacitance decrease the corresponding response time are enhanced (decreased).
The embodiments described herein are intended to be illustrative of the general principles of the invention.
Various modifications are possible consistent with the spirit of the invention. For example, switching devices Ql and Q2 could be bipolar transistors, JFETS, gated diode switches, or a variety of other types of switches.
Amplifier 1 and 2 could have different gains and response times and need not be identical. CFl and CF2 may also have different values as may C3, C4, C5, and C6. Still further~
Tl could be just a transmitter or ~ust a receiver and correspondin~Ly T2 could be just a receiver or a transmitter. Still further, additional transceivers, and/or receivers, and/or transmitters could be coupled to terminals 16 and 2~. Still further, separate voltage dividers can be inserted between the output terminal Al of circuitry 12 and the first outpu-t terminal of Ql and between the output terminal of A2 of circuitry 14 and the first output terminal of Q2 in order to attenuate information (signals) and/or to match the impedance of the bus being drivenO
IMPROVED RESPONSE TIME BIDIRECTIONAL CIRCUITRY
BACKGROUND OF THE INVENTION
This invention relates to circuitry for enhancing the speed of transfer of information from one source to another and specifically for providing a bilateral path between two transceivers with separate circuitry in each leg of the path which selectively acts to amplify/level shift and/or acts as a one termina:L negative capacitance generator which reduces capacitance loading and thus enhances response time.
Many of today's electronics systems use MOS
circuitry which selectively has to drive a relatively high capacitance line (bus). One avenue to try and enhance response time is to increase the physical size of all the MOS drive devices so as to increase the drive capability by lowering the resistance. This also increases the capacitance on the bus which degrades response time. A
point is reached at which i,ncreasing the size of the MOS
driver devices proportionally increases the capacitance on the bus such that there is little or no enhancement of response time.
The publication entitled Ap~lications of Operational Amplifier Third-Generation Techniques by .
Jerald Graeme (pp. 38-40), describes an amplifier which uses a capacitor coupled between an input terminal and the output terminal to cancel some of the parasitic capacitance associated with the input terminal of the amplifier. This serves to enhance the response time of the ampLifier but does little to enhance the response time through a heavily capacitively loaded data bus which may be coupled to the output of the ampliier.
A Canadian applicatlon Serial No. 417,099 filed December 6, 1982 in the name of R. M. Rolfe and M. Shoji, which is being fi:Led concurrently with the present appli-cation and in which there is a common assignee and one common inventor, discloses essentially a one terminal negative capacitance generator circuit which can be coupled to a data bus (conductor) and acts to reduce the loading capacitance thereon. This serves to enhance the response time of information sent through the conductor.
It is desirable in many instances to provide a bilateral path between two transceivers which includes amplification and/or level shiftincl circuitry and in which capacitive loading on electrical conduits (data buses) connecting the transceivers is reduced such that response time is enhanced.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention there is provided in combination first and second amplifiers each having a first input terminal and an output terminal; first and second capacitance means each having first and second texminals; the first and second terminals of the first capacitance means being coupled to the first input terminal and to the output terminal of the first amplifier, respectively; the first and second terminals of the second capacitance means being coupled to the first input terminal and to the output terminal of the second amplifier, respectively; the first input terminal of each of the first and second amplifiers being adapted to be coupled to a transmitter, a receiver, or a trans-ceiver; first and second switching devices each having a control terminal and first and second output terminals; a first electrical conduit (bus, data bus, conductor) having a capacitance associated therewith and being coupled by a first terminal thereof to the second output terminal of the first switching device and being coupled by a second terminal thereof to the first input terminal of the second amplifier; a second electrical conduit (bus, data bus, cond~lctor) having a capacitance associated therewith and being coupled by a first terminal to the second output terminal of the second switching device and being coupled - 2a -by a second terminal thereof to the first input terminal of the first amplifier; the output ~erminal of the first amplifier being coupled to the first output terminal of the first switching device; the output terminal of the second amplifier being coupled to the first output terminal of the first switching device; the gain of the first amplifier and the value of the first capacitance means being selected such that total load capacitance on the input terminal of the first amplifier is less than would be the case if the first capacitance means were not utilized; the gain of the second amplifier and the value of the second capacitance means being selected such that total load capacitance on the input terminal of the second amplifier is less than would be the case if the second capacitance means were not utilized; and the first and second switching devices being adapted to be coupled by the respective control terminals thereof to control means which selectively allows essentially only one of the switching means to be conductive at a given time.
One embodiment of the present invention is directed to bidirectional circuitry which couples two transceivers. The bidirectional circuitry essentially comprises two amplifiers, each of which has a separate capacitor coupled between amplifier input and output terminals and which may be denoted as an amplifier-capacitor combination, and two switching devices which each have a control terminal and first and second output terminals. The output terminal of the first amplifier is coupled through the output terminals of the first switching means to a first electrical conduit (bus or data bus) which is coupled to the second transceiver and to an input terminal of the second amplifier. The output terminal of the second amplifier is coupled through the output terminals of the second switching means to a second electrical condult (bus or data bus) which is coupled to - 2b -the first transceiver and to an input terminal of the first amplifier.
When it is desired to transmit information from the first transceiver to the second transceiver, the first switching is biased on and the second transceiver is biased off. Information passes from the first transceiver through the first amplifier~ the first switching device, the first bus, and to the second transceiver and to the input terminal of the second amplifierO The information cannot pass from the output terminal of the second amplifier since the second switching means is biased off. The first amplifier-capacitor combination acts to amplify and/or level shift the information and to reduce all load capacitance at the input terminal thereof Under these conditions the second amplifier-capacitor combination reduces load capacitance at the second transceiver by functioning essentially as a single terminal negative capacitance generator. The reduction of load capacitance serves to enhance the response time of information sent from the first to the second transceiver.
If it is desired to send information from the second to the first transceiver, then the second switching device is biased on and the first switching device is biased off. Information passes from the second transceiver through the second amplifier, the second switching device, the second bus and to the first transceiver and to the input of the first amplifier. Information cannot pass from the output terminal of the first amplifier since the first switching device is biased off~ The second amplifier-capacitor combination now acts to amplify and/or level shift the information and to reduce all load capacitance at the input terminal thereof. Under these conditions the first ampl;fier-capacitor combination reduces load capacitance at the first transceiver by functioning essentially as a single terminal negative capacitance generator. The reduction in load capacitance serves to enhance the response time of information sent from the second to the first transceiver.
It is thus clear that the first and second amplifier-capacitor combinations switch functions depending on the desired direction of the flow of information between the transceivers.
These and other novel features and advantages of the present lnvention are better understood from con~id*ration of the following detaLled description taken Ln conjunction with the accompanying drawing.
~t~
Brief Description of the Drawing The FIGURE il]ustrates an embodiment of the present invention.
Detailed Description Referring now to the FIGURE, there is illustrated a system 10 comprising a first transceiver Tl, a second transceiver T2, a first amplifier-capacitor combination illustrated within dashed line rectangle 12 and to be denoted as circuitry 12, a second amplifier~capacitor combination illustrated within dashed line rectangle 1~ and to be denoted as circuitry 14, switching device Ql having a control terminal 26 and first and second output terminals, a second switching device Q2 having a control terminal 38 and first and second output terminals, capacitors C3, C4, C5, C6 and C7 and electrical conduits Bus 1 and Bus 2O C3, C4, C5, C6 and C7 represent the total capacitive loading of all components and/or a sus on the terminal to which same is illustrated coupled.
System 10 is bidirectional in that analog or digital information may be transmitted from Tl to T2 or from T2 to Tl. Circuitry 12 and circuitry 14 provide amplification and/or level shifting and cause the capacitive loading between T1 and T2 to be reduced from what would exist if circuitry 12 and circuitry 1~ were not used. Thus the response time of signals transmitted between Tl and T2 is enhanced.
Circuitry 12 comprises a capacitance means which is illustrated as capacitor CFl, resistors Rl and R2, and an amplifier Al having a first plus input terminal~ a second minus input terminal, and an output terminal. The first plus input terminal of Al is coupled to a first terminal oE CFl, to an input/output terminal of Tl, to a Eirst terminal of C3, to a second output terminal of Q2 (which is illustrated as an MOS transistor) through Bus 2, and to Eirst system terminal 16. The output terminal of Al is coupled to a second terminal of CFl, a first output terminal of Ql (which is illustrated as an MOS transistor), to a first terminal of R2, to a first terminal of C4, and to a second system terminal 18. Rl is illustrated coupled by a first terminal to a second terminal of R2, to the second minus input terminal of Al and to a terminal 20. A
second terminal of Rl is coupled to a potential source VRef and to a terminal 22. Rl and R2 are used to set the gain of Al and are not always needed as some amplifiers may have preselected gains. The parasitic capacitance of the first plus input terminal of Al is not explicitly illustrated and labeled but is included as part of C3. Second terminals of C3 and C4 are coupled to a ground terminal Gnd 1 and to a terminal 24.
Circuitry 1~ comprises a capacitance means illustrated as a capacitor CF2, resistors R3 and R~, and an amplifier A2 having a first plus input terminal, a second minus input terminal, and an output terminal. The first plus input terminal of A2 is coupled to a first terminal of CF2, to an input/output terminal of T2, to a first terminal of C5, to a second output terminal of Ql through an electrical Bus 1, and to a third system terminal 28. The output terminal of A2 is coupled to a first terminal of C6, to a first output terminal of Q2, to a first terminal of R4, and to a fourth system terminal 30. A second terminal of R4 is coupled to the second minus input terminal of A2, to a first terminal of R3, and to a terminal 32. A second terminal of R3 is coupled to a potential source VRef2 and to a terminal 34. Second terminals of C5 and C6 are coupled to a ground terminal Gnd 2 and to a terminal 36.
R3 and R4 are used to set the gain of A2 and are not always needed as some amplifiers have preselected gains. The parasitic capacitance of A2 is not explicitly illustrated and labeled but is included as part of C5.
The control (gate) terminals of Tl and T2 are typically coupled to control circuitry (not illustrated) which provides sic~nals that allow essentially only one of Tl or T2 to conduct inEormation (signals) between the output terminals thereof while the other is held non-L~
-- 6 ~
conductive. A variety of well known control circuits canbe used to obtain this function.
System l~ operates as follows: Assuming it is desired to send information from Tl to T2, Ql is biased on by a control signal applied to gate terminal 26 and Q2 is biased off by a control signal applied to gate terminal 38.
A signal from Tl propagates through Al, Ql, Bus 1~ and is received at T2 and at the first plus input terminal of A2.
Circuitry 12 acts to amplify and/or level shift the information (signal) transmitted from Tl and reaches the first plus input terminal of ~1. It further acts to cause the load capacitance C3 to be reduced from the value that would result if Al were used but if CFl were not used.
Circuitry l~ acts as a single terminal negative capacitance generator which causes the effective value of C5 to be lower than would be the case if circuitry 14 were not coupled to terminal 28. The use of circuitry 14 as a single terminal negative capacitance is disclosed in the aforementioned Canadian application (R. M. Rolfe-M. Shoji 1-ll). No information propagates past output terminal 30 of A2 since Q2 is biased offO
If it is later desired to transmit (send) information from T2 to Tl, then Ql is biased off and Q2 is biased on. Circuitry 14 now acts to amplify and/or level shift the signal applied to the first plus input of A2. It further acts to cause the load capacitance C5 to be reduced from the value that would result if just A2 were used but if CF2 were not used. Circuitry 12 acts as a single terminal negative capacitance generator which causes the effective value of C3 to be lower than would be the case if circuitry 12 were not coupled to terminal 16. The use of circuitry 12 as a single terminal negative capacitance is disclosed in the a~orementioned Canadian Application ~ \
(R. M. Rolfe-M. Shoji l-ll). No information propagates past output terminal 18 of Al since Ql is biased off.
With Ql biased Oll and Q2 biased offl information can be trans~ni,tted from Tl through Al, Ql and Bus l and be received by T2 wlth the capacitance on terminal 16 being reduced by circuitry 12, the information being amplified and/or level shifted by A1, and the capacitance on terminal 28 being reduced by circuitry 14. With Q2 biased on and Ql biased off, inEormation can be transmitted from T2 through A2, Q2, and Bus 2 and be received by T2 with the capacitance on terminal 28 being reduced by circuitry 14, the information being amplified and/or level shifted by A2, and the capacitance on terminal 16 being reduced by circuitry 12. The reduction in the capacitive loadin~ on terminals 16 and 28 serves to enhance the response time of information transferred between Tl and T2.
In many useful cases the response time of amplifiers Al and A2 should be approximately two times or greater less than that of the enhanced response time expected and the gain of Al and A2 should be approximately two or greater. The response time of information received at Tl is proportional to the ratio of CFl to C3 and the response time of information received at T2 is proportional to the ratio of CF2 to C5. As these ratios of capacitance decrease the corresponding response time are enhanced (decreased).
The embodiments described herein are intended to be illustrative of the general principles of the invention.
Various modifications are possible consistent with the spirit of the invention. For example, switching devices Ql and Q2 could be bipolar transistors, JFETS, gated diode switches, or a variety of other types of switches.
Amplifier 1 and 2 could have different gains and response times and need not be identical. CFl and CF2 may also have different values as may C3, C4, C5, and C6. Still further~
Tl could be just a transmitter or ~ust a receiver and correspondin~Ly T2 could be just a receiver or a transmitter. Still further, additional transceivers, and/or receivers, and/or transmitters could be coupled to terminals 16 and 2~. Still further, separate voltage dividers can be inserted between the output terminal Al of circuitry 12 and the first outpu-t terminal of Ql and between the output terminal of A2 of circuitry 14 and the first output terminal of Q2 in order to attenuate information (signals) and/or to match the impedance of the bus being drivenO
Claims (6)
1. In combination:
first and second amplifiers each having a first input terminal and an output terminal;
first and second capacitance means each having first and second terminals;
the first and second terminals of the first capacitance means being coupled to the first input terminal and to the output terminal of the first amplifier, respectively;
the first and second terminals of the second capacitance means being coupled to the first input terminal and to the output terminal of the second amplifier, respectively;
the first input terminal of each of the first and second amplifiers being adapted to be coupled to a transmitter, a receiver, or a transceiver;
first and second switching devices each having a control terminal and first and second output terminals;
a first electrical conduit (bus, data bus, conductor) having a capacitance associated therewith and being coupled by a first terminal thereof to the second output terminal of the first switching device and being coupled by a second terminal thereof to the first input terminal of the second amplifier;
a second electrical conduit (bus, data bus, conductor) having a capacitance associated therewith and being coupled by a first terminal to the second output terminal of the second switching device and being coupled by a second terminal thereof to the first input terminal of the first amplifier;
the output terminal of the first amplifier being coupled to the first output terminal of the first switching device;
the output terminal of the second amplifier being coupled to the first output terminal of the first switching device;
the gain of the first amplifier and the value of the first capacitance means being selected such that total load capacitance on the input terminal of the first amplifier is less than would be the case if the first capacitance means were not utilized;
the gain of the second amplifier and the value of the second capacitance means being selected such that total load capacitance on the input terminal of the second amplifier is less than would be the case if the second capacitance means were not utilized; and the first and second switching devices being adapted to be coupled by the respective control terminals thereof to control means which selectively allows essentially only one of the switching means to be conductive at a given time.
first and second amplifiers each having a first input terminal and an output terminal;
first and second capacitance means each having first and second terminals;
the first and second terminals of the first capacitance means being coupled to the first input terminal and to the output terminal of the first amplifier, respectively;
the first and second terminals of the second capacitance means being coupled to the first input terminal and to the output terminal of the second amplifier, respectively;
the first input terminal of each of the first and second amplifiers being adapted to be coupled to a transmitter, a receiver, or a transceiver;
first and second switching devices each having a control terminal and first and second output terminals;
a first electrical conduit (bus, data bus, conductor) having a capacitance associated therewith and being coupled by a first terminal thereof to the second output terminal of the first switching device and being coupled by a second terminal thereof to the first input terminal of the second amplifier;
a second electrical conduit (bus, data bus, conductor) having a capacitance associated therewith and being coupled by a first terminal to the second output terminal of the second switching device and being coupled by a second terminal thereof to the first input terminal of the first amplifier;
the output terminal of the first amplifier being coupled to the first output terminal of the first switching device;
the output terminal of the second amplifier being coupled to the first output terminal of the first switching device;
the gain of the first amplifier and the value of the first capacitance means being selected such that total load capacitance on the input terminal of the first amplifier is less than would be the case if the first capacitance means were not utilized;
the gain of the second amplifier and the value of the second capacitance means being selected such that total load capacitance on the input terminal of the second amplifier is less than would be the case if the second capacitance means were not utilized; and the first and second switching devices being adapted to be coupled by the respective control terminals thereof to control means which selectively allows essentially only one of the switching means to be conductive at a given time.
2. The combination of claim 1 wherein the gain of the first and second amplifiers is two or greater and the response time of the first amplifier is approximately two times or greater less than that of a desired response time of information transmitted through the second electrical conduit and the response time of the second amplifier is approximately two times or greater less than that of a desired response time of information transmitted through the first electrical conduit.
3. The combination of claim 2 wherein:
the output terminals of the first and second amplifiers are non-inverting output terminals;
the first input terminals of the first and second amplifiers are plus input terminals; and the first and second amplifiers each have a second minus input terminal.
the output terminals of the first and second amplifiers are non-inverting output terminals;
the first input terminals of the first and second amplifiers are plus input terminals; and the first and second amplifiers each have a second minus input terminal.
4. A system comprising:
first and second transceivers;
first and second amplifiers each having at least one input: terminal and an output terminal;
first and second capacitance means each having first and second terminals;
first and second switching means each having a control terminal and first and second output terminals;
the first transceiver being coupled to a first input terminal of the first amplifier, to the first terminal of the first capacitance means, to a second output terminal of the second switching means through a second electrical conduit, and to a first system terminal;
the second terminal of the first capacitance means being coupled to the output terminal of the first amplifier, to the first output terminal of the first switching means, and to a second system terminal;
the second transceiver being coupled to a first input terminal of the second amplifier, to the first terminal of the second capacitance means, to a second output terminal of the first switching means through a first electrical conduit, and to a third system terminal;
the second terminal of the second capacitance means being coupled to the output terminal of the second amplifier, to the first output terminal of the second switching device, and to a fourth system terminal; and the first and second switching means being adapted to be coupled by the respective control terminals thereof to control means which selectively allows essentially only one of the switching means to be conductive at a given time.
first and second transceivers;
first and second amplifiers each having at least one input: terminal and an output terminal;
first and second capacitance means each having first and second terminals;
first and second switching means each having a control terminal and first and second output terminals;
the first transceiver being coupled to a first input terminal of the first amplifier, to the first terminal of the first capacitance means, to a second output terminal of the second switching means through a second electrical conduit, and to a first system terminal;
the second terminal of the first capacitance means being coupled to the output terminal of the first amplifier, to the first output terminal of the first switching means, and to a second system terminal;
the second transceiver being coupled to a first input terminal of the second amplifier, to the first terminal of the second capacitance means, to a second output terminal of the first switching means through a first electrical conduit, and to a third system terminal;
the second terminal of the second capacitance means being coupled to the output terminal of the second amplifier, to the first output terminal of the second switching device, and to a fourth system terminal; and the first and second switching means being adapted to be coupled by the respective control terminals thereof to control means which selectively allows essentially only one of the switching means to be conductive at a given time.
5. The combination of claim 4 wherein the gain of the first and second amplifiers is two or greater and the response time of the first amplifier is approximately two times or greater less than that of a desired response time of information transmitted through the second conductor and the response time of the second amplifier is approximately two times or greater less than that of a desired response time of information transmitted through the first conductor.
6. The combination of claim 5 wherein:
the output terminals of the first and second amplifiers are non-inverting output terminals;
the first input terminals of the first and second amplifiers are plus input terminals; and the first and second amplifiers each have a second minus input terminal.
the output terminals of the first and second amplifiers are non-inverting output terminals;
the first input terminals of the first and second amplifiers are plus input terminals; and the first and second amplifiers each have a second minus input terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US333,445 | 1981-12-22 | ||
| US06/333,445 US4434497A (en) | 1981-12-22 | 1981-12-22 | Response time bidirectional circuitry |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1183914A true CA1183914A (en) | 1985-03-12 |
Family
ID=23302816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000417100A Expired CA1183914A (en) | 1981-12-22 | 1982-12-06 | Response time bidirectional circuitry |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4434497A (en) |
| CA (1) | CA1183914A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4736385A (en) * | 1987-01-27 | 1988-04-05 | Computer Network Technology Corporation | Transmitter and receiver circuit |
| US6359315B1 (en) * | 2000-08-03 | 2002-03-19 | Cirrus Logic, Inc. | Circuits for controlling a bidirectional terminal and systems using the same |
-
1981
- 1981-12-22 US US06/333,445 patent/US4434497A/en not_active Expired - Fee Related
-
1982
- 1982-12-06 CA CA000417100A patent/CA1183914A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4434497A (en) | 1984-02-28 |
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