CA1182584A - Gate enhanced rectifier - Google Patents
Gate enhanced rectifierInfo
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- CA1182584A CA1182584A CA000397265A CA397265A CA1182584A CA 1182584 A CA1182584 A CA 1182584A CA 000397265 A CA000397265 A CA 000397265A CA 397265 A CA397265 A CA 397265A CA 1182584 A CA1182584 A CA 1182584A
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Abstract
GATE ENHANCED RECTIFIER
ABSTRACT OF THE DISCLOSURE
A high power semiconductor rectifier is constructed so that the rectifier is normally off and can be switched on by applying a bias signal to a gate of a metal-insulator-semiconductor structure monolithically integrated with the rectifier in such a manner as to induce a conducting channel between the anode and cathode of the rectifier. The device has both forward and reverse blocking capability and a low forward voltage drop when in the conducting state. The device has a very high turn-off gain and both high dV/dt and di/dt capabilities.
ABSTRACT OF THE DISCLOSURE
A high power semiconductor rectifier is constructed so that the rectifier is normally off and can be switched on by applying a bias signal to a gate of a metal-insulator-semiconductor structure monolithically integrated with the rectifier in such a manner as to induce a conducting channel between the anode and cathode of the rectifier. The device has both forward and reverse blocking capability and a low forward voltage drop when in the conducting state. The device has a very high turn-off gain and both high dV/dt and di/dt capabilities.
Description
RD 13,112 GATE ENHANCED RECTIFIER
Back round of the Invention g This invention relates to power field effect semiconductor devices, and more particularly, to field controlled semiconductor rectifiers having a field effect controlstructure monolithically integrated with the - rectifier structure.
For power switching applications, in such electrical systems as motor drives and low to medium frequency (0-2000H~ power suppliesl high speed and low loss performance at high current and high voltage levels is desirable. Prior art three terminal devices which can be used to control power delivered to a load include the MOSFET and the MOS gate thyristor. Prior art power MOSFET's include those described in U.S. Patent NoO ~,072,975, issued February 7, 1978 to Ishitani and U.S. Patent No.
4,145,703 issued March 20, 1979 to Blanchard. Typical eross sections of power MOSFET deviees are shown schemati-cally in Figs. 1 and 2 and their operating characteristics are shown in Fig. 3. These devices have been fabricated by using either planar diffusion techniques -to form a DMOS structure 20 as shown in Fig. 1, or by etching V-grooves to form a VMOS structure 21 as shown in Fig. 2.
In each case, for positive voltages applied to th~ drain, the junctions 22, 23 between the P-base regions 24, 25 and the N-drift regions 26, 27 in Figs. 1 and 2 respectively, block eurrent flow between the drains 2~, 29 and the sources 30, 31 in the absence of gate biases. Application of a sufficiently large positive gate bias with refer-ence to the source results in the formation of an n-type inversion layer 32, 33 in the respective p~base reyions under the gate electrodes 3~, 35, respectively. This RD 13,112 inversion layer allowsconduction of electrical current from the drain to the source producing the forward conduction characteristics shown in Fig. 3. Increasing the gate bias, e.g., from VGl through VG5, increases the conductivity of the inversion layer and thus allows higher drain current ID to flow. For negative voltages applied to the drain, the device conducts current like a forward biased p-n junction diode and cannot block current flow.
As a result, these devices are operated with only positive voltages applied to the drain.
In MOSFET devices, only majority carrier (electron) current flow occurs between drain and source.
This current flow is consequently limited by the majority carrier (electrons here) concentration in the channel and drift regions which determines their resistivity. For devices designed for operation at greater than 100 volts, the resistance o~ the drift region becomes large because the majority carrier concentration in the drlft region must be small and the drift region width (W) must be large in order to support the device blocking voltages.
Due to the high drift region resistance, high voltage MOSFET devices must be operated at low current densities to obtain low forward voltage drops. A typical current density of operation is about 50 A/cm2 a~ a forward voltage drop of 1.5 volts for a device capable of blocking up to 600 volts.
Despite this drawback of a high on-resistance, power MOSFBT's have the advantage of requiring lower gate drive po~Jer levels than bipolar transistors since the gate voltage signal is applied across an insulating film.
In these devices the drain current can also be turned off by bringing the gate voltage down to the source potential.
RD 13,112 This gate turn-off can be achieved with a higher current gain than for bipolar transistors.
Another type of prior art device is the MOS
gated thyristor. Typical devices are disclosed in sritish patent No. 1,356,670, published June 12, 1974, U.S. Patent No. 3,753,055, issued August 14, 1973 to Yamashita et al., and U.S. Patent No. 3,831,187, issued August 20, 1974 to Neilson. A MOS gated thyristor is a pnpn thyristor structure, shown schematically in Figs. 4 and 5, in which regenerative turn-on can be initiated by application of a voltage to an MOS gate. In the device 40 of Fig. 4, the MOS gate is formed on a surface 41 extending from the N+ cathode 42 through the P-base 43 into a small portion of the N-base 44. In the device 50 of Fig. 5, the MOS
gate is formed on a surface 51 extending alony V-groove 52 from the N+ cathode 53 through the P-base layer 5~
into N base 55. These devices will block current flow with either positive or negative voltages applied to their anodes 45, 56 in the absence of the gate bias.
However, for positive anode voltages, the devices can be triggered into the conducting mode by application of a suitable positive voltage on the respective gates 46, 57.
When a positive gate voltage is applied, the electric field across the gate oxide layers 47, 58 produces a depletion of carriers in the p-base under the gate electrode. As a result, the depletion layer in the p-base extends closer to the N+ cathode region under the gate. This reduces the thickness of t.he undepleted p-base region of the upper NPN transistor under the gate electrode and thus increases its current gain. It is well known that a pnpn thyristor structure will switch from a current blocking state to a current conducting ~ RD 13,112 iLW 5~ 3 :~
state when the sum of the current gains of the NPN and ~ ~ NPN and ~PNP~ respectively~ exceeds unity. In the MOS gated thyristor, as the gate bias is increased, the gain of the upper NPN transistor increaseS until ~NPN + ~PNP Y
point strong injection of carriers must occur from the N+
cathode into the p-base for the device to switch to the on-state. This requires that the N+ P junction become forward biased by more than 0.5 volts. Once this takes place, the device switches to the conducting state and removal of the gate bias voltage will not cause the device to return to the blocking state because of the self-sustaining regenerative action inherent in the pnpn thyristor structure. Thu$, these devices have the advantage of requiring low gate power to turn-on the thyristor via the MOS gate, but do not exhibit gate turn-off capability. Thus/ the device must be returned to the blocking state by reversal of the anode polarity.
The characteristics of the MOS gated thyristor are shown in Fig. 6, which show that these devices exhibit a negative resistance characteristic.
Summary of the Invention An object of the instant invention is to provide a field effect controlled, high current capacity rectifier that has both forward and reverse blocking capabilities and a low forward voltage drop, which can be switched on and off with a small gate voltage wi-th very low current, and therefore, low power re~uirement.
A further object is to provide a device which will have a very high gate turnoff gain, high di/dt capability, and high dV/dt capability. Further ob~ects include providing a device which will operate at elevated temperature and RD 13,112 radiation levels without damage.
Accordingly, the instant invention incorporates a monolithically integrated combination of a rectifier with a field effect control structure to control the on-off state of the rectifier by inducing a channel of conductivity within a region of the rectifier to control the on-off condition of pn junctions within the rectifier.
The rectifier includes a multiple layer structure within a body of semiconductor material having one contact on one su1face of the body and another contact on another surface of the bodv. The field eEfect control structure induces a channel of conductivity through one element of the rectifier to provide an electrically conductive path connecting one of the contacts with a second element of the rectifier.
Brief Description of the Drawings The features of the invention believed to be novel and unobvious over the prior art are set forth with particularity in the appended claims. The invention itself, however, as to organization, method of operation and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference characters refer to like elements throughout, and in which:
Figs. l and 2 are schematic partial cross~
sectional views of power MOS gated field effect transistors;
Fig. 3 is a graphical illustration of the device characteristics of the transistors shown schematically in ~igs. 1 and 2;
Figs. 4 and 5 are schematic partial cross-sectional views of MOS gated thyristors;
~D 13,112 Fig. 6 is a graphical illustration of typical device characteristics of the thyristors illustrated in Figs. 4 and 5;
Fig. 7 is a pictorial schmatic partial cross-sectional view of a gate controlled rectifier according to the instant invention;
Figs. 8-13 are schematic partial cross-sectional views of alternate embodiments of the gate controlled rectifier according to the instant invention;
Fig. 14 is a graphical representation of the device characteristics of the gate controlled rectifier of the instant invention; and Fig. 15 is a comparative graphical illustration of typical switching wave forms for the prior art devices and the gate controlled rectifier of the instant invention.
Description of the Preferred Embodiments One form of the basic device structure of the instant invention is illustrated in Fig. 7. The device 60 includes a body 61 o~ semiconductor material, such as silicon, in which a first layer 62 of one type conductivity, P in Fig. 7, and a base region 63 of opposite conductivity, N in Fig. 7, is included. A
first layer 62 can be made by diffusion into a body to produce the anode-base structure of the device, or a body of the conductivity type desired may have a layer grown epitaxially thereover to produce the two-layer combination. A plurality of islands 64, here of P type conductivity, is provided by diffusion or other suitable technique within layer 63 in spaced relationship contiguous with the free surface 65 of the body 61. Adjacent island ~ 5~L~ RD 13,112 6~, an N-~ island 66 is formed within the base layer 63.
Typical doping levels for the N type layer 63 are in the range of 10 to 10 cm of N type carriers, for the P type anode layer 62 typical doping concentrations are in the range of 10 8 to 10~ cm 3 of P type carriers;
for the P type islands 64 typical doping concentrations are 1016 to 10l8 cm 3; and for the N+ islands 66 typical doping concentrations are 10 to 10 cm 3. A layer 67 of dielectric material is Eormed over a portion of free surface 65 including part of the outer surface of adjacent ones of the islands 64 and the region of base layer 63 separating the adjacent islands 64 including island 66. A contact 68, 69 of conductive material, such as aluminum or conductive polycrystalline silicon, is formed over the dielectric layer 67 each overlapping a part of an island 64 and a part of the base layer 63 adjacent the island 64 to serve as a gate electrode. A layer 70 of conductive material such as aluminum or conduc-tive poly-crystalline silicon is deposited over the cen-ter of each of the islands 64 to form an ohmic contact thereto. On the surface 71 of the body 61 a layer 72 of conductive material, such as aluminum or conductive polycrystalline silicon, is deposited to form an ohmic contact to the layer 62. Although stripes are shown for the upper surface patter of the conductive contact 68, 69 and 70 in Fig. 7, it will be appreciated by those skilled in the art that many repetivie geometric contact patterns, such as small contact pads arranged on the surface in closely spaced relationship, could be used. The device is highly interdigitated, e.g., the width of individ-ual stripes is small and the total number of stripes large. The pattern is repeated in the lateral direction to cover the entire ~ RD 13,112 semiconductor device. Each of the conductive contacts extends to one lateral edge of the device, where the contacts 68, 69 are connected to a source of electrical potential, contacts 70 are connected to a source of electri-cal potential of a polarity different from that of the source connected to contacts 68, 69 and contact 72 is connected to a source of electrical potential of a polarity different from that of the source connected to contacts 70.
The device shown in Fig. 7 exhibits the operating characteristics shown in Fig. 14 and operates as follows.
With the contact 70 at ground potential, and no bias supplied to the gate electrode 68, negative voltages applied to the contact 72 result in no curren-t flow because the junction 73 is reversed biased. This provides reverse blocking capability. With no bias supplied to the gate electrode 68, positive voltages supplied to the contact 72 will again result in no current flow because the junction 74 will be reversed biased. This provides the forward blocking capability as well as a desired normally off device chaxacteristic. However, if a positive bias is applied to the gate electrode 68, an inversion layer extending from the ohmic contact 70 to the N-base 63 can be foxmed under the gate in the p base in the region 78 of island 64 immediately beneath the insulating layer 67, and an N accumulation layer of charge carriers can be formed in the region 79 of the N base 63. The N-type inversion layer now in region 78 of P island 64 and the accumulation layer in the region 79 of the N base now connect the ohmic contact 70 to the N+ island 66 in the middle of the device. A
positive bias applied to the con-tact 72 will now result in current flow from the P+ layer 62 functioning as an ~ Rb 13,112 anode to the N+ island 66 and then via the N-type accumulation layer 79 and the N-type inversion layer 78 to the contact 70 functioning as a cathode. The path from the layer 62 to the N+ island 66 functions analogously to a p-i-n diode, shown at 80 in Fig. 7, and the field effect control region is outlined at 8l. The conduc-tivity of the current path through the N-base 63 between the P+ layer 62 and the N+
island 66 will be modulated (increased) by the current flow due to injection of a high concentration of minority carriers (holes here) into the N-base 63 from the layer 62. Since the voltage is supported across the N-base 63 in the forward and reverse blocking modes, the wid-th W of the path between the P+ layer 62 and the P island 64 determines the maximum blocking voltages. For high voltage performance this width must be increased. The conductivity modulation flow is consequently very important for achieving a low forward voltage drop at high forward current densities in high voltage devices. A
typical forward current density of operation is about 500 A/cqn at a forward voltage drop of 1.5 volts for a device capable of blocking up -to 600 volts. If all the conductivity types are reversed, similar performance characteristics can be obtained with electrical potentials of opposite polarities applied to the conductive contacts.
An alternative embodiment of the gate controlled rectifier of the instant invention is shown schematically in Fig. 8. The device 90 of Fig. 8 differs from that of Fig. 7 in omitting N+ island 66. The elimination of the island 66 requires that adequate potential be applied -to gate contact 91 to create an accumulation layer 99 under dielectric layer 67 to produce a region of N type carriers below the gate. To accomplish this with the lowest spreading resistance in the path of current flow RD 13,112 5~
beneath the gate requires that a gate contact 91 extend across the entire width of the gate region connecting the adjacent islands 64. A contact of lesser width would create the necessary accumulation layer 99 of N carriers beneath the gate to provide the function of the N+
islands 66, when adeauate potential is applied to the gate. This decrease in the area of the gate will result in a decrease in the gate capacitance. When a positive bias is applied to the gate of the field effect control structure outlinedat 93, a three layer structure is formed in the region outlined by dashed rectangle 92 which functions as a p-i-n structure. The current path through the rectifier includes the layer 62, n base region 94 n accumulation layer 99, an inversion layer 99, and inversion layer 79 and ohmic contact 70.
A further embodiment of my invention is schematically illustrated in Fig. 9. The device 100 includes P region 62, base region 94, P islands 102 and a plurality of N~ islands 101 within each of the P islands 102. In this embodiment, the islands 101 provide a contact between the inversion layer in the islands 102 and the conductive contact 70. A pair of conductive contacts 107 separated by gap 108 is disposed on dielectric layer 67 to overlap a portion of the islands 101, a region of the islands 102 and a portion of the base 94.
Application of a positive gate bias to a control electrode 107 within dashed outline 103 will produce an accumulation layer in the N base region immediately under the gate, and an inversion layer in the P island 102 immediately under the dielectric layer 67 e~tending from the N-~
island 101 to the N-base 94 completing the current path from the M base through the P island 102 to the N-~
~ RD 13,112 island 101. This structure ineludes a parasitic p-n-p-n thyristor through the anode 62, base 94, P island 102 and n+ islands 101 in the region outlined at 106. To achieve the desired device performance of this device in switching off upon removal of the gate bias, it is very important that the regenerative turn-on mechanism in this parasitie thyristor be suppressed.
This can be aceomplished by preventing the N+
islands 101 from injeeting eleetrons into the respeetive P islands 102, eonsequently preventing the initiation of the regenerative turn-on meehanism of the p-n-p-n thyristor. The suppression of the injeetion of earriers from the N+ islands 101 can be accomplished by forming the N+ islands 101 with a small lateral dimension (L).
The lateral dimension ~L) of the N+ islands 101 must be small enough so that, when the deivce is conducting current from the ehannel ~8 to the eathode contact 70 r the forward bias of the junetion 105 between the N-~ islands 101 and the P-island 102 does not exceed 0.5 volts.
~nother technique whieh eould be used to suppress the regenerative turn-on of the p-n-p-n thyristor is the introduetion of recombination centers in the p-region 102 and the N-base 94 so as to reduce the gains ~NPN and ~PN
Reeombination eenters can be provided by diffusion of deep level impuritiesl such as gold, into the substrate or by irradiation of the substrate with high energy partieles sueh as eleetrons.
Distinguishing features between a MOS gated thyristor, such as that shown in Fig. 4/ and the device of this invention, shown in Fig. 9, are firstly, that the device of this invention eontains N+ regions 101 of much smaller la-teral dimension (L) RD 13 ,112 to prevent the reyenerative turn-on action characteristic of the MOS gated thyristor. Secondly, in the gate enhanced rectifier, the anode current flows solely via the conductive channel formed in the P-island 102 to the cathode contact 70 when the device is conducting current, while the current of the MOS gated thyristor flows vertically throughout the P-island 102 underneath the N~ island 101. Thirdly, in the gate enhanced rectifier, the anode current can be terminated by removal of the gate voltage applied to induce the conducting channel in the P-islands 102, while the anode current of the MOS gated thyristor will continue to flow after removal of the gate voltage due to the self-sustaining nature of the regenerative pnpn thyristor action. It is noted that the embodiment in Fig. 8 avoids this problem by elimination of the N+ islands within the P islands 102.
In the alternative embodiment shown in Fig. 10, N~ island 111 filling the entire width between adjacent P islands 114 and the N base 113 and impinging upon a portion of the P islands is formed in the N base. When a positive bias is applied to the gate 115 an inversion layer is created in the region of the P islands immediately under the gate and the current path from the N~ island 111 to the cathode contact 11~ is completed, thereby turning the device on and allowing current to flow through the p-i-n diode outlined at 112 and via the inversion layer to the cathode contact 116.
In the embodiment shown in Fig. 11, N-~ islands 125 have been added to the P islands 124 of the device 120 which provide current flow paths from the inversion layer in the P-islands 124 to the conductive contact 116, when a positive bias is applied to electrode 117 in gate structure ~ 5~ RD 13,112 118 to turn on the p-i-n diode 119. This embodiment also contains the parasitic pnpn thyristor described with reference to the embodiment shown in Fig. g. As discussed earlier with reference to Fig. 9, the regenerative turn-on mechanism of this parasitic thyristor must be suppressed by maintaining a small lateral dimension (L) for the N+ island 125 and by providing recombination centers in the P-islands 124 and the N-base 113. It is noted that the embodiment of Fig. 10 avoids this problem by elimination of the n+ islands within the p islands 102.
In device 130 shown schematically in Fig. 12, highly doped P+ islands 133 have been added to the P
islands 132 in the N base 131. The current path includes the p-i-n diode 134 created when a positive bias relative to the conductive contact 137 is applied to the gate 136 in the gate controlled structure 135 to produce an accumulation layer immediately under the dielectric layer 67. ~n inversion layer is produced in P island 132 between the P+ island 133 and the N-base 131 to allow current flow from the anode to the cathode.
~ further alternative device structure employing my invention is shown schematically in Fig. 13. The body of semiconductor material for device 140 has a liyhtly doped N-base region 141 and a more heavily doped N-base region 142. Within base region 142 P+ islands 143 are formed adjacent to one major free surface 144 of the body. P
islands 14S are formed into the N-region 141 and ~he N+
islands 150 are formed into the P islands 145 adjacent the other major surface 146 of the body. For a given forward conduction current density this structure provides a lower forward voltage drop in the diode 152 than -the previously described embodiments for the same forward ~ 13 -~ RD 13,112 blocking capability. However, the reverse blockiny capability is reduced to the shorting of the islands 143 by conductive contact 147. The operating characteristics of this device are similar to those of the other embodi-ments when a forward bias is applied. When a reverse bias is applied to the conductive contact 147 in the absence of a bias on gate electrode 148 in gate controlled structure 151, a substantially different characteristic is produced as shown at 160 in Fig. 14, in that breakdown occurs at a much lower reverse bias.
The operating characteristics of the gate controlled rectifier are shown in Fig. 14. In this device, the junction 73 blocks current flow when negative voltages are applied to the anode contact 72 providing the device with reverse blocking capability up to the level at which breakdown occurs as seen at 161. When positive voltages are applied to the anode contact 72, junction 74 becomes reverse biased and blocks current flow, thus providing the forward blocking capability in the absence of gate bias up to the level at which breakdown occurs as seen at 162. However, if a positive bias is applied to the gate, a path is created for the current to flow from the anode junction 73 to the cathode contact 70 producing the characteristics shown for each of the gate voltages VGl - VG4. At large gate voltages (VG4) the inversion layer conductivity will be high and the device will exhibit characteristics like those of a pn junction diode.
In this case the anode P~ region injects minority carriers into the n-base and strongly modulates (increases~ the conductivity of the n~base. As a result of this, the device can be operated at high current densities (typically 500 A/cm ) with a low forward voltage drop (about 1.5 volts).
RD 13,112 5~
At lower gate voltayes (VGl, VG2~ G3)~
flow can become limited by the conductivity o the inversion layer producing the current saturation shown in Fig. 14. These devlce characteristics are distinguishable from those of other prior art devices. When compared with the MOSFET, the gate enhanced rectifier can be operated at much higher current densities due to the modulation of the conductivity of the N-base by the anode current flow.
Unlike the MOSFET, these devices also exhibit reverse bloc]~ing capability. When compared with the MOS gated thyristor, the gate enhanced rectifier is distinguished by the absence of a negative resistance re~ion in the forward characteristics. This negative resistance region in the thyristor arises from the regenerative turn-on phenonenon which is absent in the gate enhance rectifier.
Unlike the MOS gated thyristor~ no self-sustaining regenerative turn-on occurs in the gate enhanced rectifier device. Consequently, if the gate voltage is reduced to the cathode potential while the device is conducting current, the inversion layer under the gate electrode will cease to exist and the anode current will turn off. This turn-off occurs in two stages. First, most of the injected stored charge in the N base is removed by current flow across the j~nction 74 to p region 145 until it becomes reverse biased. After this point, the rest of the minority carrier stored charge will decay by recombination.
A comparison of the switching characteristic of the MOSFET, -the MOS gate thyristor and the gate enhanced rectifier can be done with the aid of Fig. 15. In this figure, the gate voltage is turned on at times tl and e.s ~ and turned off at ~e t2 for all three cases as shown by ~D 13,112 trace 164. At -time t2, the MOSFET turns off rapidly as seen in trace 165 the duration of the turn-off transient being determined by the charging of the gate capacitance.
However, the MOS gated thyristor continues to conduct current even after the gate voltage is reduced to zero at time t2 as shown by trace 166, because the current flow is sustained by the internal regenerative mechanism in these devices. In contrast, the gate enhanced rectifier turns off at time t2 as shown by trace 167 because the inversion layer under the gate electrode will cease to exist when the gate voltage is reduced to zero and this will interrupt the current flow path between the anode and cathode terminals. In this case, the minority carriers injected by the anode into the N-base to modulate its conductivity during forward current conduction will be removed by conduction across junction 74 until it becomes reverse biased as shown at point 168. Any remaining minority carriers wil] then decay by recombination.
Consequently, the ~ate enhanced rectifier turns off at time t2 like the MOSFET but does so more slowly due to the bipolar current conduction. It should be noted that this slower switching speed of the gate enhanced rectifier is adequate for many applications such as motor drives, while its lower forward ~oltage drop when compared with the MOSFET is a major advantage, because it reduces the power dissipated and thus improves the power switching efficiency. Other advantages are better surge current handling capability, higher operating t~mperature capability and elevated radiation level tolerance made possible by the suppression of regenerative turn-on described above.
It will be appreciated by those skilled in the art that the conductivity types shown in the figures - ]6 -~ 4 RD 13,1].2 and described above are only illustrative and the polarities of the regions may be reversed without significantly arfecti.ng performance. This is especially useful in the construction of complementary devices.
Back round of the Invention g This invention relates to power field effect semiconductor devices, and more particularly, to field controlled semiconductor rectifiers having a field effect controlstructure monolithically integrated with the - rectifier structure.
For power switching applications, in such electrical systems as motor drives and low to medium frequency (0-2000H~ power suppliesl high speed and low loss performance at high current and high voltage levels is desirable. Prior art three terminal devices which can be used to control power delivered to a load include the MOSFET and the MOS gate thyristor. Prior art power MOSFET's include those described in U.S. Patent NoO ~,072,975, issued February 7, 1978 to Ishitani and U.S. Patent No.
4,145,703 issued March 20, 1979 to Blanchard. Typical eross sections of power MOSFET deviees are shown schemati-cally in Figs. 1 and 2 and their operating characteristics are shown in Fig. 3. These devices have been fabricated by using either planar diffusion techniques -to form a DMOS structure 20 as shown in Fig. 1, or by etching V-grooves to form a VMOS structure 21 as shown in Fig. 2.
In each case, for positive voltages applied to th~ drain, the junctions 22, 23 between the P-base regions 24, 25 and the N-drift regions 26, 27 in Figs. 1 and 2 respectively, block eurrent flow between the drains 2~, 29 and the sources 30, 31 in the absence of gate biases. Application of a sufficiently large positive gate bias with refer-ence to the source results in the formation of an n-type inversion layer 32, 33 in the respective p~base reyions under the gate electrodes 3~, 35, respectively. This RD 13,112 inversion layer allowsconduction of electrical current from the drain to the source producing the forward conduction characteristics shown in Fig. 3. Increasing the gate bias, e.g., from VGl through VG5, increases the conductivity of the inversion layer and thus allows higher drain current ID to flow. For negative voltages applied to the drain, the device conducts current like a forward biased p-n junction diode and cannot block current flow.
As a result, these devices are operated with only positive voltages applied to the drain.
In MOSFET devices, only majority carrier (electron) current flow occurs between drain and source.
This current flow is consequently limited by the majority carrier (electrons here) concentration in the channel and drift regions which determines their resistivity. For devices designed for operation at greater than 100 volts, the resistance o~ the drift region becomes large because the majority carrier concentration in the drlft region must be small and the drift region width (W) must be large in order to support the device blocking voltages.
Due to the high drift region resistance, high voltage MOSFET devices must be operated at low current densities to obtain low forward voltage drops. A typical current density of operation is about 50 A/cm2 a~ a forward voltage drop of 1.5 volts for a device capable of blocking up to 600 volts.
Despite this drawback of a high on-resistance, power MOSFBT's have the advantage of requiring lower gate drive po~Jer levels than bipolar transistors since the gate voltage signal is applied across an insulating film.
In these devices the drain current can also be turned off by bringing the gate voltage down to the source potential.
RD 13,112 This gate turn-off can be achieved with a higher current gain than for bipolar transistors.
Another type of prior art device is the MOS
gated thyristor. Typical devices are disclosed in sritish patent No. 1,356,670, published June 12, 1974, U.S. Patent No. 3,753,055, issued August 14, 1973 to Yamashita et al., and U.S. Patent No. 3,831,187, issued August 20, 1974 to Neilson. A MOS gated thyristor is a pnpn thyristor structure, shown schematically in Figs. 4 and 5, in which regenerative turn-on can be initiated by application of a voltage to an MOS gate. In the device 40 of Fig. 4, the MOS gate is formed on a surface 41 extending from the N+ cathode 42 through the P-base 43 into a small portion of the N-base 44. In the device 50 of Fig. 5, the MOS
gate is formed on a surface 51 extending alony V-groove 52 from the N+ cathode 53 through the P-base layer 5~
into N base 55. These devices will block current flow with either positive or negative voltages applied to their anodes 45, 56 in the absence of the gate bias.
However, for positive anode voltages, the devices can be triggered into the conducting mode by application of a suitable positive voltage on the respective gates 46, 57.
When a positive gate voltage is applied, the electric field across the gate oxide layers 47, 58 produces a depletion of carriers in the p-base under the gate electrode. As a result, the depletion layer in the p-base extends closer to the N+ cathode region under the gate. This reduces the thickness of t.he undepleted p-base region of the upper NPN transistor under the gate electrode and thus increases its current gain. It is well known that a pnpn thyristor structure will switch from a current blocking state to a current conducting ~ RD 13,112 iLW 5~ 3 :~
state when the sum of the current gains of the NPN and ~ ~ NPN and ~PNP~ respectively~ exceeds unity. In the MOS gated thyristor, as the gate bias is increased, the gain of the upper NPN transistor increaseS until ~NPN + ~PNP Y
point strong injection of carriers must occur from the N+
cathode into the p-base for the device to switch to the on-state. This requires that the N+ P junction become forward biased by more than 0.5 volts. Once this takes place, the device switches to the conducting state and removal of the gate bias voltage will not cause the device to return to the blocking state because of the self-sustaining regenerative action inherent in the pnpn thyristor structure. Thu$, these devices have the advantage of requiring low gate power to turn-on the thyristor via the MOS gate, but do not exhibit gate turn-off capability. Thus/ the device must be returned to the blocking state by reversal of the anode polarity.
The characteristics of the MOS gated thyristor are shown in Fig. 6, which show that these devices exhibit a negative resistance characteristic.
Summary of the Invention An object of the instant invention is to provide a field effect controlled, high current capacity rectifier that has both forward and reverse blocking capabilities and a low forward voltage drop, which can be switched on and off with a small gate voltage wi-th very low current, and therefore, low power re~uirement.
A further object is to provide a device which will have a very high gate turnoff gain, high di/dt capability, and high dV/dt capability. Further ob~ects include providing a device which will operate at elevated temperature and RD 13,112 radiation levels without damage.
Accordingly, the instant invention incorporates a monolithically integrated combination of a rectifier with a field effect control structure to control the on-off state of the rectifier by inducing a channel of conductivity within a region of the rectifier to control the on-off condition of pn junctions within the rectifier.
The rectifier includes a multiple layer structure within a body of semiconductor material having one contact on one su1face of the body and another contact on another surface of the bodv. The field eEfect control structure induces a channel of conductivity through one element of the rectifier to provide an electrically conductive path connecting one of the contacts with a second element of the rectifier.
Brief Description of the Drawings The features of the invention believed to be novel and unobvious over the prior art are set forth with particularity in the appended claims. The invention itself, however, as to organization, method of operation and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference characters refer to like elements throughout, and in which:
Figs. l and 2 are schematic partial cross~
sectional views of power MOS gated field effect transistors;
Fig. 3 is a graphical illustration of the device characteristics of the transistors shown schematically in ~igs. 1 and 2;
Figs. 4 and 5 are schematic partial cross-sectional views of MOS gated thyristors;
~D 13,112 Fig. 6 is a graphical illustration of typical device characteristics of the thyristors illustrated in Figs. 4 and 5;
Fig. 7 is a pictorial schmatic partial cross-sectional view of a gate controlled rectifier according to the instant invention;
Figs. 8-13 are schematic partial cross-sectional views of alternate embodiments of the gate controlled rectifier according to the instant invention;
Fig. 14 is a graphical representation of the device characteristics of the gate controlled rectifier of the instant invention; and Fig. 15 is a comparative graphical illustration of typical switching wave forms for the prior art devices and the gate controlled rectifier of the instant invention.
Description of the Preferred Embodiments One form of the basic device structure of the instant invention is illustrated in Fig. 7. The device 60 includes a body 61 o~ semiconductor material, such as silicon, in which a first layer 62 of one type conductivity, P in Fig. 7, and a base region 63 of opposite conductivity, N in Fig. 7, is included. A
first layer 62 can be made by diffusion into a body to produce the anode-base structure of the device, or a body of the conductivity type desired may have a layer grown epitaxially thereover to produce the two-layer combination. A plurality of islands 64, here of P type conductivity, is provided by diffusion or other suitable technique within layer 63 in spaced relationship contiguous with the free surface 65 of the body 61. Adjacent island ~ 5~L~ RD 13,112 6~, an N-~ island 66 is formed within the base layer 63.
Typical doping levels for the N type layer 63 are in the range of 10 to 10 cm of N type carriers, for the P type anode layer 62 typical doping concentrations are in the range of 10 8 to 10~ cm 3 of P type carriers;
for the P type islands 64 typical doping concentrations are 1016 to 10l8 cm 3; and for the N+ islands 66 typical doping concentrations are 10 to 10 cm 3. A layer 67 of dielectric material is Eormed over a portion of free surface 65 including part of the outer surface of adjacent ones of the islands 64 and the region of base layer 63 separating the adjacent islands 64 including island 66. A contact 68, 69 of conductive material, such as aluminum or conductive polycrystalline silicon, is formed over the dielectric layer 67 each overlapping a part of an island 64 and a part of the base layer 63 adjacent the island 64 to serve as a gate electrode. A layer 70 of conductive material such as aluminum or conduc-tive poly-crystalline silicon is deposited over the cen-ter of each of the islands 64 to form an ohmic contact thereto. On the surface 71 of the body 61 a layer 72 of conductive material, such as aluminum or conductive polycrystalline silicon, is deposited to form an ohmic contact to the layer 62. Although stripes are shown for the upper surface patter of the conductive contact 68, 69 and 70 in Fig. 7, it will be appreciated by those skilled in the art that many repetivie geometric contact patterns, such as small contact pads arranged on the surface in closely spaced relationship, could be used. The device is highly interdigitated, e.g., the width of individ-ual stripes is small and the total number of stripes large. The pattern is repeated in the lateral direction to cover the entire ~ RD 13,112 semiconductor device. Each of the conductive contacts extends to one lateral edge of the device, where the contacts 68, 69 are connected to a source of electrical potential, contacts 70 are connected to a source of electri-cal potential of a polarity different from that of the source connected to contacts 68, 69 and contact 72 is connected to a source of electrical potential of a polarity different from that of the source connected to contacts 70.
The device shown in Fig. 7 exhibits the operating characteristics shown in Fig. 14 and operates as follows.
With the contact 70 at ground potential, and no bias supplied to the gate electrode 68, negative voltages applied to the contact 72 result in no curren-t flow because the junction 73 is reversed biased. This provides reverse blocking capability. With no bias supplied to the gate electrode 68, positive voltages supplied to the contact 72 will again result in no current flow because the junction 74 will be reversed biased. This provides the forward blocking capability as well as a desired normally off device chaxacteristic. However, if a positive bias is applied to the gate electrode 68, an inversion layer extending from the ohmic contact 70 to the N-base 63 can be foxmed under the gate in the p base in the region 78 of island 64 immediately beneath the insulating layer 67, and an N accumulation layer of charge carriers can be formed in the region 79 of the N base 63. The N-type inversion layer now in region 78 of P island 64 and the accumulation layer in the region 79 of the N base now connect the ohmic contact 70 to the N+ island 66 in the middle of the device. A
positive bias applied to the con-tact 72 will now result in current flow from the P+ layer 62 functioning as an ~ Rb 13,112 anode to the N+ island 66 and then via the N-type accumulation layer 79 and the N-type inversion layer 78 to the contact 70 functioning as a cathode. The path from the layer 62 to the N+ island 66 functions analogously to a p-i-n diode, shown at 80 in Fig. 7, and the field effect control region is outlined at 8l. The conduc-tivity of the current path through the N-base 63 between the P+ layer 62 and the N+
island 66 will be modulated (increased) by the current flow due to injection of a high concentration of minority carriers (holes here) into the N-base 63 from the layer 62. Since the voltage is supported across the N-base 63 in the forward and reverse blocking modes, the wid-th W of the path between the P+ layer 62 and the P island 64 determines the maximum blocking voltages. For high voltage performance this width must be increased. The conductivity modulation flow is consequently very important for achieving a low forward voltage drop at high forward current densities in high voltage devices. A
typical forward current density of operation is about 500 A/cqn at a forward voltage drop of 1.5 volts for a device capable of blocking up -to 600 volts. If all the conductivity types are reversed, similar performance characteristics can be obtained with electrical potentials of opposite polarities applied to the conductive contacts.
An alternative embodiment of the gate controlled rectifier of the instant invention is shown schematically in Fig. 8. The device 90 of Fig. 8 differs from that of Fig. 7 in omitting N+ island 66. The elimination of the island 66 requires that adequate potential be applied -to gate contact 91 to create an accumulation layer 99 under dielectric layer 67 to produce a region of N type carriers below the gate. To accomplish this with the lowest spreading resistance in the path of current flow RD 13,112 5~
beneath the gate requires that a gate contact 91 extend across the entire width of the gate region connecting the adjacent islands 64. A contact of lesser width would create the necessary accumulation layer 99 of N carriers beneath the gate to provide the function of the N+
islands 66, when adeauate potential is applied to the gate. This decrease in the area of the gate will result in a decrease in the gate capacitance. When a positive bias is applied to the gate of the field effect control structure outlinedat 93, a three layer structure is formed in the region outlined by dashed rectangle 92 which functions as a p-i-n structure. The current path through the rectifier includes the layer 62, n base region 94 n accumulation layer 99, an inversion layer 99, and inversion layer 79 and ohmic contact 70.
A further embodiment of my invention is schematically illustrated in Fig. 9. The device 100 includes P region 62, base region 94, P islands 102 and a plurality of N~ islands 101 within each of the P islands 102. In this embodiment, the islands 101 provide a contact between the inversion layer in the islands 102 and the conductive contact 70. A pair of conductive contacts 107 separated by gap 108 is disposed on dielectric layer 67 to overlap a portion of the islands 101, a region of the islands 102 and a portion of the base 94.
Application of a positive gate bias to a control electrode 107 within dashed outline 103 will produce an accumulation layer in the N base region immediately under the gate, and an inversion layer in the P island 102 immediately under the dielectric layer 67 e~tending from the N-~
island 101 to the N-base 94 completing the current path from the M base through the P island 102 to the N-~
~ RD 13,112 island 101. This structure ineludes a parasitic p-n-p-n thyristor through the anode 62, base 94, P island 102 and n+ islands 101 in the region outlined at 106. To achieve the desired device performance of this device in switching off upon removal of the gate bias, it is very important that the regenerative turn-on mechanism in this parasitie thyristor be suppressed.
This can be aceomplished by preventing the N+
islands 101 from injeeting eleetrons into the respeetive P islands 102, eonsequently preventing the initiation of the regenerative turn-on meehanism of the p-n-p-n thyristor. The suppression of the injeetion of earriers from the N+ islands 101 can be accomplished by forming the N+ islands 101 with a small lateral dimension (L).
The lateral dimension ~L) of the N+ islands 101 must be small enough so that, when the deivce is conducting current from the ehannel ~8 to the eathode contact 70 r the forward bias of the junetion 105 between the N-~ islands 101 and the P-island 102 does not exceed 0.5 volts.
~nother technique whieh eould be used to suppress the regenerative turn-on of the p-n-p-n thyristor is the introduetion of recombination centers in the p-region 102 and the N-base 94 so as to reduce the gains ~NPN and ~PN
Reeombination eenters can be provided by diffusion of deep level impuritiesl such as gold, into the substrate or by irradiation of the substrate with high energy partieles sueh as eleetrons.
Distinguishing features between a MOS gated thyristor, such as that shown in Fig. 4/ and the device of this invention, shown in Fig. 9, are firstly, that the device of this invention eontains N+ regions 101 of much smaller la-teral dimension (L) RD 13 ,112 to prevent the reyenerative turn-on action characteristic of the MOS gated thyristor. Secondly, in the gate enhanced rectifier, the anode current flows solely via the conductive channel formed in the P-island 102 to the cathode contact 70 when the device is conducting current, while the current of the MOS gated thyristor flows vertically throughout the P-island 102 underneath the N~ island 101. Thirdly, in the gate enhanced rectifier, the anode current can be terminated by removal of the gate voltage applied to induce the conducting channel in the P-islands 102, while the anode current of the MOS gated thyristor will continue to flow after removal of the gate voltage due to the self-sustaining nature of the regenerative pnpn thyristor action. It is noted that the embodiment in Fig. 8 avoids this problem by elimination of the N+ islands within the P islands 102.
In the alternative embodiment shown in Fig. 10, N~ island 111 filling the entire width between adjacent P islands 114 and the N base 113 and impinging upon a portion of the P islands is formed in the N base. When a positive bias is applied to the gate 115 an inversion layer is created in the region of the P islands immediately under the gate and the current path from the N~ island 111 to the cathode contact 11~ is completed, thereby turning the device on and allowing current to flow through the p-i-n diode outlined at 112 and via the inversion layer to the cathode contact 116.
In the embodiment shown in Fig. 11, N-~ islands 125 have been added to the P islands 124 of the device 120 which provide current flow paths from the inversion layer in the P-islands 124 to the conductive contact 116, when a positive bias is applied to electrode 117 in gate structure ~ 5~ RD 13,112 118 to turn on the p-i-n diode 119. This embodiment also contains the parasitic pnpn thyristor described with reference to the embodiment shown in Fig. g. As discussed earlier with reference to Fig. 9, the regenerative turn-on mechanism of this parasitic thyristor must be suppressed by maintaining a small lateral dimension (L) for the N+ island 125 and by providing recombination centers in the P-islands 124 and the N-base 113. It is noted that the embodiment of Fig. 10 avoids this problem by elimination of the n+ islands within the p islands 102.
In device 130 shown schematically in Fig. 12, highly doped P+ islands 133 have been added to the P
islands 132 in the N base 131. The current path includes the p-i-n diode 134 created when a positive bias relative to the conductive contact 137 is applied to the gate 136 in the gate controlled structure 135 to produce an accumulation layer immediately under the dielectric layer 67. ~n inversion layer is produced in P island 132 between the P+ island 133 and the N-base 131 to allow current flow from the anode to the cathode.
~ further alternative device structure employing my invention is shown schematically in Fig. 13. The body of semiconductor material for device 140 has a liyhtly doped N-base region 141 and a more heavily doped N-base region 142. Within base region 142 P+ islands 143 are formed adjacent to one major free surface 144 of the body. P
islands 14S are formed into the N-region 141 and ~he N+
islands 150 are formed into the P islands 145 adjacent the other major surface 146 of the body. For a given forward conduction current density this structure provides a lower forward voltage drop in the diode 152 than -the previously described embodiments for the same forward ~ 13 -~ RD 13,112 blocking capability. However, the reverse blockiny capability is reduced to the shorting of the islands 143 by conductive contact 147. The operating characteristics of this device are similar to those of the other embodi-ments when a forward bias is applied. When a reverse bias is applied to the conductive contact 147 in the absence of a bias on gate electrode 148 in gate controlled structure 151, a substantially different characteristic is produced as shown at 160 in Fig. 14, in that breakdown occurs at a much lower reverse bias.
The operating characteristics of the gate controlled rectifier are shown in Fig. 14. In this device, the junction 73 blocks current flow when negative voltages are applied to the anode contact 72 providing the device with reverse blocking capability up to the level at which breakdown occurs as seen at 161. When positive voltages are applied to the anode contact 72, junction 74 becomes reverse biased and blocks current flow, thus providing the forward blocking capability in the absence of gate bias up to the level at which breakdown occurs as seen at 162. However, if a positive bias is applied to the gate, a path is created for the current to flow from the anode junction 73 to the cathode contact 70 producing the characteristics shown for each of the gate voltages VGl - VG4. At large gate voltages (VG4) the inversion layer conductivity will be high and the device will exhibit characteristics like those of a pn junction diode.
In this case the anode P~ region injects minority carriers into the n-base and strongly modulates (increases~ the conductivity of the n~base. As a result of this, the device can be operated at high current densities (typically 500 A/cm ) with a low forward voltage drop (about 1.5 volts).
RD 13,112 5~
At lower gate voltayes (VGl, VG2~ G3)~
flow can become limited by the conductivity o the inversion layer producing the current saturation shown in Fig. 14. These devlce characteristics are distinguishable from those of other prior art devices. When compared with the MOSFET, the gate enhanced rectifier can be operated at much higher current densities due to the modulation of the conductivity of the N-base by the anode current flow.
Unlike the MOSFET, these devices also exhibit reverse bloc]~ing capability. When compared with the MOS gated thyristor, the gate enhanced rectifier is distinguished by the absence of a negative resistance re~ion in the forward characteristics. This negative resistance region in the thyristor arises from the regenerative turn-on phenonenon which is absent in the gate enhance rectifier.
Unlike the MOS gated thyristor~ no self-sustaining regenerative turn-on occurs in the gate enhanced rectifier device. Consequently, if the gate voltage is reduced to the cathode potential while the device is conducting current, the inversion layer under the gate electrode will cease to exist and the anode current will turn off. This turn-off occurs in two stages. First, most of the injected stored charge in the N base is removed by current flow across the j~nction 74 to p region 145 until it becomes reverse biased. After this point, the rest of the minority carrier stored charge will decay by recombination.
A comparison of the switching characteristic of the MOSFET, -the MOS gate thyristor and the gate enhanced rectifier can be done with the aid of Fig. 15. In this figure, the gate voltage is turned on at times tl and e.s ~ and turned off at ~e t2 for all three cases as shown by ~D 13,112 trace 164. At -time t2, the MOSFET turns off rapidly as seen in trace 165 the duration of the turn-off transient being determined by the charging of the gate capacitance.
However, the MOS gated thyristor continues to conduct current even after the gate voltage is reduced to zero at time t2 as shown by trace 166, because the current flow is sustained by the internal regenerative mechanism in these devices. In contrast, the gate enhanced rectifier turns off at time t2 as shown by trace 167 because the inversion layer under the gate electrode will cease to exist when the gate voltage is reduced to zero and this will interrupt the current flow path between the anode and cathode terminals. In this case, the minority carriers injected by the anode into the N-base to modulate its conductivity during forward current conduction will be removed by conduction across junction 74 until it becomes reverse biased as shown at point 168. Any remaining minority carriers wil] then decay by recombination.
Consequently, the ~ate enhanced rectifier turns off at time t2 like the MOSFET but does so more slowly due to the bipolar current conduction. It should be noted that this slower switching speed of the gate enhanced rectifier is adequate for many applications such as motor drives, while its lower forward ~oltage drop when compared with the MOSFET is a major advantage, because it reduces the power dissipated and thus improves the power switching efficiency. Other advantages are better surge current handling capability, higher operating t~mperature capability and elevated radiation level tolerance made possible by the suppression of regenerative turn-on described above.
It will be appreciated by those skilled in the art that the conductivity types shown in the figures - ]6 -~ 4 RD 13,1].2 and described above are only illustrative and the polarities of the regions may be reversed without significantly arfecti.ng performance. This is especially useful in the construction of complementary devices.
Claims (13)
1. A gate enhanced rectifier comprising:
a body of semiconductor material including a first base region of one type conductivity and a second base region doped heavily relative to said first base region with carriers of said one type conductivity;
a carrier injection island of opposite type conductivity disposed within said second base region;
a further island of said opposite type conductivity disposed within said first base region and spaced from said second base region;
a first electrode adjoining both said carrier injection island and said second base region;
a second electrode adjoining said further island; and a gate electrode spaced insulatingly from said further island, said gate electrode and said further island being so constructed and arranged that an inversion layer is induced in said further island beneath said gate electrode upon suitable biasing of said gate electrode, said inversion layer comprising a substandtially exclusive conductive link in a main current path in said body extending from said first electrode to said second electrode during forward conduction of said gate enhanced rectifier.
a body of semiconductor material including a first base region of one type conductivity and a second base region doped heavily relative to said first base region with carriers of said one type conductivity;
a carrier injection island of opposite type conductivity disposed within said second base region;
a further island of said opposite type conductivity disposed within said first base region and spaced from said second base region;
a first electrode adjoining both said carrier injection island and said second base region;
a second electrode adjoining said further island; and a gate electrode spaced insulatingly from said further island, said gate electrode and said further island being so constructed and arranged that an inversion layer is induced in said further island beneath said gate electrode upon suitable biasing of said gate electrode, said inversion layer comprising a substandtially exclusive conductive link in a main current path in said body extending from said first electrode to said second electrode during forward conduction of said gate enhanced rectifier.
2. The invention of claim 1 wherein said gate electrode is additionally spaced insulatingly from said first base region, said gate electrode and said first base region being so constructed and arranged that an accumulation layer is induced in said first base region beneath said gate electrode upon suitable biasing of said gate electrode.
3. The invention of claim 1 wherein said body further includes a heavily doped island of the one conductivity type disposed within said further island, said heavily doped island adjoining both said second electrode and said inversion layer when present.
4. The invention of claim 1 wherein said first and second base regions comprise semiconductor material of N-type conductivity and said carrier injection island and said further island comprise semiconductor material of P-type conductivity.
5. A gate enhanced rectifier comprising:
a body of semiconductor material including a carrier injection region of one type conductivity, a base region of the opposite type conductivity adjoining said carrier injection region, and a first island of said one type conductivity disposed within said base region and spaced from said carrier injection region;
a first electrode adjoining said carrier injection region;
a second electrode adjoining a portion of said body consisting essentially of said first island; and a gate electrode spaced insulatingly from said first island, said gate electrode and said first island being so constructed and arranged that an inversion layer is induced in said first island beneath said gate electrode upon suitable biasing of said gate electrode said inversion layer comprising a substantially exclusive conductive link in a main current path in said body extending from said first electrode to said second electrode during forward conduction of said gate enhanced rectifier.
a body of semiconductor material including a carrier injection region of one type conductivity, a base region of the opposite type conductivity adjoining said carrier injection region, and a first island of said one type conductivity disposed within said base region and spaced from said carrier injection region;
a first electrode adjoining said carrier injection region;
a second electrode adjoining a portion of said body consisting essentially of said first island; and a gate electrode spaced insulatingly from said first island, said gate electrode and said first island being so constructed and arranged that an inversion layer is induced in said first island beneath said gate electrode upon suitable biasing of said gate electrode said inversion layer comprising a substantially exclusive conductive link in a main current path in said body extending from said first electrode to said second electrode during forward conduction of said gate enhanced rectifier.
6. The invention of claim 5 wherein said base region and said second electrode are so constructed and arranged as to each conductively adjoin said inversion layer when present.
7. The invention of claim 5 wherein said body further includes a second island of said opposite type conductivity disposed within said base region and constituting part of said main current path.
8. The invention of claim 5 wherein said second island adjoins said first island.
9. The invention of claim 5 wherein said gate electrode is additionally spaced insulatingly from said base region, said gate electrode and said base region being so constructed and arranged that an accumulation layer is induced in said base region below said gate electrode upon suitable biasing of said gate electrode.
10. The invention of claim 5 wherein said carrier injection region and said first island comprise semiconductor material of P-type conductivity and said base region comprises semiconductor material of N-conductivity type.
11. A gate enhanced rectifier comprising:
a body of semiconductor material including a carrier injection region of one type conductivity, a base region of the opposite type conductivity adjoining said carrier injection region, a first island of said one type conductivity disposed within said base region in spaced relationship to said carrier injection region, and a heavily doped island of said one type conductivity disposed within said first island;
a first electrode adjoining said carrier injection region;
a second electrode adjoining a portion of said body consisting essentially of said heavily doped island; and a gate electrode spaced insulatingly from said first island, said gate electrode and said first island being so constructed and arranged that an inversion layer is induced in said first island beneath said gate electrode upon suitable biasing of said gate electrode, said inversion layer comprising a substantially exclusive conductive link in a main current path in said body extending from said first electrode to said second electrode during forward conduction of said gate enhanced rectifier.
a body of semiconductor material including a carrier injection region of one type conductivity, a base region of the opposite type conductivity adjoining said carrier injection region, a first island of said one type conductivity disposed within said base region in spaced relationship to said carrier injection region, and a heavily doped island of said one type conductivity disposed within said first island;
a first electrode adjoining said carrier injection region;
a second electrode adjoining a portion of said body consisting essentially of said heavily doped island; and a gate electrode spaced insulatingly from said first island, said gate electrode and said first island being so constructed and arranged that an inversion layer is induced in said first island beneath said gate electrode upon suitable biasing of said gate electrode, said inversion layer comprising a substantially exclusive conductive link in a main current path in said body extending from said first electrode to said second electrode during forward conduction of said gate enhanced rectifier.
12. The invention of claim 11 wherein said base region and said second electrode are so constructed and arranged as to each conductively adjoin said inversion layer when present.
13. The invention of claim 11 wherein said carrier injection region, said first island, and said heavily doped island comprise semiconductor material of P-type conductivity and said base region comprises semiconductor material of N-type conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000397265A CA1182584A (en) | 1982-02-26 | 1982-02-26 | Gate enhanced rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000397265A CA1182584A (en) | 1982-02-26 | 1982-02-26 | Gate enhanced rectifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1182584A true CA1182584A (en) | 1985-02-12 |
Family
ID=4122181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000397265A Expired CA1182584A (en) | 1982-02-26 | 1982-02-26 | Gate enhanced rectifier |
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| Country | Link |
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| CA (1) | CA1182584A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114551576A (en) * | 2022-04-26 | 2022-05-27 | 成都蓉矽半导体有限公司 | Grid-controlled diode with high surge current resistance |
-
1982
- 1982-02-26 CA CA000397265A patent/CA1182584A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114551576A (en) * | 2022-04-26 | 2022-05-27 | 成都蓉矽半导体有限公司 | Grid-controlled diode with high surge current resistance |
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