CA1177881A - Power factor motor controller - Google Patents

Abstract

POWER FACTOR MOTOR CONTROLLER

ABSTRACT OF THE DISCLOSURE
The power factor for an AC induction motor (34) is controlled by selectively controlling the firing angle delay of a gate signal to a triac (36) during the cycle of the power source (32). Source voltage zero crossing (66) is sensed and a plurality of consecutively sequenced discreet windows (94, 96, 98, 100) are initiated.
If the current zero crossing (68) occurs in the first window (94), then a sudden load on the motor (34) is indicated, and any delay in the firing angle of the triac (36) is substantially eliminated. This enables conduction of the triac (36) during substantially the entire cycle of the source voltage (60), thus providing instantaneous full power to the motor (34). If the current zero crossing (68) occurs in the second window (96), then the power factor is too great, and more power is needed at the motor (34). The gate firing angle is reduced, whereby the triac (36) will conduct for a longer cycle portion and hence deliver more power to the motor (34). If the current zero crossing (68) occurs in the third window (98), then an optimum power factor is indicated and the gate firing angle is not affected. If current zero crossing (68) does not occur in any of the first (94), second (96) or third (98) windows, then it will occur somewhere in the fourth window (100) and too much power is getting to the motor (34). Upon termination of the third window (98) without zero crossing (68) of the current, the gate firing angle delay is increased so that the triac (36) will be ON for a shorter portion of the cycle, and hence less power is delivered to the motor (34).

Description

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Tsys , BACI~GROUND OI; 'PIIE INVl~NTION

[; icld of the inveIltioll:
Tlle invention relates to power input controls for ~C induction motors, and more particularly to a contIol circuit for providing variable input power in accordance with loading on the motor.
Description of the Prior Art:
AC induction motors are well known and widely used! These typcs of motors run at substantially constant speeds independent of load and applied voltage.
The most efficient operation results when the applied voltage is a function of the load, since the motor draws substantially the same current whether loaded or unloaded.
Electrical power is wasted when the motor is partially loaded or is unloaded because relatively large currents flow and little work is performed. lR losses occur in the distribution system, including the motor windings, even though no mechanical power is delivered.
Motor control systems are known which reduce power losses by sensing the phase lag between voltage and current. TZle control system forces the motor to run at a constant predetermined power factor regardless of load or line voltage variations, within the limits of the motor.
An example of a control system is silown in Nola U.S. Patent No.
~,052,G48, and NASA Tech. Brief, MFF-23280, summer 1977. Voltage is varied by a selectively triggered triac. A phase control and firing angle circuit is provided, including a ramp voltage wave form synchronized with tlle zero crossings of t1lesinusoidal load voltage, a DC error signal, and a train of pulses that become wider as the error signal hlcreases. The error signal is derived from a voltage/current pllase lag sensing circuit which produces a DC voltage proportional to the pilase lag. Since ,

-2-the current remains ;ligh in an unloaded motor, khe phase angle between voltage and current shifts with load.
- Typically, the current may lag the voltage by 80 in an unloaded motor and by only 30 when loaded. The produced DC voltage proportional to phase lag is summed with a fixed reference voltage which is indicative of a desired phase angle. The difference of these two is the error signal which hiases the ramp voltage which is in synchro-nization with the line voltage. The intersection of the ramp and error voltages are detected by a s~uaring ampiifier whose output provides the timing for turning on the triac. The ON time of the triac thus varies with the load. This in turn varies the voltage applied to the motor, to force the phase angle to remain at the commanded value. The phase angle is measured by detecting the time between the zero crossings of the voltage and the zero value of the trailing edge of the current.
While prior power factor controllers have been useful for their intended purposes, the present invention relates to improvements thereover.
SU~ARY OF THE INVEMTION

. . _ . . . _ . _ In accordance with one aspect of the invention there is provided a power factor controller for an AC
induction motor energized from an AC source via a gated semiconductor switch comprising a voltage/current phase lag sensing circuit for de~ermining the lag of the current phase including a voltage crossing circuit for detecting the zero crossing of the line voltage and a timing circuit for detecting the zero crossing of the line current and determining in which one of a plurality of specified sequential time periods the line current zero crossing occurs, the time period defining a magnitude of current 788~
phase lag; and a gate control circuit Eor determining the length of the firing angle delay of the gate signal to the semiconductor switch in response to a value stored in a memory circuit, said value being altered by said gate control circuit in response to the magnitude of the current phase lag.
In accordance with another aspect of the invention there is provided a method for controlling the power factor for an AC induction motor energised by an AC source via a gated semiconductor switch, said method comprising the steps of sensing the voltage zero crossing oE said AC source;

,, ` sensing the zero crossing of the line current; determining in which one of a plurality oE specified sequential time periods that are initialized upon the occurrence of said line voltage zero crossing that the line current zero crossing occurs, the time period defining a magnitude of current phase lag; selectively controlling the firing angle delay in response to the magnitude of the current phase lag.
The present invention provides power factor control by sensing the voltage/current phase lag in accordance with a set of consecutively sequenced time periods or windows which determine the firing angle of a gated semiconductor switch in circuit with an AC induction motor~ Upon zero crossiny of the line voltage, the sequence of windows is initiated, during one of which occurs zero crossing of the current.
In preferred form, the se~uence of windows comprises first, second and third fixed delay windows followed by a fourth window. A triac semiconductor switch is used, and turn-off thereof corresponds to zero crossing of the current.
The status of the triac is tested at the end of each fixed window to determine if there has been a zero crossing of the current.
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~'I`SYS l~pon crossing of a predetermined level by tllc line voltagc, the first wilndow is initiated and lasts a predetermined time. At the end of ~his first window, the status of the triac is tested. If thc triac has already turncd off (zero crossing of the currellt has occurred~, a sudden load on the motor is indicated. The firing angle delay of the gate signal to the triac is tllen r educed to zero. This provides instantaneous full power in a sudden load situation.
If the current has not crossed zero during the first window (the triac has not yet turned off when tested at the end of the first window), then the second window is initiated and lasts a predetermined time. After this second window hasZ0 elapsed, tlle status of the triac is tested. If the triac llas turlled off, then thc current has crossed zero in tlle second window. This indicates that the power factor is slightly ;~ above a desired Icvel, and tilat more power is needed at the motor. The firing angle delay of tlle gate signal to the triac is then slightly decreased so that the triac will be fired slightly carlier in the next cycle to thus give more power to the motor.
If the current has not crossed zero during the first and second windows, then a short third delay window is initiated and lasts a predetermined time. After this third windovJ has elapsed, the status of the triac is tested. If tlle tlriac llas turned off, tllen the currellt has crossed zero during the tllil d window. 'I`llis indicates that there is a desired amount of phase lag between current and voltage, and that thepower factor is at an optimum level. The firing angle delay of the gatc signal lo thc triac is then left unchanged so that the triac will again be fired at the same point in the ncxt cycle to thus maintain the optimum power factor for tlle motor.
~11 three windows will be sequenced regardless of time of current zero crossing. At tlle end of the windows, the firing angle delay is initiated at the end 2~ of wllich the triac is fired. During thc sequencing of tlle windows, a status register -I is sct according to the window durillg which zero crossing occurs. Later after time delay is completed and triac fired, the time delay is modificd according to the contents of the status register.

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rSY~ If zero crossing (current) does not occur by the end of the tllird window, - th,en it is assumed that it will occur later and the system is getting too mucll power.
If the current has not crossed zero during the first, second and third windows (the tri~c has still not turned off when tested at the end of the third window), then a fourth window is initiated. Zero crossing of the current will occur somewhere in the fourth window. Initiation of the fourth window indicates that the power factor is below a desired level and that too much power is getting to the motor.
Initiation of the fourth window causes the firing angle delay in the gate signal to the :~ triac to be increased so that the triac will be fired later in the next cycle. This reduces the power delivered to the motor.
The fourth window controls a variable time period, the length of wllich affects the timing of the gate signal to the triac in the next cycle. The firing angle time delay of the gate signal to the triac is incremented each cycle in which the ., fourth window is initiated. This incrementation is cumulatively repeated for each successive cycle until the test of the status of the triac at the end of tlle third window indicates that the triac has turned off, i.e. the current has crossed zero during the third window.
rr In the preferred embodiment, a microcomputer is used to set the fixed delay whldows, for imcrementation of the firing angle time delay of tlle gate signal to the triac in order to deliver less power to the motor, for decrementation Or the firing angle time delay of the gate signal to the triac in order to deliver more power to the motor. Further, the microcomputer senses a reference level crossing of the line voltage, the status of the triac, and times the firing angle delay.
BRIEF DESCRIPTION OF THE DE~WINGS
FIGURE 1 is a circuit diagram of the preferred embodiment of a power factor controller constructed in accordance with the invention.

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B3370 l`lCUI~E 2 is a wave form diagram illustrating aspects of opcration of the inyention.
l'lGllRE 3 is a wave form diagram illustrating aspects of operation of tlle invenlion.
DE'I`AILL~l) DESCI~IPTION OF TH~ PnEFEl~RED E~IBODIMENT
There is shown in FIGURE 1 a power factor controller 30 connected between an AC power source 32 and an AC induction motor 34. Source 32 llas a freyuency from 50 to 60 hertz, and produces a sinusoidfll voltage across conductors 33 nnd 35. A triac 3G is contlected in series with the motor through conductor 37 for ~- 10 controlling energization of tlle motor. Connected in parallel with the triac 36 is a normally open contactor switcll S-1 which by~passes triac 3~ during starting.
Contactor switch S-1 is actuated by a solenoid S to conduct in-rush current duriIlg : .i starting of the motor 34. Operation of the solenoid S is controlled by tlle microcomputer 54.
The triac is fired into a conductive ON state at gate 38 by signal current through r esistor 40 in response to conduclion of transistor 42. I~mitter current for transistor 42 is delivered through conductor 43 from the catllode of diode 44 orcapacitor 52. Current to the anode of diode 44 is delivered from conductor 33 tllrougIl diode 48 alld resisLor 50. Zener 4G provides voltage regulation. Resistor 50 provides curreIlt limiting. ~ capacitor 52 is connectcd between conductor 43 and conciuctor 35.
This capacitor stores current during the positive half-cycle of the line voltage, i.e., whell conductor 33 is higll and conductor 35 is low, for use during the negative half-. .
cycle and for use when curIent requirements exceed the charging ability of resistor 50.
Transistor 42 is biased into conductioll by a gate signal from a microcomputer 54. To facilitate understandillg, the drawing shows a microcomputer 54 wilh standard pin riumbers and port designations assigned thereto. The base of trarlsistor 42 is comlected to pin 8. A resistor 56 is connected between the transistor ~771!3~L

'I`SYS base and conductor 35. Pins 1~1 ancl l9 are connectcd to concluctol 43. A cupucitor B3'370 58' is connected between pin 24 and conductor 43.
'I`ransistor 42 is turned on and off by microcompuLer 5~ througll pin D102.
Pin D102 eitller pulls the base of transistor 42 to Vss or allows it to float. If the base of trallsistor 42 is pulled to Vss, tlle transistor is turned off and no current flows througll the collector to the gate 38 of the triac. Tlle triac will not turn on so long as transistor 42 is off. If the base of transistor 42 is allowed to float then resistor 56 will cause currellt to flow in the base of the transistor, turning the transistor on and pulling its collector to a voltage approaching Vss. ~esistor 40 will thcn limit the I() amount of ~currellt which will flow to the gate 38 of the triac.
~ transistor 70 has a collector connected to pin 1 of the microcomputer.
'I`ransistor 70 has an emitter connected througil resistor 72 to a point between diode 48 and zener 46. The base of transistor 70 is connected to pin 25 of the microcomputer. Wherl the positive half-cycle of the line voltage begins, the emitter of transistor 70 is pulled guickly to a voltage approximating Vss nt pins 19 and 14.
Regarclless of whether triac 36 is ON or O1 E;, the INT0 port at pin 25 will be pulled high tllrougll the base-emitter of transistor 70. This provides the signal that the positive halr-cycle has begun.
Diodes 44 and 48 allow current to pass throllgh to charge capacitor 52 so long as the ~C inpllt voltage is sufficiently positive and so long as the breakdown voltage of zener 46 is not exceeded. Diode 48 prevents power dissipation in resistor 50 during thc negative half cycle and diode 44 prevents current from flowing from capacitor 52 through resistor 72 to the emitter of transistor 70. The emitter oftransistor 70 must be held high (almost at Vss) only during the positive half cycle and gives tlle computer an indication of the state of thc ~C power input. ~ithout diode 44, tlle emitter of transistor 70 would be high reg~ardless of the condition of the I~C
power. Without diodes 44 and 48, there would be no coverage charge to capacitor 52.
Diodes 44 alld 48 prevent discharge throllgh resistor 50 during tlle negAtive half-cycle.

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, B39~lO 1 I~IGUI~E 2 shows sinusoidal line voltage 60 from souIce 32. Current G2 lags byl a phase angle G4 measured between voltage ~ero crossing 6G and current zero `` crossing 68. Tlle positive i1alf-cycle beghls at point 66 as the Iine voltage passes throllgll zero, frorn negative to positive. The pulling of pin 25 higll tiIrollgh thc base-Il emitter of transistor 70 indicates that such positive half-cycle llas bcgun.
It` triac 36 is ON at the beginning of thc positive llalf-cyclc, as seen by the current flow at 74, FIGURE 2, the triac will remain ON until the cuIrent tllrough inductive motor 34 reaches zero. The time 64 wilich elapses between the zero crossing of tlle voltage and the zero crossing of the current is related to the power I factol at whicIl the motor is operating.
The base of transistor 70 is connected through a diode 7G and resistor 78 ` to conductol 37. Whell ihe triac turns off, the voltage on the resistor 78 will rapidly, almost instantaneously, rise to tile line voltage on conductor 33. This reverse biases . , diode 76 which in turll eliminates base current for transistor 70, so that the INT1 port ]5 at piII I will now be pulled low. Tllis provides the current zero crossing signal. A
r esistor 80 is connected between the collector of transistor 70 and conductor 35.
esistor 72 provides a necessary voltage drop when transistor 70 is turned on. WitlIout resistor 72, pin 1 (INT1) of the computer 5~1 would be pulled significalltly more positive thall Vss. I his would exceed the maximum operating conditions specified for microcol7Iputer 54.
~s the AC power enters the positive half cycle, the triac is on and will remain on until the magnitude of the current in the motor clecreases to zel o. The . ~ I side of resistor 78 which is connected to the triac will thus be held at or near the I ground (VDD, or neutral) voltage. ConseqlIently when, as we enter the positive half cycle, the emitter (anc] base) of transistor 70 are pulled toward and approach Vss, currelIt will begin to flow through diode 76 and resistor 78 tuIning on transislol 70.
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I When the current in the motor decreases to zero, triac 36 will tuIn off, causing , , ! , , ; ., : --8-,. ..

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~YS conncctioIl 37 suddenly to become quite positive. Whell this l~appens, diode 76 will be reversc biased and trallsistor 70 will turn off. ~t this time, the IN'l`l input to the computer 54 will be pulled low by resistor 80 giving the computer an indication that tlle triac has turned off.
Referring to ~IGURE 2, phase angle 64 shows an optimum power factor phase lag. During each positive and negative llalf-cycle of the line voltage 60, triac 3G is fired at symmetrical points such as $2 and 8~ during the incleasing line voltnge of the respective polarity. I'or examplc, the firing of the triac at point 82 in the rising line voltage G0 initiates positive current flow through the triac. Tllis current flow terminates at positive to negative current zero crossing 86. This current zero crossing 86 lags the positive to negative voltage zero crossing 88 b~- optimum phase angle G4.
There is no limitation that the triac will only be fired during the increasing line voltnge. In many instances where small amounts of power are needed, the triac will be fired wllile tlle magnitude of the voltage is decreasing.
If thc phase lag increases, the load on the motor has been r educed, whereby less power is needed at the motor. Power to the motor can )be reduced byfiring the triac at a later time in the half cycle, such as at 90.- 'I'he triac will thus conduct for a shor~er portion of the half-cycle, whereby less power is applied to the - 20 motor.
If the phase lag decreases, the load on the motor has been increased, wheleby more p ower is needed at the motor. Power to the motor can be increased by firing the triac at an earlier time in tlle llalf-cycle, such as at 92. Tlle triac will thus conduct for a longer portion of tlle half-cycle, whereby more power is applied to the motor.
Tlle voltage/currcnt phase angle lag is sensed by a plurality of condi~ional test windows. 'l'llis is illustratively shown in r~lGURE 2. After zero crossillg of tlle line voltage at 66, there is initiated a sequence of tllree fixed timc delay periods or `

T~YS windows 94, 96, 98 and a fourth window 10(). If the power factor is at the desired leyel, the triac will turn off during the third window 98 as showll by zero crossing 68 of the current therein. This will not cause any change in tIle firing angle delay of the gate signal to the triac during the next half-cycle, i.e., triac 36 will again be gated ON at point 84 in the increasing line voltage. If the current zero crossing 68 occurs in any of tlle other windows, then the firing angle delay of the gate signal to the triac will be changed to increase or decrease the power factor as required.
The lengtll of the firing angle delay of the gate signal to the triac is - controlled by the contents of a meMory register in the microcomputer. If the memory register is incremented, the delay in activation of pin 8 (to a LOW condition) is increased. This delays the biasing of transistor 42 into conduction, which in turn delays gating of the triac 36 into conduction. If the memory register is decremented, the delay in activation of pin 8 is decreased, whereby the triac 36 will be gated into conduction at an earlier time in the cycle of the source voltage.
'I`he windows comprise a set of conditional tests. ~fter voltage zero crossing 66 is sensed, first window 94 is initiated. This first window 94 lasts a predetermined time. ~t the end of first window 94, the status of triac 36 is tested.
`~ If the triac has already turned off, i.e., current zero crossing 68 has occurled between points 66 arId 94, then the motor 34 has been subjected to a sudden load. 'I`he memory registeI in the microcomputer is then zeroed, i.e., its contents are erased. This substalltially eliminates any delay in the firing angle of the gate signal to the triac.
The triac is then gated into conduction immediately after window 98. This provides substantially instantaneous full power in a sudden load situation. Anytime the delay is already zero and an indication is present, the motor still needs more power, the triac will be îired continuously for several cycles to assure max voltage to the motor.
If lhe status test of triac 36 at the end of first window 94 indicates that triac 36 has not turned O~r, then second window 96 is initiated. Second window 96 ,.

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TSYS lasts n predetcrmincd timc. Tlle stutus Or the tlinc is tesled ~lt tllc cnd of whl(low B3~70 96. If tlle triac has tulned off, i.e., curlent zero crossillg G8 has occurled belwccn points 9~ and 96, thell the power factor is too great arld more power is needed at the motor. 'I`he microcomputer rnemory registcr is thcn decrernented to decrcasc theS firing angle delay of tlle gate signal to the triac. The triac is thus fired at earlier points in the increasing line voltage durillg subsequent half-cycles. This causes the - triac to be ON for longer portions of the lhle voltage half-cycles. This increases the power delivered to the motor.
If the status test of the triac 36 at the end of second window 96 indicates that triac 36 has not turned off, then third window 98 is initiated. Third window 98 ; lasts a predetermined time. The status of the triac is tested at the end of window 98. If the triac has turned off, i.e., current zero crossing 68 has occurred between pOilltS 96 alld 98, then the power factor is at a desired optimum level and the proper amount of power is being applied to the motor. The microcomputer memory registerlS is held stable, and the firing angle delay of tile gate signal to the triac is hot changed.
,~ The triac is thus fired at the same points 84 and 82 in the next negcltive and positive !t half-cycles. 'I'his maintains optimum power factor operation of the motor by ,~ maintairlirlg an optimum percentage of ON time of the triac in the cycle of the line voltage.
If the status test of the triac 36 at the end of third window 98 indicates that triac 36 has not turned off, then fourth window 100 is initiated. Zero crossing 68 of tlle current will occur somewhere in the fourth window. If fourth window 100 is initiated, therl the power factor is too low and too much power is getting to the motor. Initiatior-l of the fourth windo~ 100 increments the microcomputer memoryregister to hlcrease the firing angle delay of the gate signal to the triac. 'l`he triac is thlls fired at later points in the increasing line voltage durillg subscquent half-cycles. This causes the triac to be ON for shorter portions of the line voltage half-cycles. 'I`his decreases the power delivered to the motor.
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1~77 ' 'I`SYS ~ The fourlh window 100 controls a variable time delay whicll sets the time - B:~970 wllen the triac is fired in the next cycle. Upon initiation of fourtl-l window 100, the microcomputer increments a number h~ its memory register wllicll is used to generate an incremented delay in the firing angle of tile gate signal to the triac. This 1 incrementation of firing angle delay is cumulatively repeuted for eacl- successive cycle that the fourth window 100 is re-initiated. After several repetitions, forexample, the status test of the triac 36 at the end of third window 98 will again indicate that triac 36 I-as turned off, whereby zero crossing 68 Or the current has occurred before the end of third window 98.
l If the power factor swings slightly below the desired level, i.e., too little power is getting to tlle motor, then the status test of the triac at the end of second window 96 will indicate that the triac has turned off. Tlle firing angle delay of the gate signal to tlle triac is now simply decremented slightly, thus giving more power j to the motor to correct the power factor.
lS As noted above, the first delay window 94 is particularly advlantageous in sudden load situations. Simple decrementation of the firing angle delay may not provide fast enougll response to a rapidly increasing power factor due to quickly , ~ increased motor load. Whell the power factor increases to the point that the triac turns off during the first window 94, the microcomputer responds by totally zeroing any firing ullgle delay of the gate signal to the triuc. This enables immediate application of full power to the motor. There is tllus provided effective response to installtaneous zero to maximum load transitions. Once full power is applied, the~, microcomputer will immediately begin incrementing the firing angle delay if full , power is not needed. The fast response to sudden loads is desirable to prevent stalling or substantial slowdown of the motor which could cause overheatillg thereof.
Delay window times 94, 96 and 98 are scaled to a number jumpered to an input port defined by pins 2, 3, 4 and 5. Jumper 102 is connected to conductor ~3.
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'~S~S Jumper 10~ is conllected through resistor 106 to conductor 35. Diodc 108 and resistor 110 are connected in parallel between conductor 35 and pin 2~. 'I`lle Vdd port at pin 18 is connected to conductor 35. The VC port at pin 17 is connected tllrough potentiometer 112 to conductor 35. Potentiometer 112 provides a slight adjustment of the internally generated clock rate. Resistor 110, capacitor 58 and diode 108 make up a standard network to initialize the computer when power is first applied.
- The preferred system of delay windows assures stability, and provides adequate response to cl~angillg loads. This preferred system further provides instantalleous response within one cycle, of a 60 hertz source, to quickly increasing loads.
1`he triac is fired in the negative half-cycle symmetrically to ttle positive half-cycle. It should be noted that the microcomputer does not receive a true line voltage zero crossing indication. The sensed indication of voltage crossover G6 is provided by pin 25 being pulled high tilrougll the base-emitter of transistor 70. This sensed indication of crossover from negative to positive comes when the line voltage is about 12 volts for about a 60 hertz 110 volt AC source. The time lag between actual occurrence and sense indication is about 0.2 milliseconds. A sirmilar error occurs on the positive to negative crossover, making the total symmetry errol about 0.~ milliseconds. 'I`his complicates symmetrical positive and negative half-cycle firing of the triac. 'I`his problem is solved by adding a de-skew delay whicll is varied by changillg a number jumpered to tlle input port defined by pins 20, 21, 22 and 23.
Although a preferred embodiment has been describcd in detail, it will be appreciated that various substitutions, alterations and additions may become apparent to those skilled in the art. These modifications may be made without departing from the scopc and spirit of thc- invention as defined by the appended claims.
What is claimed is:

Claims (18)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A power factor controller for an AC induction motor energized from an AC source via a gated semiconductor switch comprising:
a voltage/current phase lag sensing circuit for determining the lag of the current phase including a voltage crossing circuit for detecting the zero crossing of the line voltage and a timing circuit for detecting the zero crossing of the line current and determining in which one of a plurality of specified sequential time periods the line current zero crossing occurs, the time period defining a magnitude of current phase lag;
and a gate control circuit for determining the length of the firing angle delay of the gate signal to the semiconductor switch in response to a value stored in a memory circuit, said value being altered by said gate control circuit in response to the magnitude of the current phase lag.

2. The invention according to claim 1 wherein said specified sequential time periods include a first time period during which the line current zero crossing occurrence represents a sudden application of load requiring a minimal firing angle delay in order to apply full power to the motor and said gate control circuit in response to the zero crossing of the current in the first time period zeroing the value stored in the memory circuit.

3. The invention according to claim 2 wherein said plurality of specified sequential time periods includes a second time period during which the occurrence of the zero crossing of current indicates the need for more power and said gate control circuit in response to the zero crossing of the current in said second time period incrementally decreasing the value stored in the memory circuit.

4. The invention according to claim 3 wherein said plurality of time periods includes a third time period during which the occurrence of the current zero crossing indicates an optimum motor power factor and said gate control circuit does not alter the value stored in the memory circuit.

5. The invention according to claim 4 wherein said plurality of specified sequential time periods includes a fourth time period during which the current zero crossing indicates that said motor is getting more power than necessary and the gate control circuit in response thereto incrementally increases the value stored in the memory circuit.

6. The invention according to claim 5 wherein consecutive occurrences of the current zero crossing in said second time period further decreases firing angle delay in said gate control circuit until said zero crossing occurs in said third time period.

7. The invention according to claim 5 wherein consecutive occurrences of the current zero crossing in said fourth time period further increases firing angle delay in said gate control circuit until said current zero crossing occurs in said third time period.

8. The invention according to claim 7 wherein said gate control circuit includes a microcomputer including a memory register as said memory circuit, said memory register incremented to increase said firing angle delay, and oppositely decremented to decrease said firing angle delay in response to the magnitude of the current phase lag.

9. The invention according to claim 8 wherein said an occurrence of the current zero crossing in said first time period initializes said memory register or otherwise modifies the register so that the firing angle delay will be eliminated.

10. The invention according to claim 9 wherein:
said memory register is decremented at the end of the second time period in response to the occurrence of said current zero crossing in said second time period; or said memory register is incremented at the end of said third time period in response to nonoccurrence of said current zero crossing.

11. The invention according to claim 1 wherein said time periods include at least three sequentially discrete time periods including:
an early time period decreasing the firing angle delay in said gate control circuitry to cause the switch to conduct earlier in said cycle;
a middle time period leaving the firing angle delay of said gate control circuit unchanged; and a late time period increasing the firing angle delay to cause conduction later in said cycle.

12. The invention according to claim 10 wherein said memory register is repetitively incremented cumulatively upon each successive occurrence of the current zero crossing in said fourth time period until said current zero crossing again occurs prior to the end of said third time period.

13. The invention according to claim 10 wherein said memory register is repetitively decremented cumulative upon each successive occurrence of said current zero crossing in said second time period until said current zero crossing agin occurs at the end of said second time period.

14. The invention according to claim 10 wherein said memory register is zeroed at the end of said first time period in response to the occurrence of said current zero crossing in said first time period.

15. A method for controlling the power factor for an AC induction motor energised by an AC source via a gated semiconductor switch, said method comprising the steps of:
sensing the voltage zero crossing of said AC source;
sensing the zero crossing of the line current;
determining in which one of a plurality of specified sequential time periods that are initialized upon the occurrence of said line voltage zero crossing that the line current zero crossing occurs, the time period defining a magnitude of current phase lag;
selectively controlling the firing angle delay in response to the magnitude of the current phase lag.

16. A method according to claim 15, further comprising the steps of initiating a first time period in response to the voltage zero crossing and providing a nondelayed signal to said gated semiconductor switch in response to the occurrence of the current zero crossing in the first time period to provide substantially instantaneous full power to the motor in a sudden load situation;
initiating a second time period upon termination of said first time period in providing said signal to said gated semiconductor switch earlier in the source cycle in response to the occurrence of the current zero crossing in the second time period, to increase power to the motor;
initiating a third time period upon termination of the second time period and maintaining the firing angle delay unchanged in response to occurrence of the current zero crossing in the third time period; and initiating a fourth time period upon termination of said third time period and providing said gate signal later in the source cycle to decrease power to said motor.

17. The method according to claim 16 further comprising repetitively and cumulatively increasing said firing angle delay of said gate control circuit in response to the consecutive currents of said current zero crossing in said fourth time period until said current zero crossing occurs in said third time period.

18. The method according to claim 16 further comprising repetitively and accumulatively decreasing said firing angle delay of said gate control circuit in response to each consecutive occurrence of the current zero crossing in the second time period until said current zero crossing occurs in said third time period.