CA1166700A - Cardiac pacemaker with destructible means for selecting output mode and method of making same - Google Patents

Abstract

CARDIAC PACEMAKER WITH DESTRUCTIBLE MEANS
FOR OUTPUT MODE SELECTION
AND METHOD OF MAKING SAME

ABSTRACT OF THE DISCLOSURE

A cardiac pacemaker which can be manufactured in a wide variety of models having different output modes. There is mode selection circuitry, common to a plurality of output modes, and including a destructible means, such as one or more fusible links. A predetermined link or set of links is fused to select the desired output mode.
Selection of an output mode determines a set of output pulse parameters. A variety of pulse rates, pulse widths, hysteresis and refractory modes may be selected. The mode selection circuitry is such that reconnection of the circuit across the fusible links (via dendrites, wire bond chaff, solder balls, etc.) causes the pulse width to widen, pulse rate to go to 70 ppm., the hysteresis to be shut off, and the refractory to go to 325 milliseconds.
A subcircuit prevents the outputs of the mode selection circuit from floating when the links are fused.

Description

CARDIAC PACEMAKER WITH DESTRUCTIBLE ~EANS
FOR OUTPUT MODE SELECTIO~' AND METHOD OF M~KING SAME

BACKGROUND OF THE INVENTION
, The invention in general relates to body tissue stimulators and more particularly to a cardiac pacemaker that can be manufactured in a wide variety of models having diffexent output modes, and at the same time is economical to manufacture because all models employ 10 common circuitry.
The art of implantable cardiac pacemakers was first disclosed by Gre~tbatch in U.S. Patent No. 3,057,356 entitled "Medical Cardiac Pacemaker", which issued in 1962. The device disclosed by Greatbatch included a 15 relaxation oscillator that generated electrical pulses at a fixed rate. These pulses were applied to the heart through a lead to cause the heart to contract each time a pulse occurred.
It became evident early in the development of 20 the art of cardiac pacemakers that it was desirable to desiyn pacemakers so that a range of output parameters could be obtained. For example a variety of pulse rates was desirable because different patients may require different pulse rates, for example children normally 25 require a higher pulse rate than adults. As another example, a variety of pulse widths and/or pulse ampli-tudes was desirable because different patients could have different stimulation thresholds.
In early pacemakers the output parameters were 30 changed by altering individual circuit elements within the pulse circuits. ~or example the Greatbatch patent mentioned above discloses changing the capacitances and resistances within the circuit to change the pulse rate of the pacemaker. Later improvements disclosed various ,~

5 methods for ~hanging the output parameters, usually involving a means for changing the output parameters of the implanted pacemaker xemotely from outside the body.
For example~ U.S. Patent No. 3,198,195 issued to W. M.
Chardack discloses changing the rate and amplitude of the 10 pacemaker pulse by adjusting a potentiometer in the pacemaker with a needlelike tool. V.S. Patent No.
3,311,111 issued to G. L. Bowers discloses using magnetic switches to switch resistors or capacitors in and out of the pacemaker's circuit in order to change the pulse rate 15 of the pacemaker, and U.S. Patent No. 3,518,997 issued to R. W. Sessions discloses a pacemaker with two different oscillating circuits having different output parameters, which circuits can be independently activated by a mag-netic switch.
As the pacemaker art developed many improve-ments were made which made possible a wide variety of output modes in addition to the variable rate and pulse width modes. For example, a sense amplifier was in-corporated within the pacemaker circuit in order to 25 provide stimulating pulses only when needed (the demand pacemaker - See U.S. Patent No. 3,478,746 issued to Wilson Greatbatch), and a hysteresis function was added which permits the heart to beat naturally even though it is beating at a slower rate than the rate at which the 30 pacemaker is designed to operate (reissue UOS~ Patent No.
28,003, issued to David W. Gobeli). Another improvement to the pacemaker art was the addition of a refractory period in a demand pacemaker. During the refractory period the pacemaker is rendered immune to any signals 35 provided by the sensing amplifier, in order to ensure that the pacemaker stimulation is not suppressed by the sensing of natural electrocardiac signals such as the heart T-wave or spurious electrical signals which occur in the time interval immediately following a stimulated 40 beat of the heart. See U.S. Patent No. 3,433,228 issued 5 to John Walter Keller, Jr. Such improvements greatly increased the variety of outpu~ modes that could be incorporated into a pacemaker depending upon the desires and needs of physicians and patients. Other pacemakex improvements added a variety of means and methods whereby 10 the output parameters c~uld be varied. See U.S. Patent Nos. 3,631,860 issued to Michael Lopin; 3,623,486 issued to Barouh V. Berkovits; 3,738,369 issued to Theodore P.
Adams and David L. ~owers; 3,713,449 issued t~ Pietex J.
Mulier; and 3,766,928 issued to Herbert E. Goldberg and 15 Jonathon E. Bosworth.
With the advent of a digital pacemaker many improvements were made whereby the output modes of pacemakers could be varied by programming. See U.S.
Patents Nos. 3,805,796 issued to Reese S. Terry Jr. and 20Gomer L. Davies; 3,~33,005 issued to Robert C. Wingrovei 4,024,875 issued to James J. Putzke; and 4,066,086 issued to Clifton ~ Alferness. All these digital pacemakers were programmed by means of coded radio frequency or other signals applied externally of the patient within 25whom the pacemaker was implanted.
The manufacturing of pacemakers having a vari-ety of output modes by inserting a variety of different circuit elements had many disadvantages. Insertion of special parts for each mode added complexity to the 30manufacturing process which was expensive. The modern pacemaker is a highly sophisticated electronic instrument which is very susceptible to degradation of performance by dirt, impurities or other defects. The addition of special circuit elements requires soldering and manipu-35lation of the circuitry which significantly increases thechances of impurities and other minor defects entering the pacemaker. In additioni such addition of elements requires nonstandardized manufacturing operations which can lead to error in selection of paxts, and in assemb-40 ling of parts.

7~

The improvments which permitted the changing of output mode externally to the pacemaker by tools, mag-netic fields, or R.F. programming avoided many of the above problems. However, these methods require sophisti-5 cated electronics and mechanisms which are expensive tomanufacture. Expense is particularly not warranted in the large number of cases where the pacemaker needs to be programmed only once in order to adjust it to the partic-ular parameters required by the patient. In addition 10 mechanical adjustment means require a seal about the movable part in the pacemaker, which seal is highly susceptible to failure in the hostile environment of the human body, while the magnetic and R.F. programmed pacemakers may be erroneously programmed due to improper 15 placement or handling of the program device, or may be accidently reprogrammed by spurious magnetic or electri cal signals.

SUMM~RY OF THE INVENTION
It is an object of this invention to provide a 20 cardiac pacemaker that may be economically manufactured in a wide variety of models having different output modes.
It is another object of this invention to achieve the preceding object in a cardiac pacemaker that 25 may be easily and accurately programmed to any of a wide variety of output modes.
It is another object of the invention to a-chieve one or more the preceding objects in a cardiac pacemaker that can be adjusted to any of a variety of 30 output modes in a manner that presents little risk of contamination of the pacemaker, and of errors in per-forming such adjustments.
It is still another object of this invention to achieve one or more of the preceding objccts in a cardiac 35 pacemaker that automatically reverts to the safest or 7'~

most acceptable output parameters, i the mode selection mechanism should fail.
It i5 a further object of this invention to achieve one or more Gf th~ preceding objects in a cardiac 5 pacemaker in which the mode is selected by destruction of a circuit element~
It is yet a further object of this invention to achieve one or more of the preceding objects in a cardiac pacemaker in which the outputs of the mode selection 10 circuit are prevented from floating when the mode selec-tion circuit elements are destroyed.
In the practice of the invention a pacemaker is made from components including elec~ronic pulse generat-ing circuitry communicating with at least one output 15 terminal. The circuitry include~ destructible means, such as one or more fusible links. The circuitry is adapted so that when there is conduction across the destructible means one output mode i5 generated, and when the destructible means is destroyed so that there is no ~0 conduction across its terminals, another output mode is generated. The destructible means is then destroyed, for example one or more of the fusible links may be fused, to produce a pacemaker having the desired output mode.
Pre~erably the circuitry, except th~ output terminal, is 25 then sealed within a container khat is substantially inert to body fluids so that it may be implanted in a human body.
The apparatus of the invention provides a pulse generator having output mode selection circuitry in-30 cluding a destructible means such as the one or morefusible links. Each destructible means preferably com-municates with a mode selection circuit output terminal which is also an input terminal to the portion of the circuitry which determines the output pulse parameters.
35 Preferably a determinate state circuit means also com-municates with the terminal to prevent the terminal from floating when the destructible means communicating wi-th the terminal is destroyed. Preferably the output mode selection circuitry is adapted so that the mode selected when there is conduction across the terminals of the destructible means is the safer or more acceptable of the variety of output modes selectable.
Thus, in accordance with one broad aspect of the invention, there is provided a pacer for providing therapeutic stimulation of a patient's heart through a lead system comprising; a pulse generator circuit for producing an output pulse, having at least one alterable output parameter, selection circuit means coupled to said pulse generator for selecting a value of said alterable output parameter, a destructible circuit element coupled to said selection circuit means for controlling said selection circuit means.
In accordance with another broad aspect of the invention there is provided a pacer for providing stimulation to living tissue comprising:
an output pulse generator for generating a stimulation pulse in response to a trigger signal, a digital pacer circuit coupled to said output pulse generator for generating trigger signals at selectable times, selection circuit means coupled to said digital pacer circuit for selecting the times that said trigger signals are generated.
In accordance with another broad aspect of the invention there is provided a pacer for providing stimulation to living tissue comprising:
an output pulse generator for generating a stimulation pulse in response to a trigger signal, a digital pacer circuit coupled to said output pulse generator for generating trigger signals at selectable times, selection circuit means coupled to said digital pacer circuit for selecting the times that said trigger signals are generated, wherein selection circu:i~
means comprises: a strobe means for interrogat:Lng a destructihle circuit element on a periodic basis, a latch means coupled to said strobe means for storing the value of said destructible circuit element.
Numerous other features, objects and advantages of the invention will now become apparent from the following detailed description when read '7~J~

in conjunction with the accompanylng drawings, in which:
BRIEF DESCRIPTION OF DRAWINGS
Figure 1 is a block schematic diagram of the pacemaker circuitry for a preferred embodiment of the invention showing the various signals provided between the digital and analog portions of the circuit;
Figure 2 shows the arrangement of Figures 2a and 2b which in turn show, in block format the digital circuitry portion of the invention;
Figure 3 shows the arrangement of Figures 3a through 3d, which in turn show, a more detailed diagram of the digital circuitry of the invention;
Figure 4 shows an embodiment of the circuitry for selecting the output mode and for setting the mode selection output terminals to a determined electronic state; and Figure ~ shows an alternative em~odiment of the circuitry for selecting the output mode and for setting the mode selection output terminals to a determinate electronic state.
DESCRIPTION OF THE PREFRRRED EMBODI~ENT
Directing attention to the drawings, Figure 1 shows a schematic diagram of a cardiac pacemaker circuit according to the inven-tion. The cardiac pacemaker 10 includes a digital circuit 12 which communicates with an -6a-analog circuit 1~ to produce an electrical pulse which is delivered via outputs 16 and 18 to leads (not shown) for application to the heart (not shown) to cause the heart to contract. The leads through which the pulses are applied to the heart, the type of pulses applied, and the response of the heart to the pulses is well known in the art and will not be discussed herein.
The embodiment of the pulse generator 10 which shall be described is of the type that is implantable within the human body. ~lowever, nothing herein should be construed as limiting the invention described solely to the implantable type pulse generators.
The analog circuit as shown in Figure 1 consists of a number of generally separate electrical systems. These systems include a battery status monitor, a crystal oscillator clock, a voltage control oscillator clock, a QRS sensing amplifier~ a pulse rate limiting circuit and output circuitry which includes a voltage doubler. Each of these analog systems are well known in the art and will not be discussed in detail herein.
The digital circuit 12 includes the mode selection circuitry, the digital logic necessary to produce each of the selectable output modes, and digital timing means for causing pulses to be generated from pulse generator 10 in the selected manner. A more detailed description of digital circuit 12 is gi~ven below in the discussion relating to Figures 2a and 2b and a still more detailed description is given in the discussion with respect to ~IGs. 3a, 3b, 3c, 3d, 4 and 5.
Both the digital and analog circuits are pow-ered by battery 22, which may be a conventional lithium-iodide battery generating ~V, or approximately 2.8 volts, 5 connec~ed between a source of reference potential, such as ground 24, and the circuits 12 and 14. In the present description a signal ~t the power supply voltage may be referred to alternatively as a logic "1" or a high sig-nal. A signal at the ground voltage may be referred to 10 alternatively as a logic "0" or a low signal. The digi-tal circuit 12 is connected to ground at 26 and the analog circuit 14 is connected to ground at 28. Switch 32 is a conventional reed switch and may be closed by placing a magnet (not shown) in close proximity to pulse 15 generator 10 in a manner well known in the art. When reed switch 32 is closed a +V volts or a logic "11' REED
signal is applied both to digital circuit 12 and analog circuit 14. When the magnet is removed from the ~icinity of the pulse generator 10 reed switch 32 opens and a 20 ground, or logic "0" signal is applied to digital circuit 12 and analog circuit 14. The manner in which such signals are applied shall be described in more detail below.
As mentioned above, outputs 16 and 13 com-25 municate with conventional cardiac pacemaker leads toapply the pulse generator signal to the heart. Output 18 may consist of the outer metal casing of pulse generator 10 or it may connect with an electrode wire within a lead system, depending upon the type of cardiac pacemaker lead 30 selected. Output 16 is coupled to analo~ CiICUit 14 through a capacitor 34 to prevent DC leakage in the case of some system failures. A pair of diodes 36 and 38 have their anodes coupled together and their cathodes coupled to outputs 16 and 18 respectively. Diodes 36 and 38 35 function in the conventional manner to prevent damage to the circuitry of pulse generator 10 in the case of large _g_ extraneous signals, such as may be caused by electro-cautery.
Analog circuit 14 provides the XTAL, YCO, AMP, RATE LIMIT and BATTERY signals to digital circuit 12.
5 Digital circuit 12 provides the VCO ENABLE~ BLANK, and RECHARGE signals to analog circuit 14.
The XTAL signal i5 a square-wave pulse signal occurring at a requency of 32,768 Hz and the VCO is a square-wave pulse signal having a frequency of 20,000 Hz 10 whenever the voltage of battery 22 is equal to 2.8 volts and decreases approximately proportional to the square of the voltage to about 10,000 Hz when the battery voltage is equal to 2.0 volts. This decrease of the VCO fre-quency is used, as shall be explained in more detail 15 below, to provide an increase in the pulse width as the voltage from battery 22 decreases, in order to maintain a constant energy of the pulse.
The VCO ENABLE signal provided from digital circuit 12 to analog circuit 14 is normally a logic "1".
20 However, at the time the stimulation pulse is to be pro-vided, the VCO ENABLE signal becomes a logic "0" and the VCo is enabled to begin providing pulses. The VCO ENABLE
signal remains logic "0" until aftex the stimulating pulse has been provided, at which time it returns to 25 logic "1" and the VCO becomes disabled.
The AMP signal is provided from the output of the analog QRS sensing amplifier and i~ normally a logic "1" signal. Each time the QRS amplifier senses a natur-ally ocurrring QRS signal, it becomes a logic "0" pulse 30 signal.
The BLANK signal provided from digital circuit 12 is normally a logic "1" which becomes logic "0" for approximately 100 msec following the provision of a stimulating pulse from pulse generator 10 or the sensing 35 of a natural heartbeat. The BLAN~ signal is used to prevent the QRS sensing amplifier within analog circuit .

14 from sensing any signals during the 100 msec time interval and to all~w the components within the sensing amplifier circuit to reset themselves after sensing a sign~l.
The RECHARGE signal is a normally logic "0"
which becomes logic "1" for approximately 10 msec after the stimulating pulse has been provided by generator 10.
The purpose of the REC~ARGE signal is to close a switch in analog circuit 10 to allow an output capacitor to re-10 charge after every output pulse.
The RAT~ LIMIT signal which is provided from analog circuit 14 to digital circuit 12 is a normally logic "0" signal which becomes logic "1" after the pro-vision of the stimulation pulse for approximately 500 15 msec to set an upper rate limit of approximately 120 pulses per minute for pulse generator 10. This rate limitation function is used as a backup and safety feat- f ure against the possibility of an integrated circuit or crystal oscillator failure that may cause high rate 20 output to occur.
The BATTERY signal applied from analog circuit 14 to digital circuit 12 is a logic "1" signal so long as the voltage provided from battery 22 is above a certain minimum level, for example 2.0 volts, and is a logic 10 25 signal whenever the voltage from battery 22 falls below the minimum level.
Referring now to FIG. 2, there is shown the manner of arranging FIGs. 2a and 2b to form a block diagram of digital circuit 12. In FlGs. 2a and 2b any 30 signals which are received from, or applied to analog circuit 14 are designated by the particular label for the ;
signal placed within an oval, for example the battery signal just discussed above is shown at 40 in FIG. 2a.
The oval labeled "strobe" is an output to portions of the 3s digital circuit which shall be described below. All provisions of power supply voltage or ground coupled to o each block have been deleted, although it should be understood that these ~ignals are necessary and should be coupled i~ a known and accepted manner of designing digital logic circuits. For each of the blocks shown in 5 FIGs. 2a and 2b data signals are shown as being applied to the left side of the block, reset signals are shown as being applied to the bottom of the block, set signals are shown as being applied to the top of the block, and output signals are shown as originating from the right 10 side of the block. Arrows pointing into the block indicate a signal applied to the block, whereas arrows pointing out of the block d signate a signal originating from the block. Wherever a plurality of lines are transmitted from, or to a particular block cirucit, such as a parallel 15 output from a counter or shift register such plurality of lines are represented as wide lines such as at 42 in FIG. 2a.
Turning now to a description of the manner in which the various subcircuits of the pacemaker are con-nected and interact as shown in FIGs. 2a and 2b, the 20 pulse rate and hysteresis rate selection circuitry is shown at 50, the pulse width selection circuitry is shown at 52, the hysteresis function selection circuit is shown at 54, and the refractory period selection circuit is shown at 56. Eleven pulse rates and two hysteresis rates 25 are selectable. Selecting a rate, as shall be described below, causes a predetermined combination of logic "1"
and logic "0" signals to be output from rate selection circuitry 50 and applied to rate decode logic circuitry 60. If the hysteresis function is selected a logic "0"
30 signal is output from hysteresis function selection circuitry 54 and applied to hysteresis logic 64; if the nonhysteresis function is selected a logic "1" signal is output and applied between the same circuits. The selec-tion of the pulse width causes a predetermined set of 35 logic "0" and logic "1" signals to be output from the pulse width selection circuitry 52 and applied to the -12~

pulse width decode l~gic circuitry 62. Selection of the refractory period causes a predetermined one of either a logic "0" or a logic "1" signal ~o be output from refrac-tory selectio~ circuitry 56 and applied to refractory 5 logic 66.
- The timing of ~he pulse generator function is provided ~y the XTAL oscillator and VC0 oscillator signal originating from analog circui~ outputs 70 and 72 respec-tively, and having the frequencies described above. The 10 XTAL and VC0 outputs 70 and 72 are applied to crystal/VC0 select logic 74. The VC0 output also communicates direct-ly with output logic 80, rate count set logic 82, and amp reset logic 84. Crystal/VC0 select logic 74 selects one of the XTAL or VC0 signals and provides it as the upper 15 output signal which is applied to slow clock/PW counter 76 and to the set input of the slow clock reset gate 78.
If any of the inputs to crystal/VC0 select logic 74 (other than the XTAL and VC0 inputs) are a logic "1" the circuitry selects the VC0 signal, and at the same time 20 applies a logic "U" signal through its lower output to VCo ENABLE output 86. If all of the inputs (other than the XTAL and VC0 inputs) are a logic "0" the XTA~ signal is selected and a logic "1" signal is output to-VC0 ENABLE 86. If the upper output of the crystal/VC0 select 25 logic, either XTAL or VC0 provides a fast clock signal for the pulse generator circuit. The VC0 pulse starts low (logic "0") and is triggered by the XTAL clock pulse with the result that there is an apparent synchronization between the XTAL and VC0 clocks.
Slow clock/PW counter 76 is an eightstage binary counter connected in a known manner. The output signal from slow clock 76 is provided to slow clock detect logic gO, to recharge logic 116 and to pulse width decode logic 62. When slow clock/PW counter 76 counts 35 179 fast clock cycles detect logic 90 reads this count and provides an output signal through its upper output to slow clock reset gate 78, which in turn provides an output signal to reset slowclock/PW counter 76. The resetting of the slow clock~PW counter 76 after each 179 fast clock cycles determines a time interval called slow 5 clock which is equal ~o approximately 5 . 4 9 msec .
Slow clock detect logic 90 provides a slow clock signal through its lower output to rate counter 94, which is an eightstage binary counter connected in a known manner. The output of rate counter 94 is provided 10 to rate decode logic 60, counter "1" detect gate 104, refractory logic 66, blanking logic 106, and xecharge logic 116. The count of rate counter 94 is read by rate decode logic 60 and when the number of counts determined by the inputs to rate decode logic from rate select 50 15 and hysteresis logic 64 is reached, rate decode logic 60 provides an output signal to rate gate 96. The output from rate gate 96 is provided to crystal/VC0 select logic 74, in order to turn on the VCO oscillator as described above, and to output logic 80 in order to initiate the ~0 pulse output sequence as ~hall be described below.
Output trigger 98 is a test pin by means of which an external output can be applied to rate gate 96 to force the pulse generator into rate limit either to test the rate limit circuitry and/or in order to perform a laser 25 trim of a resistor on the rate limit circuitry at the time of manufacture.
Output logic 80 is responsive to signals from the upper output of crystal/VC0 select logic 74, and the outputs of rate gate 96 and VC0 output 72. The reset 30 input of output logic 80 is responsive to the rate limit output 112 from analog circuit 14. The upper output of output logic 80 is applied to crystal/VCO select logic 74, to rate count set logic 82 and to amp disable logic 102. The middle output is applied to crystal/VC0 select 35 logic 74, to,output 110 to the analog circuit, to rate count set logic 82, to amp disable logic 102 and to the ir~

reset input of hysteresis logic 64. The lower output is applied to rechar~e logic 116 and rate gate 96.
As mentioned above ~he signal from rate ga~e g6 activates the VCO oscilla~or. On the first VCO pulse 5 output logic 80 is clocked and its upper output changes from logic ll0" to logic "1". This signal is applied to crystal/VCO select logic 74 to shut off the VCO oscil-lator during the period in which the pacemaker is in rate limit as shall be discussed further below, and clocks 10 rate count set logic 82 so that its lower output goes to logic "1". This signal is applied to the set input of rate counter 94 to force all its stages to a logic "1"
output state. Counter "1" de~ect gate 104 detects this "all l's" condition and changes its output from logic "0"
15 to a logic "1"~ This signal from counter "1" detect gate is applied to slow clock reset gate 78 to reset slow clock/PW counter 76 and to the reset input of rate count set logic 82.
On the next VCO oscillation output logic 80 is 20 again clocked and its middle output changes from logic "0" to logic "1". The application of this signal to output 110 initiates the pulse generator output in analog circuit 14. The same signal applied to crystal/VCO
select logic 74 continues to enable the VCO oscillator 25 for the duration of the output pulse. The signal is also applied to rate count set logic 82 to enable it so that on the next VCO oscillation its upper output goes from logic "0" to logic "1". This signal is in turn applied to rate counter 94 and clocks it to an overflow condition 30 removing the logic "1" status of each of its stages to prepare the rate counter for the next count cycle.
Rate limit output 112 from analog circuit 14 is applied to the reset input of output logic 89 and to crystal/VCO select logic 74. ~he rate limit function is 35 a secondary one-shot function on a separate die and is used as a ~ackup against the possibility of integrated -lS-circuit or crystal oscillator failure which might create high rate output. The signal applied from rate limit output 112 is normally a logic "0", but during an approxi-mately 500 msec period followiny the output pulse it is a 5 logic "1". The logic "1" signal applied to the reset input of output logic 80 holds the middle output at a logic "0" until the end of the rate limit period, thereby blocking the output pulse during this period. Thus the rate limit output inhibits rates faster than approxi-10 mately 120 beats,per minute and does not allow the outputto go to a 2:1, 3:1, etc. divide condition., The cir-cuitry of output logic 80 is such that if an output pulse were to be called for before ~he rate limit time period had elapsed, the circuitry is held reset. Then, on the 15 next positive clock transition after the rate limit interval runs out and the signal from rate limit 112 returns to logic "0" the output pulse is initiated.
The signal from rate limit 112 applied to crystal/ VCo select logic 74 shuts off the VCO oscillator 20 during the period in which the upper output logic 80 is logic "1" and the rate limit circuitry is on. Thus, if the pacemaker is in a runaway condition in which the output pulse is being called for during the rate limit period, the VCO oscillator is held in the OFF condition.
25 This ~unction minimizes current drain if a runaway condition should ariseO
As discussed above, just prior to the initiation of the output pulse the rate counter is set to an "all l's" condition which condition is detected by counter "1"
30 detect gate 104 which thereupon signals slow clock reset 1, gate 78 to reset slow clock/PW counter 76. Slow clock/PW
counter 70 then begins increasing its count again in response to VCO oscillator pulses from crystal/VCO select 74. Pulse width decode logic 62 reads the count of slow 35 clock/PW counter 76, and when it has reached a count determined by the output of pulse width select 52, pulse -width decode logic 62 provides a signal to pulse widthgate 100. The output of pulse width gate 100 is provided to output logic 0 to enable the output circuitry so that the output pul~e is terminated on the next-VCO clock 5 cycle.
The lower ou~put of output logic 80 changes from logic 1l0-- to logic "1" at the termination of the output pulse. This signal is applied to the recharge circui~ry to enable it so that after a period determined 10 by a signal provided from slow clock/PW coun~er 76 the output from recharge logic 116 goes from logic "0" to logic ~ to initiate the recharge interval. This signal is applied to the analog circuit through recharge output 118. Approximately 10 msec after the initiation of the 15 recharge interval recharge logic 116 is reset via a pulse from rate counter 94 and thereby resetting the output to logic "0l- to terminate the recharge interval.
- Battery output 40 from the analog circuit 14 is provided to battery depletion logic 92. Battery deple-20 tion logic 90 is also responsive to the lower output ofamp disable logic 102 and the upper output of crystal/VCO
select logic 74. The upper output of battary depletion logic 92 is provided to refractory logic 66 and the lower output is provided to slow clock detect logic 90. Battery 25 depletion logic 92 is clocked by crystal/VCO select logic 74 each time the VCO is enabled just prior to an output pulse. This timing of the clock signal prevents supply ripple during or for a period after the pulse from pre-maturely triggering the battery depletion condition. Is 30 the battery is depleted, battery depletion logic 92 provides a logic "0" signal at its lower output which is applied to slow clock detect logic 90 to extend the slow clock interval by 11.1 percent to provide a 10 percent slowdown in the pulse rate. At the same time, a logic 35 "1" signal i5 provided to refractory logic 66, from the lower output of battery depletion logic 92 to ensure a '7~J~

stable refractory interval as described below. The battery depletion logic circuit is ]atchable; i.e~ if the battery signal shows depletion at the time of any clock pulse provided by crystal/VCO select logic 74, then any subsequent clock pulse results in the output which extends the slow clock interval. The logic may be "unlatched" by the signal from amp disable logic 102, which is provided whenever reed switch 32 is closed. If the BATTERY signal no longer is indicating battery depletion at the time that the reed switch iæ closed then the battery depletion logic resets to its normal output. However, if the BATTERY signal indicates battery depletion at the time that the reed switch is closed then battery depletion logic 92 remains latched.
We now turn to a discussion of the pacemaker circuitry related to the demand function of the pulse generator, i.e. the function that prevents a generated pulse from being output if a natural heartbeat is detected. Amp output 130 from analog circuit 14 is provided as one input to amp reset logic 84. Other inputs to amp reset logic 84 are from VCO output 72 and the middle output of amp disable logic 102. The upper output of amp reset logic 84 is applied as an input to rate count set logic 82, amp disable logic 102, crystal/VCO select logic 74, and as the set input to hysteresis logic 64. The lower output is provided as an - 25 input to rate counter 94 and crystal/VCO select logic 74.
In normal operation of the pacemaker a detected heartbeat causes a clock æignal to be applied to amp reset logic 84 from output 130. If the middle output of amp disable logic 102 is a logic "1" the clock signal from output 130 causes the upper output of amp reset logic 84 to change to a logic "1" state. The logic "1" signal applied to rate count set logic 82 causes rate counter 94 to be set to "all l's" as described above and the signal to crystal/VCO select logic 74 turns the ~CO onO On the first VCO pulse amp reset logic 84 is clocked to provide a logic "1" signal at its t7~J~

second output which is applied to rate counter 94 and crystal/yCO select logic 74. The signal to the rate counter 94 clocks the rate count stages to an overflow condition, while the signal to crystal/VCO select logic 5 74 maintains the VCo ON condition. Amp reset logic 84 resets itself at the same time so that the upper output goes to a logic "0" and one VCO pulse later the second output goes to a logic "0" thereby turning off the VCO
and readying the amp reset logic for the next cycle 10 triggered by the next natural heartbeat.
Blanking logic 106 is responsive to the lower output of slow clock de~ect logic 90 and the output of rate counter 84. Its set input is responsive to the output of counter "1" detect gate 104. The upper output 15 of blanking logic 106 is provided to blank output 134 and the lower output is provided to reversion logic 108 and threshold test logic 22. Blanking logic 106 is clocked each time the lower output of slow clock detect logic 90 changes from logic "0" to logic "1". Most of these clock 20 pulses have no effect on the output states of blanking logic 106 because the circuitry has a self-latching loop that causes the output to retain their previous state with each clock pulse. This state is normally a logic "1" for the upper output and also a logic "1" for the 25 lower output. The signal from counter "1" detect gate 104 however sets blanking logic 106 at the beginning of the output pulse and after a natural heartbeat is sensed.
This changes the upper output to a logic "0" to initiate the blanking period and also changes the lower output to 30 a logic "0". The SET signal from counter "1" detect gate 104 goes to a logic "0" on the next VCO pulse, however the blanking logic 106 maintains itself latched in the blanking output condition until approximately 100 msec after the initiation of the pulse when the signal from 35 rate counter 94 relatches blanking logic 106 into the "nonblanking" state described above, thereby terminating -the blanking interval. During the blanking interval ~he sensing amplifier in analog circuit 14 is blanked thereby preventing any input to amp reset logic 84 from amp outp~t 130~
Amp disable logic 102 is responsive to the outputs of reed output 140 and reversion logic 108, the lower output of refractory logic 66, the upper output of amp reset logic 8~, and the middle and upper outputs of output logic 86. The lower output of amp disable logic 10 102 is provided to th~eshold test logic 122 and battery depletion logic 92. The middle output is provided to amp reset logic 84, while the upper output provides a strobe output 142 which is used elsewhere in the digital circuit and shall be described below. The output to strobe 142 15 is a logic "0" except in two instances: it is a logic "1" in the time period between the two output pulses from output lo~ic 86, a time period of approximately 25 ~ sec just at the initiation of the output pulse; it is also a logic "1" during the time in which the upper output from 20 amp reset logic 84 is a logic "1", that is the period during which the rate counter is being set after each detected natural heartbeat, again a very short period.
The lower output of amp disable logic 102 is normally a logic "1" but goes to a logic "0" during a time period 25 between the trailing edge of the first strobe pulse after the reed switch 32 is closed until the trailing edge of the first strobe pulse after reed switch 32 is opened.
The middle output of amp disable logic 102 is normally logic "1" whenever either the lower output from refrac-30 tory logic 55 or the output from reversion logic 108 is a logic "0". The middle output is also a logic "0" during the period described above when the lower output is "0", that is during the approximate time period during which the reed switch is closed.
Refractory logic 55 is responsive to the output of refractory select 56, the upper output of battery

2~-depletion logic 92, the lower output of slow clock detect logic 90, and to the output of the rate counter 94. The set input of refractory logic 55 i8 responsive to the output of counter "1" detect gat~ 104. The upper 5 output of refractory logic 66 is applied to reversion logic 108, while the lower output is applied to amp disable logic 102. The output of counter nl" detect gate 104 goes to logic "1" just prior to the initiation of the output pulse, and just after the detection of a natural 10 heartbeat as described above. This logic "1" signal sets refractory logic 66 causing its upper output to go to logic "1" and its lower output to go to logic "0"~ As can be seen from a discussion of the amp disable logic 102 and amp reset logic 84 above the logic "0" state of 15 the lower output of refractory logic 66 causes the middle output of amp disable logic to go to a logic "~" which in turn disables amp reset logic 84 from activation of rate count set logic 82. When the rate counter reaches the count which determines the refractory period the input to 20 refractory logic 66 from rate counter 94 goes to a logic "1". The trailing edge of the same slow clock pulse from slow clock detect logic 90 that advanced rate counter 94 to the refractory count, clocks refractsry logic 66 so that its upper output goes to a logic "0" while its lower 25output goes to a logic "1". This terminates the refractory period and allows the amp reset function to operate as discussed above. If the output of refractory select 56 is logic "0" a 325 msec refractory period is selected; if the output is a logic "1", a 400 msec refractory period 30is selected. As mentioned above, the input to refractory logic 66 from battery depletion logic 92 causes the refractory logic 66 to recognize an earlier count from rate counter 94 in order that the 11 percent slowdown of the slow clock and rate counter after the battery is 35depleted is offset and a stable refractory interval is obtained.

Reversion logic 108 is r sponsi~e to the loweI
output of blanking logic 106, the uppex output of refrac-tory logic 66, and the output of amp output 130. The output of counter "1" detect gate 104 is applied to the 5 reset input of reversion logic 1~8. The output of rever-sion logic 108 is applied to amp disable logic 102 as discussed above. The logic "1" signal from counter "1"
detect gate 104 resets reversion logic 108 just prior to the initiation of the output pulse or just after a natural 10 heartbeat. The reset signal places a logic "1" signal on the reversion logic 108 output. At the same time the upper output of refractory logic 66 has become a logic "1" also. At the end of a 100 msec blanking interval the lower output of blanking logic 106 becomes a loglc "1" as 15 discussed above. With the inputs from both refractory logic and blanking logic being a logic "1" reversion logic 108 is enabled to receive inputs from amp output 130. This enabling period ends when the upper output of refractory logic 66 goes to a logic "0" at the end of the 20 refractory interval. If two pulses from the amp output 130 are received during this reversion interval the output of reversion logic 108 goes to a logic "0" dis-abling the amp reset logic 84 through amp disable logic 102 as discussed above with respect to the refractory 25function~ Since the refractory interval is either 325 or 400 msec the reversion interval is either 225 or 300 msec; therefore the fac~ that the reversion is effective if two pulses are detected means that any continuous signal of frequency greater than 8.8 Hz or 6.6 Hz (de-30 pending upon the refractory period chosen) is rejected bythe reversion circuit.
Hysteresis logic 64 is responsive to the output of the hysteresis function select circuit 54, has a set input from the upper output of amp reset logic 84, and 35 has a reset input from the middle output of output logic 86. Both the upper and lower outputs of hysteresis logic ;'7~ ~ ~

64 are applied to rate decode logic 60. As discussed above, the amp output 130 signals a detected heartbeat the upper output of amp reset logic 84 goes to a logic "1". This signal sets hysteresis logic 64 so that the 5 upper output goes to a logic "1" while the lower output goes to a logic "0". The logic "1" signal is applied to rate decode logic 60 to enable the hysteresis rate. The logic "0" output is applied to rate decode logic 60 to disable all possible pacemaker ra~es except the two 10 hysteresis rates. Hysteresis logic 64 will remain in this state as long as the heartbeat rate remains above the hysteresis rate, since each natural heartbeat resets rate counter 94 so that the hysteresis count is not reached. If the heartbeat drops below the hysteresis 15 rate the counter reaches the hysteresis count and signals for an output pulse through rate gate 96 as described above. When the output pulse is initia~ed by the logic "1" signal from the middle output of output logic 86, a logic "1" reset signal is applied ~o hysteresis logic 64.
20 The signal causes the upper output of hysteresis logic 64 to change the logic "0" state and the lower output to change to a logic "1" state. The logic "0" signal disables the hysteresis rate in rate decode logic 60 while the logic "1" signal enables the "normal" rates in 25 rate decode logic 60 to provide an output signal at the selected rate. This continues until a natural heartbeat is again detected and the cycle repeats. If the output from hysteresis function select 54 is a logic "0" the upper output of hysteresis logic 64 will remain at a 30 logic "0" state while the lower output will remain at a log~c "1" state, which disables the hysteresis function.
If the output of hysteresis function select 54 is ~ logic "1" the hysteresis function is enabled and hysteresis logic 64 operates as discussed.
Threshold test logic 122 is responsive to the lower output of blanking logic 106. The reset input of t~

threshold test logic 1~2 is responsive to the lower output of amp disable logic 102. The upper output of threshold test logic 122 is applied to pulse width decode logic 62 while the lower outpu~ is applied to rate decode 5 logic 60. As discussed above the lower output of amp disable logic 102 is normally a logic "1" which signal holds threshold tes~ logic reset. Both outputs are held in the logic "0" s~ate in this situation. The closing of the reed switch 32 places a logic "0" signal on the lower 10 output of amp disable logic 102 coinciding with the trailing edge of the strobe pulse which comes just at the initiation of the output pulse. This signal enables threshold test logic 122. There is no immediate effect on the rest of the pulse generator circuit. A normal 15 output pulse or natural heartbeat (whichever is dictated by the circumstances) occurs. At the end of the 100 msec blanking period following either the normal output pulse or natural heartbeat the lower output of blanking logic 106 changes from a logic "0" to a logic "1". This signal 20 clocks threshold test logic 122 which changes the lower output to a logic "1", while the upper output remains at a logic IOn. The logic "1~' signal is applied to rate decode logic 60 to enable the 100 pulse per minute rate.
The next output pulse therefore occurs in 600 msec, 25 unless the pacemaker rate or the natural heartbeat rate is faster than 100 beats per minute, in which case a pulse or natural heartbeat at this faster rate occurs.
After this pulse or heartbeat threshold test logic 122 is again clocked by blanking logic 106. This third clocking 30 again places the lower output in a logic "1" state and also places the upper output in a logic "1" state. The signal from the lower output again stimulates a 600 msec pulse interval, while the signal from the upper output is applied to pulse width decode logic 62 to cause the pulse 35 width to be seventy-~ive percent of the selected output pulse width., Thus, on closing the reed switch two normal ~6'7~) -2~-output pulses at a rate of 100 beats per minute or higher are observed followed by a third pulse at the 100 pulse per minute rate, which pulse is seventy-five percent of the "noxmal" pulse width. Af~er the narrower pulse 5 threshold test logic 122 is again clocked by blanking logic 106, which signal causes the circuit to reset itself and hold itself reset until the reed switch is again closed.
Referring now to FIGs. 3a through 3d a more de-10 tailed description of each of the blocks shown in FIGs.2a and 2b will be given, except ~or blocks 50, 52, 5~, and 56 which relate to the mode selection function, which blocks will be discussed in connection with the FIGs. 4 and 5. The arrangement of FIGs. 3a through 3d in order 15 to form a single composite figure is shown in FIG. 3.
The circuits shown in FIGs~ 3a through 3d are organized in such a manner that all of the logic elements associ-ated with a particular figure block show~ in FIGs. 2a and 2b are in the same location and surrounded by a darker 20line having a number corresponding to the block number in FIGs. 2a and 2b. Insofar as possible, each numbered block in FIGs. 3a through 3d remains in the same relative position to the other numbered blocks as it was in FIGs.
2a and 2b.
The component parts of the circuit shown in FIGs. 3a through 3d include latches, AND gates, OR gates, NAND gates, NOR gates, inverters and transistors.
A latch, or flip-flop, as such are commonly re-ferred to, is shown as an element 76E in the upper left-30 hand corner of FIG. 3a. It is designated as a rectanglehàving longer verticle sides. Inputs to each latch are normally from the left side with the upper input being a data input and the lower input being a cloc~ input. The outputs of the latch are taken from the right side with 35 the upper output being a conventional "Q", and the lower output being the convention "Q" output. For selected i~~

latches, a set and/or a reset input are pro~ided with the set input being applied to the top of the rectangle and the reset input being applied to the bottom ~f the rec-tangle. In operation, a logic "1" signal applied to the 5 set input causes the "Q" output to assume a logic "1"
state and the "Q" output to assume a logic "0" state. A
logic "1" signal applied to the reset input causes the "Q" output to assume a logic "0" state. Whenever a signal which changes from logic "0" to logic "1" is 10applied to the clock input, the "Q" output assumes a logic value equal to the logic value of the, si~nal applied to the data input and the "Q" output assumes the opposite logic value.
An AND gate is shown schematically as element 1590A in FIG. 3a. Such a gate has two or more inputs and one output. The output of an AND gate is a logic "0"
signal unless the signals applied to the inputs are all a logic "1", in which case the outputs of the AND gate is a logic "1" signal. A NAND gate is shown as 92A in FIG.
203a. Such a gate also has two or more inputs and one output. The output is a logic "1" signal unless the signal applied to each of the inputs is a logic "1", in which case the output is a logic "0" signal.
An OR gate is shown schematically ais element 25 78A in FIG. 3a. Such a gate has two or more inputs and one output. The signal at the output of an OR gate is a logic "1" if any of the signals applied to the input is a logic "1", and is a logic "0" only in a case where all of the signals applied to the inputs are a logic "0".
A NOR gate is shown schematically as element 74D in the lower portion of FIG. 3b. It has two or more inputs and one output. The signal at the output of a NOR
gate is normally a logic "0" unless the signals supplied to each of the inputs are all a logic "0" in which case 35 the signal at the output is a logic "1".
An inverter is shown schematically as element ` -74A in the lower righthand side of FIG. 3b. Such an element has one input and one output with the output providing a signal having a logic value opposite to that of the signal applied to the input.
Transmission gates are shown schematically at ?4B and 74C in FIG. 3a, 74B each being composed of two transist~rs, an n-channel and a p-channel transistor. In the circuit shown the gates act simply as bilateral switches. In each switch there are two terminals indica-10 ted ~y the darkened half-circles, which terminals can be the inputs or outputs since current will flow both ways through the switch; in the application shown however signals are applied so they flow only from left to right.
The control voltages are applied to the gates of the 15 transistors which are shown in the drawing as the upper and lower terminals of the transmission gates with the logic value of the signal applied to the upper terminal of each transmission gate being opposite in value to the logic value of the signal applied to the lower terminal 20 of the transmission gate. When the common line between the transmission gates goes to a logic "1" value the p channel transistor in the upper transmission gate 74B
turns off while the n-channel in the lower transmission gate 74C turns on; at the same time the logic "O" signal 25 applied to the upper terminal of gate 74B turns off the n-channel transistor of that gate which the logic "O"
signal applied to the lower terminal of gate 74C turns on the p-channel transistor of that gate. When the signal on the common line goes to logic "O" the transmission 30 gate 74B turns on while the transmission gate 74C turns off.
As stated above, the conventional provisions of power supply voltages and ground are not shown in the circuit. However, applications of power supply voltage 35 and ground are shown when they are applied to the input of a latch. 'A power supply voltage is shown schemati-cally at 82A in the lower lefthand corner of FIG. 3c,while the ground is shown schematically at 82B in the same figureO The ovals bearing a written lable, such as at 40 in FIG. 3a refer to output or inputs, usually to 5 the analog circuit, as described above. The oval bearing no written lable, such as at 60Q in the lower lefthand cornex of FIG. 3a refer to outputs from the mode selec-tion circuitry, which shall be described in more detail below in connection with the discussion of FIGs. 4 and 5.
The detailed circuitry in FIGs. 3a through 3d shall be explained in roughly the same order in which the circuit blocks were discussed above. Referring to FIG.
3b the crystal/VCO select circui~ is shown at 74. It consists of inverter 74A, the two transmission gates 74B
15 and 74C, NOR gate 74D, AND gate 74E, and NAND gate 74F.
NOR gate 74D is responsive to inputs from rate gate 96 ~via AND gate 74E), from output logic 85, and to two inputs fxom amp reset 84~ If any of these inputs are a logic "1", the output of NOR gate 74D becomes a logic 20 "0". This logic "0" enables the VCO oscillator in analog circuit 14 through VCO ENABLE output 86. This signal is also applied to the upper terminal of transmission gate 74B and the lower terminal of transmission gate 74C, and is applied to the input of inverter 74A thereby causing a 25 signal of the opposite value, a logic "1" in this instance to be applied to the common line of the transmission gates. With this bias the transmission gate 74C will conduct while the transmission gate 74B will not conduct, causing the circuit to "select" the VCO oscillator signal 30 for its output. If all the inputs to NOR gate 74D are made logic "0" its output is a logic "1" signal. This signal disables the VCO oscillator through VCO ENABLE
output 86 and causes a logic "1" signal to be applied to the "non-common" terminals of transmission gates 7qB and 35 74C while a logic "0" signal is applied to their common line. This causes the transmission gate 74B to conduct ;

'7~
2~-and the transmission gate 74C to not conduct, hereby "selecting" the crystal oscillator signal for the oscillator output of the circuit. The signal from rate gate 96 is gated through AND gate 74E. This signal is blocXed if 5 the input to gate 74E from A~7D gate 74F is a logic "O"
which, in turn, is the case only if both of the inputs to gate 74F are logic "1". One of these inputs is applied from output logic 80 and the other from RATE LIMIT output 112. As will be seen from the discussion below of the 10 output l~gic circuit, both of ~he inputs are logic "1"
only during the period in which an output pulse has ~een called for, but the pulse has been held in abeyance by a RATE LIMIT signal. This, in effect, prevents the rate gate signal from being applied to NOR gate 74D during 15 this period, and thus prevents the VCO oscillator from being enabled, which would unnecessarily consune power during a period in which the VCO oscillator is not needed.
The output selected by crystal/VCO select 74 is 20 applied to slow clock/PW counter 76 in FIG. 3a. Slow clock/PW counter 76 is comprised of eight flip-flops 76A
through 76H. The oscillator signal from crystal/VCO
select 74 is applied to the clock input of flip-flop 76A.
The "Q" output of each flip-flops 76A through 76H is 25 applied to its own data input and is also applied to the clock inpu7~ of the next succeeding flip-flop. The reset input of each of the flip-flops 76A through 76H is responsive to the output signal of OR gate 78A in slow clock reset 78. The "Q" output of flip-flops 76A through 30 76H are applied to the slow clock detect 90, pulse width decode 62, and the recharge 116 circuits as shall be de-scribed below.
Slow clock detect logic 90 includes AND gates 90A and 90B and OR gate 90C. The "Q" output of flip-35 flops 76A~ 76B, 76E, 76F, and 76H in the slow clock/Ph7counter 76 circuit are applied to the inputs of gate 90A.
The "Q" output of latch 92C in battery depletion circuit t'(~

--2g--92 is also applied as input to gate 90A. If the latter input is a logic "1" then the output of gate 90A will become a logic "1" when the "Q" output of flip-flops 76~, 76B, 76E, 76F and 76H are all a logic "1". This con-5 dition is first reached after 179 oscillation pulses havebeen applied to the clock input of latch 76A. The output of gate 90A is applied to the input of OR gate 90C, thus when the output of gate 90A becomes logic "1" the output of gate 90C also becomes a logic "1". This signal is 10 applied to the data input of latch 78B in slow clock reset logic 78. The clock input of latch 78B is re-sponsive to the oscillator output of crystal/VCO select logic 74. Thus, on the next oscillation after the output of OR gate 90C becomes a logic "1" the "Q" output of 15 latch 78B is clocked to a logic "1" state. This output is applied to OR gate 78~, which becomes logic "1" in response to the same logic value being applied its input.
As mentioned above, the output of OR gate 78A is applied to the reset inputs of flip-flops 76A through 76H in slow 20 clock/PW counter 76. Thus, the logic "1" output of gate 78A causes flip-flops 76A through 76H to be reset so that all its "Q" outputs are 0, and a new slow clock cycle begins on the next oscillator pulse applied to the clock input of latch 76A. The "Q" outputs of flip-flops 76A, , 25 76B, 76C, 76G and 76H are applied to the inputs of AND
gate 90B. These outputs are all a logic "1" only after 199 oscillator pulses have been counted by slow clock/P~
counter 76. Normally this count will not be reached since flip-flops 76A through 76H will be reset after 179 30 clock cycles. However, if the "Q" output of latch 92C is a logic "0" then the output of gate 90A will remain a logic "0" and counter 76 will continue counting until 199 oscillator cycles have been counted, whereupon the output of gate 90B will become a logic "1". This output signal 35 is applied to OR gate 90C and flip-flops 76A through 76H
are reset through slow clock reset circuit 78 as des-6~

cribed above.
Rate counter 94 in FIG. 3c is composed of OR
gate 94A and eight latches 94B through 94I. The output of OR gate 90C in slow clock detect logic 90 is applied 5 as one input to OR gate 94A. The output of gate 94A is applied to the clock input of latch 94B. Thus, each time the output of gate 90C goes from a logic "0" to a logic "1" at the end of a slow clock cycle, the output of gate 94A will also go from a logic "0" to a logic "1" and 10 latch 94B will be clocked. The "Q" output of each of latches 94B through 94~ is applied to its own data input and is also applied to the clock input of the next suc-ceeding latch, as is usual for binary counters. The "Q"
outputs of some or all of latches 94B through 94I are 15 applied to rate decode logic 60, counter "1" detect gate 104, blanking logic 106, recharge logic 116, and refrac-tory loyic 66 circuits as shall be described below.
Rate decode logic 60, shown in FIGs. 3a and 3c comprises AND gates 60A through 60K, OR gate 60L. NOR
20 gates 60M and 60~, AND gates 60N and 60P and outputs 60Q
through 60U from the rate selection circuitry 50. The "Q" outputs of several of latches 94B through 94I in rate counter circuit 94 are applied as inputs to each of gates 60A through 60IC. For example, gate 60A has inputs from 25 the "Q" output of latches 94D, 94E, 94F, and 94I, gate 60D has inputs from the "Q" outputs of latches 94C, 94E, 94F, 94H, and 9~I and gate 60G has inputs from the nQ"
output of latches 94D, 94E, 94G and 94H. All of gates 60A through 60K except for gate 60D also have inpu~s from 30 some or all of outputs 60Q through 60U from rate select circuitry 50, and from the "Q" output of latch 64C in hysteresis logic 64. Gate 60D is the 50 pulses per minute gate; that is, when rate counter 94 has counted approximately 218 510w clock pulses equivalent to a time 35 period of 1.2 seconds the "Q" output of latches 64C, 64E, 64F, 64H, and 64I will all be a logic "1" and thus the output of gate 60D will go to a logic "1" which signal 7~

will operate on rate gate 96 to initiate an output cycle as will be discussed below. Since the 50 pulse per minute rate is the slowest rate gated by any of the gates, 60A through 60K, the 218 ~low clock cycle count 5 required to enable gate 60D will be reached only if none of the other gates are enabled, otherwise, as will be seen, the rate counter will be reset before this count is reached. Gate 60D is not connected to rate select 50 or hysteresis 64 so that it will always be enabled as a 10 safety feature. Thus, if the rate selection circuitry fails the 50 bpm rate will take over ensuring that the pacemaker does not fall below this rate.
The details of the rate selection circuitry will be discussed below in connection with FIGs. 4 and SO
15 As will ~e shown in that discussion~ outputs 60Q through 60U each can be placed in either a logic "0" state or a logic "1" state by means of the mode selection operation.
Input 60Q is the hysteresis pulse rate select input and inputs 60R through 60U arP the "normal" pulse rate selec-20 tion inputs. Each of the inputs 60R through 60U areapplied to one or more of latches 60A, 60B, 60C, and 60E
through 60K in rate decode logic 60. This circuit is essentially a four-line to ten-line decoder. That is, the four inputs 60R through 601J are considered to be a - 25 series of four binary digits and the connections between the inputs and gates 60A, 60B, 60C, and 60E through 60 are such that each configuration of input values that corresponds to a decimal number from one to ten in binary notation enables a single gate. For e~ample, the con-30 figuration of input values that corresponds to the binar~
representation of the decimal number 6, i. e. 0110, corresponds to the inputs 60R, 60S, 60T, and 60U having the values logic "0", logic "1", logic "1" and logic "0"
respectively and results in gate 60I only being enabled 35 by the outputs of rate select S0. The connections between latch~s 94~ through 94I, and gates 60A through 60K are such that a single gate is enabled each time rate counter 94 reaches a count corresponding to a time period resulting in a pulse rate of 50, 60, 65, 70, 75, 80, 85, 90, 100, 110, and 120 beats per minute. The connections 5 between inpu~s 60R thxough 60U and gates 60A through GOK
are such that the binary code for the decimals one through ten enable the gates governing the rates 50, 60, 65, 75, 80, 85, 90, 100, 110, and 120 respectively. ~n eleventh rate is selectable by means of NOR gate 60V. The four 10 inputs 60R through 60U are applied to the inputs of NOR
gate 60V and the output of the gate is applied to AND
gate 60A. Thus, when the four inputs 60R through 60U are all zero (corresponding to binary notation for a decimal zero) gate 60A is enabled. It is noted that the signal 15 from input 60R passes through OR gate 60L before being applied ~he 100 pulse per minute gate 60G. This does not change the function as described above, but merely allows the gate to be activated during the threshold margin test period, as will be discussed below, in addition to being 20 activated if 100 beats per minute is selected as the basic rate for the pacemaker. It is also noted that the signal from input 60T passes through AND gate 60N and OR
gate 60M before being applied to gate 60C, which is the gate for the 60 beat per minute rate, one of the two 25 hysteresis rates. This also does not essentially change the operation of that gate as discussed above, but per-mits the 60 beat per minute rate to be activated during hysteresis, as will be discussed below. Finally, it is noted that the input 50U, which corresponds to the first 30 binary digit, is not connected to gate 60D, the gate governing the 50 beat per minute rate, as it would be in order to be enabled only when the binary digit 0001 is coded into the inputs 60R through 60~. This connection is omitted in order that the 50 beat per minute gate will 35 always be enabled, as a safety feature as discussed above.
When one of gates 60A through 60K is enabled both -by outputs 50R through 50U and by rate counter 94 all its inputs become a logic "1" and its output therefore changes from logic "0" to a logic "1", excep* in the case when the hysteresis function is operating, which case shall be 5 discussed below. In normal operation, a specific one of gates 60A through 60K is enabled through inputs 60R
through 60U, and the rate counter 94 advances in response to pulses from slow clock detect l~gic 90 as discussed above until the count corresponding to the selected gate 10 is clocked, whereupon the output of the gate goes to logic "1". All of the outputs from gates 60A through 60K
are applied to OR gate 96A (FIG. 3b), thus if the output of any one of gates 60A through 60K goes to a logic "1"
then the output of gate 96A also goes to a logic "1".
15 Output trigger 98 is applied to one input terminal of AND
gate 96B in rate gate circuitry 96. The other terminal of AND gate 96B is responsive to the "Q" output of latch 80B in the output logic circuitry 80. As will be dis-cussed below, this output is a logic "1" whenever the ~ output pulse is not being called for, including the period when the rate limit function is operating. This permits the forcing of the pulse generator into rate limit via the output trigger as discussed above.
The output of gate 96A is applied to one of the 25 inputs of AND gate 74E in crystal/VCO select logic 74 and to the data input of latch 86A in output logic 80. The other input of gate 74E is provided from the output of gate 74F, which output is logic "0" only during the period when the rate limit function is operating, as 30 discussed above. If the pacema~er is not in ra-te ]imit thèn the output of gate 74E becomes a logic "1" when any of rate decode gates 60A through 60K becomes a logic "1".
The output of gate 74E is applied to NOR gate 74D to enable the VCO oscillator as discussed above.
Output logic 80 in FIG. 3d consists of flip-flops 80A and 80B. As mentioned above, the data input ~f flip-flop 80A responds to the output of gate 96A and xate gate circuitry 96. The c]ock input of the same flip-flop responds t~ the oscilla~or output of the VCO
output 72. On the first YCO pulse after the VCO oscillator is activated by the signal from gate 96A the 'Q" output 5 of flip-flop 80A is clocked to a logic "1" state. This signal is applied as one of the inputs to OR gate 8~C in rate count set 82 in FIG. 3c. Rate count set 82 com-prises OR gate 82C, latch 82D, and AND ga~e 82E. In response to the signal from the "Q" output of latch 86A, 10 OR gate 82C clocks latch 82D so that i~s "Q" output goes to a logic "1" state. This signal is applied to the set input of latches 94B through 94I (shown in this case at the bottom of the latches) to set all the "Q" outputs of the latches to a logic "1" state. The "Q" outputs of the 15 latches are all applied to the input of AND gate 104A
which comprises the counter "1" detect gate 104. When all the latches 94B through 94I are set so that the "Q"
outputs go logic "1", the output of gate 104A in turn goes to a logic "1" and is applied to the reset input of 20 latch 82D in the rate counter set circuit 82 to reset the "Q" output of latch 82D to a logic "0" state. It i6 also applied ~o one of the inputs to OR gate 78A in the slow clock reset circuit 78 to reset the slow clock/PW counter latches 76A through 76H as discussed above. The "all - 25 l's" signal from gate 104A is also applied to several other gates in the blanking, reversion and refractoxy logic which shall be discussed later.
Returning now to the operation of the output logic 80 in FIG. 3d, the "j" data input of latch 80B is 30 responsive to the "Q" output of latch 80A, while the clock input is responsive to VCO output 72. On the next VCO oscillation after the "Q" output of latch 80A goes to a logic "1", the "Q" output of latch 80B is cloc~ed to a logic "1", while the "Q" output goes to a logic "0". The 35 logic "1" signal from the "Q" output is applied to output 110 to the analog circuit to initiate the pulse generator 7~

output. The same signal is applied to NOR gate 74D in crystal/VCO select circuitry 74 to continue the enabling of the VCO oscillator as discussed above for the duration of the output pulse. The signal is also applied to AND
5 gate 82E in rate count set logic 82. The middle input of the same gate is responsive to the output of "all l's"
gate 104A which went to a logic "1" on the previous VCO
cycle. The third input to gate 182 is responsive to the VCO output 72, thus on the next VCO oscillation all three 10 inputs are a logic "1;' and the output also becomes a logic "1". This output signal is applied to gate 94A to clock latches 94B to 94I as discussed above; Since the latches were in the "all l's" condition this clock pulse advances them to the overflow condition.
Returning again to the output logic circuit 80 in FIG. 3d, rate limit output 112 from the analog circuit 114 is applied to the reset input of latch 80B. If the rate limit function is operating this signal will be a logic "1" and it will hold latch 80B reset for the rate 20 limit period. Thus the "Q" output of latch 80B will remain at a logic "O" and the output pulse and the resetting of the rate counters will be postponed. During this time the "Q~' output of latch 80A will remain at a logic "1" since its input from the rate gate circuit 96 25 remains at a logic "1" because all the "Q" outputs of latches 94B through 94I are at a logic "1" condition.
When the rate limit period comes to an end output 112 goes to a logic "O" and on the next VCO oscillation the "Q" output of latch 86B is clocked to a logic "1" to 30 initiate the output cycle.
As mentioned above, the output 112 is also applied to one input of gate 74F. Since the other input to this gate is from the "Q" output of latch 80A, during the time the rate limit is holding the output pulse in 35 abeyance both inputs to this gate are a logic "1" and thus the output is a logic "O". This output is applied .

to one of the inputs of AND gate 74E to disable the VCO
oscillator during this period as discussed above.
The duration of the output pulse is determined by the pulse width decode circuitry 62 which comprises 5 AND gates 62A through 62L and outputs 62M, 62N and 62P.
These three outputs are from the pulse width selection circuitry which will be discussed below in connection with FIGs. 4 and 5. These outputs each assume either a logic "0" or a logic "1" state as a result of the mode 10 selection operation discussed below. ~ike the outputs 60R through 60U in the rate decode circuitry 60, outputs 62M through 62P can be considered as a series of binary digits, except in this case there are three rather than four digit~ Gates 62A through 62L are divided into two 15 banks of gates the first being 62A through 62F and the second being 62G through 62L. The second bank is en-abled only during the threshold test cycle and will be discussed below in connection with threshold margin test circuitry 122.
The operation of the pulse width decode cir-cuitry 62 in conjunction with counter 76 is similar to the operation of the pulse rate decode circuitry 60 together with the counter 94. Each gate 62A through 62F
has one or more inputs from the "Q" outputs of latches 25 76A through 76E so that the gates are enabled at counts corresponding to time periods of .35, .4, .5, .65, .8, and 1.0 msec. respectively. The inputs to gates 62A
through 62F from outputs 62M through 62P are such that the circuit forms a three-line to six-line decoder. Each 30 combination of logic states of outputs 62M through 62P
that corresponds to the binary representation for the decimal numerals one through six enables one and only one of gates 62A through 62F. The connections are such that the code for the numerals zero thro~gh five selects the 35 pulse widths,.l, .8, .65, .5, .4, and .35 msec respec-tively, except that there is no connection between out-puts 62M through 62P and the 1.0 msec gate, 62F, so that this gate will alway~ be enabled with respect to pulse selection circuitry 52 as a failsafe measure. The out-5 puts of each of gates 62A through 62F are provided to ORgate 100A. In operation, slow clock/PW counter 76 counts oscillations until it reaches the count which enables the one of gates 62A through 62F which is also enabled by pulse width select circuitry 52. All the 10 inputs of that gate will then be a logic "1" and therefore the output will also change to a logic "1", which output applied to gate 100A causes the output of that gate to become a logic "1" which output is in turn applied to the "K" data input of latch 80B in the output circuitry 80.
15 On the next VCO clock cycle the "Q" output of latch 80B
is clocked to a logic "1" state and the "Q" output to a logic "0" state. The latter signal disables the output pulse through output 110, disables the VCO oscillator and selects the crystal oscillation through NOR gate 74D in 20 crystal/VCO select circuitry 74, and disables gate 82E in rate counter set circuit 82 terminating the reset cycle.
Recharge logic 116 comprises latches 116A and 116B. The data input of latch 116A is always held at a logic "1" and its clock input is responsive to the "0"
25 output of latch 80B.
The logic "1" signal from the "Q" output of latch 80B clocks latch 116A which changes its "Q" output to a logic "1". A short time later the "Q" output of latch 76F in slow clock~PW counter 76 goes to a logic "1"
30 and clocks latch 116B changing its "Q" output to a logic ~1 !1 . This signal initiates the recharge interval through output 11~. About 10 msec later the "Q" output of gate 94C in rate counter 94 goes to a logic i'l" which resets both latches 116A and 116B causing the "Q" output of gate 35 116B to go to a logic "0" terminating the recharge inter-val. The "Q" output of latch 80B also is applied to gate 96B in rate gate circuitry 96 enabling the output trigger to force ~he pulse generator into rate limit when an external signal is applied, as discussed above.
Battery depletion logic 92 comprises NAND gates 5 92A and 92B and latch 92C which is reversed in position from the usual position of latches so that its inputs are on the right and its outputs are on the left. Battery output 40 is applied to one of the inputs of NAND gate 92B. The "Q" output of latch 102A in amp disable/strobe 10 circuitry 102 is applied as one of the inputs of gate 92A. As will be discussed below, this latter input is a logic "0" when the reed switch is closed and is a logic "1" otherwise. If the reed switch is closed at least one of the inputs of gate 92A will be a logic "0" and thus, 15 its output will be a logic "1". If the battery is not depleted the output of output 40 i5 also a logic "1".
Thus both the inpu~s of gate g2B will be a logic "1" and therefore its output will be a logic "0". The clock input of battery depletion logic 92C is responsive to 20 the inversion of the VCO ENABLE signal from crystal/vCO
select 74 and its data input is responsive to the output of gate 92B. Thus on the first VCO ENABLE pulse after the closing of the reed switch the "Q" output of latch 92C will remain at a logic "0" state if the battery is - 25 not depleted. This output is appli~d as one of the inputs to gate 92A maintaining its output at a logic "1"
even after the reed switch is opened. Thus, as long as battery output 40 stays at a logic "1" that is, as long as the battery remains undepleted, the output of gate 92B
30 will remain a logic "0" and the circuit will remain latched with the "Q" output of gate 92C in the logic "0"
position. If the battery becomes depletedl the output of battery output 40 becomes a logic "0" causing the output of gate 92B to go to a logic "1" and on the next VCo 35 ENABLE pulse the ou~put of latch 92C goes to a logic "1".
Thus, as lons as the reed switch remains open both inputs to gate 92A remain h logic "1". Thus the output of latch 92A will be a logic "0" which signal applied to the input of gate 92B keeps the output of that gate at a logic "1" keeping the circuit latched with the "Q" output of latch 92C in the logic "1" state, even if the battery 5 returns to a nondepleted condition. However, when the reed switch is closed the upper input to gate 92A goes to a logic l0-l, the output of the gate goes to a logic "1"
whereupon the output of latch 92B will become a logic "0"
if the battery is in the nondepleted state latching the 10 circuit back into the nondepleted output state. If the battery is still depleted when the reed switch is closed then output 40 will be at a logic "0", the output of gate 92B will remain at a logic "1" and the circuit will remain latched in the "depleted" output state. From the 15 above it is seen that when the battery is in a nonde-pleted state the "O" output of latch 92C is latched in the logic "1" condition and when the battery is depleted it is latched in the logic "0" condition. This signal is applied to gate 90A in slow clock detect logic 90. Thus, 20 the battery depletion signal will disable gate 90A allowing gate 90B to trigger the slow clock output signal from gate 90C extending the period of the slow clock by eleven percent as discussed above.
Amp reset logic 84 in FIG. 3d comprises inver-25 ter 84A and flip~flops 84B and 84C.
As will be seen below, the data input to latch 84B is a logic "1" whenever the hysteresis function, reversion function, or the reed switch is not disabling the demand function of the pacemaker. The output of amp 30 output 130 is applied to the clock input of latch 84B
through inverter 84A. Thus, when a heartbeat is sensed the clock input goes from a logic "0" to a logic "1"
clocking the "Q" output of latch 84B to a logic "1"
state. This signal is applied to the input of OR gate 35 82C (FIG. 3c) causing latches 94B through 94I to be set to the "all I's" condition as described above. The signal is also applied to gate 74D in crystal/VCO select logic 74 enabling the YCO oscillator as discussed above.
In addition the signal also is applied to gate 102B in amp disable/strobe logic 102 to provide the strobe output 5 which shall be discussed below. The clock input of latch ~4C is responsive to VCO output 72 while the data input of the same latch is responsive to the "Q" output of latch 84B. Thus on the first VCO oscillation a~ter the latter input goes ts logic $'1" the "Q" output of latch 10 84C is in turn clocked to a logic "1" state. This signal is applied to latch 74D to maintain the operation of the VCO oscillator. It is also applied ~o the input of gate 94A to clock latches 94B through 94I to the overflow condition. Finally it is applied to the reset input of 15 latch 84B changing the "Q" output of that latch to a logic "0". On the next VCO oscillation the "Q" output of latch 84C is clocked to a logic "0" turning off the VCO
oscillator, and removing the reset signal from latch 84B
readying the circuit for the next cycle.
Blanking logic 106 comprises NAND gates 106A
and 106B, AND gate 106C, and flip-flop 160D. The set input of latch 106D is responsive to the output of "all l's gate" 104A. This signal becomes a logic "1" at the beginning of an output cycle and immediately after a 25 natural heartbeat is sensed so that the "Q" output of the latch goes to a logic "1" and the "Q" output goes to a logic ~0~O The logic "1" output is applied to one of the inputs of AND gate 106C and one of the inputs of NAND
gate 106B. The inputs to gate 106A are responsive to the 30 "Q" output of latches 94C and 94F in rate counter 94.
Within one VCO oscillation after the "all l's" condition these latches are clocked to the overflow state so that both the inputs to gate 106A go to a logic "0" and the output goes to a logic "1". Both inputs to gate 106C are 35then a logic "1" and the output is thus also a logic "1".
On the next slow clock pulse gate 106D i5 clocked but t, V

remains latched with its "Q" output at logic "1" since its input is also a logic "1". The "Q" output of latch 106D i5 also applied to one of the inputs of MAND gate 106B. The other input of this gate is responsive to the 5 "Q" output of latch 94F in the rate counter circuit 9 When latches 94B through 94I are clocked to the overflow condition the "Q" output of latch 94F goes to a logic "1". Thus, both inputs to gate 106B are a logic "1" at this time and the output i5 a logic "0". This logic "0"
10 signal enables the external blanking through output 134 to analog circuit 14. The "Q" output of latch 106D
provides the internal ~i.e. within the digital circuit) blanking signal which goes to reversion logic 108 and threshold test logic 122. Approximately 90 msec after 15 the initiation of the blanking period by the set signal from the "all l's" gate 104A, the "Q" output of latch 94F
goes to a logic "0", which causes the output of gate 106B
to go to a logic "1" which terminates the external blank-ing. Approximately 10 msec later the "Q" outputs of 20 latches 94C and 94F will both be a logic "1", thus the output of latch 106A will go to a logic "0" which, in turn, causes the output of gate 106C to also go to a logic "0" state. On the next slow clock pulse the "Q"
output of latch 106D is clocked to the logic "0" state 25 while the "Q" output is clocked to a logic "1" state which terminates the internal blanking period. The internal blanking period is made slightly longer than the external blanking period in order to assure that any spurious pulses that may have appeared in the amplifier 30 circuit in analog circuit 18 during the blanking period will be dissipated by the time the internal blanking goes off.
Amp diable/strobe logic 102 comprises latch 102A, OR gate 102B, and AND gates 102C and 102D. Latch 35 102A is drawn with its inputs on the right and its out-puts on the left, the reverse of the normal input/output representation for a latch. One input to gate lOZC is from the "Q" output of latch 80A in output circuit 80, while the other input is from the "Q" output of latch 30B
in the same cixcuit. The outpl-t vf gate 102C thus goes 5 from logic "O" to logic "1" when the "Q" output of latch 80B goes to logic "1" to initiate the output pulse. On the same VCO oscillation rate gates 94B and 94I are clocked to the overflow condition by means of gates 82E
and 94At which places a logic "O" signal on the input of 10 gate 80A through gates 60A through 60K and gate 96A. On the trailing edge of the same VCO pulse, latch 80A is clocked so that its "Q" output goes to a logic "O", which in turn changes the output of gate 102C back to a logic "O". Thus, the output of gate 102C is a logic "1" only 15 for a period equal to approximately one-half of a VCO
oscillation, or about 25 microseconds. This output is applied through gate 102B to strobe output 142 to produce the 25 mic~osecond strobe pulse each time the pulse generator output is called for. If a pulse generator 20 output is not called for because a natural heartbeat is detected then a logic "1" strobe output is produced from gate 102B during the time period in which the "Q" output is latch 84B and amp reset circuit 84 is logic "1". As described above, this output goes from logic "O" to a 25 logic "1" and back to a logic "O" within a time period equal to at most the time period during which the VCO
oscillator is at a logic '~0" or one-half of a VCO cycle, and thus a 25 ~sec strobe pulse is also produced each time a heartbeat is detected by amp reset circuit 84.
30 The strobe output of gate 102B is also applied to an inverted clock input to latch 102A. The data input of latch 102A is responsive to reed output 143. As men-tioned above, this output is a logic "1" only during the time period in which reed switch 32 is closed. Thus, on 35 the trailing edge of the first strobe pulse after reed switch 140 is closed the "Q" output of latch 102A will be ` - ~

clocked ~o a logic "0" state. This logic "~" signal is applied to NAND gate 92A in battery depletion circuit g2 to "unlatch" the circui~ as described above. It i~ also applied to gate 122A and latch 122D in threshold margin 5 test circuit 122 to initiate the threshold margin test unction as shall be described below. Finally it is applied to one of the inputs of gate 102D. ~ate 102D is the amp disable gate, that is, its output is applied to the data input of latch 84B in amp reset circuit 84.
10 Whenever any of the inputs of gate 102D go to a logic "0"
its output goes to a logic "0" and the amp reset cycle is disabled, that is it will not reset the rate counter as discussed above. Thus, when the reed switch is closed and the "Q" output of gate 102A goes to a logic "0" the 15 amp reset function is disabled. The other two inputs to gate 102D are from reversion circuitry 108 and the refractory circuitry 66, which circuits shall be dis-cussed below.
Refractory logic 66 comprises inverter 66A, AND
20 gates 66B through 66E, NOR gate 66F, and latch 66G. The inputs and outputs to latch 66G are reversed from the normal position, that is the inputs are applied on the right and the outputs emerge from the left. The set input to latch ~6G is responsive to the output of "all 25 l's" gate 104A. As discussed above, this output goes to a logic "1" just prior to an output pulse and immediately after a natural heartbeat is detected. These logic "1"
signals set latch 66G so that its "Q" output goes to a logic "1" and its "Q" output goes to a logic "0". The 30 "Q" output is applied to the reversion circuitry and shall be discussed below. The "Q" output is applied to one o the inputs of the amp disable gate 102D in amp disable/strobe circuitry 102. The logic "0" signal causes the output of gate 102D to become a logic "0" and 35 to disable the amp reset function as described above.
The "Q" outp~t is also applied as one of the inputs to 7~
-4~-gate 66F. The other inputs to this gate are from AND
gates 66B through 66E. The inputs to these latter gates are from the "Q" outputs of latches 94B through 94I, which outputs go to a logic "0" within a VCO cycle of the 5 "all l's" condition. The clock input to latch 66G is from the slow clock output; the latch is clocked on the trailing edge of this pulse since the input is inverted.
On the first slow clock pulse after the "all l's" con-dition, all the inputs to gate 66F will be at a logic "0"
10 and thus its output will be at a logic "1". Thus, even though the logic "1" set signal is removed by this time, latch 66G will stay latched in the set condïtion until the logic "l" signal is removed at its input through gate 60F. Gate 66B has inputs from the output of inverter 66A
15 and from the "Q" outputs of latches 94B, 94C, 94E, 94F
and 94G. The "Q" outputs of these five latches will be all a logic "l" when rate counter 94 has counted a number of slow clock pulses corresponding to a 325 msec refrac-tory period. If the output of refractory select output 20 56 is a logic "0" the output of inverter 6bA will be a logic "1". Thus, 325 msec after latch 66G has been set all the inputs to gate 66B will become a logic "l" and its output will also become a logic "l". This output is applied to NOR gate 66F and thus, its output becomes a 25 logic "0". On the trailing edge of the next slow clock pulse latch 66G will be clocked to the condition where - its "Q" output is at logic "0" and its "Q" output is at a logic "l". The logic "ll' signal applied to gate 102D
removes the disabling signal from the amp reset circuit 30discussed above. The signal applied to NOR ~ate 66F
causes its output to remain a logic "0" even after the logic "l" signal from gate 66B is removed, thus latching the refractory circuit into the "off" condition until the next set signal is applied to latch 66G from "all l's"
35 gate 104A. If the output of refractory select 56 is a logic "1" then the output of inverter 66A is a logic "0"

-~5-and gate 66B is disabled so that its output does not become a logic "1" at the end of the 325 msec period. In this case, the "Q" output of gate 66D which has inputs from the "Q" outputs of latches 94B, 94E, and 94H will go 5 to a logic "1" at the end of a 400 msec period, and will trigger the termination of the refractory period as discussed above. Gates 66C and 66E have an input from the "Q" output of latch 92C in battery depletion circuit 92. As discussed above, this output is a logic "0" in 10 the normal case when the battery is not depleted. This logic "0" signal disables these gates. However, when the battery becomes depleted the "Q" output of latch 92C goes to a logic "1" enabling these gates. Gate 66C has inputs from the "Q" outputs of latches 94B, 94D, 94F, and 15 94G. These outputs all become a logic "1" after 2 period ten percent shorter than the 325 msec period. Thus this gate will produce a logic "1" output prior to the output of gate 66B and terminate the refractory period at an "earlier" time. However, since the slow clock cycle has 20 been extended by the same amount the net result will be that the refractory period stays the same when the bat-tery is depleted. Likewise, gate 66E has connections to the "Q" outputs of latches 94B through 94I such that its output will go to a logic "1" at a ten percent shorter time than the 400 msec period of gate 66D. Thus, if the battery is depleted and the output of refractory select 56 is a logic "1" which disables gate 66C through the input to that gate applied from the output of inverter 66A, then gate 66E will provide an output that will maintain the stable refractory period of 400 msec.
Reversion logic 108 comprises AND gate 108A and latches 108B and 108C. The output of "all l's" gate 104A
is applied to the reset input of latches 108B and 108C.
This reset signal ensures that the "Q" outputs of latches 108B and 108C are a logic "1" and the "Q" output of latch 108C is at a logic "0" at the besinning of the pulse ~7~

cycle. As discussed above, the "Q" output of latch 106D
has been changed to a logic "0" output by the same "all l's" signal while the "Q" output of latch 66G has been set to a logic "1" by the same signal. The signal from 5 the "Q" output of latch 106D signal is applied to gate 84A so that its output is at a logic "0". The clock input of latch 108D is responsive to the output of inver-ter 84A in the amp reset circuit, thus each time the amplifier in the analog circuit puts out a signal through 10 amp output 130 latch 108B will he clocked. Since the input to latch 108B is held at a logic "0" no change in its outputs will ~e caused by such amplifier signals.
However, at the end of the 100 msec blanking period the "Q" output of latch 106D becomes a logic "1". Since the 15 other inputs to latch 108B, from the "Q" output of latch 108B and the "Q" output of latch 66G are already a logic "1" the output of gate 108A will change to a logic "1l' state. Meanwhile, the logic "1" reset signal has been removed since the output of "all l's" gate 104A has 20 returned to a logic "0". Thus, the next output of amp output 130 will clock latch 108B so that its "Q" output goes to a logic "0". This signal applied to the input of gate 108A will cause the output of that gate to go to a logic "0" and thus the next signal from amp output 130 25 will clock the "Q" output of latch 108B back to the logic "1" state. The change in the "Q" output from logic "0"
to logic ~'1" applied to the clock input of latch 108C
clocks this latch. Since its data input is at a logic "1" its "Q" output changes to a logic "1" and its "Q'' 30 output changes to a logic "0". The logic "0" signal is applied to the amp disable gate 102D, to disable the amp reset function as discussed aboveO Since the data input of latch 108C is held at a logic "1" and the set input is held at a logic "0" the "Q" output of latch 108C will 35 remain a logic "0" and the amp reset function will be held disabled until the reversion circuit is reset by -47~

another signal from "all 1~6" gate 104A. The logic "1"
signal is applied to the 54t input of latch 108B to latch the two reversion latches 108B and 108C in the revexsion mode until the next output pulse.
Hysteresis logic 64 comprises inverter 64~, O~
gate 64B and latch 64C. The set input of latch 64C is responsive to the "Q" output of latch 84B in the amp reset circuit. As discussed above, if the amp reset circuit is not being held disabled by the refractory, 10 reversion, or reed switch functions, a natural heartbeat detected by the amplifier in analog circuit 14 will produce an output of amp output 130 which causes the "Q"
output of latch 84B to go to a logic "1". This signal sets latch 64C causing its IIQII output to go to a logic 15 "1" and its ~'Q" output to go to a logic "0". The latter signal is applied to one of the inputs of each of rate decode gates 60A through 6GK, except for gates 60C, the 60-beat-per-minute rate decode gate, and gate 60D, the 50-beat-per~minute rate decode gate. The logic "1"
20 signal is applied as one o the inputs of AND gate 60P in rate decode circuitry 60. If the hysteresis rate output 60Q is at a logic "1" state then the output of gate 60P
also becomes a logic "1" which signal is applied through OR gate 60M to gate 60C enabling it. The Ç0-beat-per-25 minute gate will then determine the pulse rate as des-cribed in the discussion of the output pulse, since its ;
output goes to a logic "1" and resets the rate counter a~
a rate faster than the 50-beat-per-minute gate. If, .
however, hysteresis rate output 60Q is a logic "0" then 30 gate 60P will be disabled, its output will be at a logic "0" disabling gate 60M, allowing the 50-beat-per-minute gate to control the output pulse. (Note that the output of gate 60N is a logic "0" since it is also disabled by the logic "0" state of the lower output of latch 64C.) 35 As long as the natural heartbeat remains above the selected hysteresis rate the state of latch 64C will not :1~6~
-~8-change, since each heartbeat will set rate counter 94 preventing it from reaching the hysteresis count, and preventing an output pulse from occurring. However, should the heartbeat rate drop below the selected hys-5 teresis rate then the one of gates 60C or 60D which isenabled will have all its inputs go to a logic "1", its output will go to a logic "1" and a pulse will be output from the pulse generator as described above. At the initiation of the output pulse the "Q" output of yate 80B
10 goes to a logic "1" as described above. This signal is applied as one of the inputs to OR gate 64B causing its output to go to a logic "1" which signal is in turn applied to the reset input of latch 64C causing its "Q"
output to go to a logic "0" and its "Q" output to go to 15 a logic "1". (Note that the set input to latch 64C
returned to a logic "0" on the first VCO oscillation after the last detected heartbeat.) The logic "1" state of the "Q" output of latch 64C enables rate yates 60A
through 60K and allows the pulse generator to operate at 20 its selected rate. The logic "0" state of the "Q" output of gate 64C disables gate 60P, however if the 60-beat-per-minute rate is selected by the "nc,rmal" rate selec-tion outputs 60R through 60U then gate 60N will have a logic "1" output so that the gate 60C is enabled. The 25 pulse generator will continue operating at its selected rate until a detected heartbeat again sets latch 64Co If hysteresis function select output 54 is a logic "0" then the output of inverter 64A is a logic "1" which signal is applied through OR gate 64B to the reset input of latch 30 64C. This holds the latch reset and enables the pulse generator to continue operating at its selected rate as discussed above. If the output of hysteresis select 54 is a logic "1" then the output of inverter 64~ will be a logic "0" and the hysteresis function will opcrate as 35 discussed.
Threshold margin test logic 122 in FIG. 3a -4g~
comprises OR gate 122A, latches 122B through 122D, and AND gate 122E. The "Q" output of latch 102A in the amp disable/strobe circuitry 102 is applied as one input of OR gate 122A and to the reset input of latch 122D. As 5 discussed above, this output is at a logic "1" as long as the reed switch 32 is open. The logic "1" signal is applied to the reset inputs of latches 122B and 122C
through OR gate 122A, and directly to the reset input of latch 122D. This signal holds the latches in the reset 10 condition. Thus the "Q" outputs of latches 122B and 122C
will be in a logic "0" state. These outputs are applied to gate 122E holding its output at a logic "0". This signal is in turn applied to each of gates 62G through 62L in the pulse width decode circuitry holding them 15 disabled. When the reed switch 32 is closed the signal applied to the reset inputs of latches 122B, 122C and 122D changes to a logic "0" at the trailing edge of the first strobe pulse, enabling the gates. The "Q" output of latch 106D in blanking logic 106 is applied to the 20 clock input of latch 122B. When at the end of the first blanking period after the reed switch is closed the "Q"
output of latch 106D changes from a logic "0" to a logic "1" latch 122B is clocked. Since its data input is connected to its "Q" output, which was at a logic "1'l, 25 the clocking changes its "Q" output to logic "1" and its "Q" output chan~es to a logic "0". The "Q" output of latch 122B is applied to one input of gate 122E and one input of OR gate 60L and the rate decode logic 60. As discussed above in connection with the discussion of the 30 rate decode logic this signal causes the output of gate 60L to go to a logic "1" which selects the 100-pulse-per-minute rate gate. The next output pulse therefore occurs in 600 msec, unless the selected pulse rate is faster than 100-beats-per-minute, in which case a pulse at the 35selected rate occurs. At the end of the next blanking period latch l22B is again clocked. Its "Q" output changes to a logic "0" and its "Q" output changes to a logic "1". The "Q" output of gate 122B is connected to the clock input of gate 122C, and the "Q" output of gate ~ 22C is connected to its own data input. Since the "Q"
5 output of latch 122C was at a logic "1" state due to the reset signal, the change in the "Q" output of latch 122B
clocks the "Q" output of latch 122C to a logic "1" state while its "Q" output goes to a logic "0" state. The "Q"
output of latch 122C is applied to one input of yate 122E, but since ~he other input, which is from the "Q"
output of latch 122B, has now gone to a logic "0" the output of gate 122E remains a logic "0". The "Q" output of latch 122C is also applied to gate 60L and causes the next pulse to again be at the 100-beat-per-minute rate.
15 At the end of the next blanking period latch 122B is again clocked, its "Q" output goes to a logic "1" and its "Q" output goes to a logic "0". Gate 122C is not clocked since clocking takes place only on a change in state from logic "0" to logic "1". ~he logic "1" state of the "Q"
20 output of latch 122s/ applied to gate 60L, again causes the next pacemaker pulse to be in 600 msec. However, both inputs to gate 122E are now a logic "1" so that its output is also a logic "1". Thus, the disabling signal is removed from the group "B" gates 62G through 62L in 25 pulse width decode circuitry 62. Each of the gates 62G
through 62L are connected to outputs 62M through 62P in the same manner as each of the group "A" gates 62A through 62F respectively. Thus if gate 62A is enabled by pulse width selection circuitry 52 then gate 62G also is en-30 abled, etc. The inputs to gates 62G through 62L respec-tively are connected to the "Q" outputs of latches 76A
through 76H so that each of the gates 62G through 62L
will be enablea by a slow clock count that is only seventy five percent of the count that enables the corresponding 35 gate in group "B". Thus, the one of gates 62G through .62L that is enabled by pulse width select circuitry 52 67~

will be enabled by slow clock/PW counter 76 before the corresponding one of the ga~es in group "A" is enabled.
Its output will go to a logic "1" which signal will be applied to OR gate 100A to terminate the output pulse and 5 reset the slow clock/PW counter latches 76A through 76H.
Thus the third output pulse after the reed switch is closed will be a pulse having a width seventy five per-cent of the selected output width. After this output pulse, latch 122B is again clocked by the "Q" output of 10 latch 106D. This causes its 'IQ" output to go from logic "0" to a logic "1", which clocks latch 122C. The "Q"
output of latch 122C in turn goes from logic "0" to logic "ln. This signal is applied to the clock input of latch 122D, causing its "Q" output to go to a logic "1" since -15 its data input is held at a logic "1". The "Q" output of latch 122D is applied to the reset inputs of latches 122B
and 122C through OR gate 122A. Thus, the lo~ic "1"
signal resets latches 122B and 122C. This causes the "Q"
outputs of latches 122B and 122C to go to a logic "0", 20 which in turn disables gates 122E and 60L to go to logic "0" allowing the pacemaker to return to its normal opera-tion. The threshold margin test circuitry remains in this state until the reed switch is opened, which con-tinues the reset condition of gates 122B and 122C and 25 also resets gate 122D as discussed above.
Turning now to FIGs. 4 and 5, the circuitry for selecting the output mode and for setting the mode selec tion output terminals to a determinate electronic state are shown. FIG. 4 is the embodiment of the circuitry 30 used in connection with the selection of the pulse rate, refractory period, the hysteresis rate, and the hys-teresis function. FIG. 5 is the embodiment used in selecting the "reed switch mode" that is the mode of operation of the pacemaker when the reed switch 32 is 35 closed.
In~FIG. 4 the circuitry for selecting an output mode is shown at 150. This comprises a destructible - \

means 152, a ground 154, and a mode selection output terminal 156. Terminal 156 may be considered to be an output terminal for the circuitry shown in FIG. 4 or an input terminal for ~he circuitry discussed in connection 5 with the FIGso 3a through 3d. That is, terminal 156 represents any one of inputs 60Q in FIG. 3a, 62M, 62N, and 62P in FIG. 3b, 60R, 60S, 60T, 60U, and 56 in FIG. 3c and 54 in FIG. 3d. In order to emphasize the fact that these terminals are output terminals from the mode selec-10 tion circuitry they have been referred to as outputterminals in the discussions above although strictly speaking, they were input terminals in those discussions.
Destructible means 152 connects ground 154 to the cir-cuitry 158 for setting the mode selection input terminals 15 to a determinate electronic state.
The circuitry 158 for setting the mode selection output terminals to a determinate electronic state com- :~
prises strobe output 142, inverter 160, p-channel trans-istors 162 and 164, resistor 166, and inverters 168 and 20 169. Strobe 142 is applied to the input of inverter 160, while the output of inverter 160 is applied to the gate of fet 162. The input of inverter 168 is connected to one end of fusible link 152 while the output is connected to the input of inverter 169. The output of inverter 169 25 is applied to terminal 156. P-channel transistor 162 has its source connected to the +V voltage source while its drain is connected to the line between fusible link 152 and inverter 168 through resistor 166. The gate of transistor 164 is connected to the line between the 30 output of inverter 168 and the input of inverter 169.
The source is connected to the +V voltage source while ..
the drain is connected to the line between fusible link 152 and the input of inverker 168.
Circuit 158 operates to hold terminal 156 to 35 the logic "O" state when link 152 is conducting, and to hold terminal 156 to a log.ic "1" state when link 152 is -53~
destroyed. If the link 152 is conducting, that is it is not fused, then the line at 153 is a logic 1l0l'. Each time strobe output 142 goes to a logic "1" the output of inverter 160 goes to a logic "0" and transistor 162 turns 5 on. However, a voltage drop occurs across resistor 166 and the line at 153 stays low because it is tied directly to ground at 154. The output of inverter 168 is a logic "1" and thus line 165 is high and transistor 164 remains off. Thus, the drain side of transistor 164 remains low 10 which is consistent with line 153 being low. ThP output of inverter 169 is a logic "0" since its input is a logic l'l". Thus, output 156 is held to a logic "0". If link 152 is fused then on the first strobe pulse after it is fused the output of inverter 160 goes to a logic "0" and 15 transistor 162 turns on. Since the line at 153 is no longer tied to ground it goes to a logic "1". Since the input of inverter 168 is a logic "1" its output will go to a logic "0" forcing line 165 low and turning transistor 164 on. This causes the drain side of the transistor to 20 go to a logic "1" which is consistent with line 153 being a logic "1". Since the input to inverter 169 is a logic "0" its output is a logic "1" thus output 156 is held in a logic "1" state.
Resistor 166 is preferrably about 1-3 megaohms;
25 in actual implementation resistor 166 is not separate from the transistor 162 but rather the transistor is made with a narrow channel which gives the required high impedance. In its preferred embodiment destructible means 152 comprises a metal link preferrably comprised of 30 gold. It is either fused by a laser or cut with an abra-sive trimmer. It may, however, comprise a metal wire that may be cut, or any other conducting member, the conduction of which may be destroyed by alteration of its physical properties. Transistors 162 and 164 are fets in 35 the preferred embodiment, but any type of transistors may be used .

The circuit of FIG. 4 is used when the fusible link connec~s an inpu~ with a logic "0" terminal such as ground 154. When the fusible link or other destructible means connects an output terminal such as 156 with a 5 logic "1" terminal then the mirror image circuit would be used. This circuit is shown in FIG. 5. In the present embodiment of the invention the reed switch 32 connects a positive voltage source 170 with the reed input 140 to the digital circuit. Circuit 175 comprises strobe output 10 142 from the digital circuit, n channel transistors 180 and 182, resistor 178 and inverters 184 and 186. One terminal of reed switch 32 is connected to the input of inverter 184, whil.e the output of inverter 184 is con-nected to the input of inverter 186. The output of 15 inverter 186 is applied to reed output 140 to the digital circuit. The strobe input 142 from the digital circuit is applied to the gate of transistor 180. The source of transistor 180 is connected to ground while the drain is connected to the line between reed switch 32 and inverter 20 184 through resistor 178. The gate of transistor 182 is connected to the line between the output of inverter 184 and the input of inverter 186. The source of transistor 182 is again connected to ground while the drain is again connected to a line between reed switch 132 and 25 inverter 184. Resistor 178 is again implemented in this circuit simply by a 1-3 megaohm narrow channel in trans-istor 180 which provides the required high impedance.
If reed switch 32 is closed line 179 is forced to a logic "1". When strobe 142 turns transistor 180 on 30 there is a voltage drop across resistor 178 accounting for the potential difference between source 170 and ground 181. The line at 185 is a logic "0" due to inver-ter 184. This maintains transistor 182 in the off con-dition which is consistent with line 179 being in the 35 logic "1" state. Since the input of inverter 186 is a logic "0" its output will be a logic "1" and thus reed ~55-output 140 is held at the logic "1" state. If reed switch 32 i5 opened, on the first strobe pulse after it is opened transistor 180 is turned on and line 179 be-comes a logic "0". The output of inverter lB4 thus 5 becomes a logic "1" which turns transisto~ 182 on which also forces line 179 to a logic "0" latching the circuit.
The output of inverter 186 will be a logic "0" since its input is a logic "1", and thus the reed output 140 is held at a logic "0".
A feature of the circuits of FIGs. 4 and 5 axe that they permit ~he terminals 156 and 140 to be held in the required logic "0" or logic "1l' state ~ith minimum use of current. Current flows in the circuit of FIG. 4 only for the brief period when strobe 142 is on, and then 15 only if link 152 is not fused. The size of resistor 166 makes even this current minimal. Likewise current flows in the circuit FIG. 5 only when strobe 142 is on and reed switch 32 is closed, and resistor 178 makes this current minimal. As discussed above the strobe pulse has the 20 shortest on time of any signal in the digital circuit and thus the current used by the circuits in FIGs. 4 and S is neyligible.
In the practice of the method of the invention a pacemaker having circuitry such as is shown in FIGs~ 3a 25 through 3d is constructed. Each of the mode selection output terminals 60Q, 62M, 62N, 62P, 60R, 605, 60T, 60U, 50F, 50G, 50H, 56, and S4 are provided with circuitry such as shown in FIG. 4 and each of the output terminals such as 140 is provided with input circuitry such as is 30 shown in FIG. 5. There will be a fusible link 152 for each of the above designated terminals of the type in FIG. 4. One or more links are then fused to select the desired output mode of the pulse generator. Preferrably the links are arranged together in the circuitry so that 35 they may be considered to correspond to a series of binary digit places. For each model of the pacemaker a rd~3 binary code is specified and the links corresponding to the binary digit places having a logic "1" value are fused.
It is a feature of the invention that the cir-5 cuits of FIGs. 4 and 5 establish stable voltage valuesimmediately after the links 152 are fused or the reed switch is closed or opened. This permits the fact that the links are fused to be determined with certainty immediately after the fusing is complete so that the 10 operator is working on the circuit for a minimum amount of time ana applies a minimum amount of heat in fusing the link which results in minimal contamination of the pacemaker circuitry and a minimum chance of damaging sensitive circuitry elements with the heat. With respect 15 to the reed switch the rapid assumption of the stable state results in more reliable functioning of the digital circuits associated with the reed switch opera~ion.
Since the links may be used with a minimum of contamination, the chance of failure due to the contamin-20 ants is minimized. In such circui~s if failure doesoccur it generally would be due to dendrites growing across the fused ends of link 152, or small conductive dirt such as wire bond chaff or solder balls connecting across the gap due to the production process, static 25 electricity, etc. A feature of the invention is that if such failure does occur the pacemaker output mode will change toward nominal or safe output modes. The recon-nection of any of the links 1~2 corresponding to inputs 60R through 60U will result in a pulse rate no lower than 30 50 beat per minute; if all the links reconnect then the nominal seventy-beat-per-minute rate is obtained. The reconnection of links 152 corresponding to inputs 62M
through 62P will result in wider pulse widths, which provide more energy and which are more likely to stimu-35 late the heart. The reconnection of the link 152 cor-responding to input 60Q will result in the hysteresis rate changing from 60 to 50 beats per minute which allows .
- : , J~

the heart more opportunity to beat on its own which is generally preferrable if a hysteresis function is desir-able at all. The reconnection of the link 152 corres-ponding to input 54 results in the mode going from 5 hysteresis mode to no hysteresis mode, which is pre-ferrable since the low hysteresis rates may not be desirable for some patients. If the link 152 corres-ponding to input 56 reconnects the output mode changes by refractory going from 400 msec to 325 msec which is 10 generally more desirable.
The above description of the invention has been in referense to a particular embodiment. It is evident to those skilled in the art that numerous uses, and modifications of and departures from the specific embodi-15 ment described herein may be made without departing fromthe inventive concepts. For example, those skilled in the art may substitute many other materials for the fusible links including materials whose physical proper-ties may be changed so that the conductivity is destroyed 20 without actual physical separation. Any equivalent electronic parts and electronic circuits may be substi-tuted for those shown. Output parameters other than pulse rate, pulse width, hysteresis and refractory may be programmed using the inventive apparatus and method. The 25 links may be fused as part of a subassembly of the pacemaker and then the subassembly may be inserted into its place in the pacemaker circuitry. Many other vari-ations may be described. Consequently the invention is to be construed as embracing each and every novel feature 30 and novel combination of features within the appended claims.

What is claimed is:

Claims (3)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A pacer for providing therapeutic stimulation of a patient's heart through a lead system comprising: a pulse generator circuit for producing an output pulse, having at least one alterable output parameter, selection circuit means coupled to said pulse generator for selecting a value of said alterable output parameter, a destructible circuit element coupled to said selection circuit means for controlling said selection circuit means.

2. A pacer for providing stimulation to living tissue comprising:
an output pulse generator for generating a stimulation pulse in response to a trigger signal, a digital pacer circuit coupled to said output pulse generator for generating trigger signals at selectable times, selection circuit means coupled to said digital pacer circuit for selecting the times that said trigger signals are generated.

3. A pacer for providing stimulation to living tissue comprising:
an output pulse generator for generating a stimulation pulse in response to a trigger signal, a digital pacer circuit coupled to said output pulse generator for generating trigger signals at selectable times, selection circuit means coupled to said digital pacer circuit for selecting the times that said trigger signals are generated, wherein selection circuit means comprises: a strobe means for interrogating a destructible circuit element on a periodic basis, a latch means coupled to said strobe means for storing the value of said destructible circuit element.