CA1164587A - Broadcast and alternate message time slot interchanger - Google Patents

Abstract

Abstract:
The present invention relates to an apparatus for interchanging time slots. The apparatus is comprised of an input terminal which is adapted to receive an input frame. The input frame has a first plurality of input time slots with each input time slot communicating a sample of information. A data storage unit is provided having a plurality of storage locations. A unit is provided for extending an input time slot sample from an input time slot through a storage location to an output time slot and thence to an output terminal for insertion in an output frame. The output frame has a second plurality of time slots. A unit is provided for inserting an alternate message in one or more output time slots to many locations.

Description

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1.

B~OADCAST AND ALTERNATE MESSAGE TIME SLOT INTERCHAN(~ER
This is a divisîon of copending Canadian Patent Appli-cation Serial No. 358,878 which was filed on August 25, 1980.
Technical Field _. ~
This invention relates to time division multiplexing ~TDM) and, more par~icularly, to a TDM arrangement for interchanging samples among time slots.
Background of the Invention It is common that connections such as telephone calls between calling and called lines be made by sharing a single communications path on a time division basis~ Each call is assigned to a shared path for a short time interval and the connection between the two lines is completed only during the short time interval, also called a time slot in the TDM
artO Otherwise, the time slot is available to be shared by other ccnnections.
U.S~ Patent 3,263,030, discloses an arrangement for switching message bits from a first input time slot to a second output time slot. The arrangement includes two shift register message stores, which are utilized for writing digital data into one store while digital data are read out of the other store, and vice versa. The stored message bits are read through message gates in such a manner that the time sequence o~ the outgoing message bits represents the desired switched order. That is, the time sequence of the incoming multiplexed message bits is interchanged into a difference output order. The order of ~he outgoing message bits corresponds to the outgoing lines to which the respective bits are to be routed. The routing is accomplished by actuating, successively and in time sequence, line gates respectively associated with the outgoing lines.
Unfortunatelyr known time slot interchange arrangements insert an input sample in a single output time slct.
Summary of the Invent _ In accordance with an aspect o~ the invention there is .' ~

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provided apparatus for interchanging time slots said inter-changing apparatus including an input terminal adapted to receive an input frame, said input frame having a first plurality of input time slots, each input time slot for communicating a sample of information, data storage means having a plurality of storage locations, means for extending an input time slot sample from an input time slot through a s~orage location to an output time slot and thence to an output terminal for insertion in an output frame, said output frame having a second plurality of time slots and characterized in that said interchanging apparatus further comprises means for selectively inserting an alternate message in one or more output time slots to.many locations.
Brief Description The present invention taken in conjunction with the in~ention described in copending Canadian Patent Application Serial No. 358,878 which was filed on August 25, 1980 will be described in detail hereinbelow with the aid of the accompanying drawings, in which:
FIGS. 1 and 2, when arranged according to FIG. 3, illustrate one embodiment of a time slot interchanger in accordance with the principles o the invention.
Detailed Description Broadly, referring to FIGS. 1 and 2 as arranged according to FIG. 3, a digital inpu~ frame, having N time slots and supplied to input terminal 810, is processed by time slot interchanger (TSI) 1000 for interchanging time slots. Thereafter, an ou~put frame having M interchanged time slots is extended to output terminal 9000. A common digital frame is the 125 microsecond Bell System Tl carrier frame which includes digital samples of information inserted into 24 time slots. In the illustrative embodiment, it is assumed (N=) 24 input time slots and (M=) 256 output time slots. And, as will shortly be made more clear, this assumption obtains in the illustrative Abbo~-2 i~ 6~7

3.
embodiment responsive to a logic 1 RT control signal ) detected at input terminal 840. On the other hand, and as will also become more clear, responsive to a logic O RT control signal, the inverse obtains~
5 i.e., (N=) 256 input time slots can be supplied to input terminal ~10 for being interchanged and inserted into (M=) 24 output time slots. Further, a plurality of TSIs 1000 may be arranged in parallel.
According to one aspect of the invention~ an 10 input time slot sample can be interchanged and inserted in one or more output time slots for broadcasting the sample of in~ormation to a plurality of locations.
More particularly, a digital sample from an input time slot is extended in parallel from terminal 810 over 15 cable 910 to data store 2000 and written for storage therein in a memory location of either data random access memory (RAM3 200-1 or data RAM 200-2. The address of the memory location into which the sample is written is supplied to data store 2000 over either 20 cable 490 from control store 4000 or over cable S90 from sequential counter 5000. In the illustrative embo~iment, control store 4000 supplies a "random"
address while sequential counter 5000 supplies a sequential address. The source of address supply is 25 selected responsive to the aforementioned RT control signal detected at input terminal 840. For example, on the one hand, responsive to a logic O RT control signal, the address of ~he RAM memory location to be written is supplied from control store 4000. On the 30 other hand, responsive to a logic 1 RT control signal, the address of the RAM memory location to be ~ritten is supplied from sequential counter 5000. As afore-mentioned, for ease of description, we assume the RT
control signal is a logic l and hence, samples are 35 written sequentially in the data RAM. Recall, as also Abbo~ 2 ~ :~ 6~158

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aforementioned, with the RT control signal being a ) logic 1, (N=) 24 input time slots are interchanged into (M=) 256 output time slots.
While a ~emory location within data RAM 200-1

5 is being ~Iritten with a sample from an input time slot, a menlory location within data RAM 200-2 is being read for inserting a sample in an output time slot.
That is, each data RAM alternates between being written during one frame interval and being read 10 during the next succeeding frame. In that connection, the memory location address for reading a RAM is also supplied to data store 2000 from either control store 4000 or sequential counter 5000. In the illustrative embodiment, the samples are written in s`equential 15 locations and the samples are read from "random"
locations. That is, responsive to a logic 1 RT
control si~nal, TSI 1000 reads a sample from the RAM
memory location identified by the "random" address supplied by control store 4000. (It will be remembered 20 that, responsive to a logic 0 RT control signal, an opposite operation obtains.j As the sample is read from either data RAM 200-1 or data RAM 200-2, the sample i 5 extended over cable 920-1 or cable 920-2, respectively, through output selector 710 to output 25 terminal 9000 for insertion into an output time slot.
Turning now to a more detailed descript;on of the operation of data store 2000. Firstly, as to supply;ng the memory location address for wr;ting or reading a data RAM,a binary control signal laSel 30 SYNCB is provided to input terminal 880 and within TSI
1000 is extended over lea~ 881. The SYNCB signal can be a single pulse occurring at the end of each input data frame. Here, it is assumed that the SYNCB
pulse occurs once for each 125 microsecond frame 35 interval. The SYNCB signal is extended over lead 881 to an input of data store 2000and therein to an input Abbott 2 i 3 ~l~5~7 s.
of flip-flop 240. The "l" output of ~lip-flop 240 is ) extended over lead 241 jointly to a control input of address select 210-1, a first input of exclusive OR
gate 220-1, and an input of enable control 230-1. In 5 dual fashion, the "O" output o-f flip flop 240 is extended over lead 242 jointly -to a control input of address select 210-2, a first input of exclusive OR
gate 220-2, and an input of enable control 230-2. Also, the RT control signa1, supplied to input terminal 340 10 is extended jointly over lead 841 to second inputs of exclusive OR gates 220-1 and 220-2. Responsive to a logic 1 on lead 241, or on its dual lead 242, address select 210-1, or its dual 210-2, respectively, operates in the sequential mode, i.e., the address supplied 15 over cable 590 from an output oF sequential counter 5000 is extended through the address select on an ADDR
address input of the respective data RAM. On the other hand, responsive to a logic O on lead 241, or on its dual 242, the "random" address supplied over cable 20 490 from an output of control store 4000 is extended through the respective address select to the ADDR
address input of the respective data RAM. Thereby, the memory location address is supplied writing or reading a data RAM.
Secondly, as to a first enabling of a data RAM to be written or read, an output of exclusive OR gate 220-1, or its dual exclusive OR gate 220-2, is extended to an RIW (read/write) input of the respective data RAM.
In particular, the data RAM is written responsive to a 30 logic O at its R/W input and read responsive to a logic 1 at its R/W input. In our illustrative embodiment, we assume that the RT control signal, which, as mentioned is extended to secondinputs of exclusive OR gates 220-1 and 220-2, is a logic 1. Hence, inasmuch as the binary 35 control signal on each of leads 241 and 242 alternates Abbott~-2 ~ 3 6~87

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between a logic 1 and a logic 0 on a frame by frame ) basis, here the alternating occurring each 125 micro-seconds, the memory location address supply alternates between counter 5000 and store 4000, respectively, and the output of the exclusive OR gates, and hence the 5 R/W inputs, alternates in phase to sequentially write and randomly read the data RAMs. As mentioned, the randomly read samples from data RAM 200-1 or data RAM 200-2 are supplied over cable 920-1 or 920-2, respectively, through output selector 210 to output 10 terminal 9000 for insertion in an output time slot.
Thirdly, a second enabling of a data RAM occurs to aviid spurious operation. Specifically, enable control 230-1, or its dual enable control 230-2, respectively, extends a logic 1 enable signal to a 15 data RAM EN enable input. Responsive to a logic 1 EN
signal, the data RAM will either read or write responsive to the signal supplied to its R/W enable input. On the other hand, responsive toa logic O data RAM EN input, the data RAM remains inactive.
20 To provide the EN enable signal, rach enable control includes AND gates and an OR gate, as shown for enable control 230-1, which, responsive to a logic 1 supplied from flip-flop 240, on either lead 241 or lead 242, the logic 1 meaning sequential addressing, allows the 25 SYNC~ signal at terminal 830 to be extended over lead 831 th~ough the enable control to the respective data RAM ~N enable input during each CLKA pulse. On the other hand, the enable control AND gates, responsive to a logic ~ supplied from flip-flop 24G on either lead 30 241 or lead 242, the logic O meaning random addressin~
allow the enable signal provided by control store 4000 to be extended over lead 491 through the enable control to the respective data RAM EN enab1e input during each CLKB pul,e. Thereby, each data RAM is 35 enabled to be read or written and yet avoid spurious operation.

Abbot~-2 1 ~ 6~5~37 Fourthly, as to generating a sequential memory ) location address, sequential counter 5000 is enabled for providing a cyclical, sequential address over cable 590 responsive to a lo~ic 1 SYNCA signal detected at input terminal 830. Thereafter, responsive to each 5 of a CLKA clock signal at terminal 820 as extended over lead ~21 sequential counter 5000 increments its existing count by unity and extends the resultant count over cable 590 as the sequential address.
Here, while the SYNC~IA signal is a logic 1 during a 10 frame, the CLKA clock signal provides (N=l) 24 equally spaced pulses and thereafter repeats by recycling itself.
Responsive to the address on cable 590, a sample at terminal 810 is written in seqwential memory locations o~ the selected data RAM. (Recall that when the RT
15 cQntrol signal at terminal 840 is logic 0, the respective data RAM is sequentially read according to the address on cable 590.) Fifthly, as to generating a "random" memory location address, referring to control store 4000 and 20 initialization processor 6000, two states are considered. The firs~t state is for initializing control store ~000 and the second s~ate is ~or using control store 4000 for time slot interchange.
As to the first state, processor 6000 is employed 25 for initializing control store 4000 and, as will be clarified shortly, for initializing alternate message store 3000. Processor 6000 can be a state of the art microprocessor for reading and formatting predetermined initializing data extended thereto from input terminal 30 860 when enabled responsive to an enable signal supplied to its input terminal 870. The initializing data may include an address of a memory location within control RAM 400 and predetermined data to be written therein. In the illustrative embodiment, control RAM
35 ~00 includes (M-) 256 memory locations, each locatiorl corresponding to an output time slot and each location for storing an input time slot number identification.
According to the principles of the invention a specific Abbot~-2 ~J 64587 input time slot number identification may appear in ) more than one memory location. Thereby, and according to tllis aspect of the invention, a broadcast arranyement is obtainable whereby a sample of information in one 5 input time slot may be broadcast through a plurality of output time slots to many locations.
In particular, the initializing data are read by processor 6000 and processed thereby, e.g., by reformatting the data (1~ for providing the predetermined 10 data, here the input time slot number identification, and the enable control signal for later extension on lead 491, over cable 610; (2) for providing a control RAM address, here corresponding to the output time slot number identification9 over cable 620 through address lS select 410 to the ADDR address input of control RAM
400; and (3) for providing a logic O CONT2 control signal over cable 640 jointly (a) to the control input Of address select 410 for selecting the address on cable 620 and (b) to a control RAM R/W input for 20 enabling control RAM 400 to write the predetermined data in the location identified by the control RAM
address. Also, the CLKB signal detected at input terminal 890 is extended over lead 891 jointly to the EN enable input of control RAM 400 for avoiding 25 spurious operation of control store 4000 and to an input of hereinafter described enable control 330 for avoiding spurious operation of alternate message store 3000.
As to the second state, the state involving the 30 use of control store 4000 for time slot interchange, processor 6000 extends a logic 1 CONT2 control signal over cable 640 for selecting the address provided by sequential counter 430 and for enabling control RAM 400 through its R/W input to read the predetermine 35 data from the location identified by the selected address. Responsive to a SYNCB enable signal at Abbott-2 ~3 64587 terminal 880 as extended over lead 881 and to a CLKB
) clock signal at terminal 890 as extended over lead 891, counter 430 extends a cyclical, sequential address, here sequentially addresses 1 through (M=) 256, 5 through address select 410 to the ADDR address input of control RA~l 400. Here, the SYNCB signal may be substantially the same signal as the SYNCA signal while the CLKB clock signal provides (M=) 256 equally spaced pulses during one 125 microsecond frame interval.
10 Responsive thereto, the addressed memory location is read and its contents are extended over cable 490 as the rando~ address. Also, a logic 1 control signal is extended over lead 491 for controlling enable control 230-1 or 230-2 as hereinbefore described.
15 In light of the above, it should be clear that the (M=) 256 memory locations of control RAM
400 are phase sensitive to the (M=) 256 output time slots. Inasmuch as the control RAM memory location contents identify both the input time slot and the 20 data RAM memory location to be read and inasmuch as the control RAM memory location identifies the output time slot, TSI 1000 r~eadily interchanges samples from an input time slot to one or more output time slots for broadcasting the sample to many locations.
According to anotheraspect of the invention, ; rather than inserting an input time slot sample into an output time slot, the TSI 1000 includes an arrangement for selectively inserting an alternate message in the output time slot. In the illustrative 30 embodiment, alternate message store 3000 is for providing the alternate message, e.g., an error message. Broadly, rather than reading a sample from data store 2000 and inserting the sample into one or more output time slots, an alternate message can be read from alternate message 35 store 3000 and extended over cable 920-3 through output select 710 for insertion in one or more output ,, ~

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time slots. Alternate message store 3000 is initialized in a manner paralleling the initialization of control store 4000. On the one hand, resp nsive to a logic 1 CONT1 control si~nal on lead 630 as 5 extended to its R/W input, alternate message RAM 300 is enabled to be read. As to the memory location address for reading, AMS select controls 340 selects either the sequen~ial address on cable 590 or the random address on cable 490 in a manner paralleling 10 the aforedescribed data store operation. In the illustrative embodiment, inasmuch as the RT control signal at terminal 840 is assumed to be a logic 1 and the CONTl control signal is assumed to be a logic 1, AMS select control 340 extends the random address on 15 cable 490 through address select 310 to the ADDR
input of alternate message RAM 300 during the read operation. On the other hand, responsive to a logic O CONTl control signal on lead 630, alternate message store. 3000 is enabled to be written for initialization 20 with predetermined data extended thereto over cable 610. The predetermined data are written into a memory location having an address corresponding to an input time slot. The write address is extended over cable 620 through address select 310 to the ADDR
25 address input of alternate message RAM 300.
Also, to avoid the spurious operation, enable control 330 includes AND gates and OR gates for providing either a logic 1 or a logic O enable signal to the EN
enable input of RAM 300. Xesponsive to the logic 1 EN
30 signal, the alternate message RAM will either read or write responsive to the signal supplied to its R/W
enable input. On the other hand, responsive to a 10gic O EN input, the alternat;e message RAM remains inactive.
Hence, enable conrrol 330 parallels the aforedescribed 35 enable controls 230-1 and 230-2 for avoiding spurious operation.

Abbott.~2 3 11 .
In the illustrative embodi~ent, an alternate ) message RAM location corresponds to an input time slot.
Also, the predetermined data, which is written into each location, is assumed to comprise two words, herein 5 referred to as word 1 ~nd word 2, respectively, and a two-bit control signal as hereinafter described. Of course, other embodiments are possible. Hence it should be borne in mind that the description is no-t by way of limitation but rather by way of illustration.
Next, to allGw flexibility both in the operation and in the maintenance of time slot interchanger 1000, an external select signal may be extended from terminal 950 over cable 851 to one input of output select control 730 for controlling the information inserted 15 in an output time slot. Specifically, the aforementioned two-bit control signal is extended over cable 391 from alternate message store 3000 to a second input pf output select control 730. In the illustrative embodiment, there is assumed a two-bit control signal 20 in accord with the following table definitions:
Control Bits Function 00 Select data RAM unconditionally 01 Select data RAM unless external Select is a logic 1, then select word 1 of alternate message store Select word 1 o-F alternate message store unconditionally 11 Select word 2 of alternate message store unconditionally 30 Also~ it should be noted that (1) an output of flip-flop 240 on lead 242, (2) the RT control signal on - lead 841, (3) the SYNCA signal on lead 831~ and (4) the enable output of control store 400 on cable 491 are extended to other inputs of output select control 35 ~30 responsive to which a control signal is extended over cable 720 to output selector 710 for selecting Abbot~-2 ~1 64587 the proper signal, i.e., the signal on cable 920-1, ) 920-2, or 920-3, for extension to output terminal 9000.
More specifically, responsive to detecting '00' 5 control bits on cable 391, output select control 730 extends a control signal over cable 720 to output selec~ 710 for selecting and inserting the contents o~
either data RAM200-1 or data RAM 200-2 into an output time slot. As mentioned, the '0' output of flip-flop 10 240 extends a logic 1 over lead 242 responsive to which data RAM 200-2 operates in a sequential mode. Inasmuch as the RT control signal is assumed to be a logic 1, the sequential mode is employed in writing a data RAM.
Hence, a logic 1 on lead 242 implies that data RAM
15 200-1 is enabled for reading whereas a logic 0 on lead 242 implies that data RAM 200-2 is enabled for reading.
In similar.fashion, responsive to detecting '01' control bits on cable 391, output select control 730 20 extends a control signal over cable 720 to output select 710 for either (1) selecting and inserting the contents of a data RAM into an output time slot or (2) selecting and inserting word 1 of alternate message store 3000 into the output time slot.
25 Responsive to a logic 0 external select signal on lead 851, the contents of the data RAM are selected in fashion similar to that aforedescribed for detecting '00' control bits on cable 391. Responsive to a logic 1 external select signal on lead 851, word 1 of the 30 alternate message store is so selected.
Again in similar fashion, responsive to detecting '10' or '11' control bits respectively on cable 391, the output select control signal on cable 720 is for selecting word 1 or word 2 respectively, and extending 35 same over cable 920-3 for insertion in the output time Abbott-~
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slot. Thereby the TSI 1000 includes an arrangement ) for selectively inserting an alternate message in an output time slot and broadcasting same to many locations.
Although the invention has been described and illustrated in detail, it is to be understood that the same is by way of illustration and example only.
Various modifications will occur to those skilled in the art and the invention is not to be considered 10 limited to the embodiment chosen for purposes of disclosure. For example, control RAM 40~ could be updated on a dynamic basis. Thus, the spirit and scope of the invention are limited only by the appended clalms.

Claims (2)

Claims:

1. Apparatus for interchanging time slots said inter-changing apparatus including an input terminal adapted to receive an input frame, said input frame having a first plurality of input time slots, each input time slot for communicating a sample of information, data storage means having a plurality of storage locations;
means for extending an input time slot sample from an input time slot through a storage location to an output time slot and thence to an output terminal for insertion in an output frame, said output frame having a second plurality of time slots and characterized in that said interchanging apparatus further comprises means for selectively inserting an alternate message in one or more output time slots to many locations.

2. The interchanging apparatus defined in claim 1 further comprises:
means for altering said alternate messages.