CA1162320A - Microcomputer video display system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
This invention relates to a digitally controlled, raster scanned, video display for a microcomputer. The display provides color images in response to chroma signals having predetermined phase relationships to a reference signal.
A circuit which generates a digitally controlled chroma signal has a digital word generation means for generating predetermined digital signal, serializing means coupled to the generation means for repeating the word in a serial form at a predetermined frequency so as to provide frequency components at the reference signal frequency, and converting means coupled to the serializing means for converting outputs from the serializing means to an AC signal.

Description

I 16232~) 1 This application is a divisional of application serial number 377,116 filed May 7, 1981.
The invention relates to the field of digital computers, particularly microcomputers, having video display capabilities.
Prior Art In the last few years, there has been rapid growth in the use of digital computers in homes by hobbysists, for small business and for rou~ine engineering and scientific application. For the most part, these needs have been met with self-contained, relatively inexpensive microcomputers or microprocessors with essential peripherals, including disc drives and with relatively easy to manage computer programs.
The design of computers for these needs requires considerable ingenuity since each computer must meet a wide range of applications and because this market is particularly cost conscious. . ...
A home or small business computer must, for example, - operate with a number of different program languages, inc,luding -20 those requiring relatively large memories, such as Pascal.
The computer should interface with a standard raster scanned display and provide a wide range of display capabilities, such as high density alpha-numeric character displays needed for word processing in addition to high resolution graphics displays.
To meet these specialized computer needs, generally requires that a relatively inexpensive microprocessor be used and that the capability of the processor be enhanced - through circuit techniques. This reduces the overall cost of the computer by reducing, for example, power needs, bus - 1 16'~32(~

l structures, etc. Another important consideration is that the new computers be capable of using programs developed for earlier models.
As will be seen, the presently described microcomputer is ideally suited for home and small business applications.
It provides a wide range of capabilities including advanced display capabilities not found in comparable prior art computers.
The closest prior art computer known to applicant is commercially available under the trademark,-Apple-II. Portions of that computer are described in U.S. Patent No. 4,136,359.

S~J~ARY OF THE INVENTION
A digital computer which includes a central processing unit (CP~) and a random-access memory (RAM) with interconnecting address bus and data bus is described. The capability of the CPU is increased by allowing base page or zero page data to be stored throughout the memory. Alternate stack locations and an improv~d direct memory access capability are also provided by the same circuitry. Detection means are used for detecting a predetermined address range such as the zero page. This detection means causes a special register (Z-register) to be coupled into the address bus. The contents of this Z-register provide, for example, a pointer during direct memory access, or alternate stack locations for storing data normally stored on page one.
The memory of the invented computer is organized in an unusual manner to provide compatibility with the ~-bit data bus and yet provide high data rates (16-bits/MHz) needed for high resolution displays. A first plurality of memory devices are connected to a irst memory output bus; these memory devices 1 16232n 1 are also connected to the data bus. The memory includes a second plurality of memory devices which are also connected to the data bus; however, the outputs of these second devices are coupled to a second output memory bus. First switching means permit the first and second memory buses to be connected to the display for high data rate transfers. Second switching means permit either one of the memory buses to be connected to the data bus during non-display modes.
The addressing capability of the memory is greatly enhanced not only through bank switching, but through a novel remapping which does not require the CPU control associated with bank switching. In effect, the "unused" bits from onè of the first and second memcry buses are used for remapping purposes. This mode of operation is particularly useful for providing toggling between two separate portions of the memory.
The display system according to the invention generates video coIor signal in a unique manner. A 4-bit color code as used in the prior art, is also used with the described display subsystem. However, this code is used to generate an AC chrominance signal and a separate DC
luminance signal. This provides enhanced color capability over similar prior art color displays.

BRIEF DESCRIPTION OF THE DRAWINGS:
Figure 1 is a block diagram showing the major com-ponents and subsystems of the invented and described micro-computer system.

Figures 2 and 3 together show the central processing unit ~CPU) and the architecture associated with this CPU, 11~232n 1 particularly the address bus and data bus. Figure 2 is a circuit diagram primarily showing the address bus and the logic means associated with this bus. Figure 3 is a circuit diagram primarily showing the data bus and its inter-connection with the memory buses (~ bus and B bus), bootstrap read-only memory, and input/output ports.
Figures 4, 5 and 6 show the memory subsystem. Figure 4 is a circuit diagram primarily showing the circuitry for s~lecting between address signals from the address bus and display counter signals. Figure 5 is a circuit diagram primarily showing the generation of various "select" signals for the memory devices. Figure 6 is a circui~ diagram showing the organization of the random-access memory and its interconnection with the data bus and memory output buses.
Figures 7 and ~ illustrate the display subsystem of the invented computer. Figure 7 is a circuit diagram showing the circuitry for generating the digital signals used for the video display. Figure 8 is a circuit diagram of the circuitry used to convert the digital signals to analog ~ video signals.
Figure 9 is a graph of several waveforms used to describe a prior art circuit and the circuit of Figure 8.

T~ILED DESCRIPTION O~ THE INVENTION:
A microcomputer system capable of driving a raster scanned video display is disclosed. In the following description, numerous specific details such as specific part numbers, clock rates, etc., are set forth to provide a thorough understarlding of the present invention. However, it will be obvious to one skilled in the art that the inventive concepts 1 1~232~) 1 described in this patent may be practiced without these specific details. In other instances, well-known circuits have been shown in block diagram form in order n~t to obscure the present invention in unnecessary detail.
Referring first to Figure l, in general the described computer includes a central processing unit (CPU) 65, its associated data bus 42, address bus 46, a memor~ subsystem and a display subsystem 58.
The address bus 46 from the CPU is coupled to the memory subsystem to permit the selection of locations in memory. Some of the address signals pass through a multi-plexer 47: For some modes of operation, signals from a reg,ister 52 are coupled through the multiplexer 47 onto the bus 46. The register 52 is identified as the Z-register and is coupled to the multiplexer 47 by the Z bus. The general ' description of the multiplexer,47 and its'control by the logic circuit 41 are described in detail in con~unction with Figure 2. In general, the circuitry shown to the left of the dotted line 53 is included in Figure 2 while the CPU 65, memor~ 50, data bus 42 and multiplexer 43 are shown in detail in Figure 3.
' The address bus Nl is coupled to the read-only memory 50. The output of this memory is coupled to the computer's data bus 42. The read-only memory ~ROM) 50, as will be described, stores test routines, and other data of a general bootstrap nature for system initialization.
The data bus 42 couples data to the random-access memory (RAM) 60 and to,and from I/O ports. This bus also couples data to the Z-register 52 and other commonly used registers not illustrated. The data bus 42 receives data from , ` , ~ 5 ~

6232n 1 the R~l 60 through the A bus and B bus which are selected by multiplexer 43. The peripheral bus N2 is used, as is better illustr2ted in Figure 3,-for coupling to peripherals.
The memory subsystem is shown in detail in Figures 4, 5 and 6. The address control means which receives addresses on bus 46, makes the final selection of memory locations within the RA~1 60. Bank switching, addressing for display purposes, scrolling and other memory mapping is controlled by the address control means 59 as will be described in greater detail in conjunction with Figures 4 and 5. The RAM 60 is shown in detail in Figure 6. The counter 58 which is synchronized with the horizontal and vertical display signals, provides signals both to the address control means 59 and to the display subsystem 48.
The display subsystem receives data from the RAM 60 on the A bus and B bus and converts these digital signals to video signals which control a standard raster scanned display.
A standard NTSC color signal is generated on line 197 and a black and white video signal on line 198. The same signals used to generate these video signals can be used to generate separate red, green, blue (RGB) video signals.
The display subsystem 48 receives numerous timing signals including the standard color reference signal shown as 3.5MHz (C3.5M). This subsystem is described in detail in Figures 7 and 8.

- ` I 16232(~ !

~¦¦ coMp~lrER ~RCIIITFCTURE

In the presently preferred embodiment, the CPU 65 ' (microprocessor) employed with the described computer is a , commercially available component, the 6502A. ~his 8-bit processor (8-bit data bus) which has a 16-bit address bus is shown in Figure 3 with its interconnections to the remainder of the computer. The pin number for each interconnection is shown adjacent to the corresponding line. In many cases, the nomen-clature associated with the 6502A ~CPU 65) is used in this application. For example, pin 6 receives the nonmaskable interrupt signal (NMI), and pin 4 is coupled to receive the interrupt request signal (X~). Some of the signals employed with the CPU 65, which are well-known'in the art, and which are not necessary far the understanding of the present invention are not described in detail in this application, such as the various synchronization signals and clocking siqnals. The address signals from the CPU 65 ~re identified as Ao-A7 and A'8-A15.
~he data signals associated with the CPU 65 are shown as Do-D7. ' As will be apparent to one skilled in the art, the in~entive concepts described in this application may be emp,loyed with other micr,oprocessors.
, .' Referring now to Figures 2 and 3, the general architecture, particularly the architecture associated with the CPU 65 can hest be seen. The address signals Ao-A7 are coupled to a -i7-.' 11 t 1 6 2 3 2 n buffer 103 by the bus shown primarily in Figurc 2. These addre~ss signals are also coupled to the ROM 50. The signals -A7 after passing through the buffer 103 are coupled to the memory subsystem. The address signals A8-~15 (higher order address bits~ are coupled through lines shown in Figure 2 to the multiplexers 47a and 47b. The contents of the Z-register 52 of Figure 1 is also connected to the ~ultiplexers 47a and 47b through the Z-bus (Zl-z7) The multiplexers 47a and 47b allow the selection o~ either the signals ~8-A15 from the CPU 65 or the contents of the Z-register (Zl-z7) ~or addressing the RAM 60. The output of these multiplexers are shown as A8-Als;
this designation is used even when the i-bus is selected. Note in the case of the Zo signal, this signal is coupled to the multiplexer 47a through the exclusive OR gate 90 for reasons which are eY.plained later. The address signals A8-All are also coupled to the ROM 50, thus the signals ~o~A11 are used for addressing the ROM 50. The signals ~8-A15 are connected to the logic circuit shown in the lower left-hand corner of Figure 2; ~his logic circuit corresponds to the lo~ic circuit 41 of Figure 1.

The input and output data signals from the CPU 6~ are coupled by a bidirectional bus to the bidirectional buffer 99 (Figure 3). This buffer is selectively disabled by gate 100 to allow the output of RO~ 50 to be communicated to CPU 65 and during other times not pertinent to the present discussion.
.

.11 1 16232n `!

The direc~ion of flow tllroutlh th_ buffer 99 is controlled by a read/~rite signal coupled to the buffer through inverter 101.
Data ~rom the CPU 65 is coupled through the buffer ~9 and bus 42 to the R~M 60 or to I/O ports. Data from the RAM 60 is communicated to CPU 65 or bus N2 from the A bus and B bus through the buffer 99. The 4 lin~s of the A bus an~ 4 lines of the B
bus are coupled to the multiplexer 43a. Similarly, the other 4 lines of the A and B buses are coupled to the multiplexer 43b.
Multiplexers 43a and 43b select the 8 lines of the A bus or B.
bus and communicate the data through to buffer 99 and bus 42.
These multiplexers are selectively disabled (~or example, during writing) by gate 102. As will be described later, the 16 lines of the A bus and B bus permits the reading of 16-bits from the RAM at one time. This provides a data rate of _ ? 5 16-bits/M~Iz which is necessary, for example, for an 80 character . per line display. The data is loaded into the R~M 60, 8-bits at a time.
.. ' The ROM 50, as mentioned, stores test programs, data needed to initi~lize various registers, character generatio data (for RAM 162 of Figure 7) and other related~data.
. Specific programs employed in the presently preferred embodiment of the computer are set forth in Table.l. The ROM 50 is selected by control signals coupled to its pins 18 and 20, identified as signals RO~ SE.L and T ROM SEL. Any one of a plurality of commercially avai.lable read-only memories may be Il 116232(~ ~

used for the ROM 50. In the presently preferred eMbodiment, cornmerciall~ available Part No. SY2333 is used.

, Referring now to this logic circuit (lower left-hand corner of Figure 2), the NAND gate 81 receives the address signal A8 and also the alternate stack signal identified as ALl' STK.
The output of this gate provides one input to the ~NV gate 8~.
The A8 signal is also coupled throu,gh the inverter 82 to one input terminal of the NAND gates 85 and 86. The address signals , Ag and ~10 are coupled to the input terminals of the NOR gate 83.
The outpu~ of this gate is coupled to one input terminal of the NhND gates 85 and 86 and the AND gate 87. The addréss signals -¦ All~A15 are coupled to the input terminals of the NOR gate 84.
The siynal A11 is also coupled to an input ter~inal of t~e NAND gate 85. , ' - , ., ,, The outputs of the AND gate,s ~7 and 88 (through NCR gate 89), controls the multiplexers 47a and 47b. ~hen the output of ¦ yate 89 is low,the Z-bus is selected, otherwise the address I signals ~rom the CPU 65 are selected.
-~ ~
l The logic circuit above described, along with the Z-bus ¦ and Z-registér provide enhanced performance for the computer.
First,this circuit permits the zero paye or base page data ¦ to be stored throughout the RnM 60 rather t,han just on z,ero page. Secondly, this circuit enables addressing of alternate ¦ stack locations ~other than page one). Lastly, this circuit :

.,.11 .
i 116232n through the æ-register provides a R~5 pointer for direct memory access (DMA).

~ssume for purposes of discussion that the CPU 65 is , addressing the zero page of memory. Tha~ is, the hi~her order address bits ~g-Als are all zeros. The zeros for Ag-A15 are detected by the gates 83 and 84. If all the inputs to these gates are zeros, the outputs of these gates are high which condition is communicated to the gate 87. A8 which is also low, insures that the output of gate 81 will be high. Thus, al'l the inputs to gate 87 are high, causing the signal at the output of the gate 89 to drop. When this occurs, the Z-bus is sel~cted. Instead of all tlle bi,nary zeros from the CPU , ~ing coupled to the main memory (~AM 60), the contcnts of the Z-register form part of the address for the memory. Therefore . ,.. ..
' even though the CPU 65 has selected the zero page, nonetheless ,, data may be written into or from any location of XAI~ 60 (including the zero page). This enhances the perfor~ance of the CPU, since 'for example, the time consumed in shifting data - to and from a single zero page is minimized.
., ~
~ormally,,the CPU 65 selects page one for stack loca~ions.
This occurs wh-n A8 is high and Ag-Al5 are low. ~ssume first `I 116232n ` ``

that the alternate stack locations have not been selectèd.
Both inputs to gate 81 are high ar,d its output is low. The low input to tlle gate 87 prevents the selection of the Z-bus.
Thus, for these conditions the adclress signals Ao~A7 select S stack locations on page one.

~ext assume that page one has been selected by the CPU and that the ALT srrK signal is low, indicating the alternate , stack locations are to be selected. (~ flag is set by the C~U to change the ALl' STK signal). Since the ALT STK signal îs low and A8 is high, a high output occurs from the gate 81.
All the inputs to gates 83 and 84 are low, therfore, high outp~ts , occur from both these gates. The conditions of gate 87 are met, causing a high output from this gate and lowering t~e output , from tl,le gate 89. The Z-bus is thus selected by the multiplexers ,,47a and 47b. This allows the contents of the ~~register to be ¦ used as alternate locations. Non-zero paye locations are assured , by inverting A8. The exclusive OR gate 90 acts as a s~lective inverter. If A8 is high and Z0 is low, then ~8 at the output of the'multiplexer 47a will be low. Note that during z~ro 20 , page selection when A8 is low, the Z0 signal is directly communicated through gate 90 to the output of multiplexer 47a.
.. , ', ', Thus, the logic circuits along with the ALT STK signal allows alternate stack locations to be selected through the Z-bus. This further enhances the performance of the CPU
which would otherwise be lirnited to pa~e one for stack locations.

1 16232~ "

` The logic circuit of Figure 2 is also used along with the Z-register to provide a pointer during direct memory acce~s (DMA). Assume that direct access to the computer's memory is required by a peripheral apparatus. To initiate the D~ mode the CPU provides an address between E800 and F8FF.
Through a logic circuit not illustrated in Figures 2 and 3, the RO~I SEL signal is brought low for addresses between F000 and FFFF. This signal is communicated to gate 93 and causes the output of gate 92 to rise (DM~l is high at this time). This , 10 rise in potential is communicated to one input of the gate 85.
Additionally, gate 85 senses that the address bits Ag, Ag and Alo are low. This information is coupled to gate 85 through the invertér 82 and the NOR gate 83 as high signals.
~lso the act that ~11 is high is dir~ctly communicated t~
¦ gate 85. Thus, with the address between F800 and F8FF the '''D~;A OK'signal drops in potential. This is sensed by the peripheral apparatus which in turn causes the ~ 1 si~n~l to drop and provides a ready signal to the CPU 65. With the ¦ completion of this handshake, data may begin to be transferred to the R~M.
, ': . ` . ' ~ .
The DMA--r signal through gate 93 and inverter 93 forces the T ROM SEL signal low. This signal in additi,on to being communicated to the ROM 50, is coupled to the buffer ~9 through gate 100, disabling this buffer (during the r~ading o ROM 50).

6232n . ) Also, the ready signal causes the CPU to come to a hard stop.
Importantly, the DMA 1 signal, after passing through the inverter 94 and the gates 88 and 89, assures the selection of the Z-register.- The contents of the Z-register are fixed and S provide a pointer to a page in the RAM.
. . '.

Under the above conditions, the CPU increments the lower 8-bits of the address signal. The ROM 50 furnishes the instructions for incrementing the address, specifically S~C ~1 and BEQ. The peripheral apparatus provides the data or receives the data in synchronization with the CPU operation. The peripheral also furnishes a read/write signal to indicate which operation is to occur. Data is then written into RAM via bus N2 and bus 42, or read from R~ via the A and B buses and bus N2, , ,.. ..

lS Impoxtantly, with the above ~MA arrangement, addresses from the peripheral apparatus are not necessary and the ; ¦ Z-r~ or i5 used to provide a pointer to a page in RAM 60.

' ~ ~
.-. , ' , , .

¦¦ 1 16232n `
~EMORY SUBSYST~M

The memory su~system shown in Figure l as the address control means 59 and ~ l 60 is illustrated in detail in Figuxes 4, 5 and 6 as mentioned. In Figures 4 and 5, the memory control means is shown, while in Figure 6 the memory devices and their organization are illustrated. The address control means of Fi~ures 4 and 5 rcceives ~he address sicJ~I~ls from the CPU 65 (Ao~Al5), the count in the vertical and horizontal counters (counter 58 of Figure l) ~Jhich are used during display modes, control signals from the CPU and other si~nals. In general, this control means develops the address signals ~hich are coupled to the RAM of Figure 6 including the column address and row address signals/ co~nonly referred to as CAS and l~S.
Other related functions are also showr: in Figures 4 and 5, 1~ such as the circuitry which provides display scrolling, indirect RP~l addressing and memory mappina.
' The CPU 65 of ~igure 3 provi~es a 16-bit address for addressing the memory. Under ordinary circumstances this address limits the memory capacity to 64K bytes. This size me~ory is insufficient in many applications, as for example, to effectively use the Pascal prDgram languag~. As will ~e described in greater detail, the address control means of Figar~s 4 and 5 enable the use of a ~emory having a 96K byte or 12~K byte capaci~y. One well-kno~7n technique which is used with the present invention for increasing this capacity is bank s~7itching; this s~itchiny occurs under the control of the CPU.

6232n ) ¦

In addition, the address control mealls uses a uni~ue indirect addressin~ mode which provides the benefits o~ bank switching, however, this mode does not require CPU control. This greatly enhances CPU operation with the larger memory (as will be described) when compared to the CPU controlled bank switchin~.

Referring first to Figure 6, the R~M configuration is illustrated for a capacity of 96K bytes. The memory is organized into six rows, each of which includes eight 16K memory devices such as rows 111 and 112. In the presently preferred embodiment, Part No. 4116 MOS dynamic R~Ms are used. (The pin designatlons and signal designations refer to this memory device.
Obviously, other memory devices may be employed.
,' Input data ~o these memory devices 106 is provided from the ~us 42. Each line in the bus 42 is connected to the data input 1~ terminal of one device 106 in each row. The interconnection of this bus with each of the memory devices is not shown in Figure 6 in order not to overcomplicate this drawing. By way of ~ample, however, line 107 connects the data bit D7 to the data I input terminal-of one of the memory devices in each of the si~
¦ rows.
I
¦ Thxee rows of devices 106 have their output terminals ¦ coupled to the A bus, and three rows are similarly coupled ¦ to the B bus. By way of example, line 108 connects three output ¦ terminals of devices 106 to the DB7 line of the B bus while line ¦ 109 connects three output tern)iJIals of the devices 106 to ~he ¦ DA7 line of the A bas.

~ ~1 116~32~ ' I
. ` "-Thc descri~ed men)oly devices ]()G arc each orqanized as a 16KXl memory. Thus, each dcv;ce rcccives a l~ it address , wllich is time multiplexed into ~wo, 7-bit addresses. This multiplexing occurs under the control of the C~S and R~S signals as is well-known. l'he lines coupling the add~ess signals to each of the devices in Fi~ure 6 are not illus~rated ~owever, in the lower riyht-hand corner of Fi~ure 6, the variQus si~nals applied to eacll devicc (includil~c3 thc a~lclress sic~nals), along with the corresponding pin numbers are shown, Other circuitry not illustrated is the refresh control circuitry which operates in a well-known manner in conjwlction with the CAS, R~S and address signals to refresh the dynamic devices.
'.' Each row of m~moxy devic~s 106 rcccivcs a unique combin-, ation o~ C~S a~ld RAS signals. For example, row 111 receives-C~ -5, 7 and ~S 4, 5; similarly, row 112 receives C~S 0 and RIS 0, 3~ The g~neration of these C~S and RAS si~jials is described in conjunction with Figure 5. These siynals (along with the 14-bit address signals) permit the selection of a single 8-bit location in the ?6K byte memory (for writi~l~) and also the sel-ection (for reading) of lG-bit lo¢ations.

The memory of Figure 6 may be ex~panded to a 12gK byte memory by using 32K memory devices, such as Part No. 4132. In this case, four rows of eight, 32K memory d~vices are us~d with each row receiving two CAS and RAS sicJnal~, 16232n ~
`.

Before reviewin~ Fic~urc 4, a general understanding of the organization o~ the display is helpful. The display, , during ceL-tain modes, is orgallized into 80 horizontal se~ments , and 24 vertical se~ments for a total of 1920 blocks. ll-bits of the counter $8 of Figure 1 are used as part of the address signals for the memory to access data for displayinq during these modes. These counter signals are shown in Figure 4 as Ho-H5 and V0-V~. Durinc3 other display modes each horizontal segment is further divided into 8 segments (e.g. for displaying ].0 80 alpha numeric characters per l,ine). This requires 3 additional vertical timing signals showll as V~, VB and Vc in Figures 4 and 7. , -Often in the prior art, two separate counters are used to supply the timing/address signals for accessing a memory when ,,,the data in the memory,is displayed. The count in one counter represents the horizontal lines of the screen (vertical count) and the other the position along each line, (horizontal or dot count). In many prior art displays the most signifLcant bit of the dot counter is used to increment the line counter. Data in memory intended for display is mapped with a one-to-one , correlation to the counts in these counters. In another prior axt system (implemented in the Apple-II computer sold by Apple Computer, Inc.~ this one-to-one correlation is not used.
Rather, to conserve on circuitry, a single counter is employed 2S ¦ and a more dispersed mapping is used in the memory. (l~ote that ~7here a maximum horizontal c,ount of 8~ is used, this number . .,, .,'`11 . . I
~ ~232n cannot be represeIlted by all ones in a di~lital coun~er and thus thc vertical counter canllot ~a~ily ~c increm~llted b~ the mos~ si(3niicant bit in the hori~ontal counter.) Since this more dispelsed mapping techni~ue is part of the prior art and not critical to an understanding of the present invention, lt shall not bc described in detail. ~owever, the manner in which it is implemented shall be discusscd in conjunction Wit}l the adder 114 of Figure 4. For purposes of discussion, the signals from the counter 58 of Figure 1 are designated as either vertical (V) or horizontal (I~).

Referring now to Figure 4, the selection of either the co~n~er signals on the address signals from the CPU is made by the multiplexers 116, 117, 118 and 119. ~,ach of these co~-. mercially availab]e multiplexcrs (Part No. 153) couples one of lS four input lines to an output line. There are eight inputs to multiplexers 116, 117 and 118 and the outpu~s of these multi-plexers provide the addre~s si~nals for the ~emories (AI~O through AR5). The multiplexer 119 has four inputs on its pins 3, ~, 5, 6 and provides a single output on pin 7, the AR6 address signal. ~The signals supplied to pins 11, 12 and~l3 o~
~ultiplexer 119 are for clamping purposes only.) .
The AX signal is applied to the pin 14 of each o~ the multiplexers. The signal on this line and the signal applied to pin 2, determines which of the four inputs is coupled to each of the outputs of the multiplexers. The ~X signal is a R~s timing ll 1162321i) ~`

¦ sig ;1 for clocking the first 7 bits and second 7 bits of the mult:iplexed 14-bit address applied to each of the memory devices 106. The other control signal to the multiplexers is developed through the ~D gate 123. The inputs to this gate are the display signal (DSPI.Y) which indicates that the computer is in a display mode and a clocking signal, specifically a lNHz timing signal (ClM). The output of the A~D gate 123 determines whether the address signals from the CPU or the signals associated ~ith the counter 58 of Figure 1 are selected.

Assume for purposes of dis-ussion that the display has not been,selected, and thus, the output of gate 123 is low.
, The AX signal then selects for pin 7 of multiplexer 116 first , the addr~ss signal ~0 and then A6, Like~7ise, each of the , multip]exers selects an address signal (except for those '15 associated with exclusive OR gates 124 and 125 which shall be discussed). If the display siqnal is high and an output is present from the gate 123, then, by ~7ay of example, the AX
signal first causes the Hl signal and then the Vl signal to be connected to the ARl address line. Similarly, signals corresponding to the vertical and horizontal count are cou~led to the other address lines during display modes.

The adder 114 is an or~inary digital adder for adding t~o 4-bit digltal nibbles and for providing a digital sum signal.
A commercially available adder (Part No. 283) is émployed.
The carry-in terminal ~pin 7) is grounded and no carry-outs occur since one of the inputs (pin 12) i3 grounded. Thc adder sur,s Il . .
1 16232n `
.
the dic3ital si~nal corrcspondinc3 to Y3, 1l4 and ~!5 with the di~i~.al signal corresponding to V3, V4, V3, V4. The resultant sum signal is coupled to the multiplexers 116, 117 and 118 as illustrated. The summing of these horizontal and vertical counter signals is used to provide thc more dispersed mapping as previously discussed.

The adder 121 is identical to adder 114 and is coupled to sum the three least significant vertical counter bits from the counter 58 (Figure 2) with the signals V~l, VBl and VCl. The sum is selected by the multiplexer 120 during the high resolution display , modes and also durin~ scrolli.ng as ~ill be describcd. These ., sum signals ~re coupl~d to the multiplexers 117, 118 and 119.
During the low resolution display modes, the mu].tiplexer _1.20 couple~ ground signals or the page 2 signal ~G2) to the ¦ multiplexers 117, 118 and 119. (The PG2 sicJnal is uscd for special mapping purposes, not pertinent to the pr~sent invention.l During the hi~h r-esolution modes ~hen the,di~play is not beina scrolled, the VAl, VB2' and VB3 signals are at ground potential and thus no summing occurs within adder 121 and the VA, VB and VC signals are coupled directly to the multiplexc'rs 117, 118 and 119. ' '' ' The address signals Alo, All, and A13 from the CPU are coupled to the multiplexers 117, 118 and 119, respectively, through exclusive OR gates 124, 125, and 126, respectively.
25, The otller inpu,t terminals to gatcs 124 and 125 rcccive the C3 11 116232n ` ~` .
.

signal, while the other input terminal of the gate 126 receives the Cl signal. (The development o' the Cl and C3 signals is illustrated in Yi~urc 5.) Thc gates 124, 125 and 126 provide mapping compensation within the me~nory. As the computer and memory are presently implemented, the sequence in which the various portions of the display are generated is not the same as the sequence in which the data is removed from memory for display.
These gates provide compensating addresses and, in effect, cause a remapping so that the proper secuence is maintained when data is read from the memory for the dis~lay. These gates are shown to provide a complete disclosure of the presently preferred embodiment, ho~lever, they are not critical to the present invention.
~ ' , In operation, the circuitry of Figure 4, as mentioned, -selects the address signals which aré applied to each of the memory devices, either from the CPU or counter if the display mode is selected. It should be noted that not all of the address bits fro~ the CPU are coupled to the multiplexers 116 through 119.
Some of these address bits, as will be described in conjunction with Figure 5, are used to develop the various C~S and RAS signals and thus select different rows ~ithin the memory of Figure 6 The scrolling operation which is used is somewhat unusual in that each line of the display is separately moved up (line-by-line) with one line of data in merory being rnoved for each frame.

25 This technique provides a unîfor~, esthetically pleasing, scroll Scrolling the screen one line per frame can be achicved by moving 1 16~32n all the data in tlle memory ia~to a new position for each frame.
~his wou]d be very time consumin~ and impractical. With the described techniquc, only one-cicJhth of the data in the memory is moved ~or each new frame.
.'' Referring to the addcr 121, as mentioned, the signals V~
VB and Vc are the three least si~nificant vertical counter ~its from the counter 58. These }~its or counts, by way of example, represent the 8 horizontal lines of each character. In adder 12, a 3-bit digital si~nal, VAl, VBl and VCl, is added to the count from counter 58. This 3-bit si~nal is constant durin~
each frame, however, it is incremented for each new frame.
.
During a first frarne, 000 is addcd to the vertical count.
During a second frame, 001 is added;and during a third frame, 010 .is added,and so on. By adding this diyital signal to the count from counter 58, the addresses to the memory are char.ged in the vertical sense. During the first ~rame ~hen 000 is added, the display remains unaffected. During the néxt frame, when 001 is added to the vertical count, instead of first displaying the first line of a character, the second line of each character is displayed at the top of each character space and each sub-sequent line of the character is likewise moved up one line. If data in memory is not moved, the first line of the charactcr ~oulcl appear at the bottom of each character. Note whçn 001 is added to 111 from the counter, 000 results. Thus, the first line of characters would be addressed when the beam is scanning thc 1 116232n ` ` .

eighth line of characters. To prevent tl-is, the data corres-pond~ng to the first line of each character is moved in memory ~or lhis frame. The first line of one character is moved up and becomes the bottom line of the character directly above it.
When 010 is added, the process is again repeate~. For example, the third line of each character is first displayed in each character space and the second line of each character is moved up to become the bottom line of the character directly above it.
This process is repeated to scroll the data. The movement of data in memory is controlled by the CPU in a well-known manner.

Thus, through-use of adder 121, an even, continuous scroll is obtained without moving all the data in memory for each fr~me.
I~ather, only 1/8th of the data is moved for each frame. _ - Referring now to Figure 5, the circuitry used to extend the addressing from the CPU is illustrated. In general, the CAS
signals are generated by the ROMs 127 and 128. The RAS signals are genexated by the RO~I 132. The ~ultiplexer 130 allows the-selection of either the bank switching signals, or the unique indirect addressing mode when bank switching"occurs without direct commands from the CPU.

The CAS ROM 127 receives as an address the following sic3r.als:
PRAS ,~3, PRAS 1,2, AY, DHIR~S, R/~, All, A13~ A14~ and A15.
As the PRAS~, 3 and PRAS 1, 2 represent the R~S signals being used. These slgnals are high when the respective R~S signal is active.

~! 1 1 6 2 3 2 n ~! As previously mentioned, the ~Y si~nal is high fo~ display m~des ,l and ~he D~IIRES signal is high for high resolution display modes.
The CRS I~OM 128 receives as address si~nals the AnKl, ABK2, and ~i A~K3 signals and also DI~IRES, ~Y, IND, ~11~ ~13~ ~14~ a~ld A15.
.i .

' The ROMS 127 and 128 are programmed to implement the l following equations.
i, ' ' (1) . PCASO = (PR~SO, 3 (DHIRES AY + AY (A15 A14 ~

~i A13 A-II R/WN + A-r~ A14 A13 ' R/WN + A15 A14 ~,¦ A13 + A15 ~ A14 A13 ~ Pll))) ~ll (2) 1I PCAS2 = (DHII~S AY ~ AY . (ABKI A~ ABK~ IND +

ABKl ' ABK2 ABK3) (AI5 A14) + AY IND ~ ABK~
. ~BK2 ~.AB~3 ~ A~ (~I~ ' A13 + A14 ~ A~
,', ...' . , '.

I (3) 'I PCAS3 = PRASO, 3 ~ (D~IIR~S ~ AY + AY ~ (A15 ~ A-r4 ' A13 ,1 A11 + A15 ~ A14 ~ A-~ ' A~ + A15 ~ A14 ~ A13)1) ,I (4) ,~ PCAS4,6 = (AY'IND .- ABK3 ~ A15 ' (ABKl'-ABK~ + ABKl) ' ABK2) ~ A14 A13 + A14 A~) + AY IND ABK~
;1 ABKl A15 + ABK2 ABKl + ABK2 A~ A15~ A14 +
AY IND ABKl ABK2 ABK~ Al~ ' A13 -~ A15 .i ~ A-~ ~ A13~ + AY IN~ ABK3 ' ABK2 ¦A15 ABKl ~ A15 -,¦ ABKl) (A14 A~ + A14 A13)) . -25-.l `' ` 116232n J

'll (5) ~I PCAS5, 7, - (AY~ IND ~ ABK3 ~ (ABKl ~ A~ + ABKl -;1 ABK2) ' (A~ A14 ~ A13 ~ A15 ~ A14 ~ A13) ~ AY ~ IND
,~ ABX3 ' (AB~g~ ABKl A15 ~ ~ ABKl + ABK2 A-~r ',, . A15) A14 ~ AY ~ IND ABKl ABK2 ABK3 (A-1~ -.1 A14) + AY IND ABK3 ARK2 (A15 ABKl + A15 A~ (A-I~ ' A13 + ~14 A13)) I
In effect, these ROMs are programmed to allow selection of pre-I determined rows in the memory, based on the address signals Alo~ A13, A14 and A15 (ignoring for a moment the contribution of ¦ the PAS signals and the other signals appearing in the equations).
I .
. ~he outputs of the CAS ROMs 127 and 128 are coupled to the . ~ register 131. Register 131 is a commercially available re~ister Il which permits the enabliny of output signals (Part No. 374).
I During accessing o the memory the various CAS signals (CAS 0 ',¦ through CAS ~) are coupled to the memory of Figure 6 to permit ¦ selection of the appropriate memory devices. The signal USELB
¦ from CAS ROM 127 through register 131 selects either the A bus ~ or B bus. This signal is coupled to the multiplexers 43a and ~ 43b of Figure 3.
~I . .

'~ During normal operation, the multiplexer 130 selects the ! bank switchiny signals BCKSW 1 through ~CKSW 4. These four ~; signals (or alternatively four signals from the A bus) provide l¦ four of the inputs (address signals~ to the ROM 132. The other ¦11 inpu-ts to this ROM are the Dl'IRES, Z PAG~, PA8, PA15, RFSH
¦, (refresh)., and AY signals. These address signals select the 1i, , , 1 .
, . .

`` ' 1 16232n ~ '' `I
¦ R~S O, 3; R~S 1, 2; ~AS 4, 5 and RAS 6, 7 signals. The ROM
132 is proc3rammed to implement the fol].owing four equations.

' PRAS0, 3 = ~Y ' (Dl:IIP~S + RFSI~) + (ABK4' (Z P~ge ~ P~) i . ) ~ ABKl ABK2 ~BK3) AY . ~6) , . .~
j PRASl, 2 = AY (DHIRES ~ RFSI~) + AY ~ Kl ~ ~BK2 -ABK3 ~ (ABK4~ (ZP~GF.~ P~8) ~ ) ~ ABKl ' ABK2 ABK3) AY ~BK3 (A~ A~K2 ~ ABK4 ~ (ZPAGI~PA-~
PA15 + ~BKl ABK2 (A~K4 (ZP~GE PA8) P~ ) (7) 11 PR~S4, 5 RE'SH ~Y + ~ ~BK3 (A~
10 ll ABK4 (ZPAGE ~ P~) PA15 + ABKl (ABK4 (ZPAGE ~ (8) ll ' P~) ' ~) l , ,.
PR~S6, 7 = RFSH ~ AY ~ AY A~ ABXl ABK2 ABK4 ¦ (Z~GE P~8)- PA15 + ABKl ABK2 (ABX4 (ZPAGE ~
. ~ ~) P~) Thus, the bank switching signals (along with the other input signals to ROM 132) select predetermined ro~7s in memory in conjunction with the CAS signals.
. . ~ ' . .
¦ The output signals of the ROM 132 are coup~ed through the N~ D g tes 192, 14 3, 1-~ ancl 14 5 to the rnemory . rhe oth-r input --2 7-- :
., "~ 1 16232Q ~ j , terminals of these gates receive the R~S timing signal. In this' i manner, the outpu~ signals of the ROM 132 are clocked thrQugh i the ga~es 142 through 145 to provide the R~S signals shown in ,~ Figures 5 and 6.

1 An lmportant feature to the presently described computer is 5 il provided by the circuitry shown within the dotted line 146. The ¦ AND gate 148 receives, at its input terminals, the DA7, A12, and ~! C3 signals. The NOR gate 149 receives the zero page and A15 i; signal. The'output of gate 149 provides one input to the gate !¦ 148 and also one input to the AND gate 150. The output o gate 10 Ij,148 provides another input signal to gate 150 and this signal 1l ~line 153) is one of the two control signals coupled to the il multiplexex 130. The ~ND gates 150 and 151 also receive a SYNC
'¦ siynal and the ~0 signal. The output,of the ga~es 150 and 151 ~ are coup1ed to a NOR gate 152 with the output of the gate 152 15 13 (line 154) coupled to the other control terminal of the multi-!¦ plexer 130.
.1 , ' ' .
The gates lS0, 151 and 152 effectively form a clock for ~1 ~ multiplexer/register 130 (multiplexer 130 is a commercial part, ' Part No. 39~, which effectively is a register/multiplexer). This ¦ selects the lower four input lines to the multiplexer 130.
¦ However, because of the synchronization signal applied to gate 151 the multiplexer 130 selects the bank switching signals each ¦ time an OP code is fetched by the CPU.
.. 'I . . :
!l .
'I -28- 1 `11 !
` ~ 16232(~ "
' 'l~o unclers~and tllc opc~r(l~:ioll oE ~lle circuit ~ owll wi~llin the dotted line 146 it should be recalled that thc memory o~
Figure G providcs a lG-bit output. ~s men~ionecl, during certain display modes, 16-bi.ts/msec. are needed ~or display ~urposes.
In nondisplay modes, only 8-bits are recluired, particularly for i.nteraction with the CPU. When the memory is addressed b~
the CPU during the indirect addressing modes the data on the A bus is not ordinarily used. ~owever, with the circuitry sho~n within the dotted line 146, this other~ise "unused" data is put to use to provide the e~uivalent of the bank switchin~ sig~,als through multiplexer 130.
, ,' Whenever the,CP~ selects a predeterm~ned range of addresses, th~ ~.ultiplexer 130 selects the cquivalellt of the bank switchirg signals from the ~. bus pr~vided DA7 is high. (This occurs when lS addressing as zero paye the address space -1800 through lFIF.) Once the signal on line 153 is hi~h it is latched through ga~es 150, lSl and 152 causing the multiplexer 130 to select the four bits from the A bus (assuminy the timing signals are high~.
Even if the next reference from the CPU is not to this special address range, the multiplexer 130 nonetheless remains latched with the four bits from the data bus. Qnce the ~YN pu]se drops, however, which is an indication that an ~P code is bei fetched, th~ sIgnal on line 154 ri.ses in potential, causing the multiplexer to switch back to the ~ank switching signals.

116232n ~

E~fectively, wha~ occurs is that when the CPU selects this special address xanc~e, (and provided D~7 is hic~h) the bits D~0 throuyh DA3 which are stored in memory, cause a remapping, that is, the address from the CPU accesses a different part of the memory. With the fetching of each OP code, the mapping automatically returns to the bank switching signals. Importantly, the remapping, which occurs is controlled by the bits stored in the RAM ~DA~through D~3). Thus, with the remapping information stored in-RAM, toggling can occur between different portions of the memory without requiring bank switching signals, or the li~e from the CPU. This enhances the CPU's pexformance since CPU
time is not used for remapping. Additionally, it provides an easy to~1 for programmi.n~ . I

For some program languages it is desirable to separate data and the program into separate portions of the memory. For . example, the 128K memory can be divided into two 64K memories, one for program and one for data. ~witching can occur between these memory portions without the generation of bank switching signals by the CPU with the above described circuit. This arrangement is particularly useful when using the Pascal program languac3e.

Il 116232n ` `

DISPLAY s~sysTl~r~

The display subsystcm 48 of ~igure 1 receivcs data from the ~ bus and B bus and converts the data into video si~nals which may be used for displaying a]pha-numeric characters or other images on a standard raster scanned cathode ray tube display. The display subsystem 48 specifically gellerates on line 197, a standard NTSC color video signal and a video black and white video signal on line 198 (Figure 8). This display subsystem, in addition to other inputs, receives ~ synchroniza-tion signal, and several clocking si~nals. For sake of simpli--city, the standar~ color reference signal of 3.579545M~z is ~hown as C3.5M. Twice this ~requency an~ four times this ~requerlcy are s~ as C7 M and C14M, respectively.
,,, _ , Before describing the details of the display subsystem 48, a discussion of a prior art display system will he helpful ¦ in understanding the present display subsystem. In U.S. Patent No. 4,136,359, ~ video display system is described which is implemented in a commercially available computer, A?ple-II, sold by Apple Computer, Inc., of Cupertino, California. In this system, 4-bit digital words are shifted in parallel into a shift register. These words are then circulated in the shi~t register ¦ at 14MHz to define a waveform having components at 3.5MHz.
¦ Referring to Figure 9, line 206, assume that the digital word ¦ 0001 is placed in the shift register and circulated at a rate of ¦ 14~H% . The resultant signal which has a component of 3.5M~IZ is Il 116232n `

¦~ s wn on line 206. The phase relationship of this component to the 3.5M~z reference signal determines the color of the resultant video si~nal. This relationship is changed by chan~ing the 4-bit word placed in the shift register. As ex~lained in the above-referenced patent, if the signal 1000 is placed in the register and circulated, the resultant phase relationship of the 3.5M~z component results in the color brown, this signal is shown on line 208. With this prior art technique, the luminance was determined by the DC component of the signals such as shown on lines 206 and 208.
.
The display subsystem 48 of Figure 1 also uses 4-bit ~iords to generate the various color si~nals in a manner somewhat simi~
lar to the above-described system. Referring to Figure 8~, 4-bit words representative of colors (16 possible colors) are coupled to the bus 180. (The generation of these words shall be described in detail in conjunction with Figure 7.) Instead o~
using a shift register which circulates the 4-bit word, the same result is achieved by using a multiplexer 205 which sequentially selects each of the lines of the bus 180. The signals on bus 180 also provide a luminance signal and a black and white video signal with a gray scale.
.
The 4 lines of the bus 180 are coupled to multiplexer 205; this multiplexer also receives the C7~ and the C3.5~1 timing signals. These two timing signa]s cause each o~ the four lines --I I 16232(-.

to be scquelltially sclected and coupled to line 191. (Notc that the order in which each of the lines of the bus 180 is s~ cted does not changc.) In effect, the multiplexer operates to serialize the parallel signal from bus 180. Assume for sake of e~planation that the digital signals on bus 180 are 1000 as indicated in - Figure 8. The signal on line 191 will then be 10001000 The output of the multiplexer 205 coupled to the input of the inverter 204 also receives in a sequential order, the signals from bus 180, however, in a different order. For the example shown, the input to inverter 20~ is 00100010 ... . After inversion, this results in the signal 110],11~. ... on line 192.
Efectively, the signals on lines 191 and 192 are added ~y , resistors 199 and 200. The resultant waveform .is an AC si~nal -(no DC component) shown in Figure 9 on line 209. Thus, with the described circuit, a chroma si.gnal is generated, having a predetermined phase relationship to the 3.5MH~ color reference . signal. This phase relationship ~,hich is varied by changin~
¦ the s.~gnals on bus 180 determines the color of the video ~ signal on line 197.
.
In the prior art display discussed above, the DC component, ¦ of the color signal determines the luminance. In the pres~nt ¦ inventi,on, the si.gnals on bus 180 are coupled to the base of ¦ transistor 195, COIlSiStS o~ an AC signal ~rom resistors 199 and .
¦ 200, and ~he luminance leve], also determ,ined by the signals on~

11 116232n `: ¦
.
bus 180. These inputs to transistor 195, alon~ with the C3. SM signal, ~ent-~rate a ~T~C color signal on line 197 of improved quality when compared to the discussed prior art system.

In some cases, the signals on bus 180 are all binary ones or all binary zeros. When this occurs, there is no AC component from resistors 199 and 200 (no color si~nal) and the resultant signal on line 197 is either "black" or "white".
..
The lines of bus 180 are also coupled through resistors , , to the base of a transistor 196. Each of these resistors have J,0 a different value to provide a "weighting" to the binary signal.
This weighting is used for non-color displays to provide "gray"
shades as opposed to having a display with only black and white.
, The binary signals on bus 180 drive the transistor 196 to ,,provide a video signal on line 198. RGB is generated with , wei~hte~d sums of these same five signals.
Referring now to Figure 7, data from memoxy is coupled from the A bus and B bus to registers 159 and 158, respectively.
These ret~isters are clocked by the 1 M}lz clocking si~nal and its ,complement, thus permitting the~ sequential transfer of 8-bit words every 0.5msec. As will be described, in some displa~
modes the data is transferred at the 2~lHz rage, and in other ~ display modes, at a lMHz rat,e.
1, .

The registers lS8 and 159 are coupled to an 8 line display bus 160. This disl~lay bus transfers data to registers 164 and , -34-. ll, . .
1 16232n ¦ 173, an~ al~o addresses eo a memory 162. Tlle registers 164 and 173 an~ memory 162 arc enabled during specific display modes as will be apparen~.
..
The character memory 162, in the presently pr~ferred cmbodiment, is a random-access memory which stores patterns representative of alpha-numeric characters. ~ach time the -computer is powered up, the charac~er information is transferred from the ROM 50 into tile character memory 162 during an initialization period. During character display modes, the signals from the display bus 160 are addresses, identifying particular alpha-numeric characters stored within the character memory 160, The vertical counter signals VA, VB, and Vc (previously discu.ssed in conjunction wi~h adder 121 of Pi~ure 4 identiy the particular line in each character which is to be displayed. Thus, the generation of the digital signals repre-sentative of each of the characters occurs in an ordinary manner.
The 7-bit signal representative of each line of each character (memory output) is coupled to the shift register 167. Through timing signals not sho~n, either the re~ister 164 or the character memory 162 is selected to allow the shi`ft register 167 to receive either data directly from the A bus or B bus, or alpha-rumeric character information rom the memory 162.
' , . . , ':

11623211 ) The 7-bits of information from either memory 162 or -rec~ister 164 are serialized by the shift register 167 either at a 7~ Z rate or 14M~z rate, depending upon the display mode.
The serialized data is coupled by line 185 to the multiplexer 169, pins 1 and 4. The inverse of this data is also coupled to muitiplexer 169, pin 3. Line 185 is also coupled as one input to the multiplexer 166 and to the register 170 (input 1).

The output 1 of regist~r 170 (line 186) is coupled to the multiplexer 169, pin ~ to register 170 (input 2); and to multi-plexer 166. Output 2 of register 170 (line 187~ is coupled to input 3 of register 170 and also to multiplexer 166. Output 3 of reyister 170 (line 187) provid~s a third input to the multiplexer 166. Input 4 of the register 170 receives the output of thc multiplexer 169 (llne 189). Output 4 of register 120 (line l90)provides one control signal for the multiplexer 171.
, The multiplexer 171 selects either the four lines of bus 183 or the four lines of bus 18~. The output of multiplexer 171, bus 180, provides the 4-bit signal discussed in conjunction ¦ with Figure 8. During one of the hi.gh resolution display modes (AXIRES), the multiplexer 171 is controlled by a timing signal from the output of the gate 178.

The multiplexer 166 selects either the lines of bus 181 or bus 182. The output of this multiplexer provides the sianals for the bus 184. In all but the A~IRES display mode, multipl~xer ... 11 i 1`
116232n `
I

166 selects bus 181. Thus, typically, the multiplexer 171 rec~ives the signals from bus 174.
, For purposes of description above, and also for purposes of explaining ~or some of the display modes below a simplifyin~
assumption has been made. The signals cou~led to the bus 180 by multiplexer 171, for ~ost modes, are controlled by tile serialized signal on line 190. This serialized signal is in sychronization ~ith the C7M or C14M cloc~ing si~nals. The multiplexer 205 of Figure 8, which as described above, does the "spinning" for the parallel digital signal on bus 180, operates in sychronization with the multiplexer 171. In the de~cription above, and except when othcrwise not~d below, it is assumed that, by way of example, if the multiplexer 171 is coupling all binary ones and zeros onto ~us 180, the signal on line 191 will be either ones or ~eros. Also for this condition the signal on line 192 will be all binary zeros or ones,and thus, no AC signal is generated at the base of transistor 195. However, as actually implemented, there is a "phase" difference be-tween the clocking of the mu~iplexer 171 when compared to tlle sampling of the signals from bus 180 by the multiplexer 2~5.
This results in a first constant PC signal on the gate of transistor 195 even when it appears that all binary ones are on bus 180, and a second constant ~C signal when all binary zeros are on the bus 180. Thus, in this specification, when it states ~5 that "black" or "white" signals are being ~enerated inste~, .

` ~ ~
116232n as currently implcmcn~ed, two constant colors are qenerated on a color display. Where a true black and white is desired, color suppression is introduced such as through the color burst signal.

The circuit of Figure 7, along with the circuit of Figure 8, provides the capability for several distinct display modes.
The first of these modes provides a display consisting of 40 characters (or spaces) per horizontal line. This requires a data rate of 8-bits/MHz or half the data rate the memory is-capable of delivering. In this mode, dat~ is loaded rom the A bus during every other O.S~sec period. (B bus is not used during this mode.) Thi~ data addresses the character memory 162, and along ~1ith thé signals VA, VB and Vc, provides the appropriate character line (7-bits) to the shift register 167.
Du~ing this mode, registers 164 and 173 are disabled. ~he shift register 167 for this mode shifts the data at a data rate of 7MHz ~note CH80 is high, allowing the 7MJ~z signal from gate 175 to control the shift register 167). Each 7-bit signal is shifte~
serially onto line 185 and then to line 189`since multiplexer 169 selects pin 4. The data is shifted through the register 170 onto line 190. The serial binar~ signal on line 190 causes the selection of buses 183 or 184.
~. .
: . ~he four lines of bus 183 during this mode are coupled to ~V (register 173 is disabled); thereore the selection of ~us 184 provides four binary ones. The selection of bus 184 provides :`

6~32n ~our binary zero~ throuc31l bus 181. Thus, the serial binary si~nal on line 190 provides either all binary ones or all binary zeros to bus 1~0. ~s discussed, the circuit of Figure 8 ~7ill provide a black and white display with 40 characters per line S If the inverse and flashing timing means 172 is selected, each time the shift register 167 is loaded, multiplexer 169 shifts between pins 3 and 4. This causes the characters to change from ~hite characters on a black background to black characters on a white background, and so on.

¦ During the 80 character per line clisplay mode, the regist~rs ¦158 and 159 are each loaded duriny scquential 0.5)1sec periods ¦~this utilizes the 2MHz cycle rate previously discussed). The ~shift register 167 shifts the charactex data from memory 162 at la 14I~Hz rate. The serialized data at the 14~1JTz ratc is shifted ¦throu~h the register 170 and again controls the multiple~er 171 las previously described. tNote that regis~er 170 is ~lways ¦clocked at the 14M~z rate.) Flashin~ again can be obtained as ¦previously discussed.
' I''' ¦ In another alpha-nur.leric character display mode, the ~Q. background of each character may be in one color and the character itself (foreground) in another color. This mode provides 40 characters per line. The character iden~ification (address for R~M 162), is furnished on the ~ bus to registcr 159 at a frequency of lM~z. The color informa~ion (ba_kground coior .. .

6232n . ~and foreground color) is furnished on the B bus as two 4-bit ¦words to register 158. In the manner previousIy descr.ibed, the ¦addre~s from recJister 159 selects the appropriate character ¦from memory 162 and provides this information to shift register ' ¦167. Irhe color.information from the B bus is transferred to ¦register 173. For purposes of explanation, assume that the ' .
¦4-bits identifying the color red ~or the background are on ¦bus 184 (from registex 173 and multiplexer 166) and that 4-bits ¦representing the color blue for the foreground are on bus 183.
(Note that when register 173 is enabled, the signals from the register overrlde the binary ones and zeros which otherwise appear on the lines of bus 174.) The serial binary signal repres~ntative o the charact,er itself on line 190, selects either'the color blue from bus 183 for the character itself or the .l5 color red from bus 184 for the background. The digital signals . representative of these colors are transferred to bus 180 and provide the color data to the circuit of Figure 8. For black and white displays, a "gray" scale is provided through the . weighting circuit associated with transistor 196 of Figure 8.
Again, the multiplexer 169 may, through the timing means 172, ¦alternate between the signal of line 185 and its inverse, which ¦will have the effect of interchanging the foreground and ¦background colors.
I
.

1 16232n During the hi~h resolution c~raphics mo~es, thc character memory 162 is not used, but rather, data from the memory dir~c~ly provides pattern information for display. This requires more mapping of data from within the main memory since new data is required for each line of the display. (Note that when charac~ers are displayed, the character memory 162 provides the different signals required for the 8 lines of each character row.) Dùring these high resolution modes, the register 164 is enabled and the character memory 162 is disabled. rrhus, the data from thc ~-bus lQ and B bus is shi~ted into the shift register 167. In these modes, the 'IHR~S" signal to multiplexer 169 causes this multi-pl~xer to select between pins 1 and 2. Pin 2 provides the signal directly ~xom the shift register 167 while the siynal on pin 1 is e~fectively the signal on line 185 delayed by o~e lS period of the C14M signal. This de]ay occurs through the register 170 from input 2 to output 2 since register 170 is clocked at C14M.

During a first graphics mode, data from the display bus 16 is loaded into shift register 167 at l:he rate of 7-bits/MHz.
¦ The data is serialized on line 185 and in the m~nn~r previously described for-displaying characters, controls the selection o . . all binary ones and all binary zeros through the multiplexcr 171. ¦
Note, as mentioned before, in the presently preferred embodiment, ~ unless color suppression is used, this will not result in a ~ Iblack an hite display, but rather a two-color display. I_ a . -~
-, , I

116~32n ' ¦

high ~it is present on line 140 of the display bus, the inverse and ~lashing timing means 172 causes the multiplexer 169 to I altcrnate between pins 1 and 2. This switching occurs at a ¦ l~Hz rate and provides a phase shift for every other 7-bits of ¦ data coupled to the multiplexer 171 on line 190. This results in an additional color being generated on the display for every other 7 bits of data.

For the above-described graphics modes when shift register 161 is shifting at a 7MI~z rate, 8 bits may be coupled to the bus 160 during each period. Specifically, as in the case of the differing background and foreground colors for the 40 character per line display mode, two 4-bit color ~70rds are shifted into register 173 at a rate of lM~I~. Then, the multiplexer 171 ~elects bctween two predetermined colors on buses 183 and 184.
~ote these colors can be changed at a l~l~lz rate.

~n an additional color mode identified as "A~ S", multi-plexer 171 operates under the control o gates 176, 177 and 178.
In effect, multiplexer 171 selects bus 184 and latches the signals on this bus every four cycles of the C14M clock. Dat~
is shifted into the shift register 167 from the A bus and B bus every 0.5~ sec the register 167 operates under the control of the C14M signal. Each data bit on line 185 is shifted first to line 186, then to line 187 and finally to line 188. These lines are coupled to the multiplexer 171 through multiplexer 166 ~7hich selects bus 182 since AHIRES is hi~h. In effect, what 1 16232n -I
! occurs is that ~-bit color words are serialized onto line 185 ¦ and then brought back into parallel on hus 182. Since multiplexer ¦ 171 latches the signals on bus 184 every four cycles of the C14M
l ,signal, a new color word is generated at a 3.5~ z rate on the ¦ bus 180. The resultant display is 140 by 192 colored blocks l wherein each block can be any one of 16 colors.
l '.
¦ In the last display mode, typically used with color suppression, data is shited into ~he shift register 167 from , ¦the display bus at the rate of 14-bits/~ z. The data is serial-¦ized onto line 185 and controls the selection of either all ¦binary ones or all zeros through m~ltiplexer 17,1. This provides ¦the highest resolution graphics display for the system.

¦ Thus, a microcomputer with video display capability has been , ~described. The computer is fabricated from commercially ¦available parts and prov1des high utilization of these parts.
¦Numerous existing programs including many of those which operate lon the Apple-II computer, may be e~.ployed in the above-described omputer.

Claims (11)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a digitally controlled, raster scanned, video display for use with a microcomputer, or the like, which display provides color images in response to chroma signals having predetermined phase relationships to a reference signal of frequency (f), a circuit for providing a digitally controlled chroma signal comprising:
digital word generation means for generating pre-determined digital signals;
serializing means coupled to said generation means for repeating said word in a serial form at a predetermined frequency so as to provide frequency components at said frequency f;
converting means, coupled to said serializing means for converting outputs from said serializing means to an AC
signal;
whereby a video chroma signal is generated.

2. The circuit defined by claim 1 including additional circuit means coupled to said digital word generation means for providing a DC luminance signal.

3. The circuit defined by claim 1 wherein said digital words are coupled to a resistive weighting network for providing a gray scale video signal.

4. The circuit defined by claim 1 wherein said digital words are 4-bit words and wherein said predetermined frequency is equal to 4f.

5. The circuit defined by claim 4 wherein said serializing means comprises a multiplexer which is controlled in synchro-nization with said frequency f.

6. The circuit defined by claim 4 wherein said converting means includes an inverter coupled to an output of said multiplexer.

7. The circuit defined by claim 6 including additional circuit means coupled to said digital word generation means for providing a DC luminance signal.

8. The circuit defined by claim 1 wherein said digital word generation means comprises:
a source of digital data for controlling said display;
a first register coupled to receive data from said source of data;
a multiplexer for selecting between two buses, the output of said multiplexer coupled to said serializing means, said buses coupled to said first register, a shift register coupled to receive data from said source of data, said shift register providing a serialized digital signal for controlling said multiplexer.

9. The circuit defined by claim 8 including a character memory for storing data representative of alpha numeric characters, said memory coupled to receive address from said source of data, the output of said memory coupled to said shift register.

10. The circuit defined by claim 9 wherein when said first register is disabled, one of said two buses is clamped to provide all binary ones, and the other of said buses provides all binary zeros.

11. The circuit defined by claim 10 wherein said shift register is controlled by a plurality of clocking signals, all of which are synchronized with said frequency f.