CA1160349A - High resolution fast diode clamped comparator - Google Patents
High resolution fast diode clamped comparatorInfo
- Publication number
- CA1160349A CA1160349A CA000366596A CA366596A CA1160349A CA 1160349 A CA1160349 A CA 1160349A CA 000366596 A CA000366596 A CA 000366596A CA 366596 A CA366596 A CA 366596A CA 1160349 A CA1160349 A CA 1160349A
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- Prior art keywords
- stage
- differential amplifier
- output
- output node
- leg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
HIGH RESOLUTION FAST DIODE CLAMPED COMPARATOR
Abstract of the Disclosure An electronic comparator circuit adapted for implemen-tation as an integrated circuit semiconductor device provides high resolution and high speed performance. The circuit com-prises a first differential amplifier with clamped diodes that allow a fast response; a source-follower stage connected to the first differential amplifier for buffering its output to enable it to be broad banded; a second differential ampli-fier driven by the source-follower stage for handling large signal swings while providing additional gain to the output;
and a third cascoded gain stage connected to said second differential amplifier to provide increased circuit gain with a rail-to-rail output.
Abstract of the Disclosure An electronic comparator circuit adapted for implemen-tation as an integrated circuit semiconductor device provides high resolution and high speed performance. The circuit com-prises a first differential amplifier with clamped diodes that allow a fast response; a source-follower stage connected to the first differential amplifier for buffering its output to enable it to be broad banded; a second differential ampli-fier driven by the source-follower stage for handling large signal swings while providing additional gain to the output;
and a third cascoded gain stage connected to said second differential amplifier to provide increased circuit gain with a rail-to-rail output.
Description
~ 3~g 5218 1 SPECIFICA~ION
3 Background of the Invention This invention relates to an improved comparator circuit 6 particularly adaptable for implementation as an integrated 7 circuit device using complementary metal-oxide-silicon (CMOS) 8 technology.
9 Comparators have long been used extensively as building 10 blocks in electronic circuits for the purpose of comparing and 11 amplifying the difference between two signal sources, as for 12 example, in analog to digital conversion circuits. Often this 13 difference between two signal sources is required to be sensed 14 at a very rapid rate. Such speed requirements became especially 15 difficult to obtain in the attempted implementation of compara-16 tor circuits as part of larger integrated circuit devices where 17 the difference in the signal values is small. Previous attempts 18 to achieve relatively high speed are described, for example, in 19 IEEE Journal of Solid State Operation Circuits, Feb. 1979, 20 pp. 38-46, and Memorandum No. UCB/ERL M7~/27 24 May 1978, 21 College of Engineering, University of California, Berkeley, CA,
3 Background of the Invention This invention relates to an improved comparator circuit 6 particularly adaptable for implementation as an integrated 7 circuit device using complementary metal-oxide-silicon (CMOS) 8 technology.
9 Comparators have long been used extensively as building 10 blocks in electronic circuits for the purpose of comparing and 11 amplifying the difference between two signal sources, as for 12 example, in analog to digital conversion circuits. Often this 13 difference between two signal sources is required to be sensed 14 at a very rapid rate. Such speed requirements became especially 15 difficult to obtain in the attempted implementation of compara-16 tor circuits as part of larger integrated circuit devices where 17 the difference in the signal values is small. Previous attempts 18 to achieve relatively high speed are described, for example, in 19 IEEE Journal of Solid State Operation Circuits, Feb. 1979, 20 pp. 38-46, and Memorandum No. UCB/ERL M7~/27 24 May 1978, 21 College of Engineering, University of California, Berkeley, CA,
2" Page 128. However, such circuits as disclosed therein require 23 a relatively large amount of integrated circuit 'Ichip'' area and 24 also large amounts of power. In providing a comparator as part 25 of a monolithic integrated circuit, such as a "codec" for use 26 in digital transmission, such e~cessive requirements for chip 27 area and power are not desirable. The present invention solves 28 this problem.
29 It is therefore one object of the present invention to 30 provide an improved comparator circuit particularly adaptable 31 for implementation as an integrated circuit device.
32 Another object of the invention is to provide a compara-33 tor which has a high resolution capability with high speed,
29 It is therefore one object of the present invention to 30 provide an improved comparator circuit particularly adaptable 31 for implementation as an integrated circuit device.
32 Another object of the invention is to provide a compara-33 tor which has a high resolution capability with high speed,
3~ (e.g., a comparator capable of resolving less than 3~ ~V in 35 less than 2 ~secs.) Still another object of the invention is to provide a 37 comparator having good common mode rejection characteristics 38 which is an important criteria for high resoluti~n systems.
r~
Another object of the invention is to provide a comparator with rela-tively low power dissipation using Class A-B drive for the output.
; A comparator according to the principles of the present invention comprises a CMOS circuit consisting of four stages. The first stage is an input preamplifier in the form of a differential amplifier which receives the two input signals to be compared. Connected to this differential amplifier is a source follower stage that provides a low impedance output which drives an-other differential amplifier. This second differential amplifier drives as connected to a level shift stage to drive another cascoded gain stage. The input preamplifier is a high gain, broad banded stage that serves to deliver, with speed, a relatively large signal to the succeeding gain stages which in turn are designed to respond rapidly to large signal stimuli. The broadbanding is achieved by the source followers which buffer the input capacitance of elements from the second differential amplifier. Diode clamping is used to force the preamplifier to remain in the saturation region to provide adequate gain during operation with a relatively small voltage differential between the ; two input signals and also a relatively fast response for the input stage.
In summary, the present invention is an electronic comparator circuit comprising: a first differential amplifier stage having a relatively high outputimpedance including: a first current source; an inverting input leg containing a load device, an inverting input transistor having an inverting input lead, and a first output node; and a noninverting input leg containing a load de-vice, a noninverting input transistor having a noninverting input lead, and a second output node; a second differential amplifier stage having a relatively high input capacitance including: a second current source, an inverting leg containing a load device and an inverting transistor having an inverting input lead; and a noninverting leg containing a load device, a noninverting transis-3~9 tor having a noninverting input lead, and a third output node; an impedance converting stage for reducing the relatively high output impedance of said first differential amplifier stage to drive the high input capacitance of said second differential amplifier stage, said impedance converting stage containing a first and a second leg, said firs~ leg of said impedance converting stage containing a fourth output node, a third current source and a transistor having its control electrode connected to said first output node of said in-verting input leg of said first differential amplifier stage, said fourth out-put node of said first leg of said impedance converting stage being connected to said noninverting input lead of said second differential amplifier stage, said second leg of said impedance converting stage containing a fifth output node, a fourth current source, and a transistor having its control electrode connected to said second output node of said noninverting input leg of said first differential amplifier stage, said fifth output node of said second leg of said impedance converting stage being connected to said inverting input lead of said second differential amplifier stage; a level shift stage having an input lead connected to said third output node of said second differential amplifier stage, and having a sixth output node; and an output stage including a first output transistor having its control electrode connected to said third output node of said second differential amplifier stage, a second output transistor having its control electrode connected to said sixth output node of said level shift stage, a third output transistor having its control elec-trode connected to a voltage source, and a seventh output node.
~ith reference to the drawing, a circuit diagram is sho~n for a com-parator 10 embodying principles of the present invention which are particu-larly adapted for implementation as part of a monolithic integrated circuit semiconductor device. In broad terms, the circuit comprises a first differen-3~
tial amplifier section 12 which is essentially an input preamplifier that re-ceives the two voltage inputs to be compared. Connected to the amplifier -3a-! J
633~
section 12 is a source-follower stage 14 which supplies inputs to a second dif-ferential amplifier section 16. The latter is connec~ed through a level shift network 18 to a third cascoded gain stage 20 that provides the circuit output.
All of the aforesaid circuit components may be comprised of MOSFET
elements as part of a monolithic integrated circuit structure. Thus, as shown, all circuit elements are connected between V~D and Vss power leads 22 and 24.
The first differential amplifier 12 is comprised of a constant current MOSFET
26 having its drain connected to the Vss power line 24 and its source connected to a lead 28 that also interconnects the drains of each of a pair of signal input ~OS~ETS 30 and 32. The gate of MOS~ET 30 is connected ~ia lead 34 to an input signal source to be compared, and the gate of MOSFET 32 is connected b~ a ; lead 36 to ground. The source leads o~ MOSFETS 30 and 32 are connected by a pair of leads 38 and 40 to the drain terminals of another pair of MOSFETS 42 and 44. The source terminals of each of these latter MOS~ETS 42 and 44 are connected to the VD~ power lead 22 and their gates are interconnected by a lead 46. A lead 48 from this lead 46 extends to the interconnecting lead 38 between MOSFETS 30 and 42. In two separate leads extending between leads 38 and 40 are two clamping diodes 50 and 52 which are important to the operation of the cir-cuit.
The source-follower stage 14 comprises a first pair of MOSFET de-vices 54 and 56 connected in series between the power leads 22 and 24 and a second pair of MOSFET devices 58 and 60 that are similarly connected. The gate of MOSPET 54 is connected to a junction 62 in the lead 38 of ~he first differ-ential amplifier which is also the junction for one end of the interconnecting lead from diode 50. The otber end of the lead from diode 50 is connected to a junction 64 in ~he interconnecting lead 40. This latter junction is also con-nected to the gate of the source-follower MOSFET 58. The gate of MOSFET 56 is . 4 , . ~, .~, supplied with a ~ias voltage VBB and is connected to the gate of the differen-tial amplifier MOSFET 26 whose gate in turn is also connected to source-follow-er MOSFET 60.
The source-follower MOSFETS 54 and 55 are interconnected by a lead 66 and the MOSFETS 58 and 60 are similarl~ interconnected by a lead 68. Con-nected to and extending from these leads 66 a~d 68 is a pair of leads 70 and 72 respectively, extending to the gates of a pair of MOSFETS 7~ and 76. These latter MOSFETS are the input devices for the second differential amplifier 16.
The drain leads of ~hese latter MOSFETS 74 and 76 are interconnected by a lead 78 which is connected to the source of a ~OSFET 80 whose drain is connected to the Vss power line 24. The gate of MOSFEI' 80 is colmected to the gate of the source-follower device 60 and thus to the bias voltage V~B. Connected to the sources of MOSFETS 7~ and 76 by a pair of leads 82 and 8~ respectively, are the drains of another pair of MOSFETS 86 and 88. The source leads of these latter devices 86 and 88 are connected to the V~v power line 22 and the gates of MOSFETS 86 and 88 are interconnected by a lead 90 ~hich is connec~ed by a lead 92 to a junction 9~ in the lead 82.
As described above, the second differential amplifler 16 is con-nected to a level shift network 18 comprising a pair of ~OS~ETS 96 and 98 con-nected in series between the power leads 22 and 2~. The gate of MOSFET 96 is connected to a lead 100 from an output junction 102 in the lead 84 of the sec-ond differential amplifier 16. The ga~e of ~OSFET 98 is connected to the lead 104 which is also connected to the gate of MOSPETS 26, 60 and 80 and in turn to the bias voltage VBB. The two MOSFETS g6 and 98 are interconnected by a lead 106 and an output junction 108 therein is connected to the gate of a MOSFET 110 of the cascoded gain stage 20 of the comparator 10.
The latter gain stage 20 also includes ~OSFETS 112 and 11~ which : -5-3~
are connected in series with MOSFET 110 between ~he power leads 22 and 24. The gate of ~OSFET 112 is connected to the lead 100 from the second differential amplifier 16 and the gate of MOSFET 114 is connected to ground. The MOSFETS 110 and 114 are interconnected by a lead 116~ having a junction 118 which provides the output signal from the comparator 10.
In operation, when power is supplied across the leads 22 and 24, all of the circuit elements are "on" and ready to operate. An input signal is ap-plied to the gate of input MOS~ET 34 and the gate of input MOSFET 32 is ground-ed. This causes the difference of the input signals to be amplified b~ the first differential amplifier 12, and this amplified signal i9 present at junc-tion 64. The function of the diodes 50 and 52 is to maintain or clamp node 64 within one diode voltage drop from node 62. This clamping limits the voltage excursion of node 64 and thus keeps the first differential amplifier stage 12 in the saturation region of operation longer. Thus, this first differential amplifier stage can recover faster from the linear region of operation, for ex-ample, when a large differential input signal was present on its input and the input leads 34 and 36 are then presented with small differential input signals of the opposite polarity.
The output signal appearing on nodes 62 and 64 of the differential amplifier 12 drives the source-follower MOSFETS 54, 56, 58 and 60. The source-follower 14 buffers the output signal from the first differential stage 12 from the input capacitance of the second differential stage 16. The input capaci-tance of the second differential stage 16 can be large due to Miller multipli cation of the gate drain overlap capacitance of the MOSFETS. Thus~ the source follower stage 14 serves to "broadband" the first gain stage or differential amplifier 12 providing increased circuit speed.
The output of the source follo~er stage 14 directly drives the in-. ,,;, 3~g put MOSFETS 74 and 76 of second gain stage or differential amplifier 16. This stage 16 does not require diode clamping since it is designed to handle large vol~age swings. This stage lG drives the flnal gain stage 20. The final gain stage 20 is a cascoded stage, thus reducing the input capacitance of this final stage 20 and thus increasing the band~idth o~ the comparator lO.
The cascode stage 20 comprises ~OSFETS 112, 11~, and 110. ~OSFET
114 limits the signal swing and thus the gain on the node between ~OS~ETS 112 and 114. This reduces the input capasitance of this gain stage. The ~OSFETS
96 and 98 are connected between the second and third gain stages so that power is conserved by causing the ~hird ga~n stage-~OS~ETS 110 and 112 to operate in Class A-B mode ~i.e., when 110 tends to turn on, 112 tends to turn off and vice versa.~
[n summary, it is seen that the comparator circuit 10 operates to receive and compare relatively small signals which are amplified by stages which allow relatively large input signal swings. Thu~j the circuit has a wide range of performance that can be applied to a variety of uses; and it also com-prises relatively few components that can be compactly arranged in an integrated circuit semiconductor device.
In one embodiment of the comparator according to this invention an overall gain of 125 dB was achieved with 25 M~lz unit gain bandwidth. Compared with prior art comparator circuits, this is a relativel~ high gain for a large bandwidth.
To those skilled in the art to which this invention relates, many changes in construction and widely differing embodiments and applications of the invention will suggest themselves without departing from ~he spirit and scope of the invention. The disclosures and the description herein are purely illustrative and are not intended to be in any sense llmitlng.
r~
Another object of the invention is to provide a comparator with rela-tively low power dissipation using Class A-B drive for the output.
; A comparator according to the principles of the present invention comprises a CMOS circuit consisting of four stages. The first stage is an input preamplifier in the form of a differential amplifier which receives the two input signals to be compared. Connected to this differential amplifier is a source follower stage that provides a low impedance output which drives an-other differential amplifier. This second differential amplifier drives as connected to a level shift stage to drive another cascoded gain stage. The input preamplifier is a high gain, broad banded stage that serves to deliver, with speed, a relatively large signal to the succeeding gain stages which in turn are designed to respond rapidly to large signal stimuli. The broadbanding is achieved by the source followers which buffer the input capacitance of elements from the second differential amplifier. Diode clamping is used to force the preamplifier to remain in the saturation region to provide adequate gain during operation with a relatively small voltage differential between the ; two input signals and also a relatively fast response for the input stage.
In summary, the present invention is an electronic comparator circuit comprising: a first differential amplifier stage having a relatively high outputimpedance including: a first current source; an inverting input leg containing a load device, an inverting input transistor having an inverting input lead, and a first output node; and a noninverting input leg containing a load de-vice, a noninverting input transistor having a noninverting input lead, and a second output node; a second differential amplifier stage having a relatively high input capacitance including: a second current source, an inverting leg containing a load device and an inverting transistor having an inverting input lead; and a noninverting leg containing a load device, a noninverting transis-3~9 tor having a noninverting input lead, and a third output node; an impedance converting stage for reducing the relatively high output impedance of said first differential amplifier stage to drive the high input capacitance of said second differential amplifier stage, said impedance converting stage containing a first and a second leg, said firs~ leg of said impedance converting stage containing a fourth output node, a third current source and a transistor having its control electrode connected to said first output node of said in-verting input leg of said first differential amplifier stage, said fourth out-put node of said first leg of said impedance converting stage being connected to said noninverting input lead of said second differential amplifier stage, said second leg of said impedance converting stage containing a fifth output node, a fourth current source, and a transistor having its control electrode connected to said second output node of said noninverting input leg of said first differential amplifier stage, said fifth output node of said second leg of said impedance converting stage being connected to said inverting input lead of said second differential amplifier stage; a level shift stage having an input lead connected to said third output node of said second differential amplifier stage, and having a sixth output node; and an output stage including a first output transistor having its control electrode connected to said third output node of said second differential amplifier stage, a second output transistor having its control electrode connected to said sixth output node of said level shift stage, a third output transistor having its control elec-trode connected to a voltage source, and a seventh output node.
~ith reference to the drawing, a circuit diagram is sho~n for a com-parator 10 embodying principles of the present invention which are particu-larly adapted for implementation as part of a monolithic integrated circuit semiconductor device. In broad terms, the circuit comprises a first differen-3~
tial amplifier section 12 which is essentially an input preamplifier that re-ceives the two voltage inputs to be compared. Connected to the amplifier -3a-! J
633~
section 12 is a source-follower stage 14 which supplies inputs to a second dif-ferential amplifier section 16. The latter is connec~ed through a level shift network 18 to a third cascoded gain stage 20 that provides the circuit output.
All of the aforesaid circuit components may be comprised of MOSFET
elements as part of a monolithic integrated circuit structure. Thus, as shown, all circuit elements are connected between V~D and Vss power leads 22 and 24.
The first differential amplifier 12 is comprised of a constant current MOSFET
26 having its drain connected to the Vss power line 24 and its source connected to a lead 28 that also interconnects the drains of each of a pair of signal input ~OS~ETS 30 and 32. The gate of MOS~ET 30 is connected ~ia lead 34 to an input signal source to be compared, and the gate of MOSFET 32 is connected b~ a ; lead 36 to ground. The source leads o~ MOSFETS 30 and 32 are connected by a pair of leads 38 and 40 to the drain terminals of another pair of MOSFETS 42 and 44. The source terminals of each of these latter MOS~ETS 42 and 44 are connected to the VD~ power lead 22 and their gates are interconnected by a lead 46. A lead 48 from this lead 46 extends to the interconnecting lead 38 between MOSFETS 30 and 42. In two separate leads extending between leads 38 and 40 are two clamping diodes 50 and 52 which are important to the operation of the cir-cuit.
The source-follower stage 14 comprises a first pair of MOSFET de-vices 54 and 56 connected in series between the power leads 22 and 24 and a second pair of MOSFET devices 58 and 60 that are similarly connected. The gate of MOSPET 54 is connected to a junction 62 in the lead 38 of ~he first differ-ential amplifier which is also the junction for one end of the interconnecting lead from diode 50. The otber end of the lead from diode 50 is connected to a junction 64 in ~he interconnecting lead 40. This latter junction is also con-nected to the gate of the source-follower MOSFET 58. The gate of MOSFET 56 is . 4 , . ~, .~, supplied with a ~ias voltage VBB and is connected to the gate of the differen-tial amplifier MOSFET 26 whose gate in turn is also connected to source-follow-er MOSFET 60.
The source-follower MOSFETS 54 and 55 are interconnected by a lead 66 and the MOSFETS 58 and 60 are similarl~ interconnected by a lead 68. Con-nected to and extending from these leads 66 a~d 68 is a pair of leads 70 and 72 respectively, extending to the gates of a pair of MOSFETS 7~ and 76. These latter MOSFETS are the input devices for the second differential amplifier 16.
The drain leads of ~hese latter MOSFETS 74 and 76 are interconnected by a lead 78 which is connected to the source of a ~OSFET 80 whose drain is connected to the Vss power line 24. The gate of MOSFEI' 80 is colmected to the gate of the source-follower device 60 and thus to the bias voltage V~B. Connected to the sources of MOSFETS 7~ and 76 by a pair of leads 82 and 8~ respectively, are the drains of another pair of MOSFETS 86 and 88. The source leads of these latter devices 86 and 88 are connected to the V~v power line 22 and the gates of MOSFETS 86 and 88 are interconnected by a lead 90 ~hich is connec~ed by a lead 92 to a junction 9~ in the lead 82.
As described above, the second differential amplifler 16 is con-nected to a level shift network 18 comprising a pair of ~OS~ETS 96 and 98 con-nected in series between the power leads 22 and 2~. The gate of MOSFET 96 is connected to a lead 100 from an output junction 102 in the lead 84 of the sec-ond differential amplifier 16. The ga~e of ~OSFET 98 is connected to the lead 104 which is also connected to the gate of MOSPETS 26, 60 and 80 and in turn to the bias voltage VBB. The two MOSFETS g6 and 98 are interconnected by a lead 106 and an output junction 108 therein is connected to the gate of a MOSFET 110 of the cascoded gain stage 20 of the comparator 10.
The latter gain stage 20 also includes ~OSFETS 112 and 11~ which : -5-3~
are connected in series with MOSFET 110 between ~he power leads 22 and 24. The gate of ~OSFET 112 is connected to the lead 100 from the second differential amplifier 16 and the gate of MOSFET 114 is connected to ground. The MOSFETS 110 and 114 are interconnected by a lead 116~ having a junction 118 which provides the output signal from the comparator 10.
In operation, when power is supplied across the leads 22 and 24, all of the circuit elements are "on" and ready to operate. An input signal is ap-plied to the gate of input MOS~ET 34 and the gate of input MOSFET 32 is ground-ed. This causes the difference of the input signals to be amplified b~ the first differential amplifier 12, and this amplified signal i9 present at junc-tion 64. The function of the diodes 50 and 52 is to maintain or clamp node 64 within one diode voltage drop from node 62. This clamping limits the voltage excursion of node 64 and thus keeps the first differential amplifier stage 12 in the saturation region of operation longer. Thus, this first differential amplifier stage can recover faster from the linear region of operation, for ex-ample, when a large differential input signal was present on its input and the input leads 34 and 36 are then presented with small differential input signals of the opposite polarity.
The output signal appearing on nodes 62 and 64 of the differential amplifier 12 drives the source-follower MOSFETS 54, 56, 58 and 60. The source-follower 14 buffers the output signal from the first differential stage 12 from the input capacitance of the second differential stage 16. The input capaci-tance of the second differential stage 16 can be large due to Miller multipli cation of the gate drain overlap capacitance of the MOSFETS. Thus~ the source follower stage 14 serves to "broadband" the first gain stage or differential amplifier 12 providing increased circuit speed.
The output of the source follo~er stage 14 directly drives the in-. ,,;, 3~g put MOSFETS 74 and 76 of second gain stage or differential amplifier 16. This stage 16 does not require diode clamping since it is designed to handle large vol~age swings. This stage lG drives the flnal gain stage 20. The final gain stage 20 is a cascoded stage, thus reducing the input capacitance of this final stage 20 and thus increasing the band~idth o~ the comparator lO.
The cascode stage 20 comprises ~OSFETS 112, 11~, and 110. ~OSFET
114 limits the signal swing and thus the gain on the node between ~OS~ETS 112 and 114. This reduces the input capasitance of this gain stage. The ~OSFETS
96 and 98 are connected between the second and third gain stages so that power is conserved by causing the ~hird ga~n stage-~OS~ETS 110 and 112 to operate in Class A-B mode ~i.e., when 110 tends to turn on, 112 tends to turn off and vice versa.~
[n summary, it is seen that the comparator circuit 10 operates to receive and compare relatively small signals which are amplified by stages which allow relatively large input signal swings. Thu~j the circuit has a wide range of performance that can be applied to a variety of uses; and it also com-prises relatively few components that can be compactly arranged in an integrated circuit semiconductor device.
In one embodiment of the comparator according to this invention an overall gain of 125 dB was achieved with 25 M~lz unit gain bandwidth. Compared with prior art comparator circuits, this is a relativel~ high gain for a large bandwidth.
To those skilled in the art to which this invention relates, many changes in construction and widely differing embodiments and applications of the invention will suggest themselves without departing from ~he spirit and scope of the invention. The disclosures and the description herein are purely illustrative and are not intended to be in any sense llmitlng.
Claims (6)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An electronic comparator circuit comprising: a first differential amplifier stage having a relatively high output impedance including: a first current source; an inverting input leg containing a load device, an inverting input transistor having an inverting input lead, and a first output node; and a noninverting input leg containing a load device, a noninverting input tran-sistor having a noninverting input lead, and a second output node; a second differential amplifier stage having a relatively high input capacitance inclu-ding: a second current source, an inverting leg containing a load device and an inverting transistor having an inverting input lead; and a noninverting leg containing a load device, a noninverting transistor having a noninverting input lead, and a third output node; an impedance converting stage for reduc-ing the relatively high output impedance of said first differential amplifier stage to drive the high input capacitance of said second differential amplifier stage, said impedance converting stage containing a first and a second leg, said first leg of said impedance converting stage containing a fourth output node, a third current source and a transistor having its control electrode connected to said first output node of said inverting input leg of said first differential amplifier stage, said fourth output node of said first leg of said impedance converting stage being connected to said noninverting input lead of said second differential amplifier stage, said second leg of said impedance converting stage containing a fifth output node; a fourth current source, and a transistor having its control electrode connected to said second output node of said noninverting input leg of said first differential amplifier stage, said fifth output node of said second leg of said impedance converting stage being connected to said inverting input lead of said second differential amplifier stage; a level shift stage having an input lead connected to said third output node of said second differential amplifier stage, and having a sixth output node; and an output stage including a first output transistor having its control electrode connected to said third output node of said second differential amplifier stage, a second output transistor having its control electrode connected to said sixth output node of said level shift stage, a third output transistor having its control electrode connected to a voltage source, and a seventh output node.
2. Structure as in claim 1 wherein said level shift stage includes a fifth current source and a transistor having its control electrode connected to said input lead of said level shift stage.
3. Structure as in claim 1 including clamping means in said first dif-ferential amplifier stage for limiting the voltage on said first and second output nodes, thereby maintaining said first differential amplifier stage in saturation, thus increasing the speed of said first differential amplifier stage in response to large variations in input signals.
4. Structure as in claim 3 wherein said clamping means are diodes.
5. Structure as in claims 1, 2 or 3 wherein all of said transistors are MOSFET devices.
6. Structure as in claim 1 wherein one of said transistors of said out-put stage is an N channel MOSFET and the other said transistor of said output stage is a P channel MOSFET.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11160680A | 1980-01-14 | 1980-01-14 | |
| US111,606 | 1980-01-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1160349A true CA1160349A (en) | 1984-01-10 |
Family
ID=22339449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000366596A Expired CA1160349A (en) | 1980-01-14 | 1980-12-11 | High resolution fast diode clamped comparator |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS57500090A (en) |
| CA (1) | CA1160349A (en) |
| FR (1) | FR2473745A1 (en) |
| GB (1) | GB2081045A (en) |
| NL (1) | NL8020510A (en) |
| SE (1) | SE8105424L (en) |
| WO (1) | WO1981002079A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60182207A (en) * | 1984-02-29 | 1985-09-17 | Fujitsu Ltd | Differential amplifier circuit |
| US4874969A (en) * | 1988-06-08 | 1989-10-17 | National Semiconductor Corporation | High speed CMOS comparator with hysteresis |
| US4885484A (en) * | 1988-07-05 | 1989-12-05 | Motorola, Inc. | Voltage clamped differential to single ended converter circuit |
| US6320429B1 (en) | 1991-06-28 | 2001-11-20 | Fuji Electric Co., Ltd. | Integrated circuit having a comparator circuit including at least one differential amplifier |
| JPH0514073A (en) * | 1991-06-28 | 1993-01-22 | Fuji Electric Co Ltd | Differential amplifier and comparator |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5292469A (en) * | 1976-01-30 | 1977-08-03 | Hitachi Ltd | Mutual compensation type mis inverter circuit |
| US4053795A (en) * | 1976-07-06 | 1977-10-11 | Texas Instruments Incorporated | Low level field effect transistor amplifier |
| JPS5460841A (en) * | 1977-10-25 | 1979-05-16 | Fujitsu Ltd | Comparator circuit |
| JPS5937893B2 (en) * | 1978-05-23 | 1984-09-12 | 富士通株式会社 | comparison circuit |
| JPS5824874B2 (en) * | 1979-02-07 | 1983-05-24 | 富士通株式会社 | sense circuit |
-
1980
- 1980-11-24 JP JP81500736A patent/JPS57500090A/ja active Pending
- 1980-11-24 WO PCT/US1980/001569 patent/WO1981002079A1/en active Application Filing
- 1980-11-24 NL NL8020510A patent/NL8020510A/en not_active Application Discontinuation
- 1980-11-24 GB GB8127338A patent/GB2081045A/en not_active Withdrawn
- 1980-12-11 CA CA000366596A patent/CA1160349A/en not_active Expired
-
1981
- 1981-01-12 FR FR8100388A patent/FR2473745A1/en not_active Withdrawn
- 1981-09-11 SE SE8105424A patent/SE8105424L/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| WO1981002079A1 (en) | 1981-07-23 |
| JPS57500090A (en) | 1982-01-14 |
| SE8105424L (en) | 1981-09-11 |
| FR2473745A1 (en) | 1981-07-17 |
| GB2081045A (en) | 1982-02-10 |
| NL8020510A (en) | 1981-10-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |