CA1159956A - A-to-d converter of the successive-approximation type - Google Patents
A-to-d converter of the successive-approximation typeInfo
- Publication number
- CA1159956A CA1159956A CA000300605A CA300605A CA1159956A CA 1159956 A CA1159956 A CA 1159956A CA 000300605 A CA000300605 A CA 000300605A CA 300605 A CA300605 A CA 300605A CA 1159956 A CA1159956 A CA 1159956A
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- Prior art keywords
- transistors
- converter
- analog
- successive
- digital
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/42—Sequential comparisons in series-connected stages with no change in value of analogue signal
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
An integrated-circuit analog-to-digigal converter of the successive-approximation type formed on a single mono-lithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I2L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator The inverted mode tran-sistors provide an internal clock and successive-approrximatior control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.
An integrated-circuit analog-to-digigal converter of the successive-approximation type formed on a single mono-lithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I2L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator The inverted mode tran-sistors provide an internal clock and successive-approrximatior control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.
Description
` ~ ` 935.0~7 , i .
1 159956 . I
.
B~CE~GROUND OF THE INVEWTI0~7 Field of the Invention j Thi~ invention relates to analog-to-digital convèrte ~s adapted to receive an electrical analog input signal and to produce a corresponding electrical digital output signal.
More particularly, this invention relates to a successive- ¦
approximation A/D converter constructed in integrated circuit (IG) form.
10 ¦~ Description of the Prior Art ¦
¦ Analog-to-digital converters o various types have - l¦been in use for many years, typically employed for converting analog measurements and the like into corresponding digital Isignals for processing by high-speed digital computers. For lS ¦Icertain applications, there has been considerable use of - ¦¦converters incorporating electronic ramp-signal integrators ilw.ith clock-pulse timing devices for producing a digital count ~ corresponding to the magnitude of an analog signal A convert r ' llof the latter type having important advantageous features is 20 Idisclosed in U. S. Patent 3,872,466 issued to Ivar Wold on I March 18, 1975 '! - ~
,, -2- ~
j'l 935.027 ~ 11 1 1599~6 ', For other applications, there has been widespread !~ use of so-called successive-approximation conVerters. Such ¦¦converters include a digital-to-analog converter(often called la DAC) whiCh during the conversion cycle is sequenced through I
la predetermined algorithm whereby the DAC output at appropriale stages is compared with the analog input signal to determine whether a corresponding bit o~ the final digital output signa~
should be "high" or "low". The results of this determination are used to set the respective stages of the successive-approximation register (SAR). ~he nature of such operationiS in general well known, and iS described for example at Page II-81 of the "A D Conversion Handbook" published by Analog Devices, Inc, of Norwood, Mass. Still further informa-~1 tion on various converters may be found in the book "Electroni 15 Analog/Digital Conversions" by H. A. Schmid (Van ~ostrand -¦
Reinhold, 1970).
. :'',`
Among the important requirements for interface l devices such as analog-to-digital converters is that they be i small in size and economical to manufacture. Although such an objective has been suitably realized in a-to-a converters of the ramp-signal integrator type by constructing the con- ¦
verter as an integrated circuit on one or two monolithic chips;~
Ithere has been no comparable advance achieved in the developmept ¦¦o~ successive-approximation converters. In part, this has beep jldue to the difficu1ty of using conventional processing technol~gy I _3_ Il 935.027 1 1 j., l 159~56 ', ,~to place on one or two chips a complète DAC together with all !
,~of the circuitry required for the successive approximation functions for controlling the DAC and storing the results o~ ¦
jthe successive analog comparisons.
,1 .
SUMMARY OF ~HE I~VENTION
In accordance with an important aspect of the present invention, a superior IC analog-to-digital converter of the successive-approximation type is provided by diffusing the substrate in such a way as to produce a composite of norm 1 mode transistors and inverted mode transistors, i.e. I2L
(integrated injection logic) transistors for carrying out the analog-to-digital conversion operations. By such composite construction, as will be described in detail hereinbeiow, it becomes possible to place on a single relatively small mono-lithic chip all of the circuit elements needed for a completesuccessive-approximation converter. This represents a signi -ficant step forward, particularly since efforts to combine ordinary bipolar linear circuits with logic using the linear ~I parts in conventional format have produced configuratlons whic ¦~are prohibitively large. However, it has been found that in ¦accordance with the present invention the entire converter lfunction can be carried out by elements occupying only a rela-¦tively small area, and which can be manufactured using procesJes very similar to conventional dif~usion processes.
Il . .
11 ~4~-Il 935.027 115`9356 `
¦ I .
For further information on I2L processes and .
~techniques, reference may be made to "Design Considerations ! for Merged Transistor Logic (Integrated Injection Logic)"
by Horst H. Berger, pps. 14-15 of the Digest of the 1974 IEEE
! International Solid State Circuits Conference. There are numerous other publications providing additional information on this subject. . - .
Accordingly, it is an object of this invention to provide a significantly improved analog-to-digital converter of the successive-approximation type Still other objects, aspects and advantages of the invention will in part be p~inte oùt in, and in part apparent from, the following detailed description considered together with the accompanying drawings ' ,.
- BRIEF DESCRIPTION OF THE D~AWI~GS
¦ : PIGURE 1 is a schematic diagram, partly in block format, showing one embodiment of the present invention com-Iprising a complete analog-to-digital converter formed on a .
single monolithic chip;
-2G l FIGURE 2 shows diagramatically the positional rela-. Iitionsh_p for combining Figuxes 3 through 6; -1~ :
Il FIGURES 3 through 6 together present a detailed Scbematic of the embodiment of Figure 1 and 1~l 35.02 11 59g5B `
ll l FIGURE 7 shows certain details of the successive-approximation register which were omitted from Figure 4 for the sake of simplicity.
DETAILED DESCRIPTIO~ OF A PREFERRED EMBODIME~T
,1 .
1, A pxesently preferred analog-to-digital converter ¦!in accordance with this invention comprises a single substrate which is subjected to a multi-step diffusion process to form a monolithic chip having in certain regions thereof, inverted mode I2L transistors. Figure l shows this embodiment diagram-matically. In this Figure, and also in Figures 3-6, the inverted mode transistors are located in an I L "pocket"
portion o~ the substrate, indicated by a dashed-line block, and the individual transistors thereof are signified by emitters with a half-arrowhead; all of these emitters have a common connection to the logic return. The I2L injection rail R is shown as a so-labelled, filled-in arrowhead. The remaining portions of the chip comprise (with one minor excep-tion) normal-mode transistors which are therefore not speciall identified symbolically.
~1 , ` ' ' ' ` ' ll The composite chip in accordance with the invention is made by a diffusion process having only one more step than ~Ithe standard process, that o~ di~fusing a deep n~ to prevent I,cross-talk between adjacent gates in the structure. The pro-Icess produces all of the standard components in addition to 1~I2L txansistors. This can be achieved in an essentially ~jstandard process because in making the I L gate device (l) th~
~ 3S 027 Il 1 159956 normal emitter diffusion forms the I L collectors, (2) 1he bases are the same and are formed simultaneously, and ~! ' 3) the epitaxial region normally used for the collector j~ serves as the I L emitter. Since each multi-collector I2L transistor is a self-contained logic gate, the packing density can be substantially improved.
Referring now to the lower right-hand corner of Figure l, the chip includes a lO-bit current-output DAC 30 - (shown within an interrupted l~ine ~lock) and comprising a plurality of normal-mode transistor current sources 32A, 32B, etc. The currents produced ~y these sources are binarily weig~ted by means of a resistive network 34 con-nected to the emitters of the transistors. Each current source is controlled by a respective switch 36~, 36B, etc., lS ¦ comprising a differential pair of transistors arranged to divert the source current either to a digital common line 38 or to a current summing line 40, in accordance with the state of the control signals supplied to the bases of ~he differential pair switches. A DAC of the type shown herein is described in detail in U. S. Patent ~o 3,940,760, ~ issued to A. P. Brokaw on February 24, 1976.
. I . ' - .
The switc'nes 36A, etc., of the DAC 30 are Il operated by a successive-approximation control means, ¦¦ generally indicated at 42, which carries out a conventional jl successive-approximation algorithm such as is well known Il in khe art of analog-to-digital converters. During i~ ' 7 . ' . .
1'` ` 935.027 . l 159956 ` I
., . I
eYecution of this al~orithm, DAC output currents on line ~0 are compared to the analog input signal which is fed through the analog input terminaL 44 and an input resistor 46 ¦
,~to a summing point 48 which is connected to a comparator 50.
"The results of the comparison are directed ~hrough a line 52 ¦ to the successive-approximation control means 42 to determine ¦
the state of the individual bit flip-flops 54A, etc., forming part thereof~ ' In brief, the DAC 30 is controlled by the successiv~ _ approximation control means 42 in such a way that the most significant bit (MSB) source 36A irst is turned-on, and its value is compared to the input analog signal. If the analog-input is larger, the Bit 1 flip-flop 54A is set, and the MSB
current source is maintained on by the associated control circuitry. Thereafter, the next current source 32B is turned on (having half the value of-the MSB current), and another comparison is made between the analog input signal and the combined currents of the first two current sources 32A, 32B.
I If the analog input signal is greater, the Bit 2 flip-flop 1 54B is set, and the current source 32B is thereafter maintained ¦ in its on state by the associated control circuitry. If the ¦
¦lanalog input is smaller, the Bit 2 flip-flop is placed in reset state, and the current source 32B is turned off. This pro- ¦
llcedure continues in the well known manner until all current ¦
Isources have been tested and compared wi-th the analog input signal. The final state of the flip-flops 54A, etc., represen ts the digital number corresponding to the analog input si~nal These flip-flops are connect:ed to respective three-state 1 159g~6 output buffers such as buffers 56A, formed of normal mode lin-ear transistors etc., which are activated at the end of the conversion cycle so as to produce a digital output signal on the bit output terminals 58A, etc.
A conversion cycle is initiated by applying a start signal to the "Blank & Convert" terminal 60. This start sig-nal first goes high to produce the "blank" ~unction, wherein the converter circuitry is reset to an initial condition, and thereafter goes low, to begin the successive-approximation conversion sequence.
Referring now to Figure 3 a~ well as to Figure 1, in the "blank" mode with B&C high (above the threshold level at the base of Q322), current from Q320 is conveyed by Q322 to the base of Q341. This current drives Q341 on which in turn drives on Q137. (Schematically, Q137 is shown in Figure 3 as a single, multiple-collector transistor, in the`actual chip, it is composed of a number of one and two collector transis-tors which are connected in parallel so as to act like a mul-tiple-collector device responding to the drive signal from Q341. ) As Q137 comes on, it begins to steal the base drive from Q341 by way of one of its collectors returned to the Q341 base. Q341 is a normal mode transistor with relatively high ~ so that it requires only a small base current in order to ,,,~ _ g _ '' `935027 ~ I
", I 159i~6 ., .
deliver enough drive to turn on Q137. As Q137 comes on, an equilibrium is reached wherein the collector current of Q137 ~rises to equal the collector current of Q322, less only the 'small base current of Q341. Bias circuits, consisting of ~,Q139 (a current limiter), Q340, Q329 ~nd Q328 establish this jcurrent at a level which is somewhat greater than the base current of any injected transistor in the I2L array. As a result, Q137 is turned on with sufficient drive to insure that its collectors can sink the base current of any tran- 1-sistor in the array.
(Note: To simplify Figure 4, only the circuitry ¦-~or the first two and the last two bits is shown. The output ¦
buff~ers and the DAC current sources for the other six bits are identical to those shown. To complete the presentation, Figure 7 has been included to show the details of the control circuitry for the other six bits.) -.~ ' .
~¦ One collector of Q137 drives the base of Q126 and ¦Ithereby presets the condition of a clock 62 the operation of llwhich will be described hereinbelow. Referring also to Figure 0 ¦¦4, the other collectors of Q137 drive points in the successive-approximation control lo~ic 42 to establish the initial con-¦ditions of all of the bit flip-flops 54A, etc.
Il '335.027 1 1599~6 After all of the converter circuits have been , cleared to initial condition, the B&C input will be driven '' i low. This causes the current from Q320 to be diverted ~rom Q322 to Q321 which drives the base of Q125. Lacking base drive, Q341 switches off and the collector of Q125 speeds 'Ithe turn-off of Q137. When Q137 is off, its collectors ¦¦release the successive-approximation control logic and also release the clamp on Q126 in the clock to initiate a conversioin.
The internal clock 62 is a ring oscillator consisti~ g of Q123, Q124, Q126-Q129 and Q131. Since the ring has an odd number of transistors (7), it is unstable, and oscillates at a frequency determined b~ the logic signal propagation times.
.. This arrangement minimizes problems due to processing-rela.ted variations in propagation deIay slnce the clock speed changes with the inherent logic speed.
: .
¦ The main clock loop drives two functions. One .
provides the comparator latch/sense signals on lines 63, 64;
the other operates a divide-by-two flip-~lop 66 the output of llwhich drives the successive-approximation control and register .
~1,42 (hereinafter the "SAR") through its algorithm. The SAR
',ladvanceS on both rising and falling edges of the clock drive ' .
, -11- 1 ~' . I
~ 935.027 , l 159~56 `
'~' .
it receives from the flip-flop 66. As a result, the SAR runs !
j ` !
''at twice the apparent clocking frequency. The divide-by-two ¦Iflip-flop, composed of Q130, Q132-Q136 and Q342 halves the llclock frequency so that the SAR advances one step or each full cycle of the clock 62.
The I L transistors in this divide-by-two circuit make. up a D flip-flop with the ~ output tied back to the D
input. The normal mode transistor Q342 is a buffer which drives the base of Q136. Drive for Q342 is derived from the same bias circuitry 67 as the B&C control current, i. e. - .
. transistors Q139, Q340, Q329 and Q328 as shown in Figure 3. . .
The drive is controlled by Q134 and Q135 which would drive Q136 directly in a conventional D flip-flop. The buffering, supplied by Q342, is needed to drive the multiple collectors of Q136. These collectors control the clocking of thè SAR.
(As with Q137, the schematic of Figure 3 shows Q136 as a single multiple-collector device altha~ it is actually a nu ~ er of individual transistors driven b~ a common base line ).
I
!l Adeq~ate drive is insured by supplying the base of 20 ¦¦ Q342 with`somewhat more than the normal I2L gate current ¦Iderived from the in~ector rail R. When Q342 drives Q136 on, ¦ Q136 must sink more than the normal gate cur.rent before reach- . E
~ing equilib.rium with the current from Q328. As a result, Q13 I is driven hard enough that the other collectors can all sink 25 11 at least the maximum gate current.
~ 12-l 159~5~ 935.027 ."
The current from Q328 is limited, however, so that t~e ~ase voltage of Q342 can be controlled by the double-sized collectors of either Q134 or Q135. These drive transistors ~lalso have a collector driving the base of Q136 to remove ¦excess charge when Q342 switches off.
The circuit described provides a clock drive servinc all of the SAR 42,-and which alternates once each time Q131, in the main clock oscillator, switches off. Use of the D
flip-flop 66 to halve the frequency results in a lower tran-¦ sistor count than would be required to achieve the same i `
I frequency with a ring oscillator of twice the num~er of stagec ~ -IjAlso, use of frequency division allows the comparator to be latched just before each advance of the SAR. Since the SAR
,advances on both leading and trailing edges o its clock ~¦drive, the comparator must be latched (and unlatched) at jl .
Iltwice the SAR clock frequency. The comparatox is therefore ; I,operated from the-ring oscillator loop and the SAR is operate ,from the rlng oscillator frequency divided by two.
,'1 , ,l In the diffused chip, the b~ses of Q127 and Q131 are ~enlarged to partially surround their respective injector regiol.
~s a result, they have an excess of base drive, sorae of which ¦
is used to supply the base currents of Q355 and Q356 in the c ~parator 50 These last two transistors control one of the i' Il 935.027 1 1 ` 1 1599~B
`;
. . .
~main bias circuits in the comparator. When Q355 is on, curren;t "from Q372 drives the comparatox input stage and the comparator!
joperates in a linear mode. If Q356 is switched on and Q355 ~lis switched off, the current from Q372 is by-passed around the input stage and through a flip-flop circuit connected with th~
comparator, and which latches in the current state of the comparator. Since under that circumstance the input stage is disabled, subsequent changes in the comparator input signal wi 11 have no effect and the comparator output will remain latched With the information present at the switching time. The com-parator can be restored to linear, or input-sensitive opera-tion, simply by reversing the drive to the cohtrol transistor , switching Q356 off and Q355 back on again.
, ~ ' `' .
When the B&C signal goes low to "convert" and causes Q137 to release the base of Q126, an inversion begins to propagate around the ring oscillator of clock 62 . The ¦base of Q126, which was low, rises and Q126 turns on driving the base of Q127 ~o-~. When Q127 goes off, Q131 iS allowed to ~go on, and the inversion continues around the ring. With the base o~ Q127 held low and the base of Q131 high, the comparato ¦ is in the input-SenSitive mode and senses the difference between the MSB and the analog input signal~
'~ ' ~.
~ 14-~ ' 935.027 ~ ~j ',~
! When the inversion completely circles the ring, Q1~7 will be switched on and it will, in turn, switch off Q131.
IThese two base signals will cause the comparator to latch the ,~,state of its output. As Q131 goes off, two of its collectors ¦trigger the flip-flop 66 and cause it to toggle, advancing the ¦state of the S~. When the SAR advances, a new test condition is presented to the ~omparator. However, the results of the previous test will remain latched into the comparator until th appropriate switching is complete. The inversion which trigge e~
the D flip-flop 66 will continue around the ring until it reaches Q127 and Q131 again, whereupon the comparator will be xestored to the input-sensitive mode to examinethe new test condition, and the flip-flop inputs will be driven low to arm it for the next clock pulse.
. ,.
¦ Test Sequence of the Successive-ApProximation Reqister i`
The individual bit current sources 32A, etc. of the DAC 30 are controlled by the flip-flops 54A, etc., in the SAR.
Each of these flip-flops consists of a pair of transistors:
'IQ2 and Q4 for the MSB; Q12 and Q14 for the 2nd SB; Q82 and -liQ84 for bit 9, etc., and in general Qx2 and Qx4 for bit x + 1.
¦iEach of the bits is sequentially tested beginning with the MSB
and progressing to the LSB. The SAR circuitry repeats on a
1 159956 . I
.
B~CE~GROUND OF THE INVEWTI0~7 Field of the Invention j Thi~ invention relates to analog-to-digital convèrte ~s adapted to receive an electrical analog input signal and to produce a corresponding electrical digital output signal.
More particularly, this invention relates to a successive- ¦
approximation A/D converter constructed in integrated circuit (IG) form.
10 ¦~ Description of the Prior Art ¦
¦ Analog-to-digital converters o various types have - l¦been in use for many years, typically employed for converting analog measurements and the like into corresponding digital Isignals for processing by high-speed digital computers. For lS ¦Icertain applications, there has been considerable use of - ¦¦converters incorporating electronic ramp-signal integrators ilw.ith clock-pulse timing devices for producing a digital count ~ corresponding to the magnitude of an analog signal A convert r ' llof the latter type having important advantageous features is 20 Idisclosed in U. S. Patent 3,872,466 issued to Ivar Wold on I March 18, 1975 '! - ~
,, -2- ~
j'l 935.027 ~ 11 1 1599~6 ', For other applications, there has been widespread !~ use of so-called successive-approximation conVerters. Such ¦¦converters include a digital-to-analog converter(often called la DAC) whiCh during the conversion cycle is sequenced through I
la predetermined algorithm whereby the DAC output at appropriale stages is compared with the analog input signal to determine whether a corresponding bit o~ the final digital output signa~
should be "high" or "low". The results of this determination are used to set the respective stages of the successive-approximation register (SAR). ~he nature of such operationiS in general well known, and iS described for example at Page II-81 of the "A D Conversion Handbook" published by Analog Devices, Inc, of Norwood, Mass. Still further informa-~1 tion on various converters may be found in the book "Electroni 15 Analog/Digital Conversions" by H. A. Schmid (Van ~ostrand -¦
Reinhold, 1970).
. :'',`
Among the important requirements for interface l devices such as analog-to-digital converters is that they be i small in size and economical to manufacture. Although such an objective has been suitably realized in a-to-a converters of the ramp-signal integrator type by constructing the con- ¦
verter as an integrated circuit on one or two monolithic chips;~
Ithere has been no comparable advance achieved in the developmept ¦¦o~ successive-approximation converters. In part, this has beep jldue to the difficu1ty of using conventional processing technol~gy I _3_ Il 935.027 1 1 j., l 159~56 ', ,~to place on one or two chips a complète DAC together with all !
,~of the circuitry required for the successive approximation functions for controlling the DAC and storing the results o~ ¦
jthe successive analog comparisons.
,1 .
SUMMARY OF ~HE I~VENTION
In accordance with an important aspect of the present invention, a superior IC analog-to-digital converter of the successive-approximation type is provided by diffusing the substrate in such a way as to produce a composite of norm 1 mode transistors and inverted mode transistors, i.e. I2L
(integrated injection logic) transistors for carrying out the analog-to-digital conversion operations. By such composite construction, as will be described in detail hereinbeiow, it becomes possible to place on a single relatively small mono-lithic chip all of the circuit elements needed for a completesuccessive-approximation converter. This represents a signi -ficant step forward, particularly since efforts to combine ordinary bipolar linear circuits with logic using the linear ~I parts in conventional format have produced configuratlons whic ¦~are prohibitively large. However, it has been found that in ¦accordance with the present invention the entire converter lfunction can be carried out by elements occupying only a rela-¦tively small area, and which can be manufactured using procesJes very similar to conventional dif~usion processes.
Il . .
11 ~4~-Il 935.027 115`9356 `
¦ I .
For further information on I2L processes and .
~techniques, reference may be made to "Design Considerations ! for Merged Transistor Logic (Integrated Injection Logic)"
by Horst H. Berger, pps. 14-15 of the Digest of the 1974 IEEE
! International Solid State Circuits Conference. There are numerous other publications providing additional information on this subject. . - .
Accordingly, it is an object of this invention to provide a significantly improved analog-to-digital converter of the successive-approximation type Still other objects, aspects and advantages of the invention will in part be p~inte oùt in, and in part apparent from, the following detailed description considered together with the accompanying drawings ' ,.
- BRIEF DESCRIPTION OF THE D~AWI~GS
¦ : PIGURE 1 is a schematic diagram, partly in block format, showing one embodiment of the present invention com-Iprising a complete analog-to-digital converter formed on a .
single monolithic chip;
-2G l FIGURE 2 shows diagramatically the positional rela-. Iitionsh_p for combining Figuxes 3 through 6; -1~ :
Il FIGURES 3 through 6 together present a detailed Scbematic of the embodiment of Figure 1 and 1~l 35.02 11 59g5B `
ll l FIGURE 7 shows certain details of the successive-approximation register which were omitted from Figure 4 for the sake of simplicity.
DETAILED DESCRIPTIO~ OF A PREFERRED EMBODIME~T
,1 .
1, A pxesently preferred analog-to-digital converter ¦!in accordance with this invention comprises a single substrate which is subjected to a multi-step diffusion process to form a monolithic chip having in certain regions thereof, inverted mode I2L transistors. Figure l shows this embodiment diagram-matically. In this Figure, and also in Figures 3-6, the inverted mode transistors are located in an I L "pocket"
portion o~ the substrate, indicated by a dashed-line block, and the individual transistors thereof are signified by emitters with a half-arrowhead; all of these emitters have a common connection to the logic return. The I2L injection rail R is shown as a so-labelled, filled-in arrowhead. The remaining portions of the chip comprise (with one minor excep-tion) normal-mode transistors which are therefore not speciall identified symbolically.
~1 , ` ' ' ' ` ' ll The composite chip in accordance with the invention is made by a diffusion process having only one more step than ~Ithe standard process, that o~ di~fusing a deep n~ to prevent I,cross-talk between adjacent gates in the structure. The pro-Icess produces all of the standard components in addition to 1~I2L txansistors. This can be achieved in an essentially ~jstandard process because in making the I L gate device (l) th~
~ 3S 027 Il 1 159956 normal emitter diffusion forms the I L collectors, (2) 1he bases are the same and are formed simultaneously, and ~! ' 3) the epitaxial region normally used for the collector j~ serves as the I L emitter. Since each multi-collector I2L transistor is a self-contained logic gate, the packing density can be substantially improved.
Referring now to the lower right-hand corner of Figure l, the chip includes a lO-bit current-output DAC 30 - (shown within an interrupted l~ine ~lock) and comprising a plurality of normal-mode transistor current sources 32A, 32B, etc. The currents produced ~y these sources are binarily weig~ted by means of a resistive network 34 con-nected to the emitters of the transistors. Each current source is controlled by a respective switch 36~, 36B, etc., lS ¦ comprising a differential pair of transistors arranged to divert the source current either to a digital common line 38 or to a current summing line 40, in accordance with the state of the control signals supplied to the bases of ~he differential pair switches. A DAC of the type shown herein is described in detail in U. S. Patent ~o 3,940,760, ~ issued to A. P. Brokaw on February 24, 1976.
. I . ' - .
The switc'nes 36A, etc., of the DAC 30 are Il operated by a successive-approximation control means, ¦¦ generally indicated at 42, which carries out a conventional jl successive-approximation algorithm such as is well known Il in khe art of analog-to-digital converters. During i~ ' 7 . ' . .
1'` ` 935.027 . l 159956 ` I
., . I
eYecution of this al~orithm, DAC output currents on line ~0 are compared to the analog input signal which is fed through the analog input terminaL 44 and an input resistor 46 ¦
,~to a summing point 48 which is connected to a comparator 50.
"The results of the comparison are directed ~hrough a line 52 ¦ to the successive-approximation control means 42 to determine ¦
the state of the individual bit flip-flops 54A, etc., forming part thereof~ ' In brief, the DAC 30 is controlled by the successiv~ _ approximation control means 42 in such a way that the most significant bit (MSB) source 36A irst is turned-on, and its value is compared to the input analog signal. If the analog-input is larger, the Bit 1 flip-flop 54A is set, and the MSB
current source is maintained on by the associated control circuitry. Thereafter, the next current source 32B is turned on (having half the value of-the MSB current), and another comparison is made between the analog input signal and the combined currents of the first two current sources 32A, 32B.
I If the analog input signal is greater, the Bit 2 flip-flop 1 54B is set, and the current source 32B is thereafter maintained ¦ in its on state by the associated control circuitry. If the ¦
¦lanalog input is smaller, the Bit 2 flip-flop is placed in reset state, and the current source 32B is turned off. This pro- ¦
llcedure continues in the well known manner until all current ¦
Isources have been tested and compared wi-th the analog input signal. The final state of the flip-flops 54A, etc., represen ts the digital number corresponding to the analog input si~nal These flip-flops are connect:ed to respective three-state 1 159g~6 output buffers such as buffers 56A, formed of normal mode lin-ear transistors etc., which are activated at the end of the conversion cycle so as to produce a digital output signal on the bit output terminals 58A, etc.
A conversion cycle is initiated by applying a start signal to the "Blank & Convert" terminal 60. This start sig-nal first goes high to produce the "blank" ~unction, wherein the converter circuitry is reset to an initial condition, and thereafter goes low, to begin the successive-approximation conversion sequence.
Referring now to Figure 3 a~ well as to Figure 1, in the "blank" mode with B&C high (above the threshold level at the base of Q322), current from Q320 is conveyed by Q322 to the base of Q341. This current drives Q341 on which in turn drives on Q137. (Schematically, Q137 is shown in Figure 3 as a single, multiple-collector transistor, in the`actual chip, it is composed of a number of one and two collector transis-tors which are connected in parallel so as to act like a mul-tiple-collector device responding to the drive signal from Q341. ) As Q137 comes on, it begins to steal the base drive from Q341 by way of one of its collectors returned to the Q341 base. Q341 is a normal mode transistor with relatively high ~ so that it requires only a small base current in order to ,,,~ _ g _ '' `935027 ~ I
", I 159i~6 ., .
deliver enough drive to turn on Q137. As Q137 comes on, an equilibrium is reached wherein the collector current of Q137 ~rises to equal the collector current of Q322, less only the 'small base current of Q341. Bias circuits, consisting of ~,Q139 (a current limiter), Q340, Q329 ~nd Q328 establish this jcurrent at a level which is somewhat greater than the base current of any injected transistor in the I2L array. As a result, Q137 is turned on with sufficient drive to insure that its collectors can sink the base current of any tran- 1-sistor in the array.
(Note: To simplify Figure 4, only the circuitry ¦-~or the first two and the last two bits is shown. The output ¦
buff~ers and the DAC current sources for the other six bits are identical to those shown. To complete the presentation, Figure 7 has been included to show the details of the control circuitry for the other six bits.) -.~ ' .
~¦ One collector of Q137 drives the base of Q126 and ¦Ithereby presets the condition of a clock 62 the operation of llwhich will be described hereinbelow. Referring also to Figure 0 ¦¦4, the other collectors of Q137 drive points in the successive-approximation control lo~ic 42 to establish the initial con-¦ditions of all of the bit flip-flops 54A, etc.
Il '335.027 1 1599~6 After all of the converter circuits have been , cleared to initial condition, the B&C input will be driven '' i low. This causes the current from Q320 to be diverted ~rom Q322 to Q321 which drives the base of Q125. Lacking base drive, Q341 switches off and the collector of Q125 speeds 'Ithe turn-off of Q137. When Q137 is off, its collectors ¦¦release the successive-approximation control logic and also release the clamp on Q126 in the clock to initiate a conversioin.
The internal clock 62 is a ring oscillator consisti~ g of Q123, Q124, Q126-Q129 and Q131. Since the ring has an odd number of transistors (7), it is unstable, and oscillates at a frequency determined b~ the logic signal propagation times.
.. This arrangement minimizes problems due to processing-rela.ted variations in propagation deIay slnce the clock speed changes with the inherent logic speed.
: .
¦ The main clock loop drives two functions. One .
provides the comparator latch/sense signals on lines 63, 64;
the other operates a divide-by-two flip-~lop 66 the output of llwhich drives the successive-approximation control and register .
~1,42 (hereinafter the "SAR") through its algorithm. The SAR
',ladvanceS on both rising and falling edges of the clock drive ' .
, -11- 1 ~' . I
~ 935.027 , l 159~56 `
'~' .
it receives from the flip-flop 66. As a result, the SAR runs !
j ` !
''at twice the apparent clocking frequency. The divide-by-two ¦Iflip-flop, composed of Q130, Q132-Q136 and Q342 halves the llclock frequency so that the SAR advances one step or each full cycle of the clock 62.
The I L transistors in this divide-by-two circuit make. up a D flip-flop with the ~ output tied back to the D
input. The normal mode transistor Q342 is a buffer which drives the base of Q136. Drive for Q342 is derived from the same bias circuitry 67 as the B&C control current, i. e. - .
. transistors Q139, Q340, Q329 and Q328 as shown in Figure 3. . .
The drive is controlled by Q134 and Q135 which would drive Q136 directly in a conventional D flip-flop. The buffering, supplied by Q342, is needed to drive the multiple collectors of Q136. These collectors control the clocking of thè SAR.
(As with Q137, the schematic of Figure 3 shows Q136 as a single multiple-collector device altha~ it is actually a nu ~ er of individual transistors driven b~ a common base line ).
I
!l Adeq~ate drive is insured by supplying the base of 20 ¦¦ Q342 with`somewhat more than the normal I2L gate current ¦Iderived from the in~ector rail R. When Q342 drives Q136 on, ¦ Q136 must sink more than the normal gate cur.rent before reach- . E
~ing equilib.rium with the current from Q328. As a result, Q13 I is driven hard enough that the other collectors can all sink 25 11 at least the maximum gate current.
~ 12-l 159~5~ 935.027 ."
The current from Q328 is limited, however, so that t~e ~ase voltage of Q342 can be controlled by the double-sized collectors of either Q134 or Q135. These drive transistors ~lalso have a collector driving the base of Q136 to remove ¦excess charge when Q342 switches off.
The circuit described provides a clock drive servinc all of the SAR 42,-and which alternates once each time Q131, in the main clock oscillator, switches off. Use of the D
flip-flop 66 to halve the frequency results in a lower tran-¦ sistor count than would be required to achieve the same i `
I frequency with a ring oscillator of twice the num~er of stagec ~ -IjAlso, use of frequency division allows the comparator to be latched just before each advance of the SAR. Since the SAR
,advances on both leading and trailing edges o its clock ~¦drive, the comparator must be latched (and unlatched) at jl .
Iltwice the SAR clock frequency. The comparatox is therefore ; I,operated from the-ring oscillator loop and the SAR is operate ,from the rlng oscillator frequency divided by two.
,'1 , ,l In the diffused chip, the b~ses of Q127 and Q131 are ~enlarged to partially surround their respective injector regiol.
~s a result, they have an excess of base drive, sorae of which ¦
is used to supply the base currents of Q355 and Q356 in the c ~parator 50 These last two transistors control one of the i' Il 935.027 1 1 ` 1 1599~B
`;
. . .
~main bias circuits in the comparator. When Q355 is on, curren;t "from Q372 drives the comparatox input stage and the comparator!
joperates in a linear mode. If Q356 is switched on and Q355 ~lis switched off, the current from Q372 is by-passed around the input stage and through a flip-flop circuit connected with th~
comparator, and which latches in the current state of the comparator. Since under that circumstance the input stage is disabled, subsequent changes in the comparator input signal wi 11 have no effect and the comparator output will remain latched With the information present at the switching time. The com-parator can be restored to linear, or input-sensitive opera-tion, simply by reversing the drive to the cohtrol transistor , switching Q356 off and Q355 back on again.
, ~ ' `' .
When the B&C signal goes low to "convert" and causes Q137 to release the base of Q126, an inversion begins to propagate around the ring oscillator of clock 62 . The ¦base of Q126, which was low, rises and Q126 turns on driving the base of Q127 ~o-~. When Q127 goes off, Q131 iS allowed to ~go on, and the inversion continues around the ring. With the base o~ Q127 held low and the base of Q131 high, the comparato ¦ is in the input-SenSitive mode and senses the difference between the MSB and the analog input signal~
'~ ' ~.
~ 14-~ ' 935.027 ~ ~j ',~
! When the inversion completely circles the ring, Q1~7 will be switched on and it will, in turn, switch off Q131.
IThese two base signals will cause the comparator to latch the ,~,state of its output. As Q131 goes off, two of its collectors ¦trigger the flip-flop 66 and cause it to toggle, advancing the ¦state of the S~. When the SAR advances, a new test condition is presented to the ~omparator. However, the results of the previous test will remain latched into the comparator until th appropriate switching is complete. The inversion which trigge e~
the D flip-flop 66 will continue around the ring until it reaches Q127 and Q131 again, whereupon the comparator will be xestored to the input-sensitive mode to examinethe new test condition, and the flip-flop inputs will be driven low to arm it for the next clock pulse.
. ,.
¦ Test Sequence of the Successive-ApProximation Reqister i`
The individual bit current sources 32A, etc. of the DAC 30 are controlled by the flip-flops 54A, etc., in the SAR.
Each of these flip-flops consists of a pair of transistors:
'IQ2 and Q4 for the MSB; Q12 and Q14 for the 2nd SB; Q82 and -liQ84 for bit 9, etc., and in general Qx2 and Qx4 for bit x + 1.
¦iEach of the bits is sequentially tested beginning with the MSB
and progressing to the LSB. The SAR circuitry repeats on a
2-bit cycle inside the register. The beginning and end (MSB
liand Status) of the register are modified slightly from the ,'cyclic pattern to accommodate their start and finish functions ,~
,l -15-i,i ~35.027 , i~ l 1599 .~
The resetting function of the B~C input, which is implemented by Q137, clears the flip-flops associated wi~h bits 2 through 10 so that these bits are not expressed in the l,DAC output. The MSB is switched on by a collector of Q137 1 which drives the base of Q2. When a conversion begins, Q137 is switched off leaving the 10 flip-flops in their cleared state, but capable of being flipped by other signals.
The reset functions of Q137 also clears 5~control flip-flops 68A/B...68I/J, one for each adjacent pair of bit flip-flops 54A, 54B; 54C, 54D; etc., and consisting of pairs of transistors Q27-Q28...Q107-Q108. These flip-flops control the sequence of events in the SP~R. In partic~lar, Q27 is on after the reset signal fFom Q137 and holds off Q31 (Figure 7), Q51 is held off by Q47 and so forth-to Q91 which is held off by Q87. There is no preceding control flip-flop to hold of~
5211 (which is similar in function to Q31, Q51, etc )~ Howevex when the convert sequence begins, Q136 is on, holding all SAR
clock lines low. During the first clock interval, while the ¦
Ibase oE Qll ls held lowj the Q2-Q4 flip-flop is on alone and ¦! the MSB is tested. At the end o the first main clock cycle, ¦ the D flip-flop 66 is switched and Q136 goes off allowing Qll ¦Ito come on. When Qll comes on, it switches Q12 off causing ¦Ithe Q12-Q14 flip-flop to toggle Outputs from Q12 and Q14 llswitch on the second bit of the DAC 30 by way of Q217 and ~~Q218. During t~e interval following this transition, the Il second bit is tested.
I
1~ 935.027 - -`' 1 159~56 .
In the reset state, Q12 holds Q21 off. When Qll j `
comes on, switching Q12, Qll holds Q21 off. At the end of !
'the high clock cycle at the base of Qll, however, Qll is llswitched off, Q12 has been previously switched off, and Q21 l~is allowed to come on. When Q21 comes on, it drives Q27 off ithereby toggling the Q27-Q28 flip-flop. Since this flip-flop can be cleared only by the general B&C reset, it will remain set for the remainder of the conversion. Outputs from Q28 `
now go low blocking any subsequent operation of Qll, Q21, Q3 or Q13. Once Q28 comes on, it insures that the preceding portions of the successive-approximation sequence will not be repeated in this cycle.
When Q21 comes on it also drives Q22 off (Figure 7) setting the Q22-Q24 flip-flop and initiating the testing of ¦bit 3. This test will continue while the collectors of Q136 Iremain low. `
'' il . .' .
One additional change during this interval is the t enabling of Q3~. When Q27 is switched off, it releases the I base of Q31 which, however, continues to be held low by a llcollector of Q136. When this clock cycle ends and the D
'Iflip-flop 66 t:urns off Q136, Q31 will come on setting the ~Q32-Q34 flip-flop. This situation is analogous to the sequenc , -17-~i `` `' 935.027 I 159gS6 initiated by the cloc~ing o~ Qll. Subsequent operations are also analogous. That is, bit 4 is tested while Q136 is off.
When Q136 is next switched on, Q41 comes on setting both the Q47-Q48 and the Q42-Q44 flip-flops. Bit 5 will be tested, ~the preceding circuits will be blocked by Q48, and Q51 will be enabled by Q47. Each succeeding rise and fall of the clock signals from Q136 will advance the test bit by one position until all 10 bits have been tested. `
l ~ it the end of the test interval for the tenth bit, the collectors of Q108 "jam" preceding sections of the regis-ter. Also, one co~bctor of Q108 is returned to the base of l Q126 to stop the clocX 62 after 10 bits have been converted.
¦IOne collector of Q107 drives Q109, a controlled ~I2L tran-! sistor comprising a half-size current-limiting collector ¦ connection to its base. This transistor switches on and draws a current which approaches twice the gate current of ! a single in~ected device. This current drives the status ¦buffer 70 by way of Q302.
Il, .
I~ The status buffer 70 indicates that a conversion is ~,complete, and it also arives, via a line 71, the 10-bit three-state output buffers 56A, etc., into the indicating state.
,Each of the bit ou~put buffers is driven by a collector from the DAC control flip-flop (Q4, Q14, Qx4) to indicate the final state of the DAC. This state will be within one bit of balan~-25 li ing the input signal (for signals inside the converter's rang~ )and so indicates digitally the magnitude of the analog input.
' 935.02/ 1 1 I 1 1599~ 1 ComParator Control ; The description of the test se~uence above shows how each bit of the DAC 30 is switched on as the conversion pro- i ceeds. In order for the DAC output to converge on a value approximating the analog signal input, means mus~ be provided ,to switch off bits which, when summed with previously selected jbits, exceed the input signal. The comparator cixcuit detects ¦the sign of the difference of the analog input and the DAC
output. Its output through line 52 drives the base of Ql38 with the result of the comparison, and the output is latched on or off by the clock 62 during a particular period of the clock cycle-, I . ~
When the analog input exceeds the DAC output, Ql38 l~
~will be driven on; when the DAC output exceeds the analog ¦linput Ql38 will be driven off. Figure 3 indicates that Ql38 is a single multiple-collector device, but like the clock and ,reset transistors Ql36 and Ql37, it is actually composed of a !~number of transistors driven in para~lel. Unlike the clock ¦land reset transistors, however, it does not use feedbacX con-~itrol of its drive. Instead, the base connection to Ql38 is "overdriven by the comparator in the on state.
,,, !
!, .',1 :i --19--::
.!
~'.
ii ' ' ` '~
~ 935~0~7 ~.i 1 I, I 15995~
The collectors of Q138 control the transistors Q3, Q13...Qx3 associated with the bit flip-flops 54A, etc. These 'transistors Q3, etc., are arranged so that they will reset "their associated flip-flop at the end of the test interval llunless they are inhibited by Q138.
Il .
Consider the action of Q3 on the Q2-Q4 flip-flop.. .
During the test of the MSB, the collectors of Q136 are low. .
One of these collectors drives Q3 and prevents it from resetti lg Q2-Q4. At this time both Q14 and Q28 are off so that at the end of the MSB test interval when Q136 goes off, Q3 will come on and reset the Q2-Q4 flip-flop unless the collector of Q138 driving Q3 inhibits it.
. . l ~ When the cloc~ transistor Q136 goes off, the previou ly describea sequence where Qll sets the Q12-Q14 flip-flop begins ~Therefore, after three gate de}ays, Q14 comes on and inhibits !Q3 from resetting the Q2-Q4~lip-flop. That is, w~en the clo - ~collectors go high at the end of the MSB test interval, Q3 is ~enabled ~or a period of three gate delays, to reset the Q2-Q4 ¦Iflip flop unless it is inhibited by the comparator by way of 20 ~Q138. Subsequently, when the clock transistor iS driven back IOA, Q14 may be reset. HoweveF ~28 will come on and remain on Il -20- ~
., . I
' 935.027 1 15g9~ .
for the remainder of the conversion to inhibit Q3. Since the ¦
Iclock collectors are low during this change, any underlap between Q14 and Q28 is masked by QI36 at the base of Q3.
Therefore, Q3 has only one possible opportunity during the jentire conversion to reset the Q2-Q4 flip-flop.
i When the collectors of Q136 go high to initiate test ing of the second bit, Qll is driven on setting the Q12-Q14 flip-flop and inhibiting Q13 from resetting it. At the end of ~he bit 2 test interval, the clock collectors go-low switching Q11 off and removing its inhibiting effect on Q13, If Q13 is lOt inhibited by its drive from the collector of Q138, it will ~ome on and reset the Q12-Q14 flip-flop. When Qll goes off, nabling Q13, it also initiates the chain of events which t l~rives Q21 on, Q27 off and Q28 on. One collector of Q28 is Fonnected to inhibit Q13 so that Qll enables Q13, and three gate delays later Q28 disables it again. Since Q28 will remai n for the entire remainder of the conversion, Q13 is enabled o ~eset the Q12-Q14 flip-flop for only this three-gate delay I~nterval at the end of the second bit test. Depending on the ~tate of Q138, which is controlled by the comparator, the secor d ~it will be retained or rejected at this time.
The function of Q23 in resetting the Q22-Q24 flip-~lop is nearly identical to that of Q3 with respect to its ~lip-flop. During the second bit test interval, Q23 is enablec .
,,1 ,'~, .
,, -~1-~ 5~g5~ 935 027 I I
i~ ' .' ,I~Iowever, at that time the Q22-Q24 flip-flop is still in its ,Iinitial reset state so that Q23 has no effect. At the begin-~! ning of the fourth bit test interval, Q23 is enabled by the ~¦clock for the three gate delay interval necessary to switch 5 I Q34 on. During this enabled time, bit 3 is retained or reject~d ~under control of the comparator. After this time and for the remainder of the convert cycle, Q23 will be inhibited by one or more of Q34, Q48, Q138 or Q136. The operation of Q33 in relation to bit 4 is identical to that of Q13 to bit 2 Each stage of the SAR has a reset transistor Q3, Q13, Q23, Q33, .
etc., whiCh iS enabled for three gate delays at the end of itS
test interval so that the stage may be reset ~y the comparato as appropriate.
.. ., , ,': , I Q5, Q6~ Q15, Q16; Q25, Q26; etc., shown as collector-less I L transistors on the schematic, are clamped current sources Which supply the drive for the DAC current diverters ¦~Q207, Q208; Q217, Q218; Q227, Q228; and so on. These tran-¦sistors Q5, etc., are simply injected I2L gates without ~Icollectors. Their unloaded voltage will rise to, approximatel r, 20 ¦~ the injector voltage and they can supply a normal I2L gate ¦Icurrent to a load. They are driven off, in alternation, by the bit control flip-flops 54A, etc., so as to cause only one llof a pair of transistors Q2x7 and Q2x8 to conduct. This ¦larrangement allows the flip~flop to divert the individual bit !l . , ~., ~ 22~
'' 935.027 . 1 159956 ~curren~ of the D.~C to the analog summing p~int or ground This method is preferred to direct drive of the current ¦
'idiverters by the flip-flop bases, so as to provide adequate l~base drive for the high oraer bits, and to prevent unwanted ¦~dynamic interaction between the DAC and the logic.
Ii ~ i l The circuitry of the comparator 50 provides for fas latching, in part because it includes as an integral element thereof an internal flip-flop controlled directly by the com-parator currents. In more detail, the sense comparison is effected primarily by a pair of transistors Q351, Q352 the currents of which pass through respective load circuits com-prising R410, Q347; and R411, Q348. Transistors Q347 and ~' Q348 are provided with additional emitters which, when the ~ clock 62 switches transistor Q356 on, conduct current through t ¦that transistor. When switchover occurs, the flow of current ~activates an internal f1ip-flop comprising Q345, Q346 which ~¦thereupon latches the sensed state of the comparison and Ilfixes the output signal of the comparator at the latched ! value.
. I, ' ' . .
Ill The double~ended output signal from the comparator ¦¦ 50 is directed through respective circuits to a pair of level ¦i shiEting Zener diodes 73, 74 dif~used into the substrate !
,.j .
,j ~i 935~0~7 ` I 15995~ `
. .
together with respectlve transistor Q343, Q344. These tran- I
~sistors form a dif~erential pair the collectors of which are ! connected to a circuit Q331, Q370 arranged to convert the l~double-ended comparator signal to a corresponding single-ended ,lsignal for the comparator output line 52.
Il .
¦ The currents flowing through the comparator 50 and its output circuitry are controlled by conventional negative bias circuits indicated at 77. The summing point 48, at the input to the comparator, also is connected to a bipolar offset current source in the form of a current mirror 75. The curren t o~ t~is source is controlled by a current developed by a tran sistor Q378 supplied by a voltage supply 76 which applies a supply voltage to a common base line 78. When the current mirror is activated, it supplies to summing point 48 a current equal to one-half the full-scale current, thus providing the required offset effect to achieve bipolar operation. The l voltage supply 76 comprises a Zener diode D402 which prefer-¦~ably is di*fused to provide a sub-surface breakdown Zener l!diode, i.e. a so-called buried-layer Zener. The other Zener ,D401 provides circuit start up.
The ~ransistor base line 78 is connected to the current sources 3~, etc., of the DAC 30, and includes inter- ~ ;
'base resistors R451, ~77, etc., through which is directed a ~,PTAT (proportional-to-absolute-temperature) current in accord-~,ance with the teachinys of U. S. Patent 3,940,760 referred to~ above. The voltage reference 76 includes suitable circuitry ''` 935.027 -I
1 159956 ` I
proportional current variation with temperature.
Biasinq . In addition to generating the various bias currents and voltages used in the converter, and mentioned elsewhere, the biasing of the I2L circuitry is specially arrangea to tak ~maximum advantage o existing bias levels and to avoid the ¦need for level translator structures. The I L circuitry is connected so that the injector R, which is its most positi e power terminal, is driven from a bias voltage which is negati~e with respect to ground. This low impedance bias is generated by the foward conducting voltage drops of Q323 and Q324 - acting as diodes. The switches 36A, 36B,...etc., must be ¦ negative with respect to ground in order to ~rive the summing point 48 of the comparator 50 so as to converge toward ground ¦ potential. The negative bias voltage of the successive-¦~approximation control 42 permits it to directly drive the ¦¦switches without voltage level translators, which would be ¦Irequirea using conventional logic power voltages.
:' , li Moreover, because it is the positive power connectic n ! to the successive-approximation control logic 42 which operates at fixed voltage (two diode-drops below ground), the I2L
circuitry can be powered in part by currents derived from operation of the Zener supply voltage source 76 and the DAC
.
,1 -25- - I
,~
~ ' 935.0~7 . 1 15g95~ . I
circuits. This current is used by these circuits, wllich approximately regulate its amplitude, and they have sufficient, voltage compliance to permit them to be connected to the 1, ' Inegative side of the logic. In this way these currents are iiused to power the I2L transistor circuitry as they are returne~
l~to ground. This permits a saving oE overall power over the ¦
jconventional approach wherein the negative power connection is fixed by a low impedance connection and additional fixed current would be used to power the positive logic connection.
. ' ,~
¦ The negatively biased I2L circuitry must drive the f output buffers 56~, 56B,~..etc~, which are biased between grou~ d nd the positive supply or compatibility with, external circui- :ry.
onnection between the I2~ logic and the buffers is accomplish~ ~d ~y driving a single inverted mode ~P~ collector which has ¦sufficient voltage compliance to accommodate the difference in ¦~ias voltage levels. This represents no increase in com~lexity over a conventional biasing arrangement.
i! Although a preferred embodiment of the invention has ~een described ~erein in detail, it is desired to emphasize ¦
that this is for the purpose of illustrating the principles ~of the invention, and should not necessarily be construed as ¦limiting of the invention since it is apparent that those ~skilled in this art can make many modified arrangements of l,the invention without departing from the true scope thereof.
..
, -26- 1
liand Status) of the register are modified slightly from the ,'cyclic pattern to accommodate their start and finish functions ,~
,l -15-i,i ~35.027 , i~ l 1599 .~
The resetting function of the B~C input, which is implemented by Q137, clears the flip-flops associated wi~h bits 2 through 10 so that these bits are not expressed in the l,DAC output. The MSB is switched on by a collector of Q137 1 which drives the base of Q2. When a conversion begins, Q137 is switched off leaving the 10 flip-flops in their cleared state, but capable of being flipped by other signals.
The reset functions of Q137 also clears 5~control flip-flops 68A/B...68I/J, one for each adjacent pair of bit flip-flops 54A, 54B; 54C, 54D; etc., and consisting of pairs of transistors Q27-Q28...Q107-Q108. These flip-flops control the sequence of events in the SP~R. In partic~lar, Q27 is on after the reset signal fFom Q137 and holds off Q31 (Figure 7), Q51 is held off by Q47 and so forth-to Q91 which is held off by Q87. There is no preceding control flip-flop to hold of~
5211 (which is similar in function to Q31, Q51, etc )~ Howevex when the convert sequence begins, Q136 is on, holding all SAR
clock lines low. During the first clock interval, while the ¦
Ibase oE Qll ls held lowj the Q2-Q4 flip-flop is on alone and ¦! the MSB is tested. At the end o the first main clock cycle, ¦ the D flip-flop 66 is switched and Q136 goes off allowing Qll ¦Ito come on. When Qll comes on, it switches Q12 off causing ¦Ithe Q12-Q14 flip-flop to toggle Outputs from Q12 and Q14 llswitch on the second bit of the DAC 30 by way of Q217 and ~~Q218. During t~e interval following this transition, the Il second bit is tested.
I
1~ 935.027 - -`' 1 159~56 .
In the reset state, Q12 holds Q21 off. When Qll j `
comes on, switching Q12, Qll holds Q21 off. At the end of !
'the high clock cycle at the base of Qll, however, Qll is llswitched off, Q12 has been previously switched off, and Q21 l~is allowed to come on. When Q21 comes on, it drives Q27 off ithereby toggling the Q27-Q28 flip-flop. Since this flip-flop can be cleared only by the general B&C reset, it will remain set for the remainder of the conversion. Outputs from Q28 `
now go low blocking any subsequent operation of Qll, Q21, Q3 or Q13. Once Q28 comes on, it insures that the preceding portions of the successive-approximation sequence will not be repeated in this cycle.
When Q21 comes on it also drives Q22 off (Figure 7) setting the Q22-Q24 flip-flop and initiating the testing of ¦bit 3. This test will continue while the collectors of Q136 Iremain low. `
'' il . .' .
One additional change during this interval is the t enabling of Q3~. When Q27 is switched off, it releases the I base of Q31 which, however, continues to be held low by a llcollector of Q136. When this clock cycle ends and the D
'Iflip-flop 66 t:urns off Q136, Q31 will come on setting the ~Q32-Q34 flip-flop. This situation is analogous to the sequenc , -17-~i `` `' 935.027 I 159gS6 initiated by the cloc~ing o~ Qll. Subsequent operations are also analogous. That is, bit 4 is tested while Q136 is off.
When Q136 is next switched on, Q41 comes on setting both the Q47-Q48 and the Q42-Q44 flip-flops. Bit 5 will be tested, ~the preceding circuits will be blocked by Q48, and Q51 will be enabled by Q47. Each succeeding rise and fall of the clock signals from Q136 will advance the test bit by one position until all 10 bits have been tested. `
l ~ it the end of the test interval for the tenth bit, the collectors of Q108 "jam" preceding sections of the regis-ter. Also, one co~bctor of Q108 is returned to the base of l Q126 to stop the clocX 62 after 10 bits have been converted.
¦IOne collector of Q107 drives Q109, a controlled ~I2L tran-! sistor comprising a half-size current-limiting collector ¦ connection to its base. This transistor switches on and draws a current which approaches twice the gate current of ! a single in~ected device. This current drives the status ¦buffer 70 by way of Q302.
Il, .
I~ The status buffer 70 indicates that a conversion is ~,complete, and it also arives, via a line 71, the 10-bit three-state output buffers 56A, etc., into the indicating state.
,Each of the bit ou~put buffers is driven by a collector from the DAC control flip-flop (Q4, Q14, Qx4) to indicate the final state of the DAC. This state will be within one bit of balan~-25 li ing the input signal (for signals inside the converter's rang~ )and so indicates digitally the magnitude of the analog input.
' 935.02/ 1 1 I 1 1599~ 1 ComParator Control ; The description of the test se~uence above shows how each bit of the DAC 30 is switched on as the conversion pro- i ceeds. In order for the DAC output to converge on a value approximating the analog signal input, means mus~ be provided ,to switch off bits which, when summed with previously selected jbits, exceed the input signal. The comparator cixcuit detects ¦the sign of the difference of the analog input and the DAC
output. Its output through line 52 drives the base of Ql38 with the result of the comparison, and the output is latched on or off by the clock 62 during a particular period of the clock cycle-, I . ~
When the analog input exceeds the DAC output, Ql38 l~
~will be driven on; when the DAC output exceeds the analog ¦linput Ql38 will be driven off. Figure 3 indicates that Ql38 is a single multiple-collector device, but like the clock and ,reset transistors Ql36 and Ql37, it is actually composed of a !~number of transistors driven in para~lel. Unlike the clock ¦land reset transistors, however, it does not use feedbacX con-~itrol of its drive. Instead, the base connection to Ql38 is "overdriven by the comparator in the on state.
,,, !
!, .',1 :i --19--::
.!
~'.
ii ' ' ` '~
~ 935~0~7 ~.i 1 I, I 15995~
The collectors of Q138 control the transistors Q3, Q13...Qx3 associated with the bit flip-flops 54A, etc. These 'transistors Q3, etc., are arranged so that they will reset "their associated flip-flop at the end of the test interval llunless they are inhibited by Q138.
Il .
Consider the action of Q3 on the Q2-Q4 flip-flop.. .
During the test of the MSB, the collectors of Q136 are low. .
One of these collectors drives Q3 and prevents it from resetti lg Q2-Q4. At this time both Q14 and Q28 are off so that at the end of the MSB test interval when Q136 goes off, Q3 will come on and reset the Q2-Q4 flip-flop unless the collector of Q138 driving Q3 inhibits it.
. . l ~ When the cloc~ transistor Q136 goes off, the previou ly describea sequence where Qll sets the Q12-Q14 flip-flop begins ~Therefore, after three gate de}ays, Q14 comes on and inhibits !Q3 from resetting the Q2-Q4~lip-flop. That is, w~en the clo - ~collectors go high at the end of the MSB test interval, Q3 is ~enabled ~or a period of three gate delays, to reset the Q2-Q4 ¦Iflip flop unless it is inhibited by the comparator by way of 20 ~Q138. Subsequently, when the clock transistor iS driven back IOA, Q14 may be reset. HoweveF ~28 will come on and remain on Il -20- ~
., . I
' 935.027 1 15g9~ .
for the remainder of the conversion to inhibit Q3. Since the ¦
Iclock collectors are low during this change, any underlap between Q14 and Q28 is masked by QI36 at the base of Q3.
Therefore, Q3 has only one possible opportunity during the jentire conversion to reset the Q2-Q4 flip-flop.
i When the collectors of Q136 go high to initiate test ing of the second bit, Qll is driven on setting the Q12-Q14 flip-flop and inhibiting Q13 from resetting it. At the end of ~he bit 2 test interval, the clock collectors go-low switching Q11 off and removing its inhibiting effect on Q13, If Q13 is lOt inhibited by its drive from the collector of Q138, it will ~ome on and reset the Q12-Q14 flip-flop. When Qll goes off, nabling Q13, it also initiates the chain of events which t l~rives Q21 on, Q27 off and Q28 on. One collector of Q28 is Fonnected to inhibit Q13 so that Qll enables Q13, and three gate delays later Q28 disables it again. Since Q28 will remai n for the entire remainder of the conversion, Q13 is enabled o ~eset the Q12-Q14 flip-flop for only this three-gate delay I~nterval at the end of the second bit test. Depending on the ~tate of Q138, which is controlled by the comparator, the secor d ~it will be retained or rejected at this time.
The function of Q23 in resetting the Q22-Q24 flip-~lop is nearly identical to that of Q3 with respect to its ~lip-flop. During the second bit test interval, Q23 is enablec .
,,1 ,'~, .
,, -~1-~ 5~g5~ 935 027 I I
i~ ' .' ,I~Iowever, at that time the Q22-Q24 flip-flop is still in its ,Iinitial reset state so that Q23 has no effect. At the begin-~! ning of the fourth bit test interval, Q23 is enabled by the ~¦clock for the three gate delay interval necessary to switch 5 I Q34 on. During this enabled time, bit 3 is retained or reject~d ~under control of the comparator. After this time and for the remainder of the convert cycle, Q23 will be inhibited by one or more of Q34, Q48, Q138 or Q136. The operation of Q33 in relation to bit 4 is identical to that of Q13 to bit 2 Each stage of the SAR has a reset transistor Q3, Q13, Q23, Q33, .
etc., whiCh iS enabled for three gate delays at the end of itS
test interval so that the stage may be reset ~y the comparato as appropriate.
.. ., , ,': , I Q5, Q6~ Q15, Q16; Q25, Q26; etc., shown as collector-less I L transistors on the schematic, are clamped current sources Which supply the drive for the DAC current diverters ¦~Q207, Q208; Q217, Q218; Q227, Q228; and so on. These tran-¦sistors Q5, etc., are simply injected I2L gates without ~Icollectors. Their unloaded voltage will rise to, approximatel r, 20 ¦~ the injector voltage and they can supply a normal I2L gate ¦Icurrent to a load. They are driven off, in alternation, by the bit control flip-flops 54A, etc., so as to cause only one llof a pair of transistors Q2x7 and Q2x8 to conduct. This ¦larrangement allows the flip~flop to divert the individual bit !l . , ~., ~ 22~
'' 935.027 . 1 159956 ~curren~ of the D.~C to the analog summing p~int or ground This method is preferred to direct drive of the current ¦
'idiverters by the flip-flop bases, so as to provide adequate l~base drive for the high oraer bits, and to prevent unwanted ¦~dynamic interaction between the DAC and the logic.
Ii ~ i l The circuitry of the comparator 50 provides for fas latching, in part because it includes as an integral element thereof an internal flip-flop controlled directly by the com-parator currents. In more detail, the sense comparison is effected primarily by a pair of transistors Q351, Q352 the currents of which pass through respective load circuits com-prising R410, Q347; and R411, Q348. Transistors Q347 and ~' Q348 are provided with additional emitters which, when the ~ clock 62 switches transistor Q356 on, conduct current through t ¦that transistor. When switchover occurs, the flow of current ~activates an internal f1ip-flop comprising Q345, Q346 which ~¦thereupon latches the sensed state of the comparison and Ilfixes the output signal of the comparator at the latched ! value.
. I, ' ' . .
Ill The double~ended output signal from the comparator ¦¦ 50 is directed through respective circuits to a pair of level ¦i shiEting Zener diodes 73, 74 dif~used into the substrate !
,.j .
,j ~i 935~0~7 ` I 15995~ `
. .
together with respectlve transistor Q343, Q344. These tran- I
~sistors form a dif~erential pair the collectors of which are ! connected to a circuit Q331, Q370 arranged to convert the l~double-ended comparator signal to a corresponding single-ended ,lsignal for the comparator output line 52.
Il .
¦ The currents flowing through the comparator 50 and its output circuitry are controlled by conventional negative bias circuits indicated at 77. The summing point 48, at the input to the comparator, also is connected to a bipolar offset current source in the form of a current mirror 75. The curren t o~ t~is source is controlled by a current developed by a tran sistor Q378 supplied by a voltage supply 76 which applies a supply voltage to a common base line 78. When the current mirror is activated, it supplies to summing point 48 a current equal to one-half the full-scale current, thus providing the required offset effect to achieve bipolar operation. The l voltage supply 76 comprises a Zener diode D402 which prefer-¦~ably is di*fused to provide a sub-surface breakdown Zener l!diode, i.e. a so-called buried-layer Zener. The other Zener ,D401 provides circuit start up.
The ~ransistor base line 78 is connected to the current sources 3~, etc., of the DAC 30, and includes inter- ~ ;
'base resistors R451, ~77, etc., through which is directed a ~,PTAT (proportional-to-absolute-temperature) current in accord-~,ance with the teachinys of U. S. Patent 3,940,760 referred to~ above. The voltage reference 76 includes suitable circuitry ''` 935.027 -I
1 159956 ` I
proportional current variation with temperature.
Biasinq . In addition to generating the various bias currents and voltages used in the converter, and mentioned elsewhere, the biasing of the I2L circuitry is specially arrangea to tak ~maximum advantage o existing bias levels and to avoid the ¦need for level translator structures. The I L circuitry is connected so that the injector R, which is its most positi e power terminal, is driven from a bias voltage which is negati~e with respect to ground. This low impedance bias is generated by the foward conducting voltage drops of Q323 and Q324 - acting as diodes. The switches 36A, 36B,...etc., must be ¦ negative with respect to ground in order to ~rive the summing point 48 of the comparator 50 so as to converge toward ground ¦ potential. The negative bias voltage of the successive-¦~approximation control 42 permits it to directly drive the ¦¦switches without voltage level translators, which would be ¦Irequirea using conventional logic power voltages.
:' , li Moreover, because it is the positive power connectic n ! to the successive-approximation control logic 42 which operates at fixed voltage (two diode-drops below ground), the I2L
circuitry can be powered in part by currents derived from operation of the Zener supply voltage source 76 and the DAC
.
,1 -25- - I
,~
~ ' 935.0~7 . 1 15g95~ . I
circuits. This current is used by these circuits, wllich approximately regulate its amplitude, and they have sufficient, voltage compliance to permit them to be connected to the 1, ' Inegative side of the logic. In this way these currents are iiused to power the I2L transistor circuitry as they are returne~
l~to ground. This permits a saving oE overall power over the ¦
jconventional approach wherein the negative power connection is fixed by a low impedance connection and additional fixed current would be used to power the positive logic connection.
. ' ,~
¦ The negatively biased I2L circuitry must drive the f output buffers 56~, 56B,~..etc~, which are biased between grou~ d nd the positive supply or compatibility with, external circui- :ry.
onnection between the I2~ logic and the buffers is accomplish~ ~d ~y driving a single inverted mode ~P~ collector which has ¦sufficient voltage compliance to accommodate the difference in ¦~ias voltage levels. This represents no increase in com~lexity over a conventional biasing arrangement.
i! Although a preferred embodiment of the invention has ~een described ~erein in detail, it is desired to emphasize ¦
that this is for the purpose of illustrating the principles ~of the invention, and should not necessarily be construed as ¦limiting of the invention since it is apparent that those ~skilled in this art can make many modified arrangements of l,the invention without departing from the true scope thereof.
..
, -26- 1
Claims (19)
1. An analog-to-digital converter comprising a single monolithic integrated-circuit chip formed in a multi-step diffusion process with:
a set of normal mode transistor current sources ar-ranged to produce binarily-weighted currents;
a set of switch means for controlling said current sources individually so as to sum the currents thereof selectively in accordance with the activation of said switch means;
successive-approximation control means comprising inverted mode I2L transistors coupled to said switch means to control the switches thereof in a sequential successive-approximation algorithm;
a clock pulse generator comprising inverted mode I2L transistors producing clock pulses for said successive-approximation control means to effect the sequencing thereof;
a comparator formed of normal mode transistors having input means to receive an unknown analog signal for comparison with a signal responsive to said sum of currents means under the control of said clock pulse genera-tor for activating said comparator;
register means for said successive-approximation control means to store the results of each comparison in the sequence;
means responsive to the output of said comparator to set said register means in accordance with the result of each comparison; and digital output means coupled to said register means to produce a digital output signal at the completion of a conversion.
935.027
a set of normal mode transistor current sources ar-ranged to produce binarily-weighted currents;
a set of switch means for controlling said current sources individually so as to sum the currents thereof selectively in accordance with the activation of said switch means;
successive-approximation control means comprising inverted mode I2L transistors coupled to said switch means to control the switches thereof in a sequential successive-approximation algorithm;
a clock pulse generator comprising inverted mode I2L transistors producing clock pulses for said successive-approximation control means to effect the sequencing thereof;
a comparator formed of normal mode transistors having input means to receive an unknown analog signal for comparison with a signal responsive to said sum of currents means under the control of said clock pulse genera-tor for activating said comparator;
register means for said successive-approximation control means to store the results of each comparison in the sequence;
means responsive to the output of said comparator to set said register means in accordance with the result of each comparison; and digital output means coupled to said register means to produce a digital output signal at the completion of a conversion.
935.027
2. A converter as in Claim 1, including voltage reference means formed on the same chip to provide an absolute analog-to-digital converter.
3. A converter as in Claim 2, wherein said voltage reference means is formed of normal mode transistor means,
4. A converter as in Claim 1, wherein said switch means include a plurality of individual switch circuits each comprising a differential pair of normal mode transistors coupled to a corresponding one of said transistor current sources.
5. A converter as in Claim 4, wherein said switch means further comprises a plurality of inverted mode tran-sistors for operating said individual switch circuits respec-tively.
935.027
935.027
6. A converter as in Claim 1, wherein said clock pulse generator comprises a ring oscillator producing an output frequency responsive to the gate delay of the inverted node gates forming the ring, whereby the oscillator frequency is automatically compensated for variations in gate delay in the associated inverted mode logic circuitry of the converter, regardless of the cause of such variations.
7. A converter as in Claim 1, wherein said register means is formed of inverted mode transistors.
8. A converter as in Claim 1, wherein said digital output means comprises output buffers formed of normal mode linear transistors.
9. A converter as in Claim 1, wherein all of said inverted mode transistors and the normal mode current source transistors are operated in a below-ground potential range.
10. An analog-to-digital converter comprising substrate means having first and second portions;
a plurality of normal mode transistor current sources formed in said first substrate portion and individually con-trollable to produce respective binarily-weighted currents for summation into a composite signal;
I2L inverted mode transistor means formed in said second substrate portion including circuit means defining suc-cessive-approximation control means capable of carrying out a successive-approximation algorithm; and transistor switch means on at least one of said substrate portions responsive to said successive-approximation control means and serving to control said current sources to carry out said algorithm for developing a digital output corresponding to an unknown analog signal.
.
a plurality of normal mode transistor current sources formed in said first substrate portion and individually con-trollable to produce respective binarily-weighted currents for summation into a composite signal;
I2L inverted mode transistor means formed in said second substrate portion including circuit means defining suc-cessive-approximation control means capable of carrying out a successive-approximation algorithm; and transistor switch means on at least one of said substrate portions responsive to said successive-approximation control means and serving to control said current sources to carry out said algorithm for developing a digital output corresponding to an unknown analog signal.
.
11. A converter as in Claim 10, wherein said first and second substrate portions form a single monolithic chip.
12. A converter as in Claim 10, wherein said switch means comprises a plurality of individual switch circuits formed on said first substrate portion of normal mode transistors circuit means providing a current summing point:
each of said switch circuits being connected to a corresponding current source and arranged to controllably divert the current thereof to said summing point to develop a composite signal for comparison with an analog input signal.
each of said switch circuits being connected to a corresponding current source and arranged to controllably divert the current thereof to said summing point to develop a composite signal for comparison with an analog input signal.
13. A converter as in Claim 12, wherein said switch means further comprises inverted mode transistor means operable with said successive-approximation control means and connected directly to said individual switch circuits to control the operation thereof.
14. An analog-to-digital converter comprising a single monolithic integrated-circuit chip formed with:
normal mode linear transistor means including means providing binary current sources for producing an analog signal for comparison with the analog input signal;
I2L inverted mode transistor means including means providing a register for developing and storing a digital output signal; and means interconnecting a control signal developed from said analog signal comparison to said inverted mode transistor means register to develop said digital said digital output signal, providing on said single chip the functions for converting an analog input signal to a digital output signal.
935.027
normal mode linear transistor means including means providing binary current sources for producing an analog signal for comparison with the analog input signal;
I2L inverted mode transistor means including means providing a register for developing and storing a digital output signal; and means interconnecting a control signal developed from said analog signal comparison to said inverted mode transistor means register to develop said digital said digital output signal, providing on said single chip the functions for converting an analog input signal to a digital output signal.
935.027
15. The method of making an analog-to-digital converter comprising the process of carrying out a series of diffusions into a single substrate to form said substrate with normal mode linear transistors and with I2L inverted mode transistors;
certain of said normal mode transistors being formed as a digital-to-analog converter having a plurality of switch-controllable current sources;
certain of said inverted mode transistors being formed as a successive-approximation control means;and other of said transistors being formed to provide means for cooperatively relating said successive-approximation control means and said digital-to-analog converter to effect a conversion of an unknown analog signal into a corresponding digital signal.
935.027
certain of said normal mode transistors being formed as a digital-to-analog converter having a plurality of switch-controllable current sources;
certain of said inverted mode transistors being formed as a successive-approximation control means;and other of said transistors being formed to provide means for cooperatively relating said successive-approximation control means and said digital-to-analog converter to effect a conversion of an unknown analog signal into a corresponding digital signal.
935.027
16. An integrated circuit analog-to-digital converter comprising:
substrate means having transistors and associated circuitry diffused therein;
d-c power supply bus means for said substrate means and comprising a positive voltage bus, a negative voltage bus, and a ground common bus;
said transistors including a set of inverted mode transistors arranged as a successive-approximation control means and register means;
said transistors further including a set of normal mode transistors serving as switch-controllable current sources;
switch means coupled to said successive-approximation control means for controlling said current sources so as to produce summation currents for comparison with an analog input signal, whereby to determine the digital signals to be stored in said register means; and circuit means coupling said sets of transistors between said common bus and said negative bus to supply operating power thereto.
935.027
substrate means having transistors and associated circuitry diffused therein;
d-c power supply bus means for said substrate means and comprising a positive voltage bus, a negative voltage bus, and a ground common bus;
said transistors including a set of inverted mode transistors arranged as a successive-approximation control means and register means;
said transistors further including a set of normal mode transistors serving as switch-controllable current sources;
switch means coupled to said successive-approximation control means for controlling said current sources so as to produce summation currents for comparison with an analog input signal, whereby to determine the digital signals to be stored in said register means; and circuit means coupling said sets of transistors between said common bus and said negative bus to supply operating power thereto.
935.027
17. A converter as in Claim 16, wherein said circuit means couples said transistors to the power supply such that said inverted mode transistors operate in a voltage range which is more positive than the power supply voltage range of said normal mode transistors.
18. A converter as in Claim 17, wherein said normal mode transistors include a group of transistors arranged as individual switch circuits for respective current sources;
said inverted mode transistors including a group connected directly to said switch circuit transistors to operate said switch circuits-selectively in accordance with the algorithm of said successive-approximation control means.
said inverted mode transistors including a group connected directly to said switch circuit transistors to operate said switch circuits-selectively in accordance with the algorithm of said successive-approximation control means.
19. A converter as in Claim 16, including a second set of normal mode transistors arranged as output buffers;
said circuit means including means coupling said output buffers between said positive supply bus and said common bus, to furnish operating power to said buffers.
said circuit means including means coupling said output buffers between said positive supply bus and said common bus, to furnish operating power to said buffers.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US78532277A | 1977-04-07 | 1977-04-07 | |
| US785,322 | 1977-04-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1159956A true CA1159956A (en) | 1984-01-03 |
Family
ID=25135117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000300605A Expired CA1159956A (en) | 1977-04-07 | 1978-04-06 | A-to-d converter of the successive-approximation type |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS53146563A (en) |
| CA (1) | CA1159956A (en) |
| DE (1) | DE2814868A1 (en) |
| FR (1) | FR2386940A1 (en) |
| GB (1) | GB1599538A (en) |
| NL (1) | NL7803536A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5923727Y2 (en) * | 1980-07-28 | 1984-07-14 | 三洋電機株式会社 | equipment packing equipment |
| US4381497A (en) * | 1981-04-03 | 1983-04-26 | Burr-Brown Research Corporation | Digital-to-analog converter having open-loop voltage reference for regulating bit switch currents |
| DE3640276A1 (en) * | 1986-11-25 | 1988-06-09 | Telefunken Electronic Gmbh | Digital/analog converter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3961326A (en) * | 1974-09-12 | 1976-06-01 | Analog Devices, Inc. | Solid state digital to analog converter |
| US3940760A (en) * | 1975-03-21 | 1976-02-24 | Analog Devices, Inc. | Digital-to-analog converter with current source transistors operated accurately at different current densities |
-
1978
- 1978-04-03 NL NL7803536A patent/NL7803536A/en not_active Application Discontinuation
- 1978-04-06 CA CA000300605A patent/CA1159956A/en not_active Expired
- 1978-04-06 DE DE19782814868 patent/DE2814868A1/en active Granted
- 1978-04-06 GB GB13600/78A patent/GB1599538A/en not_active Expired
- 1978-04-07 FR FR7810462A patent/FR2386940A1/en active Granted
- 1978-04-07 JP JP4114578A patent/JPS53146563A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE2814868A1 (en) | 1979-01-18 |
| DE2814868C2 (en) | 1989-06-15 |
| JPS53146563A (en) | 1978-12-20 |
| GB1599538A (en) | 1981-10-07 |
| NL7803536A (en) | 1978-10-10 |
| FR2386940B1 (en) | 1984-11-16 |
| FR2386940A1 (en) | 1978-11-03 |
| JPS6340049B2 (en) | 1988-08-09 |
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