CA1157591A - Byte data activity compression - Google Patents

Abstract

BYTE DATA ACTIVITY COMPRESSION

Abstract In a TDMA satellite communications system, the data ports at two different earth stations have their data rates synchronized. The origination port stores the last eight-bit byte of data in each 480-bit packet which is transmitted via the satellite. The last byte is compared with each of the 60 bytes of data in the next channel's worth of information received from the ter-restrial source. If all of the bytes of data in the new channel's worth of information are identical to the last byte of data transmitted from the originating port, no information is transmitted for this data port in the next TDMA frame. The synchronized data port at the receiving earth station expects a channel's Worth of data to be received during the next TDMA frame. The last byte of received data for the recipient data port in the last frame is stored. If no data is received by the recipient data port in the present frame, the data port will infer that the next 60 bytes of data in the channel which would have been received in the present frame are each replications of the stored last byte of data. The receiving port then replicates the last byte of data 60 times and delivers it to the recipient terrestrial receiver connected to the data port. The transmitting data port will continue to not transmit succeeding channel's worth of data for every new channel whose bytes are the replication of the last byte stored from the last frame. The recipient data port at the destination earth station will continue to infer that the succeeding channels which are not received from the originating station are in fact replications of the last byte stored from the last received channel, for every TDMA frame which does not contain a transmission from the originating data port. Thus, without the necessity for transmitting control information such as a VAC mask to affirmatively signal the destination data port that byte replication is to be carried out, the destination station will continue to replicate succeeding channels of information for an arbitrary number of TDMA frames.

Description

1~7591 BYTE DATA ~CTIVIT~ COMPRESSION

Field of the Inven~ion The invention disclosed broadly relates to telecommuni-cations technology and more particularly relates to time domain multiple access communications.

~1~9- ~v-002 11575~1 Background of the Invention Conventional time domain multiple access (TDMA) satel-lite communication networks employ multiple radio stations which communicate through an earth satellite repeater by transmitting time-synchronized bursts of xadio energy relative to the repeater and which receive a time multiplex composite of bursts containing corre-sponding modulated in~ormation from the repeater. In TDMA operations, multiple ground stations associated with radio signaling nodes transmit bursts of time concentrated information signals on a shared carrier frequency spectrum and receive the same information signals after repetition by the satellite repeater on a shifted carrier frequency spectrum. Each ground station is assigned a particular time slot in a con-tinuum of recurrent frames for transmission of its bursts and for the reception of its own bursts and the bursts of other stations. The bursts intPrleave at the satellite in close time formation without overlapping.
Each earth station includes connections to incoming digital lines originating from terrestrial sourcesO
These input lines are respectively connected to digital data ports on a satellite communications controller (SCC) at the station.

The basic time assigned speech interpolation technique which the prior art has applied to voice is based upon the transmission station recognizing that the voic0 ~5A 9 ~ 0 0 2 1 1~759 ~

level to be transmi-tted is below a certain threshold and therefore no information is transmitted. The --receive side then infers that the voice level was not high enough to justify transmission and therefore inserts background noise for example to the recipient at the destination station. The prior art TASI tech-niques do not apply to a data stream which is examined for replicated bytes of information and when such replication is recognized, and no data transmitted over the medium, the recipient station infers that repli~
cation has taken place and therefore replicates the last stored byte at the receive station.

USP 2,963,511 shows a pulse code modulated stream which is followed by run length encoding word and USP 2,978,535 discloses a facsimile transmission scheme in which sample sizes of 1, 2, 4 or 8 bits are examined and then a control word sent for run length encoding of a number of bit or byte lengths for which data is to be replicated.

What is needed is an improved technique for reducing the bandwidth necessary to carry out data activity com-pression in a TDMA satellite communications network.

~9- d~ 002 ~157591 Objects of the Invention It is therefore an object of the invention to carry out time domain multiple access telecommunications in an improved manner.

It is another object of the invention to carry out time domain multiple access communications in a manner to reduce the bandwidths necessary to carry out data activity compression, in an improved manner.

~9 ~0-002 115759~

Summary of the In~ention These and other objects, features and advantages of the invention are accomplished by the byte data activity com~ression invention disclosed herein. In a TDMA
satellite communications system, the data ports at tWQ

~ 1575~ 1 different earth stations have their data rates synchro-nized. The origination port stores the last eight-bit byte of data in each 480-bit packet which is trans-mitted via the satellite. ~he last byte is compared with each of the 60 bytes of data in the next channel's MA9-~0-002 t ~5~591 worth of information received from the terrestrial source. If all of the bytes of data in the new-chann~l's worth of information are ldentical to the last byte of data transmitted from the originating port, no infor-mation is transmitted for this data port in the next TDMA frame. The synchronized data port at the re~
ceiving earth station expects a channel's worth of data to be received during the next TD~ frame. The last byte of received data for the recipient data port in the last frame is stored. If no data is recei~ed by MA9~ 002 the recipient data port in the present frame, the data port will infer that the next 60 bytes of data ln the channel which would have been received in the present frame are each replications of the stored last byte o data. The receiving port then replicates the last byte of data 60 times and delivers it to the recipient terrestrial receiver connected to the data port. The transmitting data port will continue to not transmit succeeding channel's worth of data for every new channel whose bytes are the replication of the last MA9-8~-002 1 ~57~9 ~
g byte stored from the last frame. The recipient data port at the destination earth station will continue to infer that the succeeding channels which are not received from the originating station are in fact replications of the last byte stored from khe last received channel, for every TDMA frame which does not contain a transmission from the originating data port.
Thus, without the necessity for transmitting control information such as a VAC mask to afirmatively signal the destination data port that byte replication is to be carried out, the destination station will continue to replicate succeeding channels of information for an arbitrary number of TDMA frames.

~9-80-002 l 15~5~

Description of the Figures These and other objects, features and advantages of the invention will be more fully appreciated with reference to the accompanying figures.

S Figure 1 shows a transponder relative to the earth.

Figure 2 illustrates the TDMA superErame format~

Figure 3 is an overall block diagram of a satellite communications controller station in the TDMA network.

Figure 4 is a functional block diagram of the digital switch architecture in the satelli-te communications controller.

Figure 5 is a functional block diagram of the organization for the transmit and receive burst buffers.

Figure 6 (which appears on the page containing Figure 1) is a schematic representation of the switch control memory organization.

Figure 7 is an illustration of the voice port transmit operation.

Figure 8 is an illustration of the voice port receive operation.

1 ~5~5~ 1 Figure 9 is a schematic illustration of message routing ~o~ a 56 Xbps data port operating point-to-point.

Figure 10 is an illustration of the format during one superframe for the port channels sent for the 56 Kbps port of Pigure 9.

Figure 11 is a schematic representation of the message routing for intranodal communication on an even SC~
scan.

Figure 12 is a schematic illustration of the message routing for intranodal communication during an odd SCM
scan.

Figure 13 is a schema~ic illustration of the switch control memory.

Figure 14 is a functional block diagram of the burst prioritization mechanism.

Figure 15 is an illustration of the organization o the burst priority RAM.

Figure 16 is an illustration of the transmit list structure in the burst priority RAM.

Figure 17 is a timing diagram of the operation of the burst prioritization mechanism.

Figure 18 shows an overall block diagram of the digital data port.

Figure 19 is a functional block diagram showing the signal path from a transmitting data port to a receiving data port via the satellite transponder.

Figure 20 shows the transmission pattern generators in a data port.

Figure 21 shows the receive pattern generator in a data port.

Figure 22 is a timing diagram of the data port selection by the digital switch.

Figure 23 is a timing diagram of the data port synchronization pulses.

Figure 24 is a timiny diagram of the transmit and receive data slots for a 9.6 Kbps port.

Figure 25 is a functional block diagram of the transmit side of the data port.

Figure 2~ (which appears on the page containing Figure 18) is a functional block diagram of the data port transmit buffer.

Figure 27 is a functional block diagram of the receive side of the data port.

~ 1575~ ~

1 Discussion of -the Preferred Embodimen-t TDMA System Overview A schematic illustration of the rela-tive posi-tion of the earth stations and the transponder sate:llite for the time domain multiple access (TDMA) satellite communications system is illustrated in Figure 1. Subsidiary earth sta-tions 1 and 2 and the reference station 3 on the surface of the earth 4 communicate via the synchronous satellite transponder 5 which orbits at approximately 22,500 miles above the surface of the earth 4, in a geo-synchronous orbit. The reference station 3 maintains a uniform tim-ing for the subsidiary stations 1 and 2 and assigns the traffic channel allocations to the subsidiary sta-tions 1 and 2 as is described in the Fennel, et al Cana-dian patent application no. 356,155 Eiled July 14, 1980 and assigned to the assignee of the present application.
The TDMA communication between the earth stations 1, 2 and 3 is carried out employing a format such as is shown in Figure 2. Each earth station includes connections to incoming digital lines 10 and voice lines 12 originat-ing from terrestrial sources. These input lines are respectively connected to digital data ports 14, 16 and 18 and voice ports 20 on a satellite communications con-troller (SCC) 22, shown in functional block diagram in Figure 3. The SCC 22 is a computer controlled satellite communications switching system which employs digital transmission techniques in the time division multiple access format shown in Figure 2, which is output to a 1~A9-80-002 11575~1 ~ 19-hurst modem 24. On a real time basis, the burst modem

2~ encodes ~he baseban~ sign~ls received from the satellite communications controller 22 and interfaces with radio frequency equipment 26 at an intermediate frequency. During reception, the burst modem 24 decodes the signal~ received from the RF equipment 26 and - interfaces with the SCC 22 at a baseband frequency. The burst modem 24 is gated on and off during transmission by the SCC 22. The burst modem 24 has a low duty cycle with the on period burst being interleaved with that of the other earth stations on a time sharing basis with the same carrier frequency, consistent with the ~DM~
mode of operation.

As is shown in the format of Figure 2, time at the satellite is divided into 15 millisecond units called frames. Each earth station 1, 2 and 3 commu~icating with the transponder 5 is assigned, by the reference station 3, a portion of the frame in which to transmit its traffic burst. For example, subsidiary station 1 will transmit its traffic burst 7 to the satellite transponder 5 on a first frequency and the satellite transponder 5 will retransmit that traffic burst at a second, noninterfering frequency over the paths 6 and 8 to the other earth stations 2 and 3, respectively, in the network. Each traffic burst is received by all earth stations in communicating on the same transponder frequencies. The amount of time assigned for each earth station's traffic burst may be different for each earth station and also may vary over time. The length of time assigned to each earth station is determined by a demand assignment mechanism disclosed in the above-cited Fennel, et al. pa~ent application. That demand as-signment mechanism considers the traffic requirements of each earth station and of the total network to determine

3~ on a statistical basis the amount of time each earth station will ~e assigned in a fraNIe.

~9-80-002 ~ 1575~ l As is shown in Figure 2, a frame consists of a fixed time period allocated for transmission of network con~rol and synchronization information and for trans-mission of traffic, from the active earth stations in the network to one or more other earth stations in the networ~. The 15 millisecond frame is divided into two segments, the control and the traffic fields. Bursts of information from each of the ground stations are trans-mitted on a time division multiple access ~asis in each frame~ Each burst contains units of information called channels which consist of 512 binary bits each.

'rhe first part of the frame is the control field. The control field i9 10 . 5 channels in length. The frame control field consists of the frame reference burst (FRB) and five transmit reference bursts (~P~). The F~B
is a 2.5 channel burst plus one-half channel of guard time, transmitted once each frame by the refërence station. It contains assignment information for 21 earth stations and marks the beginning of each frame.
The FRB is used by the SCC 22 at each ground station to maintain frame synchronization.

The transmit reerence burst is one channel burst plus a one-half channel of guard time transmitted by each ground station once every 20 frames, called a super-frame, as is shown in ~igure 2. Each ground station isassigned a fixed position in one of the frame control fields into which it bursts its transmit reference burst. Each SCC 22 at each ground station uses its transmit reference burst to maintain the transmit clock synchronization. Each SCC 22 also uses its transmit reference burst to transmit demand requests for a transponder capacity, to the reference station 3.

M~g-80-002 I ~$759 1 With reference to the format of Figure 2, the remainder OI . the frame after the control field is the traffic segment. The traffic segment consists of a single traffic burst from each earth station 1, 2 and 3. The length of a traffic burst is variable. Its length and position are assigned in the frame reference burst by the reference station 3. ~he traffic bursts are used by the earth stations 1, 2 and 3 to transmit traffic and signaling information. During initial transmit acqui-sition, the transmit reference signal is sent by a localearth station in the traffic field to determine the range to the satellite. That part of the traffic field which remains after all of the subsidiary stations have burst is called the unassigned field.

A frame group consists of five frames and has a period of 75 milliseconds. A frame group is the timing basis for the transmission of the burst assi~nments to all subsidiary stations in the transponder. The frame group consists of five frame reference bursts with each containing 105 burst assignments. The frame group also contains slots for 25 transmit reference bursts from the respective 25 subsidiary stations to the reference station.

As is shown in Figure 2, a superframe consists of four frame groups and has a period of 300 milliseconds. The superframe is used as the timing basis ~or the transmit reference bursts and for changes in the traffic burst assignments. Each earth station transmits i~s transmit reference burst once every superframe. The reference station 3 transmits a complete set of assignments which is repeated four times in a superframe. New assignments become effective on a superframe boundary, two super-frames after the transmission thereof.

~9-80-002 -1 157~ 1 Satellite Communications Controller Overview --The satellite communications controller (SCC) 22 of Figure 3 has five major functional areas, the voice ports 20 which include the associated call processor 28, the data ports 14, 16 and 18, the digital switch 30, the satellite communications processor 32 and the timing and acquisition mechanism 34 and its associated burst modem interface circuitry 36.

As is shown in Figure 3, the SCC 22 interconnects with telephone facilities via the port adapter su~system 12.
In addition, digital data lines 10 from mode~s, termi-nals, and business machines may be directly connecte~ to the data ports 14, 16 and 18. The burst modem interface 36 is provided to enable transmission of information to the burst modem 24 directed to an intended destination earth station and its SCC via the radio fre~uency terminal 26 and its antenna 38. The monitor and command loop 42 provides a communication path to the other subsystems in the earth station from the satel-lite communications processor 32 and the monitor andcommand loop terminals (MC~T) ~0 permit the other subsystems to attach to the loop 42.

The voice ports 20 are combined into six voice ports per voice processing unit (VPU) 25 or voice card which converts the analog voice signals to digital form using a delta modulation technique at 32 kilobits per second (~bps) sampling rate. Conversely, the VPU 25 converts a received digital signal to the corresponding analog voice signal for each Voice port. An example of the 30 capacity of an SCC 22 is the servicing of 63 VPUs 25 or 378 voice ports 20.

The data ports 1~, 16 and 18 are of three basic t~pes deper.dillg Oll the interface and speed of the data source.
The data ports are packaged on one of three diyital l 157~9 1 data processing unit (DDPU) types depending upon the interrace and s~eed. For rates less than 1.344 mega-bits per second (Mbps), each DDPU provides two data ports which must operate at the same rate. The rate is selected under program control. For 1.344 and 1.54~
r~pS, each DDPU supports one data port. As an example, the SCC 22 can support as many as 126 data ports or 63 DDPUs and the mix of VPUs and DDPUs, providing the aggregate bandwidth is less than the total SCC band-width of 12.288 Mbps.

The voice ports 20 and data ports 14, 16 ànd 18 share a common bus 44 to the digital switch 30. The digital switch 30 synchronously samples each port 14, 16, 18 and 20 periodically in a rotating fashion buffering information to be transmitted and routing buffered received information to the appropriate port. The common bus 44 is one eight-bit byte wide and full duplex permitting the simultaneous reception and transmission between the ports and the digital switch 30.

For a convenience, the basic bit rate for the ports in the SCC 22 is defined as the 32 Kbps sampling rate of the voice ports 20, so that all data ports 14, 16 and 18 ~ill be generally referred to herein as being comprised of as many voice-equivalent ports as the magnitude of their respective data rates is related to the magnitude of the voice port sampling rate. For example, a data port having a data rate of 1.280 M~ps which is 40 times the basic voice port sampling rate of 32 Kbps would be considered as being e~uivalent to 40 voice-equivalent ports. A generalized ~oice-equiva}ent port will be designated by the number 21 in Figure 4 but it is to be recognized that higher sp2ed data ports are equivalent to combinations of the number of voice-equivalent ports 21 having an aggregate data rate whichis an integral multiple of that for the basic voice-e~uivalent port 21.

r~9-80-002 1 15759 ~

The digital switch 30 is shown in more detail in the fl~nctional block diagram of Figure 4. The digital switch 30 is under the control of the satellite com-munications processor (SCP) 32. The SCP 32 is a stored program general purpose digital computer and controls a connection matrix within the digital switch 30, called the switch control memory (SC~I) 50~ The SC~I 59 es-tablishes a correspondence between a particular port 14, 16, 18 or 20 and the address of a connected port at the destination earth station's SCC 22. The SCP 32 control over the SCM 50 is generally indicated by the digital switch addressing and controls 31 shown in Figure 3. The digital switch 30 appends the port àddress to transmitted information and directs received information to the addressed port. By appropriately loading and unloading the SCM 50, the SCP 32 can establish point-to-point, multipoint, conference, and broadcast connections and route information to other ports 21 intranodally within the local SCC or inter-nodally to any other SCC 22 in the TDMA network. TheSCP 32 can also direct busy and dial audible tones from a read-only storage 46 to any voice port 20.

Signaling lnformation derived from the E and PI leads for voice is routed to the SCP 32 via the call processor 28. The SCP 32 accumulates the signaling information and establishes a connection with the destination SCC
22 using a software protocol.

Provision may aiso be made within the SCC 22 of Figure 3 to permit dual tone multifrequency and multifrequency (DTMF and MF) converters 48 to be connected between dedicated voice ports 20 and the call processor 28.
The converters 48 which are transmitters and receivexs, permit the conversion of DTMF/MF tones to a digit and, conversely, a digit to corresponding tone. The digit ,~ i processed by the call processor 28 in the same way as a normal rotary dial digit. By intranodally con-11575gl necting the DT~lF/~F trunk voice port to a voice port dedicated to a converter 48, converted DT~5F/~ digits can be routed between the trun~ and the SCP 32 via the call processor 28.

The timing and acquisition mechanism 34 in Figure 3 controls the transmission and reception of information between the burst modem 24 and the digital switch 30 via the burst modem interface 36. The timing and acquisition mechanism 34 also provides cloc~s for digital data ports 14, 16 and 18 and internal clocks for all areas of the SCC 22 which are synchxonized with the node designated as the reference station 3. The timing and acquisition mechanism 34 also provides the initial acquisition of the satellite under program control by the SCP 32 and insures proper ~urst synchro-nization to the satellite 5.

The monitor and command loop 42 is driven and termi-nated by the SCP 32 and used to gather status, monitor and control the other subsystems in the earth station.
The monitor and command loop terminals (MCLT) 40 permit the subsystems to attach to the loop 42.

The system management facility 52, shown in Figure 3, which controls the network, is connected to each SCC 22 via the satellite 5 through a dedicated data port and, as an alternate path, through the public switched telephone network to an auto-answer modem connected to the SCP 32.

Flow of Voice Traffic in the SCC
.

The voice ports 20 are combined si~ at a time into voice processing units 25 which convert incoming analog signals for each voice port to a 32 Xbps digital bit stream in a manner simi}ar to that descri~ed in the ~9-80-002 ~57591 ~ 21-copending Canadian patent application by Hallett, et al, serial number 337,634, that pa-tent application being en- ¦
titled "L~yarit ~ c CcmpHnded Delta Mbdulator," filed Octo ~ 15, 1979! and assiyned to the instant as-5 signee. The voice processing unit 25 will format this resultant bit stream into eight-bit bytes which are sent to the digit~l switch 30 once an analog connection has been established. If the connection is internodal, that is to another voice port 20 at another earth 1~ station's SCC 22 via the satellite transponder 5, the byte from the voice port 20 at the transmitting lo-cation enters the transmit burst buffer 54 shown in Figure 4, which is located in the digital switch 30, where 60 bytes from the voice ports 20 are accumulated, 15 plus a 32 bit destination address. The complete block of 512 bits, 32 bits for the destination address and 480 bits representing the voice signal, will be transferred from the transmit burst ~uffer 54 to the burst modem 24. Alternately, if the connection is 20 intranodal, that is to another voice port 20 within the same SCC 22, the byte goes to the intranodal buffer 56 o of Pigure 4 in the digital switch 30 for transmission to the local destination voice port 20.

The above process is reversed for voice signal6 being 25 transferred to the port adapter subsystem 12 from the SCC 22. The voice processing unit 25 will receive the bytes, representing voice signals from a distant earth station's SCC 22 or alternately from another voice port 20 within the same SCC 22, ~ia the digital switch 30.
30 These bytes are processed at a 32 Rbps rate and con-verted back to an analog signal in the voice processing unlt, representing the original analog signal. The voice processing unit 25 has the capability of simul-taneously processing the receive signals for six voice 35 ports 20. When a voice port 20 is idle in an on-hook CO,.ditiOIl, an alternating one/zero pattern will be injected into the voice port unit demodulator which wiil result in an idle noise level.
~.

~9-80-002 I ~S759~

The voice processing unit 25 also provides for a voice activity compression ~AC~ function fox each voic~ port 20. The purpose of the VAC function is to minimize the required s~tellite link channel capacity be ween different SCCs 22, by not sending the resultant digital blocks when the lack of voice activity is detected on the incoming analog voice signals. The voice process-ing unit 25 receiving the dlgital blocks will fill in the bit stream for con~ersion to analog signals, with digital blocks repxesenting background noise, when the VAC function occurs at the sending end voice processing unit. The normal receiving rate is 480 bits every 15 milliseconds, that is every TDMA frame, without any VAC
function.

Flow of Di ital Data Traffic in the SCC
g The digital data ports 14, 16 and 18 are capable of communicating with business machines and modems~ The digital data processing units (DDPU) support a variety of data rates and have a modularity of either one of two data ports per DDPU. A first type of digital data processing unit 14 can serve as a data port for data rates of 2.4, 4.8, 9.6 or 19.2 Kbps. A second type digital data processing unit 16 can serve as the data port for 56, 112, or 224 Xbps data rate. A third type digital data processing unit 18 can serve as the data port for 448, 1,344 and 1,544 Kbps data rates. The se- _ lection of a data rate is programmably set by the SCP
32. The first and second type digital data processing units 14 and 16 can serve as two data ports each. The third type digital data processing unit 18 can serve as a single data port. The SCC 22 can support as many as 126 data ports, for example, provided that the aggre-sate data rate does not exceed the 12.288 Mbps total digital switch bandwidth of the SCC. A data buffer in each data port pro~ides elasticity to compensate for the differences between the external interface timing 1 1~7~g ~

an~ the internal SCC timing and also accumulates information in 480 bi~ bloc~s between the port and the' digital switch 30. Information is transferred between the port and the digital switch 30 via the ~yte wide S transmit receive common bus 4~. Forward error cor~
recting codes can be applied selectively to the data ports under the SCP program control.

Data activity compression (DAC~ is provided for each data port 14, 16 and 18. DAC is analogous to VAC, since information is not transmitted if each byte in the frame is identical to the last byte transmitted in the previ-ous frame. When the destination SCC fails to receive a block as expected, it repeats the last byte previously received for the duration of that block. In this ~ay, the satellite link channel capacity is conserved by not transmitting idle characters and repetitive information.

Overview of the Digital Switch The principal function of the digital switch 30 is to support the transfer of traffic among the ports 21 both intranodally within a single SCC and internodally between separate earth station's SCCs. The digital switch 30 interfaces with the ports 21 via the byte wide full duplex transmit/receive bus 44 which is capable of, supporting 384X32 Kbps full duplex. A byte of trans-mitted information acquired from a port 21 over thetransmit bus 44a is retained in the intranodal buffer ' (INB) 56 of Fi~ure 4. This b~te can subsequently be delivered via the receive bus 44b to another port 21 connected intranodally to the first port. The byte of transmit information is also retained in the transmit burst buffer (TBB) 54, where transmit bytes from the same port 21 are accumulated into 60 byte bloc~s which is equivalent to a channel, prior to transmission to the satellite 5.

~9-80-002 1 15759 ~

In a given TD~ frame, not all active ports 21 require the transmission of a channel or channels of inf~r-mation due to voice activity compression (V~C) and data activity compression ~DAC). Advantage is taken of this fact and, as a result, the SCC 22 will have fewer channels allocated to it than would be re~uired if the ports 21 operated without VAC and DAC. It is therefore possible that the number of channels to be sent may eY~ceed the number allocated to the SCC 22 at a par-ticular earth station. Those ports 21 with channelswhich require transmission but which were not sent or referred to as being "frozen-out." Because freeze-out is a possibility, the ports 21 are assigned a relative priority to assure that information with the highest requirement for integxity is sent first.

Traffic to be sent to the satellite 5 can be error protected using the forward error correction (FEC) and cyclic redundancy code (CRC) encoder 58 of Figure 4, the encoding of which is a selectible option for each port 21.

All traffic channels to be sent to the satellite 5 are appended with a destination address and serialized by symbol to the burst modem interface 36. Upon receipt of a traffic channel and subse~uent to its error correction, the destination address is examined by the receive address interpretation mechanism 60 to de- _ termine if the associated channel of information is destined for this SCC. If the channel of information is in fact destined for this SCC, the channel is placed in an elastic buffer 62 of Figure 4. The elastic buffer 62 is employed to decouple the receive path from variatiOns in receive timing due to eccentricities and variations in ~he inclination of the ~rbit of the satellite 5.

~9-80-002 1 1575~ 1 Received channels which have passed through the elastic bufCer 62 are moved into the receive burst buffer (RBBY
64. The contents of the RBB 64, the INB 56 and the tone ROS 46 which contains specific audible tones, are the potential sources of receive information for each port 21 in Figure 4.

The satellite com~unications processor (SCP) 32 con-tains a control program which accepts call messages and allocates satellite transmission resources locally.
Call information is received from a local trunk via E
and M signaling, and from a distant SCC via the common signaling channel from the satellite 5. Connections are made by passing control information to the digital switch 30 via the digital switch addressing and con-trols 31. The SCP control program also continuouslycollects hardware status information and call activity information for transmission to the system management facility (SMF) 52.

The system management facility (S~) 52 has indirect monitoring and contro-l capability over the SCC hard-ware. An ~MF communications controller is the primary station in the data link 66 connecting it to each respective SCC 22, and periodically polls each SCC 22.
The data link 66 is a dedicated, multidrop satellite circuit.

- Detailed Description of the Digital Switch .. . .
Turning now to a more detailed description of the operation of the digital switch, the digital switch 30, shown in Figure 4, supports the functions of moving information from the voice and digital data ports to ~he burst modem and vice yersa, supports intranodal connections between ports, supports conferencing and multipoint data connections, ar,d delivers audible tones to the voice ports. All of these operations are con-~9-80-002 ~57~1 ~2G-trolled indirectly by the SCP 32 via parameters which are specified by the SCP and retained in the swi-tch control memory (SCM) 50. These parameters identify a specific local port 21, where information from that port is to be retained prior to transfer (to either a local port Yia the intranodal buffer 56 or to the burst modem via the transmit burst buffer 54), and the source of information which will be going back to ~he local port (that is the intranodal buffer 56, the receive burst buffer 64, or the tone ROS 46).

The VPUs 25, each with six voice ports 20, and the data ports 14, 16 and 18 are mounted on voice/data boards labeled 27 in Figure 5, within the SCC 22. Figure 5 illustrates the bus connection between the voice/data boards 27 and the transmit burst buffer 54, intranodal buffer 56 and receive burst buffer 64. A transmit bus 44a connects the voice/data boards 27 to the transmit burst buffers 54 and the intranodal buffer 56. The output of the transmit burst buffers 54 is connected through the output bus 45 to the FEC encoder 58 and transmit source selection mechanism 68.

The receive bus 44b connects the inputs of the voice/
data boards 27 to the output of the tone ROS 46, the output of the intranodal buffer 56, and the outputs of the receive burst buffer 64. The inputs of the receive burst buffer 64 are connected by means of the bus 47 to the elastic buffer 62.

The switch control memory (SCM) 50 has as the contents of each of its RAM locations, the identity of a local port, the type of port identified, the buffer location (intranodal buffer or transmit burst buffer partition) in which data from a port is retained prior to trans-mission, and the buffer location (intranodal buffer or receive burst buffer ~artition) in which receive data is held prior to delivery to the port, the identity of ~ 80~002 I 1~7~ 1 an audible tone to be delivered to the port and ad-ditional controls. Each SCM RAM location is six byte~
long with the bytes labeled zero through five. Table I
indicates the significance of each byte in the SCM word format.

57~ 1 U~ : ::
a) a~ ~
m m æ
a~
m a) ~ o _ ~`
U~

~ o C~ o h O P~
~

~9-80-002 ~ 157~g 1 - ~ 9 -Each of the SCM bytes in the SCM word contain eight bits. There are 420 R~ locations or entries in the SCM 50. An entry is accessed in the SCM once every 595 nanoseconds. The entire SCM 50 is scanned in 420Y~595 nanoseconds or 250 microseconds. This is referred to as the SC~I scan time. A11 420 SCM entries are selected independent of the actual number of ports 21 installed on a particular SCC.

The ordering of the SCM entries is shown in Figure 6.
There are 384 SCM entries which are used to transfer data to/from the ports 21. Each of these port access entries accept a byte of information from a specific port 21 and delivers a byte of information t~ that port 21 every 250 microseconds. Therefore, an SCM entry accepts/delivers data from/to a port 21 at eight bits/
250 microseconds which is equivalent to a 32 Kbps data rate. The data bandwidth of the bus 44 is therefore 384X32 Kbps which is 12.288 Mbps. The times on the transmit/receive bus 44 associated with these SC~I
entries are referred to as port access slots.

The remaining 36 SCM entries are set aside to provide the SCP 32 with an oppor~unity to pass co~trol inor-mation to the ports 21 or to update the SCM 50. Six of these 36 SCM entries are set aside in order that the SCP 32 can transfer a byte of control information (referred to as status) to a specific port 21. Six of these status entries are required in order to assure the SCP access to any of the six voice ~orts 20 as-sociated with a voice processing unit card 25. The times on the transmit~receive bus 44 associated with these six SCM entries are referred to as por~ status slots. The other 30 of the 36 SC~ entries are s~t aside in order that the SCP 32 can update the SCM 50.
Any six byte SC~I entry can be updated during any one of these 595 nanosecond slots. The times on the transmit/
receive bus 44 associated with these 30 SCM entries are 1 1~75~ l referred ~o as the SCM update slots. These entries are normally set to zero and are not used. Howevex ~lhen ~he SC~l 50 is conflgured ~ith six SCM update slots, the 24 update slots which are not adjacent to status slots can be used as port access slots. The SCM hardware can treat all 30 o these entxies as port access entries if no SCM update is pending, to increase overall bandwidth.
Table II shows the SCM entry format for the CCM byte zero through five, each byte containing eight bits of control information.

~ ~ $75~1 . SCkl ~NTRY FOR~AT ., SCM BYTE O
hen Bit 0 = 1, bits 1 through 7 identify a por~ to be selected olce or Data Port Selection When Bit 0 = 1, then Bits 1-2 : port board address 3-6 : port card address 7 : digital data port address (i.e. port 0 or 1) (The Digital S~itch is structured to support 384X32 K~ps ports. The ports to be selected and the order in which they are to be selected are specified in the SCM. The seven bit port address is decoded to select a board and one of 16 cards within that board. The seventh bit is used to identify one of two ports associated with a digital data card).
hen Bit 0 = 0, bits 1 through 7 identify alternate functions to be performed by the SCM
lternate Decodes of Byte 0 When Bit 0 = 0, then a. 0 > 3 > 4 : test card select Bits 1-2 : identify the board containing the test card~
Bits 5-6 : must equal 0 0 Bit 7 : reserved b. 0 ~ 3 > 4 : Mode Set Command (this command is valid only in a port status entry).
Bit 5=0 : SCM su~ports 30 "SCM update slots"
Bit S=1 : SCM suppor~s 6 "SCM update slots"
c. 0 > 3 > 4 : force errors d. 0 > 3 > 4 : SCM invalid Reserved for program ~A9-80~002 ~1575~

SCM ~NTRY ~'OR~T
(continued) ~it 0: Satellite active l: apply FEC
2-fi: poxt type code defined as follows:
000: 2.4K deferrable da~a port -- 00l: 4.8K deferrable data port 0l0: 9.6K deferrable data port 0ll: l9.2X deferrable data port l00: diasnostic code l0l: unused ll0: voice port lll: non-de~errable data port 5-7: reserved (must be zero) : SCM B _ _ Bit 0: port wrap l: reserved 2: use RBB
3: use INB

4: intranodal conference

5: not last partition user

6-7: INB/TBB/RBB partition address (2 most significant bits) SCM B _ 4 Bit 0-6: INB/TBB/RBB partition address (7 least significant bits)

7 : conditional write Note: For status entries, byte 4 is loaded with the status to be sent to the port. (See SCM ORGANIZATION below.) When SCM byte 0 indicates some state other than mode set, then SCM byte 5 is defined as follows:
Bit 0-2: reserved 3-7: tone address field When SCM byte 0 indicates the mode set state, then SCM
byte 5 is defined as follows:
Bit 0: ignore tone error Bit l: ignore RBB error Bit 2-7: identifies the ~50 usec boundary of the transmit cloc~; on wllich the receive frame sync should be raised.

~9-80-002 ~157~91 The operation o~ the SCM 50 in carrying out voice port selection can be exp].ained as follows. Each voice card 25 supports one encode/decode module tCODEC), which in turn supports six voice ports 20. Each CODEC multi-plexes the output of six voice ports 20 onto the trans-mission bus 44a, as is shown in Figure 7. A new byte of information from a given voice port 20 is available for transmission every 250 microseconds. A byte of information from one of the six voice ports 20 as-sociated with a given voice card 25 is available every250~6 or 41 microseconds. Operations on the receive bus 44b are similarly multiplexed. Figure 7 is a representation of the voice card 25 and the operations that occur during one 41 microsecond period when, or lS e~ample, voice port zero is capable of pl.acing a byte on the transmit bus 44a and accepting a byte from ~he receive bus 44b, shown in Figure 8.

All of the voice cards 25 are in frame synchronization;
that is, transmit frame synchronization causes all voice cards 25 to make port zero available to the bus 44 simultaneously. All voice ports labeled 1 will be available to the bus 41 microseconds later, and etc. A
specific voice port 20 can be selected in any one of the sixty-four 595 nanosecond port access slots that occur during the 41 microsecond period when that voice port is accessible.

The SCM 50 is also in frame synchronization. The bus slot counter 70 of Figure 13, which addresses ent~ies in the SCM 50, is re~urned to 0 at transmit frame sync time, thereby selecting the 0-th entry of the SCM 50.
This 0-th entry will be selected again, 250 microseconds later after a complete scan of the SCM 50. The receive timing will be adjusted via the digital switch elastic buffer G2 in such a manner that the receive frame sync timins, as seen ~y the voice ports 20, will occur on a 250 microsecond boundary of the transmit clock. This w l be coincldent with access to the location zero of the SC~ sn.

1 157~9 1 Therefore, the fixst sixty-four port access entries of the SC~I 50 will control transmit/recei~e operati~ns for all of the voice ports labeled as 0; ~rhe second set of sixty-four port access entries of the SCM 50 will control operations for all voice ports labeled 1, and etc.

A voice port 20 is selected 60 times in one lS milli-second frame. The G0 bytes presented to the bus ~4 as a result of these selects are accumulated in a partition of the transmit burst buffer (TBB) 54. Selected par-titions of the TBB 54 will subsequently be transmitted to the satellite 5 in the form of traffic channels.
Therefore, each entry of the SCM 50 must be thought of as developing one channel (referred to as a port channel) of information per TD~ frame. Each byte presented to the bus 44 by a voice port 20 is accompanied by an indication as to whether or not the byte exceeded the voice activity compression (VAC) threshold. Signals below the VAC threshold contain so little information that they can be ignored. A channel in which the VAC
threshold was never exceeded contains no useful infor-mation and is not transmitted from the T~B 54.

The receive burst buffer (RBB) 64 performs a buffering function for reception of informatlon from the sa~ellite 5 in a manner analosous to that performed by the ~BB 54 for transmit operations. A received channel of infor-mation destined for a local voice port 20 is buffered in a partition of the RBB 64. The 60 bytes so buffered will be subse~uently delivered to the voice ports 20 during one 15 millisecond frame. If no channel is received, the missing channel is assumed to have been subjected to voice activity compression and background noise is then delivered to the local voice port 20.

~ ~$759 ~

The operation of the SCM 50 in selecting digital data por~.s will now be described. A digital data por~ 1~, 16 or 18 may operate at one of several rates such as is shown in Table III. Table III illustrates the average port rate achieved by varying the number o~ 32 Kbps char.nels sent per frame.
. .

~A9-80-002 o~joololc~ I l l O r` ¦ O 0~ 0 0 0 O I ~
c ~-11 .

~ 0~ 0 ~r o o o o ~ o N

~ O O O O O O e K u~ ~ ¦ o o o o c ~ o ~
~ oo oo o o oo ~9 S::
a~ O o o o o o o o . u~ a) ~::) ~ ~-- O ~1 O N ~ N ~1 ~`1 15~ U~
~9 O O C O O O O O
Il~ 00 00 O O O O Ci~ 1~ CO
~I X ~r 5 0 O o ~--1 N r~l N ~ tl'l a~
O ~ O O O O O O O O O O N ~ CO 111 tD . ,C;
R -- N O O O O O O O O r 1 N N ~ 0~ Lf~ ~D U~
E~ ~i o o o o o o O --1 N ~) ~O . ~r In a~ ~1 Z lt O ~1 O N O ~1 N ~1 N ~ N N ~ ~ 00 1~ N CO CO C3 U ) ~D N
. . O

K ~ 1 ~h ~-1 ~ ~1 -1 r-~ ~_1 -1 ~1 N ~ ~r ~r ~` 1- ~1 ~1 'r Ci~ W
X ~ ~.~

~ O ~ h ~,1 0 O N N O O f~ ~ ~ ~ N N r I` 'r N ~ CO K 1/~ c,~ ~ o ~S~OH l ~
~ _ ~ ~ . l ~F~4 ~

~ ~ O ~ ~ ~ ~ 3 3 ~ r C 3 3 ~ ~ 3 ` ~ 3 O Q o l_ ~1 r Q Q ~O ~ <`I ~ H

. # CO ~D N ~O N ~ 'r ~

~Ag-80-002 1157$91 3~

1 1S75~1 An entry from the SCM 50 will support a 32 KLps full duplex data rate. It follows that a digital data port will require a magnitude of N such entries in the SCM 50 where N is the data port rate as seen at the bus 44 divided by the basic 32 Kbps data rate, with N being rounded up to the next whole integer. The data port 14, 16 or 18 is selected N times every 250 micxoseconds, - once for each associated entry in the SCM 50. The data port transmits/receives a byte as a result of each select by the SC~1 50. These data byt2s are accumulated in/retrieved from the TBB 54/RBB 64 partitior identified by each entry of the SCM 50. No reLationship exists among these N partitions in the TBB 54 (or REB 64).
Every N-th byte transmitted/received by the data port 15 14, 16 or 18 will be associated with the same partition in the TBB 54/RBB 64.

Each byte transmitted from a digital data port 14, 16 or 18 is accompanied by an indication as to whether the byte currently being transferred is equal to the last byte of the immediately preceding frame. This is referred to as the data activity compression (DAC) indication. Each byte transmitted by a digital data port is also accompanied by an indication as to whether the data port detected a carrier from its terrestrial source when the byte was acquired at the port interface.
This is referred to as the carrier detect indication.
This bit is a reflection of the state of the receive __ line slgnal detector located in the data port.

If all bytes of the channel have been accompanied by a DAC indication, the channel contains no new information beyond that contained in the last byte of the preceding frame, and is therefore not transmitted from the par-tition within which it is stored in the TBB 54. This channel can then be reconstructed at the destination digital data port at the receiving earth station by the receiving data port remembering the last byte received in the last frame.

~9-80-002 ~15759 l As can be seen with reerence to Table III, not all data speeds result in an integral number of channels:per -frame. Of those data spe~ds which do not, the data port 14, 16 or 18 varies the number of channels developed psr frame, in order to achieve the desired average data rate. The digital data port accomplishes this by sending data in only N-l of the ~ channels associated - with a particular data speed for a specific number of frames. The N-th channel select is subjected to data activity compression and, therefore, the N-th channel is not transmitted from the data port to the TBP 54 or from the TBB 54 to the satellite 5. In the next frame, all ~1 channels are transferred from the data port to the TB3 54. Table II~ shows the number of channels associated with each frame over the number of frames the digital data port must average the data rate of that data port.

Digital data port speeds of greater than 32 Kbps are referred to as non-deferrable data. At these data speeds, a digital data port develops at least one channel's worth of information per TDMA frame. The variation in the number of channels developed per frame is never greater than one for a specific digital data port. That is, it develops either M or N-l channels per frame. Several digital data ports, for example P ports, operating at the same speed will amplify this variation in channels developed, since they are in synchroni-zation. For P ports, the variation would be P channels.

Digital data ports 14 having data speeds less than or equal to 32 Rbps are referred to as deferrable data. At these relatively slower data rates, a digital data port does not develop a channel's worth of information every TDM~. frame. Several digital data ports operating at the same speed can each develop a channel's worth of infor-mation for transmission in the same frame. Thus, a ~ossible surge in traffic channel demand might occur.
This demand can be smoothed by carrying out the trans-~9-80-002 11~75~1 mission of the channel's worth of information accumu-lated in the associated partition of the TBB 54-in some frame preceding the frame in which the digital data port presents still another channel's worth of information for transmission by the TBB 54. Thus, the average data rate of such a relatively slow digital data port 14 is sustained although the frame in which a channel may be transmitted/received may vary. Digital data ports managed in this manner are referred to as deferrable data ports.

A channel of information developed by a digital data port operating in this deferrable mode is placed in an associated partition of the TBB 54. As is seen with reference to Figure 5, the TBB 54 is an A/E buffer with sufficient buffering to retain one channel in the A
side and one channel in the B side for a number of voice-equivalent ports. During one frame, the A side of the TBB accumulates channels from a number of vaice-equivalent ports. During the same frame, the B side of the TBB is available for transmission to the burst modem 24. In the next frame, the roles of the ~ side and the B side of the TBB are reversed. Th~s for illustrating the operation of the deferrable data mode for relatively low speed data ports 14, it is assumed that a channel of information developed by the data port is placed in the partition location X of the A
side of the TBB 54 during one frame and in the cor~e- __ sponding partition location X of the B side of the TBB
54 during the following frame. In this manner, it is certain that the channel of information will be available for transmission during any frame. This channel of information is serviced at the lowest priority level until the frame occurs in which the deferrable data port 14 develops a new channel's worth of ir.formation and places it in the 3 side of the TBB
54. If the old chanr.el's worth of information has not yet been sent by the ~ side of the TBB 54, the old ~9-80-002 1 1~7$91 channel of information is serviced at the highest data port priority level to assure that the channel ~s transmitted from the TBB over the burst modem 24 so that the integrity of the communications is maintained.

By deferring low speed data transmission in this manner, the demand f~r transmitted channels can typi-cally be smoothed across many frames by using un-occupied channels in the TDM~ burs~ which would other-wise be unused. A number of such unoccupied channels 1~ in the TD~ burst will normally be available to low priority ports due to variations in the number of transmit channels required per frame for data speeds greater than 32 Kbps and those channels not required as a result of voice activity compression and data ac-tivity compression generating unoccupied channels inthe TDMA burst.

Information buffering in the transmit operations is explained as follows. A port 21 selected by the SCM 50 will place a byte of information on the transmit bus 44a. If the selected port 21 is a voice port 20, the information byte is accompanied by an appropriate VAC
indication. If the selected port is a digital data port 14, 16 or 18, the information byte will be ac-companied by an appropriate DAC and carrier detect indications. The contents of the transmit bus 44a are written into the intranodal buffer (INB) 56 and the transmit burst bùffer ~TBB~ 54 partition identified by~
the entry in the SCM 50 which selected the ports 21.

Figure 9 is a schematic representation of the message routing or an example 56 Kbps data port 16 and Figure 10 illustrates how a channel's worth of information developed by the digital data port 16 is formatted during one TD~A super~rame, when the 56 Kbps digital data ~ort lG operates point-to-point via the satellite 5. A 56 Kbps digital data port represents two voice ~9-80~002 ~ 15759 1 equivalent ports 21 ~that is N~2~. ~or Figures 9 and 10, Pl and P2 represent the partitions in the intra-nodal bu~fer 56 and the transmit burs-t buffer 54 identified ~y the two ent~ies in the SCM 50 associated with this particular port. The port 16 will tran~fer one channel's worth of information to the digital switch 30 in the first TDMA frame of the superframe and two channels' worth o~ information in the next three TD~I~ frames, as is shown in Table III. The pattern will then be repeated. The resultant average data rate is then 56 Kbps. In those TDMA frames in which the port 16 is transferring one channel's worth of infor-mation, the select generated by the second entry of the SCM 50 is responded to by the port 16 with a DAC
lS indication. Thus, the INB/TBB partition P2 will be interpreted to contain no useful information and will not be transmitted. The select as~ociated with the first entry of the SCM 50 is responded to by presenting information received from the terrestrial interace to the port 16. As a result, the INB/TBB partition Pl will contain port information and will ~e transmitted (assuming it is not subjected to DAC). The receiving port at the destination earth station is in synchro-nization with the transmitting port 16 and expects only one channel of information.

In those TD~A frames in which the 56 Kbps port 16 is transferring two channels' worth of information, the __ selects associated with the first/second entries of thè
SC~ S0 result in data bPin5 retained in the Pl/P2 TBB
partitions, respectivelY. Again, the receiving port at the destination location is in synchronization with the transmitting port 16 and expects two channels~ worth of information. ~ destination port which does not receive the anticipated two channelsl worth of information will assume those two channels to have been subjected to L,~C .

~9-80-002 1 157~1 In summary, it is the data port 16 which manages the presentation of the channel's worth of infor~ation to the digital switch 30 in order to achieve the desired average data rate~

The intranodal buffer (INB) 56 buffers all information passing among ports 21 associated with the same SCC 22.
The INB 56 is an A/B buffer with sufficient buffering to retain one byte in the A side and one byte in the B
side for each of the 384 voice equivalent ports se-lected by the SCM 50. During one 250 microsecond scan of the SCM 50, one side of the INB 56, for example the A side, is loaded with one byte from each of the 384 voice equivalent ports selected by the SCM 50. The other half of the INB 56, that is the B sic'.e, is available as a source of receive information (alongwith the tone ROS 46 and the RBB 6~) for tAe ports 21.
In the next scan of the SCM 50, the roles of the A side and B side of the INB 56 are reversed. The VAC or carrier detect indication accompanying each transmit byte from ports 21, is retained in an array referred to as the INB-loaded array 72. The INB-loaded array 72 is an A/B buffer with 384 partitions such that a VAC or carrier detect indication is retained for each byte in the INB 56. The contents of this array influences the choice of the source of receive information for the port 21.

The SCM 50 associates a voice equivalent port 21 with a single partition of the TBB 54, the RBB 64, and the INB
56. The partition of the INB 56 with which the voice equivalent ports 21 is associated is alternated between two partitions by inverting the low order bit of the partition address on odd scans of the SCM 50, that is every first, third,...59th, scan of the SCM 50. Two ports 21 communicating intranodally within the same SCC
r 2'` I are assi~-ned h even/odd pair of partitions (for a voice port, N equals one). Therefore, in one 250 ~ 157~ 1 microsecond scan of the SCM 50, a port 21 writes N
bytes into the IN~ 56 (which will be read by the other`
poxt in the following SCM scan) and it reads N bytes (which we-e written by the other port into the INB in the preceding SCM scan). Figures 11 and 12 are a representation of two voice ports, X and Y, communi-cating intranodally. The ports X and Y are assigned - partitions P (which is of even value) and P~l (which is of odd value), respectively. In even numbered scans of the SCM 50, the port X writes into the location P on the A side of the INB 56 and reads from location P of the B side of the INB 56. Similarly, the port Y writes into the P+l location of the A side of the INB 56 and reads from the P+l location on the B side of the INB
5~. In the following scan of the SCM, the port X
writes into the P+l location on the B side of the INB
56 and reads from the P~l location on the A side of the INB 56. Similarly, the port Y writes into the P
location on the B side of the INB port 56 and reads from the P location on the A side of the INB 56. This alternation between a pair of partitions, as is illus-trated in Figures 11 and 12, occurs only in the INB 56 and not in the TBB 54 or the RBB 64. In this manner, a local port has access to information placed into the INB 56 in the preceding SCM scan by another local port with which it is communicating. Thus, a single par-tition address in the SCM 50 indicates where infor-mation is to be buffered for transmission either in the INB 56 or the TBB 54 and also where information is to be obtained from either the INB 56 or the RBB 64.

The operation of the transmit burst buffer 54 is as follows. All information generated by the ports 21 which is to be sent to the burst modem 24 is accumu~
lated in the TBB 54. The TBB 54 is an A/B buffer with sufficient buffering to retain one channel in the A
sldc anu olle channel in the B side for a number of voice equivalent ports 21. During one TDMA frame, the ~ 1~7591 A side of the TBB 54 accumulates a channsl's worth o~
information from a number of voice equivalent ports ~1.
During the same TDMA frame, the B side of the TBs 54 is available for transmission of a channel's worth of information to the burst modem 24. In the next TD~
frame, the roles or the A side and the B side of the TB~ 54 are reversed.

As is shown in Figure 5, the design of the T~B 54 is modular with two TBB units referred to as a storage group, required to support 128 voice-equivalent ports 21 which are destined for transmission to the satellite 5.

An ancillary task performed by the TBB 54 is that of logically ORing together the one byte transmit bus 44a coming from each of the four voice/data boards 27 showr.
in Figure 5. A TBs storage group (TBB pair) as is shown in Figure 5 supports a pair of port boards 27 , also shown in Figure 5.

Overview of Port 3urst Prioritization Port burst prioritization for a satellite transmission can be described as follows. For a given n~ber of active ports 21, lf the port speed were the only consideration, the demand for satellite capacity would determine which channels would be transmitted. How ~-ever, an additional consideration must be the i~po-sition of voice activity compression (VAC) and data activity compression (DAC) which are employed to identify and preclude from transmission activity which appears to be either unintelllgible or redundant in order to minimize the demand for a satellite channel capacity. It should be recognized that the need to compress information only pertains to the satellite traffic since the digital switch 30 is capable of supporting all 384 voice eauivalent ports when they MA9-80-00~

1 11)7~91 operate intranodally. The results of VAC and DAC are only statistically predictive. It is possible,~-there-fore, that at times the number of channels ~o be sent e~ceeds the n~mber which have been allocated to the SCC
22. Those voice equivalent ports 21 whose channels of information require satellite transmission ~ut which are not sent, are referred to as having beer. frozen-- out. Because freeze-out is a possibility, the ports 21 are assigned a relative priority in order to assure that information with the highest requirement for inteyrity is sent first in the TDMA burst.

The SCM 50 identifies a voice-e~uivalent port 21 and associates it with a particular partition in the TBB
54. A voice-equivalent port 21 is a~sociated with one of three priority levels by means of the port type code stored in byte 2 of the SCM entry corresponding to that port. The SCM 50 scans each of the 384 voice equiva-lent ports 60 times in one 15 millisecond TD~A frame.
For each port type, particular scans are employed through the SCM to review the activity of that port type and to form threaded lists of associated par-titions in the TBB 54 which contain channels of infor-mation to be transmitted to the satellite 5. The order in which the partitions of the TBB 54 appear within a transmit list associated with a particular port type is a function of the order in which the voice-equivalent ports 21 ~"ere scanned for activity in the SCM 50.

The order of bursting within a particular transmit list is last in/first out (LIFO). The order of bursting among txansmit lists is a function of the port type, that is the relative priority.

Transmit priority levels are denominated 0, 1, 2 and 3.
Priority level 0 is the highest priority level and is the level with ~Ihich si~nzliny i.nformation channels which are originated by the SCP 32 are associated.

M~9-80-002 ~ 1~7~9 ~
-~6-Priority level 1 is the highest port traffic priority level and follows level 0 in the TDM~ burst ord~r. ;
Level 1 is the level with which digital data from data ports 16 and 18 having data rates greater than 32 Kbps is associated. It can be appreciated, however, that any port type, voice or digital data, could be placed at the level 1 priority.

An entry is placed in the level 1 transmit list if the level 1 voice-equivalent port has been active any time during the TDMA frame. In order to accomplish this, the activity indication (VAC/DAC~ associated with each byte transmitted by each voice equivalent port 21 is logically ANDed with its previous value throughout the frame. (DAC/o~f is used by digital ports to indicate lS activity.) This accumulated VAC/DAC indication is examined during the last scan of the TDMA frame (that is scan 60 of the SCM 50). If the VAC/DAC indicator is on (that is no activity indication), no action is taken. If the VAC/DAC indication is off, the identity of the partition in the TBB 54 with which the voice e¢uivalent port 21 is associated is placed in the level 1 transmit list.

The level 2 priority follows the level 1 in burst order and is the level with which voice ports are normally associated. Ihere is evidence which indicates that the loss of speech as the result of freeze-outs early in a talkspurt is subjectively less objectionable to the listener than loss of speech later in a talkspurt. As a result, the level 2 priority contains four priority 3Q sublevels based on talkspurt duration. Talkspurts whose durations have exceeded 45 milliseconds are given a higher priority than newer talkspurts in order to bias freeze-outs such that, if they occur, they tend to occur at the besinning of a talkspurt.

~3-80-002 1 15~5~ ~

The priority sublevels for voice messages is organized so that sublevel 0 is the highest priority with~n the level 2 priority group. Sublevel. 0 corresponds to a talkspurt duration of 45 milliseconds or longer, sub-level 1 corresponds to a talkspurt duration of 30 to 45milliseconds, sublevel 2 corresponds to a talkspurt duration of 15 to 30 milliseconds and sublevel 3 ccrre-- sponds to a talkspurt duration shorter than 15 milli-seconds.

The level 2 sublevel 0 is referred to as "old voice."
The other sublevels are collectivel~ referred to as "new voice." A new talkspurt will progress up through the voice sublevels until it enters the old list whe.re it will remain until the end of the talkspurt.

Priority level 3 is the lowest priority level and is the level to which deferrable data is assigned. Only data ports 14 operating below a 32 Kbps rate can be deferrable. Level 3 is actually composed of four priority sublevels, one for each data speed below 32 Kbps. The sublevel 0 is the highest of the level 3 priority group. Sublevel 0 corresponds to the 19.2 Kbps data port, sublevel 1 corresponds to the 9.6 Kbps data port, sublevel 2 corresponds to the 4.8 Kbps data port, and sublevel 3 corresponds to the 2~4 Kbps data port.

An entry is placed in the appropriate level 3 sublist if the port 14 has been active any time during the TD~1A
frame. The accumulated YAC/DAC indication provided by the port 1~ is used to determine port activity during the last SCM scan of the frame.

A level 3 demand is serviced during that portlon of the TD~ burst where surplus channel capacity is avallable ai'~er haVill~ serviced prioriti~ levels 0, 1 and 2.
level 3 port whose channel has not been transmitted ~A9-80-002 11575~1 ~48-before the beginnning of the TDMA frame in which another channel's worth of information is to be-.de- -veloped, is serviced at the level 1 priority. That is, the priority of the channel's worth of infor~.ation is raised in order to assure that the information is transmitted and the integrity o~ the communications is maintained.

Port Burst Prioritization Mechanism _ _ _ _ Figure 14 shows a detailed functional block d.iagram of the burst prioritization mechanism 74 in conjunction with the SCM 50 and the TBB 54. To gain a better appreciation of the part played by the SCM 5G in the formation of burst lists and the transmission of burst lists, the diagxam of the SCM organization in Figure 6 has been redrawn in Figure 13 to incorporate the function of the six respective bytes in each SCM entry as was described in Tables I and II. The outputs labeled port identification (ID) 78, port type 80, and ~-partition address 82 from the SCM 50 will be employed in the discussion of the operation of the burst pri-oritization mechanism of Figurz la. In addition, the slot counter 70, which is a modulo 420 countex, has a first slot count output 75 which goes ~rom 0 to 419 and accesses the correspondingly numbered 0 through 419 entries of the SC~ 50. The slot counter 70 has a second output which is the byte scan count 77, which is incremented every time the slot count 75 reaches 419. -The byte scan count goes from 1 to 60 and counts the number of bytes per channel's worth of traffic transferred from a given voice-equivalent port 21 to its corres-ponding TBB partition 54. These outputs will be con-nected to the burst prioritization mechanism as will now be e~plained.

MA9-8~-002 ~ 137591 ., ~, g The TBB partition addresses from the SCM 50 o~er line 82 pass through the par~ition register 102 and into thr~ I
address register 104 where they are used to address the ', burst priority RAM 100. Partition addresses which are to be included in a transmit list are transferred from the address register 104 to the data register 106 and from there are written into the burst priority R~M 100 - where the ordered lists of partition addresses are formed for use in bursting port trafic to the satel-lite.

The organization of the burst priority RAM 100 is shown in Figure 15. It is divided into two identical regions to permit bursting from a transmit list in one region while simultaneously forminy a transmit list of the same type in the other region. Each region contains a partition chain area 103 and 103' and an initial pointer -area 101 or 101'. The initial pointer area 101, 101' consists of a fixed location initial pointer section lOla and a burst-ordered initial pointer section lOlb.
Partition addresses are read from the burst priority R~M
100 during the traffic burst and written into the RAM
register file 122. From there, they are txansferred to the next partition register 124 which is fed to the transmit space signaling buffer 126 for the purpose of obtaining the destination address for the, next TBB
partition to be burst. The next partition register 124 feeds the TBB address register 128 which is used for addressing the TBB-54 while bursting port traffic over, the line 45 to the burst modem interface 36.

30 B asic Transmit List Formation Sequence Transmit list formation is done in the burst priori~
tization mechanism of~Fi~ure 14, in synchronism with the scanning by the slot counter 70 of the SCM 50.
Transmit lists related to data ports 14, 16 and 18 of a ~9-80-002 1 157~ l 5~
specific speed each require one pass through the SCM 50 for their formation. Transmit lists related to voice ports 20 require two passes through the SCM 50. The basic sequence oE steps involved in forming transmit lists in one pass through the SCM 50 is as follows.

1. At the beginning of the scan of the SC~': 50, the ~ data register 106 is cleared to 0.

2. As each entry in the SCM 50 is accessed by the SCM
slot count 75, the partition address 82 from that entry is loaded into the partition register 102.

3~ Each par~ition address is then transferred from the partition register 102 to the address reyister 104 with a bit called the "last entry" turned on in the address register 104.

4. A decision is made based on the state of the VAC/DAC bits 85 received from the ports 14, 16, 18 and 20, whether to include this partition address on line 82 in the list being formed. If not, no further action is taken with regard to this par-tition address. If however the partition is to be included in the list, the contents of the data register 106 is written into the location 103 of the burst priority RAM 100 specified by the par-tition address in the address register 104, after which the contents of the address register 104 are transferred into the data register 10~.

5. Steps 2, 3 and 4 are repeated for each access to the SCM 50 throughout the scan by the SCM slot count 75 from 0 through 419. If a partition ad-dress is encountered that causes the burst pri-ority R~M 100 to be written in step 4, then all subsequent transfers to the address register 104 in step 3 will be with the "last entry" ~!it off.

~9-80-002 t 157~ 1 6. ~t the end of the scan of the SC~ 50 when the SCM
slot count 75 has reached a value of 419, the contents of the data register 106 is written into t~.e burst priority RAM 100 in the fixed location initial pointer area lOla, at the appropriate location for the partic~lar list being formed.

- As a result of the above sequence, a linked list o~
partition addresses representing port activity is formed. The list header is contained in the fixed location initial pointer area lOla.

Figure 16 shows a simple example of a transmit list formed as described above. Partition addresses which have satisfied the conditions for inclusion in the list are assumed to have been encountered during the scan of the SCM 50 in the order 4-10-2-6. When partition address 4 appeared in the address register 1~4, it caused the cleared data register 106 to be stored at location 4 in the partition chain area 103 OL the burst priority RAM 100. This entry is not shown in Figure 16 since it is not considered to be part of the transmit list. Partition address 4 was then transferxed from the address register 104 into the data register 106 with the "last entry" bit on since no previous par-tition address had caused the burst priority RAM 100 to be written.

Sometime later, when partition address 10 appeared in .
the address register 104, it caused the contents of the data register 106, that is the partition address 4 with the "last entry" bit on, to be written into location 10 of the burst priority RAM 100. Partition 10 was then transferred from the address register 104 to the data register 106, but this time the "last entry" bit is off. In the same fashion, partition address 2 caused partition address 10 to be stored in location 2, and partition address 6 caused partition address 2 to be stored in location 6 ~9-80-002 I 1 S7'~9 ~

At the end of the scan of the SCM 50 when the SCM slot count 75 has the value o~ 419, the contents of the data re~ister 106, containing the par~ition address 6 with the "last entry" bit off, is stored in the appropriate fixed address initial pointer location lOla of the burst priority RAM 100. That completes the transmit list formation sequence for this particular list.

If there had been only on~ partition address which satisfied the conditions for inclusion in the list, it would have been stored in the fixed address initial pointer location lOla with the "las~ entry" bit on. If there had been no such partition addresses, the cleared data register 106 would have been stored as the initial pointer. This corresponds to a partition address 0 in the TB~ 54 which is an invalid partition address and is recognized as representing an empty list.

During bursting of the transmit list, the order of accessing is shown by the arrows in Figure 16. The initial polnter serves as the entry point to the list.
Each entry provides the address of a partition in a TBB
54 to be burst as well as the pointer to the next partition address in the list. An entry with the "last entry" bit on siynifies that the end of the list has been reached.

The elements in the burst prioritization mechanism of Figure 14 which carry out the decision as to whether a~
particular port is to be enqueued into a particular burst list will now be described. The operation can be more fully appreciated with reference to Figure 17 which is a timing diagram for burst list formation and transmission. It will be recalled from the prior dlscussion of the SCM organization and the operation of the voice ports and digital ports, that each voice port operates at 32 Kbps which produces exactly one channel's worth of 60, eight-bit bytes of information per frame.

MA9-80-0~2 ~1S7591 The slot counter 70 scans ~hrough the SCM 50 at a rake of 60 times per frame, in synchronism with the sampling in the ~oice ports 2Q. As long as there is voice activity on a voice port 20 so that the VAC 85 is not on, the burst prioritization mechanism can continuously er.queue 60, eight-bit bytes of information per frame.

- In a similar manner, high speed data ports having data rates greater than or equal to 32 Kbps, will be pro-ducing at least one channel's worth of 60 eight-bit bytes of data per frame. If the data rate for a par-ticular high speed data port is not an integral multi-ple of 32 Kbps, it will be recalled that the data port 18 will transmit either N or N-l channel's worth of information per frame to the digital switch 30 based upon a stored pattern in the data port 18. And that when N-l channel's worth of information are to be transmitted, the N-th channel's worth of information which is omitted will have substituted for it a DAC bit indication. Thus it can be seen that whenever a particular SCM entry is encountered wherein the port type 80 is indicated as being either voice or high speed data, in the absence of a VAC or DAC indication on line 85, the burst priority RAM 100 can be enabled to enter the partition address for that port into its corresponding burst list.

A different situation is encountered for those data ports which, as was previously described, are low speed, having a data rate which is less than 32 Kbps.
These data ports do not develop a channel of infor-mation every frame but accumulate a channel's worth ofdata in the buffer 14' at the data port 14 over a predetermined number of frames and only after that predetermined number of frames will the channel's worth of data be transmitted to the digital switch 30. Thus it is necessary to know in which fra~e a particular type of low speed data port can be expected to transmit its channel's worth of information to the digital s~itch 30.

~9-80-002 11~7591 -5~l-- Reference should now be made to the SCM organiz~tion shown in Figure 6 and the timing diagram shown in Figure 17 to better understand the burst list formation operation. As was mentioned before in the discussion of the SC~ organization, the SCM has 420 entries numbered from 0 through 419, which are accessed by the slot counter 70 ovar the SCM slot count line 75. Each - one of the 60 scans of the SCM slot count 75 through the SCM S0 will enable each consecutive port 21, i~entified on line 78 from the SCM 50, to transmit one eight-bit byte of information to the partition address in the TBB 54 indicated on line 82 from the SCM 50. At this point there is no defined burst order for the information which is being stored in the TBB 54~
However, the relative priority of the various types of information, that is high speed data, low speed data, voice, etc., which is being stored in the TBB, dictates that some order be imposed upon the bursting of this information to the satellite, so that higher priority information is more certain of being successfully transmitted and lower priority information can be sacrificed, if necessary. This is accomplished, starting with the 37th scan of the SCM slot count 75 through the SCM 50, tha~ is, when the byte scan count 77 is equal to 37. Beginning with the 37th scan through the SCM 50, the port type indication stored in each entry in the SCM and output over line 80 is examined. Particular scans through the SCM 50 will concentrate on a particular type of port and will pick~
out those entries in the SCM 50 under examination in that particular scan, and examine those corresponding ports 21 for past and present activity. When voice ports 20 or high speed data ports 18 are being ex-amined, only the past or present activity of that port during the frame will be examined and if activity is indicated, that particular port will have the co~res-ponding TBB partition address en~ueued in the burst priority R~M 100. If the particular SC~I scan is MA9-80~002 ~ 1575~ l examlning a low speed data port 1~, not only will the past or present activity of that port during the fram~-be examined, but recognition will be made of the frame count for the present ~rame to determine whether the S data port's transmission pattern can be expected to enable the transmission of a channel's worth of data during this frame. The operation continues until the - byte scan count 77 has reached 60 at which time the end of the frame has been reached and the burst priori-tization mechanism 74 then prepares the heads of the respective burst lists for read-out during tne assigned burst time in the next T~MA frame.

Figure 14 shows the slot counter 70 connected by means of the SCM slot count output 75 to the SC~ 50 so as to consecutively address the ~20 SCM entries. As an example of burst list formation, assume that the SCM
scan count 75 has progressed 41 times through the SCM
50 so that the byte scan count 77 has a value of 41. In accordance with the timing diagram of Figure 17, during '~~
the 41st scan, voice ports 20 will be searched fox on the port type output line 80 which is connected from the SCM 50 to the enqueue control read-only storage (ROS) 88. The VAC/DAC line 85 connected from the voice port 20 identified on the port ID line 78, is also input to the enqueue control ROS 88. If the VAC line 85 indi-cates that the port 20 is active, the enqueue control P~OS 88 will output on line 94 an enqueue enable signal which is transmitted over line 136 as a write enable signal to the burst priority F~ 100. The corresponding TBB partition address output on line 82 from the SC~ 50 is then input to the partition register 102 and will p-ogress through the address register 104 and the data register 106 so as to be enqueued in a burst list being prepared for this type of v,oice port 20 in the burst priority F~M 100. After the slot counter 70 has counted through 419 on the SCM slot count 75 during this 41st scan for the byte scan count 77, during which 1 ~575~1 the byte scan count decode ~OS 88 has delivered an enabling signal to the burst priority RAM 100, the -condition of having reached-the end of the 41st scan in the SCM 50 will be indicated over the SCM slot count line 75 to the slot count decode ROS 114. At this juncture, the slot count decode ROS 114 will signal to the list pointer control 112 that the last voice port TBB partition address is to be stored in the burst priority ~M 100 in the fixed location initial pointer address 101a corresponding to this type of voice port, as is indicated by the byte scan count 77 line input to the list pointer control 112. The initial pointer address generated by the list pointer control 112 will be entered through the register file 108 to the address register 104 and the last voice port TBB partition will be stored at that address location in the fixed location initial pointer 101a. That completes the ormation of that particular voice port list. If a voice port of that type were active during a portion of the frame but ceased activity or had intermittert activity during the ~~
frame, the voice activity memory 96 connected to the enqueue control ROS 88, will have stored the condition that there was activity for that particular voice port at least during some portion of the frame and that will satisfy the condition of port activity durlng the SCM
scan when that type of port is being examined for activity.

A similar operation- is carried out for high speed data..
ports 16 or 18.

When low speed data ports are being examined during the 56th, 57th, 58th or 59th SCM scan as indicated in Figure 17, recognition must be taken of the particular frame count for the present ~rame since, as is shown in Table III, low speed data ports transmit their channel's worth of information only during ce~tain predetermined frames in a 40 frame period of time. The frame count - 11S75~

is input on line 91 to the low speed data control ROS
90 which also has an input on the line 80' for low speed data port types whlch comes from the SCM entry for that particular port 1~. When the byte scan count 77 from the slot counter 70 indicates to the byte scan count decode ROS 8Ç that the 56th through S9th SCM scan is presently underway, indicating that a particular - type of low speed data port is under lnvestigation, then the enqueue control ROS 88 will require that the output from the low speed data control ROS 90 indicate that the desired frame count for the particular port type under investigation, be present before an enqueue enable signal on line 94 will be issued. When this circumstance obtains, then the enqueuing of that particular low speed data port's T~B partition address in the burst priority RAM 100 will be carried out as has been previously described for voice ports 20 and high speed data ports 18.

At the end of the 60th scan through the SCM when the present frame has ended, the burst prioritization mechanism 74 will reorder the initial pointers from the fixed location area 101a into a new order stored in the burst ordered initial pointer area 101b. It will then fetch the highest priority initial pointer from the burst ordered initial pointer list 101b in the burst priority ~ 100 and load it into the RAM register file 122 and from this point on, every 14th SCM update entry slot shown in Figure 6 will be used to access the burst priority RAM 100 to fetch the next list entry for bursting when the timing and acquisition controls 34 signal the burst prioritization mechanism 74 to commence the burst transmission to the satellite.

Voice Port Buxst List Formation A more detailed description of the particular operalion of the burst prioritization mechanism for carrying out the formation of voice port transmit lists is disclosed ~A9-80-002 1~5~l591 in the copending Canadian patent application 367,340-S, Eiled December 22, 1980 by J.A. Alvarez et al and en-titled "Priority Threaded Message Burst Mechanism for rDMA Communicationll~

Low Speed Data Port Burst List Formation ..
Data ports 14 operating at 2.4 Kbps, 4.8 Kbps, 9.6 Kbps and 19.2 Kbps do not produ~e a channel's worth of information every frame, as can be seen fxom Table III
and the previous discussion, and thus do not require transmission to the satellit~e every frame. ~ecause of this characteristic, efficiency in the use of the assigned satellite bandwidth may be increased by placing these ports in a deferrable mode. DeferrabLe mode operation i5 basically as fol?ows: j 1. The data port 14 trans~rs a channel's worth of information to the TBB 54 during one of the frames so designated in Table III. If a DAC bit pre-sented by the data port is turned off at any point in this frame, it will remain off until the end of the frame, indicating that some activity was present at the port during the frame.
.
2. The-burst prioritization mechanism enters the data ports' partition address in the appropriate de-ferrable data transmit ~ist in the burst priority R~ 100 if the-DAC bit presented by the data port -is off.

3. In the following frame the port re~ransfers the same channel's worth of information to the TBB 54, thus providing copies of the channel in both the A
' part of the TBB and the B part of the TBB, as was described above. An exception to this occurs every fifth frame for the 19.2 Kbps ports which transfer a new channel to the TBB 54 rather than a ~4 repeat of the channel transferred in the previous - ~35 frame.

~IA9-80-002 11575~3 ' _Sn-4. In this followinglframe also, the burst prioriti-zation mechanism begins to use, at low priority, the ~ransmit list formed in the previous frame for transmission to the sateLlite f~om the TB~ loaded in the previous frame.

5. In all subsequent frames, until the last frame involving the transfer of a new channel to the T~B
54, the data port 14 prevents the TBB 54 from being written into at its corresponding partition address and the burst prioritization mechanism continues using the same transmit list at low priority.

6. During the next rame in which the data port l~
transfers a new channel of information to the corresponding partition address in the TBB 54, the burst prioritization mechanism elevates the old transmit list containing the remaining portion of the deferred data ports which have not yet been transmitted, to a higher priority, bursting from ~o - the opposite side:of the TB9 54 to that side which is being loaded by the data port 14.

7. At the SCC 22 at.the receiving earth station, the recëiving data port 14 must be capable of handling the channel's worth of information whether it is transmitted at the earliest opportunity or at the latest. The receiving data port 14 accomplishes this by holding the channel's worth of information in a buffer 14" at the time of its receipt until the occurrence of the frame after the latest one possible, at which time it starts unloading the buffer.

The dynamically varlable priority feature for the low speed data ports is carried out by the elements shown in the detailed diagram of Figure 14. In particular, ~:157591 the low speed data pr ority ROS 120 has as an input, the frzme count 91 and the port type 81'. After bur-st lis~
formation has taken place during a particular frame and the 60th SCM scan has been completed! ~he fixed location initial pointers in section lOla of the burst priority R~M 100 are updated based on the traffic burst in the previous frame, under the control of the list pointer control 112. As each deferred data port list is re-viewed in this updatlng operation, the low speed data priority ROS 120 compares the frame count 91 to the latest frame during which the deferred must be burst before it is lost. If that latest frame has occurred, then the relative priority of the lo~ speed data port list undèr examination is increased so as to be equiva-lent to the high speed data port priority and that list will be placed in the burst ordered initial pointer area lOlb just behind the high speed data list for burs.ing during the next frame.

In particular, the 2.4K deferrable data transmit list is -~
formed during the 56th SCM scan at each frame in which 2.4K data ports produce their channels. Entries in this list are partition addresses associated with the SC~
entries wherein the data port type is 2.4X deferrable data and the internodal ~it is on and the DAC bit presented by the port during the 56th SCM scan is off.

During the 60th and last SCM scan of each of these frames, a bit in the port activity me~ory 96 is turned on for each 2.4K data port presenting a DAC bit off but which was not included in the list formed in the 56th SCM scan. These bits then identify those 2.4K par-titions in the TBB 54 containing information that should be transmitted to the satellite, but for which the DAC-off activity was not detected until after the 56th byte of the channel. These partition addresses are included in a transmit list formed durirlg the 56th ~A9-80-002 I ~ 5759 1 SC~I scan o~ the followin~ frame, called the 2.4K
residual list. It is formed in the same manner as the 2.4K primary list except the bit in the port activity memory 96 is used instead of the DAC bit from the port 14.

4.8 Kbps defexrable data transmit lis~s are formed in a fashion identical to that for the 2.4K lists except that the 57th SCM scan is used to form the lists. Thus the 4.8K residual list represents channels in which the DAC-of~ activity was not detected until after the 57th byte.

9.6 Kbps deferrable data transmit lists are formed in a fashion identical to that for the 2.4K list except that the 58th SCM scan is used to form the list. Thus the 9.6K residual list represents channels in which the DAC-off activity was not detected until after the 58th byte.

19.2K deferrable data transmit lists are formed in each of the frames 0 and 2 in Table III. The list formed in frame 0 is used at low priority in frame 1 and at high priority in frame 2. The list formed in frame 2 is used at low priority in frame 3 and at high priority in frame 4.

The 59th SCM scan is used to form those lists of par-tition addresses wherein the data port type is 19.2K
deferrable data and the internodal bit is on, and the DAC bit presented by the data port is off. Ports not indicating DAC-off until the 60th SCM scan are flagged in the port activity memory 96 and included in the non-deferrable data transmit list in the following frame,since ro deferring will be possible for these ports.

~g-80-002 t 1S7~g 1 Similarly, in frame 4 of Table IIIj the channels pro-duced by the 19. 2K ports are not deferrable sinGe a new channel is produced again in frame 5. Thus, in frame 4, a 19.2K deferrable data transmit list is not formed but rather, 19.2K ports indicating DAC-off for the 60th SC~I scan are entered into the non-deferrable data transmit list along with the ports defined as non-deferrable or high speed data ports in the SCM.

High speed or non-deferrable daka transmit lists are formed in the 60th and last SCM scan o each frame.
Partition addresses associated with SCM entries wherein the port type is non-deferrable and the internodal bit is on, and the ~AC bit presented by the port was of~
any time during the frame, are always included in this list. In addition, 19.2X partition addresses for which deferrin~ is impossible are included in this list as discussed above.

Traffic Bursting from Transmit Lists The following sequènce of operations is performed by the burst prioritization mechanism each frame. The order given below is that actually used, starting at the beginning of the frame. The first two operations take place during the first 10~1/2 channels of the frame during which no traffic bursting may occur.

2S 1. Update fixed location initial pointers 101a based.
on trarfic bursts in the previous frame under the control of the pointer control 112.

2. Order initial pointers by priority in burst ordered initial pointer lists 101b for traffic bursti~g in current frame under the control of the pointer control 112 and the low speed data priority ROS
120.

.MA9-80-002 1 15759~

3. Count freeze-outs based on traffic bursting in previous frame. ~-Supply partition addresses frc~ the burst priority RAMlO0 under the control of the pointer control 112, as initiated by the request on line 138 from the timing and acquisition mechanism 34 to burst the next channel partition from the TBB 54. This initiates the bursting of traffic using the burst ordered initial pointers and their associated transmit lists in the burst priority 10 RA-~ 100.

Each of these operations is discussed below, but in a different order than given for reasons of clarity.

The burst ordering of initial pointers occurs at the beginning of each frame, the se~ of initial pointers existing in the fixed location initial pointer area lOla of the burst priority RAM lO0 which represents the transmit list which should be considered for use in bursting in the cuxrent frame. These initial pointers are examined for validity, and if valid, placed in the burst ordered initial pointer list lOlb, according to their respective priorities in the frame, along with an identification of the initial pointer. An invalid initial pointer which is all zeros, is stored as the last entry in this list.

The ordering of which the initial pointers are examined and placed in the burst ordered initial pointer list lOlb is as follows:

1. Won-deferrable data 2. Deferrable data when no longer deferrable 3. High priority voice ~'f.A9-80-002 4. Low priority voice 5. Deferrable data when deferrable The deferrable data initial pointers are examined in the order of 19.2X, 9.6R, 4.8K and ~.2R. The primary list is examined be~ore the residual list for each respective speed.

Traffic Burstins In preparation for traffic bursting, the burst priori-tization mechanism 74 fetches the highest priority initial pointer from the burst ordered initial pointer list 101b under control of the pointer control 112 and the register file 108, and loads the pointer in the address register 104. When the timing and acquisition mechanism 34 transmits a signal over the line 138 requesting the burst of the first channel partition from the TBB 54, the pointer control 112 responds by exe-cuting an access to the burst priority RAM 100 on every 14th SCM slot as determined by the slot count decode ROS
114. This corresponds to the location of the update slots as is seen in Figure 6 for the SCM organization.
This access fetches the next list entry from the burst priority P~M 100 for bursting and loads that list entry into the RP~l register file 122. T~70 locations in the RAM register file 122 are used for this purpose with one holding the entry uséd to access the list and the other being loaded with the entry thus accessed. The roles of these file locations reverse as each entry is used for bursting.

During traffic bursting, the timing and acquisition mechanism 34 repeatedly issues a next partition request on line 138 to the burst prioritization mechanism 74.
Each "ne~t partition request" causes the appropriate RAM register file 122 location to be loaded into the 1 15759 ~

next partition register 124 as well as a reversal o~ the roles of the RAM register file 122 locations. Thus, during the next SCM update slot, which is approximate~

8 microseconds after the previous SCM update slot, the 5 next element in the partition address list will be fetched and loaded into the RAM register file 122 in preparation for being transferred to the next partition register 124 when the next partition address is re-quested. The next partition address should be requested approximately 12 microseconds after the previous ad-dress, and it is therefore seen that the SCM scanning operation passes through SCM update entry points at a faster rate than the rate at which requests are received from the timing and acquisition area 3~ for new TBB
partitions to be transmitted.

When an entry is encountered in the burs~ priority RAM
100 having the "last entry" bit on, that entry is not used for accessing a next entry, but rather the next initial pointer in the burst ordered initial pointer list lOlb is accessed. When an invalid initial pointer is encountered in the next partition re~ister 124, as will occur when the transmit lists have been exhausted in the burst priority ~AM 100, the next partition register 12~ is locked in that state for the remainder of the frame. The burst control area in the timing and acquisition mechanism 34, in turn, causes no channels to be burst when it is presented with an invalid partition address.

At the end of each frame, the partition address in the ~A~ register file 122 that would have been used next for bursting, had the bursting continued, is stored as the new fixed location initial pointer in area lOla for the transmit list in use when the bursting stopped.
Inva~id partition addresses are stored as the fixed location initial pointers in area lOla for the transmit lists which were exhausted during the traffic burst.

l 157~1 Descri~ion of the List Pointer Control A more c~mplete understanding of the operation of manipuLating the list pointers during the burst list formation stage, during the burst list reordering stage and during the burst list transmission stage can be had by referring to the copending Canadian pa-tent applica-tion 366,998-0, filed December 17, 1980, by J.A.
Alvarez et al entitled "Vynamically Variable Prlority, Variable Position Channels in a TD~ Burst" in which is described a detailed functional block diagram of the list pointer control 112.

Overview of the Mechanism for_Synchronization of Data Ports The SCC 22 is capable of interfacing with local, ter~
restrial data sources ~ia the data ports 14, 16 and 18.
As was previously mentioned, the data ports in the SCC
can be conveniently packaged with either one or two data ports per digital data processing unit (DDPU) 15, as is indicated in Table IV. The control and data interface protocol for each type of data port is referred to in Table IV.

~'~9~80-002 TABLE IV

Ty2~ Data RateModularity I~nter~ace (Label) Kbps Ports/DDP~

1 (14) 2.4,4 8,9.6,19.2 2 RS-232-C (EIA) -2 (16) 56,112,224 2 V.35 ~CCITT) 3 (18) 1,344 and 1,544 1 Bell 306 1 15759 l -~8-functional block diagram of a DDPU 15 is shown in Figure 18. Each DDPU lS or port 1~, 16 or 1~ p~ovides interface circui~ry and controls 200 to accommodate the interface as specified in Table IV. The elastic buffer 202 manages data buffer read and write pointers ln a manner to compensate for the differences between the external interface timing and the internal SCC timing.
A minimum separation i5 maintained be~ween these two pointers to compensate for the worst case asynchronous variation between the rates at which information enters and leaves the elastic buffer 202. A forward error correction code (FEC} mechanism 206 can apply FEC
selectively to data ports under control of the SCP 32.
~or example, for low speed data ports 14 and medlum speed data ports 16 having speeds of 224 Kbps or less, FEC can be applied centrally by the encoder 58 in the digital switch 30, thereby allowing the use of shared FEC circuitry. In that case, a quadratic residue code (17,19) shortened to QR (16,18) can be used, for example.
~or high speed data ports 18 having speeds above 224 Kbps, for example, a (32,28) convolution code can be used. For the high speed case, FEC can be applied on transmission and data corrected on reception in the D~PU
15. A data activity compression (DAC) mechanism 204 is provided for each port within a DDPU 15. DAC is analo-gous to V~C, as was described above, since information is not transmitted if each byte in a frame is identical to the last byte transmitted in a previous frame. When the destination SCC fails to receive a channel of information as expected, it repeats the last byte previously received for the duration of the channel.
This frees the channel's time slot in the transmission burst for use by another port at the transmitting station. The receiving station's data port must be able to recognize that the DAC operation has taken place so that it can replicate the last byte of data received in the last transmitted channel for the intended destination data port.

1 1575~ 1 This problem is complicated by data ports having a data rate which is a non-integral multiple of the bas~ic data rate for the trans~ission of one channel of information per TD~l~ frame. For example, in a TDMA s~stem where the transmission of one channel (60 bytes) of information per TDMA frame (every 15 milliseconds) is equivalent to a 32 Kbps data rate, if a local data port services a data source having a 48 Kbps data rate, the data source is operating at 1.5 times te basic data rate for the transmitting station. To accommodate the 48 Kbps data port, the transmitting station transmits two channels every even numbered frame and one channel every odd numbered frame. This techni~ue is implemented by the use of a pattern generator in the transmittiny station which controls the transmission of two channels of information on even Crames and one channel of infor-mation on odd frames, giving a net data transmission rate of 4~ ~bps, as desired.

However the use of a repetitive pattern of channels in succeeding frames creates another problem for the receiving station as to how to distinguish between those TDMA frames wherein fe~er than the maximum number of expected channels is to be received, from a situation where no information has been sent by the transmitting - 25 station because of the DAC operation. This proble~ is addressed and solved by employing a synchronizing signal in the form of a special reference burst sent by the reference station in the TD~ network once every 40 TDMA frames, to all participating stations in the network. This special reference ~urst synchronizes a local data port clock in every earth station partici-pating in the network. Each data port has a pattern generator which is connected to the synchronizing mechanism, for est2blishing a pattern for a particular data rate type of data port, ~hich pattern is uniformly s-~nchronous through.out the satellite co~unication system. Corresponding pattern generators for that particular pattern type are in synchronous operation for every data port in the system.

: ~A3-80-002 ~ 1~759 1 A receive burst buffer in every receiving station accepts the incoming channels of information andt through a dlgital switching mechanism, directs them to the intended data port. Each data port has a receive RAM which is one byte wide and 256 bytes long, thereby capable of storing our channels' worth of information.
When the receive burst buffer (RBB) receives a full - channel of information (60 bytes), the RBB sends con-secutive bytes of information from that channel to ~he data port, for storage at a location in the receive RAM
indicated by a write pointer. The receive RAM is operated as a wrap-around memory. A read pointer points to the location in the receive memory where one byte of data is ready to be transmit~ed from the data port to the local data user. The write pointer is indexed i~
synchronism with the system synchronized pattern gener-ator. The read pointer is indexed in synchronism with an external clock provided by the local data user. It can be seen that the distance between the write pointer and the read pointer varies with the relative rates of reception from the satellite and retransmission to the local data user, so that the receive RAM can be viewed as an elastic bufer in the data port. The location in the receive memory accessed by the read pointer is output to an eight-bit wide shift register to enable serialization of the byte of information for retrans-mission to the local dat,~ user.

Each byte of data received from the RBB by the data port is stored in the receive memory at the position indi-cated by the write pointer, along with a DAC bit position.The DAC bit will be "off" because data has actually been received by the receiving station as receive burst buffer. As the read pointer accesses each byte of information in the receive m~mory, it transfers that byte of information to the output shift register only if the DAC bit is in its "off" state. ~Ihenever a byte of information stored in the receive memory is transferred ~A9-80-002 ~ ~5759 1 by the read pointer to the output shift register, that byte is rewritten into the receive memory at the same -location with the DAC bit turned to the "on" siate.
Later, if the read pointer ever accesses a b~te in the recei~e memor~ having the DAC field in its "on" state, then no alteratlon is made to the contents of the one byte wide output shift register, so that the contents re~ain the same as the last byte received from the last frame.

During the course of transmitting 48 Kbps data stored fro~ the transmitting station to the receiving station, a consecutive pair of channels of data (60 bytes each) can have each of the bytes in the second occurring channel identical to the last byte in the first oc-lS curring channel. This is the circumstance which iscompared or in the data port at the transmitting station and which satisfies the DAC requirement. Assume that the circumstance occurs in a TD~ frame-where ordinarily two channels of information for the ~8 Kbps data port would have been sent. The data port transmits the first channel of information b~t omits transmitting the second channel of information. The transmitting station allocates a time slot of only one channel during this TDP~ frame, instead of the expected two channel time slot. A single channel of information is trans-mitted via the satellite transponder and is received at the receiving station and stored in the receive burst buffer. The synchronized pattern generator in the receive station has been synchronized so as to operate in step with the pattern generator at the data port in the transmitting station. Thus as the bytes from the first channel received in the receive burst buffer are consecutively passed to the data port in the receive station, they are stored at consecutive locations in the receive memory pointed to by the write pointer, as usual. However as the last of the bytes in the first channel are passed to the data port, the synchronous 1 15759 ~

pattern generator detects that there is no second channel stored in the receive burst buffer, as expectecl.
The write pointer for the receive memor~ is ~ontinuously indexed as during normal operation, but no in~ormation is written into the byte field pointed ~o in the receive memory. However, the DAC bit field is written with the "on" state for each of the 60 null bytes written in the receive memory, corresponding to the second channel whose transmission was omitted by the DAC operation.

As the wrap-around receive memory is indexed by the rhythm established by the synchroni~ed pattern gener-ator, the read pointer points to the first null byte position and detects that the DAC bit is in its "on"
state~ Thus for this null byte and all of the other 59 succeeding null bytes stored in the receive RAM, the eight-bit wide output shift register does not have its contents changed. Thus a block of 60 bytes of data, with each byte identical to the iast received byte in the preceding frame, is output to the local data user at the e~ternal clock rate.

By synchronizing the transmission and reception pattern generators for all data ports operating at the same data rate throughout the enti~e TDMA system, a necessity for bit stuffing to accommodate non-integral multiple data rate data ports is eliminated and yet data activity compression operations can be carried out.
_ Overview of the Signal Path From a Transmitting_Data Port to a Receiving Data Port Via the Satellite Transponder Figure 19 is a functional block diagram showing the signal path from a transmitting data port X at station 1 to a receiving data port Y at station 2 via the satel-lite transponder 5. Data is input to the transmit RAM
214 from the input 194 shown in Figure 18, through the input registers 195 and 196 shown in Figure 25. The 1 157~ 1 transmit ~NM 21~ carries out the elastic buffering and data buffering functions for the input data, as will ~e described later. Data is read out of th~ transmit R~
214 into the transmit register 216 under the control of the transmit pattern generator 224, shown in greater detail in Figure 20. Each byte of data from the trans-mit RAM 214 is sequentially passed from the transmit - register 216 to the port register 220 and the data in registers 216 and 220 are compared in a comparator 218 to establish whether the DAC bit on output 85 is to be a zero if they are not equal or is to be a one i they are equal. A DAC bit for each byte of data read from the transmit R~'l 214 is output over line 85 to the enqueue control ROS 88, as previously described. The corre-sponding byte of data in register 216 is output overline 4~a to ~he transmit burst buffer 54. The SCM slot in the SCM 50 which has selected over llne 78, the transmit pattern generator 224 of the data port X, also contains the TBB address on line 82 for the particular 20 byte of data output on line 44a is to be loaded in the .~
TBB S4, as previously described. The port ac~ivity memory 96 has as many one-bit storage positions as there are separate SCM slots in the SCM 50 and those one-bit positions in the port activity memory 96 are accessed in the same sequential manner and simultaneously with the accessing of the slots in the SCM 50 by the slot count 75. The enqueue control ROS 88 has an output 131 to the port activity memory 96 which resets all of the bits in the port activity memory 96 at the beginnlng of each ~ ~
frame to a DAC value of one. During each of the 60 SCM
scans through the SCM 50, the enqueue control ROS 88 simultaneously accesses the corresponding bit location in the port activity memory 96 for each SCM slot and sets any one-bit location in the port activity memory 96 to a DAC value of zero indicating activity, when the corresponding DAC bit on the line 85 from the comparator 218 in the data port 15 being selected over line 78 by the SCM 50, indicates a zero value. That zero value ~9-8~002 ~ 15759 1 stored in the correspondingly accessed location of the port activity memory 96 is never again reset to.~the no-activity value of one during the rest of the frame. In this manner, at the beginning of a particular frame, if the last byte of data from the preceding frame, which is stoxed in the register 220, is equal to the first byte of data for the data port 15 in the present frame, stored in register 216, and is equal to all of the other 60xN (where ~ is an integer) stored in the transmit RAM
214 for the present frame, then the comparator 218 will issue DAC bits having a value of one on line 8S for all of the bytes transferred on line 44a to the TBB 54.
This will cause the enqueue control ROS 88, which had - reset the corresponding one-bit slot of the port ac-tivity memory 96 to a no-activity value of one at the beginning of the present frame, to never set that corresponding one-bit value to zero during the entire present frame.

As was previously described, the burst priority mecha- -nism 74 compiles threaded lists of each category o~ data ports during each TD~ frame in preparation for bursting during the next frame. As was previously described, during a particular byte scan through the SCM 50, or example the 60th scan where the 56 Kbps data ports are ~5 enqueued, as the slot count 75 increases accessing consecutive SCM slots in the SCM 50, a particular SCM
slot for a 56 Kbps data port will be encountered in the SCM 50 and the corresponding one-bit activity indication in the port activity memory 96 will be output to the enqueue control ROS 88. ~f that activity indication in the port activity memory 96 shows that the particular data port has been DACed, that is that all the bytes of data in the present frame are identical to the last byte in the precedin~ frame for this data port, then the enqueue control ~OS 88 will not transmit an enabling signal over line 54 to the burst priority mechanism 74 and thus the TBB address on line 82 from the SCM slot accessed in the SCM 50 will not be enqueued for trans-mission during the next frame.

1 1S759 l On the other hand, if any byte accessed from the trans-mit RAM 214 and loaded into the register 216 is not identical to the next Rreceding byte of data in the register 220, the comparator 218 will output a DAC bit value of zero on line 85 to the enqueue control ROS 88.
The enqueue controL ROS 88 will then issue a signal over line 131 to the correspondingly accessed one-bit lo-cation in the port activity memory 96, setting that location to a zero value indicating that the corre-sponding SCM slot in the SCM 50 associated with the dataport being selected on line 78, does have port activity and thus that the T~B partition associated with the TBB
address on line 82 from that SCM slot will be enqueued in the burst priority mechanism 74 for bursting during the next TDMA frame.

This DAC operation can be more fully appreciated with reference to T~ble V which shows the operation of the data port and digital switch for a 32 Kbps data rate.
The 32 Kbps data rate of the data port lS i9 identical to the basic data rate of one 60 byte channel of eight-bit bytes each TDMA frame of 15 milliseconds duration.
This is the minimum continuous data transmission speed for the digital switch 30 connected to the data port 15 and serves as the simplest illustration of the DAC
operation. Table V shows transmit frames 1 through 4 during each of which 60 bytes of data are accumulated in the transmit RAM 214 of the transmitting data port 15.
The pattern generator 224 enables over line 227 a .~ -transfer of one byte of data for each of the 60 SCM
scans in a frame, to register 216. Each of these 60 bytes of data is sequentially transmitted during each of the corresponding, succeeding SCM scans, over line 44a to the TBB 54.

The A side of the TsB 54 shown in Figure 19 has its partitions shown as horizontal rows of 60 bytes each, the rows being organized so that corresponding byte ~9-80-002 1 1$759~

locations in succeeding rows are vertically jux~taposed -as in a m~trix. To facilitate describing the storage -pattern for the TBs 54, the byte locations in the TBB
will be referred to in conventional matrix notation as is shown in Figure 19. The byte locations for the first horizontal row will be referred to as matrix elements al,l; al,2...al,60. The second horizontal row in the TBB 54 will have its byte locations respectively juxta-posed beneath the corresponding byte locations in the .first row and will be referred to as a2 l; a2 2;...a2 60 In the preferred em~odiment, the TBB 54 has 384 par-titions of 60 bytes each and therefore the last row in the A side of the TBB 54 would have 60 byte locations, each juxtaposed with the corresponding 60 byte locations in the precedlng partitions and referred to as a3~4 l;
a384 2;' a3~4 60.

During each scan of the SCM 50 ~y the slot count 75, when the SCM slot corresponding to the data port X is encountered, the TBB partition address output over line 82 from the SCM 50 accesses the horizontal row partition in the TBB 54 corresponding to the data port X identi-fied on the port select line 78. The particular byte location within the horizontal partition row accessed over line 82, is designated by the byte scan count 77 which is input to the TBB 54 and indexes the byte locations l through 60 corresponding to the byte scan count 77. Thus it is seen that for a 32 Kbps data port as is used in this example, the 60 bytes of data trans-mitted from the data port over line 44a to the TBB 54 will be loaded in a single row partition from location l,l g 1,60' P
During each SCM scan of the SCM 50, as the SCM slot corresponding to the data port X is encountered in the SCM 50, the data port X is selected over line 78 from the SCM S0 with a signal which is input to the transmit pattern yenerator 224~ The enabling signal from the MA9~80-002 t ~5~59 1 pattern generator 224 over line 227 to the register 21fi accesses one of the 60 bytes of data stored in.transmlt R~l 214 and causes the comparator ~18 to compare that accessed byte of data in register 216 with the next preceding byte of data in register 220 accessed from the transmit RAM 214. The comparator 218 then outputs the appropriate DAC bit on line 85 to the enqueue control ROS 88, as was previously described. During the 60th scan of the SCM 50, all 32 Kbps data ports will have their TBB partition addresses output on line 82 from the SCM's 50, enqueued by the burst priority mechanism 74 if the cumulative DAC bit in the port activity memory 96 indicates there is activity for that port.

In the following TDMA frame, the burst priority mecha-nism 74 accesses selected ones of the hori20ntal row of partitions in the TBB 54 based upon the prioritized threaded lists of TBB partition addresses compiled in the preceding frame, as has been previously described.
~hen the burst priority mechanism 74 accesses the TBB 54 -for bursting, the entire row partition ai 1 tllroughai 60 is burst out over the output line 45 to the transmit time division switch where a 32 bit destination address is appended to the 60 byte channel's worth of data and is transmitted via the burst modem 24 to the satellite transponder 5, as has been previously de-scribed. This transmit operation is summarized in Table V for a 32 Kbps data port where, in transmit frame number 1, there is at least one DAC blt indicating non-replication and therefore the cumulative DAC bit in the port activity memory indicates activity and therefore the corresponding TBB partition is en~ueued and trans-mitted.

MP.9-80-002 ~ 1 ~759 1 TABI.E V
32 Kbps Transmit 1 . 3 . 4 .:
Frame Bytes 60 60 60 60 Accumulated at Port _ _ Transmit 1 1 1 Pattern Generator _ _ _ Channels Al..... A~o A60... A60 60 60 3' 58 1C2 2 3 59 Output from Port to Digital Switch __ .
DAC Bits 0... ;.. ..0 1..... ..1 1 1 0 .... 0 0 0 1 0 .... 0 no activity) .... _ _ PAM Bit 0 1 1 - 0 0 activity) ..
.
T3B-A Al... A60 . A60A60B3... B58 _ TBB-B . A60..... A60 ClC2C2C3 C59 Enqueue Yes No Yes Yes Transmit TBB-A _ . ........... TBB-A TBB-B
__ _ _ Receive ¦ 1 2 3 4 Frame ¦ __ __ RBB-A ¦ Al... A60 _ _ A60A60B3... B58 Receive l Empty C~C2C2c3:--c59 RBB-B
RBB ¦ 0 1 0 0 Loaded _ ._........ .

Receive ¦ 1 1 1 Pattern l Generator _ .
Receive ¦ Al.... A60 A60... A60 A60A60B3... B58 ClC2C2c3---c59 Da~a -~ -80-002 11575~1 he_se.cond transmit frame in Table V illustrates the operation when a 60 ~yte channel output from the data -port X to the digital switch 30 has each byte equal to the last byte in the preceding frame 1. In this circum-stance, all of the ~AC bits produced by the comparator 218 are equal to one, causi.n~.~ the enqueue control ROS 88 to maintain a cumulative value of one in the corxe-sponding one-bit position of the port activity memory 96, indicating complete replication by all of the 60 bytes in the present frame, of the last transmitted byte in the preceding frame. Thus, during frame 2, when the burst priority mechanism 74 compiles the list of 32 Kbps .
data ports to be trancmitted during the next frame, the indication of no activity stored in the port activity memory 96 for the data port X will cause the encueue control ROS 88 to omit t~ansmitting an enablin~3 signal over line 94 to the burst priority mechanism 74, so that the corresponding TBB partition address on line 82 for the data port X will not be included in the list of 32 Xbps data ports to be transmitted during the next frame.
This is illustrated by frame number 2 in Table V.

The transmit frames 3 and 4 in Table V illustrate the circumstance that there is some replication of the bytes in the frame to the last byte in the preceding frame but that whenever a non-replicating byte is encountered in the frame, the cumulative activity value stored in the port activity memory 96 corresponding to the data port will show activity, thereby causing the 60 byte channel produced during that frame to be enqueued in the burst priority mechanism 74 for transmission in the next ` frame.

~ransmission operations for the data port 15 and digital s-~itch 30 are synchronized to the instant the frame reference burst from the reference station 3 is trans-ponded from the satellite 5. The local transmit framesynchronization pulse on line 91 is iocally tirned at the .4~9-~0-002 I 1 575g ~

local SCC station 1 to occur at the instant in time so that a pulse transmitted` rom station 1 would arrive ~t the satellite transponder 5 simultaneously with the frame reference burst from the reference station 3~ ~he actual instant of transmission of bursts from the local station 1 are delayed with respect to the instant o~ the transmit frame synchronization pulse at the local - station 1 by a duration speci~ied by the position in the T~MA frame assigned to the local station for its burst, as has been previously discussed with reference to Figure 2. The receive frame begins at an instant called the receive frame synchronization time which is signaled on line 93 at each local station. The receive frame synchxoni~ation pulse occurs at an instant which is delayed with respect to the transmit frame synchro-nization pulse at a local station by a duration equal to the round trip path delay between the transmission and reception of a ~iven signal by the local station. ~ince all of the SCCs in the TDMA network have their receive 20 frame synchronization pulses synchronized with respect ,~
to the instant of reception of the frame reference burst transmitted from the reference station 3 through the satellite transponder 5, if SCCs 1, 2 and 3 were to transmit an integral number of channels to a fourth SCC
during the transmit frame 0, that same number of channels will be received b~ the fourth SCC on the receive frame 0. This operation is carried out by the timing and acquisition mechanism 34 connected in the SCC 22 as is shown in Figure 3.

The TDMA burst transmitted from station 1 and tran-sponded through the satellite 5 is received at station 2 where the destination address is decoded in the receive address interpretation mechanism 60 to determine whether the associated 60 byte channel of traffic information is intended for station 2. If the channel of traffic information is intended for the local station, it is passed through the elastic buffer 62 to the receive ~A9-80-002 burst buffer (R~B) ~4 and loaded into either the A side or the B slde o~ the RBB 64 depending upon whether the frame during ~hich the burst was received was odd or even.

The RBB 64 shown in Figure l9 is organized in the same manner as the organization of the TBB 54, as previously described. Each horizontal ro~/ partition in the RB~ 64 is loaded with a channel partition's worth of the 60 bytes of da~a transmitted from a 60 byte channel par-titlon in the TBB 54 at station l. Prior to the com-mencement of data transmission from station l to station.
2, the satellite communications processor 32 at station 1 initiated the call to station 2 by communicating with the satellite communications processor 32 at station 2, transmitting the intended destination data port Y at station 2. The satellite communic2tions processor 32 at station 2 responded by selecting a particula* channel partition in the RBB 64 in station 2 which would be associated with the destination data port Y at station 2 for the dura-tion of the call. The identity o-f the selected partition in the RBB 64 was transmitted by the satellite co~munications processor 32 at station 2 to the satellite cor~munications processor 32 at station l.
The SCP 32 at station 1 then defines the destination address which was t3 be stored in the transmit space signaling huffer 126 at station 1 as the identity of the receiving station 2 and the identity of the partition in the P~BB 64 in station 2 corresponding to the data port.. Y -~
at station 2. Thus, as has been previously descri~ed, 30 when the burst priority mechanism 74 at station 1 accesses the TBB 54 during TD~ burstin~ in a frame, the partition address is also transferred o~er line 123 to the transmit space signaling buffer so that the correct destination address can be appended to the corresponding partition in the TBB 54 which is being transmitted from station l to station 2.

~'~9-80~002 11575,~1 Thus, durlng e~ert~ TDMA frame, the 32 '~bps data port X
at the transmitting station 1 has a channel partition~s worth of information stored in a horizontal row par-tition of the TBB 54 which can be appended to the destination a~dress for the station 2 and transmitted in the station l's TDMA burst for that frame. During the corresponding receive frame at station 2, all of the - channels of information whose destination addresses indicate that station 2 is the intended recipient, are loaded in the hori~ontal row channel partitions in the RBB 64 t,~hich are designated by the corresponding desti-nation addresses. When the call was initially being set up by the satellite communications processor 32 ir~
station 2, an SCM slot was selected in the SCM 50, into which was written the RBB partition address for the horizontal rot~ partition which was to receive the channels of information during this call, and the identity of the data port Y. During the receive frame following that during which the channel partitions are 20 loaded in the A side of the RBB 6~, the A side of the -RBB 64 is accessed by the SCM 50 in the same manner as the TBB 54 for that station. The local slot count 75' at station 2 is derived from the local transmit frame synchronization pulse at station 2 in the same manner as is the slot count 75 derived from the transmit frame synchronization pulse in station 1. Similarly, the byte scan count 77' in station 2 corresponds to the local timing in station 2 in the same manner as does the byte scan count 77 in station 1, as previously discussed.
During each byte scan count 77', the SCM 50 in station 2 sequentially accesses the SC~l slots and each time it encounters the SCM slot corresponding to the data port Y, the corresponding PBB partition address is output on line 82 to the A side of the RBB 64, reading out the next byte of data in the accessed channel partition, corresponding to the value of the byte scan count 77', sequentially inde:cing from location aj 1 through a~ 60.
In this manner, the G0 bytes of data are transferred ~9-80-002 1 ~5759}

over line 4~b to the data port Y during the recei~Je ~rame follo~iny the 4rame in which the data was loade~
into the RBB 6~ from the received TDM~ burst.

Whenever data is loaded into a particular horizontal row partition in the XBB 64, a bit is turned on in the ~BB
load memor~f 266 indicating that information has in fact been recei~-ed in the corresponding Rss partition. As each byte of data in a horizontal row partition in the RBB 64 is read O'1t on line 44b to the data po~t, a corresponding bit from the RBB load memory 226 is transferred over line 208 to the data port and is located as the DAC indication in the register 230 in association with the byte of data also loaded in the register 230. If data is present in the RBB pa~ti~ion accessed by the SC~ slot, then the RBB load bit on line 208 will be a zero indicating that data has in fact been received. If there is no data in the RBB partition accessed hy the SCM slot corresponding to the data port Y, then when that slot is accessed in the SCM 50 during each scan of the slot count 75', the RBB load memory 226 will output a binary 1 on line 208 indicatlng this condition. This DAC bit is then sequentially loaded in the receive R~l 232 and will serve to indicate to the DAC logic 234 that the last received byte of data during the last receive frame for the accessed Rss partition, must be replicated and output on the output line 241 for the data port Y. This operation is shown in ~able V.
It is seen that during receive rame 1, the channells worth of information transmitted from station 1 during transmit frame 1 is received in the A side of the ~BB 64 at station 2 and the RBB loaded bit corresponding to that partition is indicated as a zero indicating the partition is loaded. All 60 bytes of data are then sequentiall~ loaded into the receive RA~I 232 and output over the output line 241.

1 ~75g ~

During recelve rame 2 of Table V, the ~Ced channel of in~ormation .~hich was not transmitted from station 1 results in there being an empty partition in the RBB 64 during receive frame 2 at station 2. The RBB load memory 226 then has a binary 1 output on line ~08 which causes the DAC bit to be turned on for 60 byte positions in the receive R~M 232. This causes the DAC logic 234 to replicate the last byte in the last partition lo-cation aj 60 for 60 times and output the 60 replicated bytes on the output line 241. In this manner, the desired replicated channel's worth of data is produced at the receiving data port Y without having consumed the bandwidth required for its transmlssion through the satellite transponder S.

Receive frames 3 and 4 in Table V are handled in a manner similar to that for receive frame 1. ~he functional block diagram for the receive part of the data port is shown in Figure 27. The operation of the receive portion of the data port is under the control of the receive pattern generator 244 which is shown in greater detail in Figure 21.

Overview of Pattern Generator Operation For data rates which are not multiples of the basic 32 Kbps data rate of the digital switch, the transmit pattern generator 224, shown in greater detail in Figure 20, and the receive-pattern generator 244, shown in greater detail in Figure 21, are synchronized with one another through the transmit frame s~nc pulse and the receive frame sync pulse, so that-channels of data can be periodically omitted from transmission in order to equalize the effective transmission rate of the SCC to that of the data source.

.~9-80-002 -" 115~91 This operation can be illustrated with reference to Table VI which shows the operation o~ the pattern generators, in conjunction with the DACing logic, to create data patterns which are 2.4 Kbps, 4.8 Kbps, 9.6 ~bps, 19.2 ~bps, 56 Kbps, 112 Kbps, and 224 Kbps.

It should be noted that the 2.4 Kbps pattern repeats every 40 frame~ whereas the 22~ Kbps pattern is a constant seven channels per ~rame.

~9-80-002 ~ :L 5759 1 TABEE Vl T~ANMISSION PATTERN CYCLE
IN FR~S/CHANNEL < 19.2 Khps I~ C-~NE~S/F ~E ~ 56 Xbps DATA RATE ~ POINTER OFFSET
(BYTES) _ 2400 bps 14-13-13 57 4800 bps 7-7-6 54 9600 bps 4-3-3 48 19200 bps 2-2-1 36 56~0 Kbps 1-2-2-2 15 112.0 Kbps 3-4 30 224.0 ~bps 7 O
1.344 mbps* 48 48 1.344 mbps** 42 O
1.544 mbps* 55-55-S5~55-55-56 52 1.544 mbps~* 48-48-48-49 45 LOW SPEED
OFFSET-60[(Data Rate bytes) NF-RF]F
_____ Frame NF - Maximum number of frames before buffer full F = Number of times NF occurs per pattern cycle .
RF = Number of bytes read by Digital SW at Buffer full time.
this number equals 60 bytes for rates < 19~2Kbps HIGH SPEED
OFFSET=60[(Data Rate(bytes) - MF (bytes~) Xl Framel f _____ _____ Fra~e Frame MF = Minimum digital switch read rate f - Number of contiguous times MF occurs per pattern cycle.
* Transmission pattern for these rates is adjusted for 7/8 rate FEC code ** No 7/8 rate FEC code applied ~9-80-002 As was mentioned above, the digital switch 30 reads data from the data por~ 15 in Nx60 byte blocks per ~rame whexe ~I depends upon the data rate. Each select to the data port from the digital switch reads one byte of data from the data port to the TBB and loads one byte of data from the RBB or INB back to the data port. The de-scription of the digital switch operation above includes a description of the operation of the data port se-lection mechanism. The digital switc}l presents a given data port with the same number of selects every 250 microsecond scan of the SCM 50. A data port is scanned 60 times per TC~ frame. ~s is shown in Table VI, which is a simplified version of Table III, a 56 Kbps port is selected two times per SC~l scàn since two SC~ slots correspond to each 56 Kbps data port. ~owever in one out of every four frames, the 56 Kbps data port is selected only once. The transmit pattern generator 224 of Figure 20 applies the pattern shown in Table VI to control this periodic withholding of one of the two 20 channels every fourth frame. -As is shown in Figure 20, a byte counter 217 is driven by the SCC byte clock 215 associated with a given port rate. For example, for a 56 Xbps data port, the SCC
byte clock produces 56x103 bits per second times 0.015 seconds per frame divided by eight bits per byte which e~uals 105 bytes per frame. In other words, 105 pulses per frame are provided on the SCC byte clock line 215 for a 56 Kbps data port. The output of the counter 217 drives a channel counter 219 which counts the number of 60 byte channels of data accumulated by the data port in one 15 millisecond frame. ~ctual discrepancies between the SCC byte clock and the external clock associated with the external data source are corrected in an elastic buffering operation which will be described later in conjunction with Figure 26. Every 15 milli-seconds the transmit frame sync pulse on line 91 turns on the gate 221 connecting the output of the counter 219 ~9-80-00, 1 ~5759 1 to the transmit status register 229 so that the con~ents of the channel counter 219 are loaded into the status register 229. Simultaneously, the transmi~ ~rame s~nc pulse on line 91 controls the gate 231 to transfer the contents o~ the counter 219 to -the transmit selects counter 233. Every time the data port is selected by means of an input signal on line 78 from the SC~ 50, the - selects counter 233 is decremented by one until it is zero at which time no more selects on line 78 are accepted for that scan. Every 250 microseconds, the gate 239 receives a control pulse for the byte scan counter on line 77, enabling the transfer of the contents of the transmit status register 229 to the transmit selects counter 233. Thus every 250-microseconds, the selects counter 233 is preset with the value in the status register 229. The value in the status register will vary every frame according to the pattern shown in Table VI.

At data rates equal to or lower than 19.. 2 Kbps, the -transmit pattern generator 22~ is synchronized every ~0 frames with the transmit frame synchronization pulse on line 91. Forty frames is chosen because at 2.4 Kbps, the pattern repeats every 40 frames and the 60 byte counter 217 will have a value of %ero. The counter is reset to zero every 40 frames with the transmit frame sync pulse on line 91.

When the transmit selects counter 233 has been decre-mented by the select signal 78 down to zero, the zero detector 237 outputs a pulse on line 222 which forces a DAC bit value of one out of the comparator 218 on the DAC bit line SS to the enqueue control ROS 88~ For e~ample, reference can be made to Table VII for a 56 Kbps data port to illustrate the operation of the transmit pattern generator 22~. During frame 1, if 120 bytes of data had been accumulated in the data port, this corresponds to two 60 byte channels and thexefore ~ 15~9 ~
-8~-the counter 217 will have transferred the value of two to the transmit channel counter 219 at the begi~lning of frame 1. The transmit frame sync pulse on line 91 will have caused the gate 221 and the gate 231 to transfer the value of two to the transmit status register 229 and the transmit selec~s counter 233. Since the 56 Kbps data port s~ill have ~wo SCM slots in the SCM 50, during each 250 microsecond scan of the SCM 50, two select signals will be input from the SC~l 50 on line 78 to the transmit selects counter 233. Since the contents of the transmit selects counter 233 is not zero, the output OL
the zero detector 237 on line 222 will be a binary zero so that the inverter 223 will apply a binary one signal to one of the two inputs of the AN~ gate 225. The other input of the AND gate 225 is connected to the select line 78 so that when each of the two select pulses during each 250 microsecond scan of the first frame is input on line 78, the AND gate 225 will output each of two enabling signals on line 227 to the register 216, thereby transferring two bytes of data from the transmit RA.~ 214 to the output line 44a to the TBB 54.- Thus it is seen that during the first frame in Table VII, two complete channels of 120 bytes of data are transferred from the transmit RA~l 214 over the line 44a to the TBB
54.

~'A9-80-002 ~r ~

_ _~ ~ ,~ . ~ ~ er ~ u~ ~ ~ co ~ ~

~ ~ CO CO

- - - - - - - - -o~c~ ~ c : ~ ~

~- ~- ~
~ o - -- ~ _ _ J
¦ ~ ~ ~ ~ ~ I U ~ V ~ 5 V U I a ~ ~ ~ v D D e j e D D

~ 15759 ~

l ~ ~( l o c~rt ~o~ r~ o ~r ~ ----~1 ~ o o ~
~ ~ o ro r~ -~0 ~ 1~O
~ o ~
t~ O
.' ~ U~ ~D r-t 'O
.. . ~0 _ ~ __ ~ I ~ ~, O
'~1 ~1 ~ o ~1 ,., _ . _ __ O
I ~ ~ ~ O
__ R'= . L~
,, ~ o _ ~

~ ~o o rl O ~1 G
. _ __ _ _ _ _. _ ';4 1 ¢ ,~ O ~ c ~ I
G r O v ~ ~ u r.~J JJ ,~ p~ U r,~l ~ r~ ,C r C: v ¦ ~
CJ r- .-1 I I Ll )~ ~ . ~ O E~ v ~ rrJ V
~D ~J ,t~ IP~ 1~, J ~ r-~ O ~0~ U 5 .1 U IJ
~;~ j759~1 1 157~9 ~

The pattern of loading the TBB 54 will now be described.
This will be done in conjunction with Table VII. As was mentioned be~ore, each 56 Kbps data port has two sepa-rate SCM slots associated with it in the SC~ 50. The first SCM slot contains a first TBB partition addre5s, for e~ample al 1 through al 60 and the second SCM slot specifying a second ~not necessarily contiguous) TBB
partition, for example, a2 1 through a2 60. Beginning with the first SCM scan, the first select from the first SCM slot will cause the first byte accessed from the transmit R~l 214 in the register 216 to be transferred to the ~osition al 1 in the TBB 54. As the scan con-tinues, the second SC~l slot is encountered causing the second byte accessed from the transmit RP~ 214 to be loaded in the second partition location a2 1 in the TBB
54. During the second scan of the SCM 50, the first SC~I
slot corresponding to this 56 Kbps data port will cause the third byte accessed from the transmit RP~I 214 to ke loaded into the first TBs partition's location al 2.
As the second scan continues, the second SCM slot will be encountered ~hich causes the fourth byte accessed from the transmit RP~l 214 to be loaded in the second TBB
partition's location a2 2. As the scan is continued, the 30th SCM scan is achieved. When the first SCM slot for this 56 Kbps data port is encountered in the 30th SCM scan, the 59th byte accessed rom the transmit RAM
214 is loaded in the first TBB partition's location al 30. As the 30th SCM scan continues and the second SCM slot is encountered for this 56 Kbps data port, the 60th byte is accessed from the transmit RP~I 214 and is loaded in the second TB~ partition's location a2 30 Thus it is seen that the first 60 byte channel of data accessed from the transmit RP~I 214 occupies the first half of two TBB partitions. As the SCM scans continue and the 31st scan commences, the first SCM slot corre-sponding to this 56 ~bps data port is encountered which accesses the first byte of the second channel of infor-mation to be transmitted from the transmit R~ 21~ to 1 1~7~ 1 the TBB 5~. This first byte is loaded into the first TBB partition's location al 31 ~5 the 31st scan continues in the SC~I 50, the second SCM slot for this 56 Kbps data port is encountered which loads the second byte of the second channel o~ in~ormation into the second TBB partition's location a2 31 As the SC~
scans continue and the 60th scan is achieved, the 59th byte for the second channel is loaded in the first partition's location al 60 and the 60th byte of the second channel is loaded in the second partition's location a2 60. Thus it is seen that the second channel of information accessed from the txansmit ~ 214 has half of it loaded in the second half of the ~irst partition and the o-ther half of it loaded in the second half of the second partition in the TBB 54.

During the next frame when the TBB-A side is burst to the satellite transponder 5, the first parti.tion is burst and then the second partition is burst. The first partition and the second partition are loaded in the previously designated recipient partitions of.the RBB 64 at the receive station 2 and are read from the RBB 64 at the receive station 2 in the reverse order of their having been wri.tten into the TBB 54 at station 1. Thus r the interleaved pattern is unscrambled as the data is loaded into the receive RAM 232 at the receiving station 2.

In the second frame as shown in Table VII, only 105 bytes of data wi.ll be stored in the transmit RA~1 214 of the data port, and thus only one full channel of data is available for transfer to the TBB 54. The byte counter 217 therefore transfers a value of one to the transmit channel counter 219 at the beginning of the frame. The transmit frame sync pulse transfers the value of one through the gates 221 and 231 to the transmit status 35 register 229 and the transmit selects counter 233. As before, during each 250 microsecond scan, the SCM 50 ~9-80-002 I 1 ~759 ~

~ill transmit two select pulses on llne 78 to the transmit selects counter ~33. ~t the time o~ arrival of the first select pulse on line 78, the transmit selects counter 233 has the value of one stored in it and therefore the zero detector 237 has a binary output of zero, and thus the inverter 223 supplies a binary one enabling pulse to one of the inputs of the AND gate 225, - the other input of which is enabled by the first select signal on line 78, thus outputting an enabling pulse on 10 line 227 to the register 216, as previously described.
This enables the transfer of one byte of data over line 44a to TEB 54 partition a1 1 The first select signal on line 78 decrements the value stored in the transmit selects counter 233 to zero. Thus, when the second select signal is input on line 78, the value stored in the transmit selects counter 233 is detected as being zero by the zero detector 237 and the zero detector outputs a binary one value on line 222 which applies a binary zero vaLue through the inverter 223 to the one input of the AND gate 225. Thus when the second select appears on the line 78, the AND gate 225 is not satis-fied and no enabling pulse is transmitted over line 227 to the register 216. However the line 222 transfers an enabling pulse to the comparator 218 which forces a binary one value for the DAC bit on line 85 to the enqueue control ROS 88. During the second SCM scan, the gate 239 resets the value of one in the transmit selects counter 233 and when the first of the two SCM slots is encountered for the 56 Kbps data port, an enabling pulse 30 is output on line 227 to the register 216 transferring a second b~te from the transmit R~M 214 over line 44a to partitlon location al 2. As the SCM scan continues, and the second SCM slot is encountered for the 56 Kbps data port, no enabling pulse is output over the line 227 to the register 216, and in the same manner, another DAC
bit having a binary value of one is output on line 85 to the enqueue control ROS 88. This process continues for all 60 scans throush the SCM 50 and thus i~ is seen that ~9-80~002 ~ 1~7~9 1 the single-bit location in the port activity memory 96 corresponding to the first SCM slot and the first -partition al 1 through a1 60 of the T~B 54 will have a port activity indication whereas the second single-~it location `n the port acti~ity memory 96 corresponc.-ing to the second SCM slot of the 56 Kbps data port in which DAC bits having a value of one have been forced by the pattern generator 224 to be entered into the enqueue control ROS 88, the cumulative activity value in the port activity memory 96 for that second SC~ slot lo-cation will be a no activity or hinary one value. This corresponds to the second partition in the TBB 54 of a2 1 throug~l a2 60. It is therefore seen that when the 60th SCM scan occurs during which the 56 Kbps data ports have their TBB partitions enqueued in the burst priority mechanism 74, that the active condition for the port activity memory 96 corresponding to the first partition al 1 through al 60 will cause that first pa.rtition to have its address enueued in the burst priority mecha-nism 74. However the no activity condition of thesecond location in the port activity memory 96 corre-sponding to the second SCM slot for the second partition a2,1 through a2 60~ will cause that second partition to be ignored during the burst list formation sequence in the burst priority mechanism 74. Thus it is seen that during the next frame when the burst from the station 1 is carried out, onl.y the contents of the first partition al 1 through al 60 will be burst and the contents of the second partition twhich is empty) of a2 1 through a2 60 will not be burst since its partition address is not present in the burst list. ~hus it is seen how the operation of the pattern generator, in conjunction with the D~C bit generation, makes a non-integral multiple rate for a data port, such as the 56 Kbps data port, compatible with the basic 32 Kbps data rate of the digital switch 30.

~'~9-80-002 1 ~7~9 ~

Table VII shows how the operation of DACiny occurs when tha single channel to be transmitted duxing the. second frame has all of its bytes replicating the last byte transmitted in the last frame number one. This oper-ation is analogous to that described for the 32 ~bpsdata port DACing operation which was illustrated in Table V. Table VII further illustrates the DACing - operation for the 56 Kbps data port when in frame 4 all of the bytes in both channels which would have been transmitted, instead are identical to the last byte transmitted during the third frame. This operation is also analogous to that described for the 32 Kbps data port discussed in conjunction with Table V.

The receive pattern generator 24~ is shown in more lS detail in Figure 21. It generates in a pattern in a manner very similar to that generated by the transmit pattern generator 224 of Figure 20, as was discussed above. The byte counter ~17' operates in a manner similar to the byte counter 217 of the transmit pattern ~
generator 224, having as an input the SCC byte cloc~ 215 for the particular type of data port being employed.
The other input to the ~yte counter is the receive frame sync pulse 93 which resets the byte counter 217' every 40 frames in a manner similar to the resetting of the byte counter 217, as discussed above, The channel counter 219' counts the number of 60 byte channels which should be received over the satellite transponder 5 during each 15 milIisecond frame. Every 15 milliseconds, the receive frame synchronization signal on line 93 transfers the contents of the channel counter 219' through the gate 221' to the satellite status register 229' and through the gate 231' to the satellite selects counter 233'. Every time the data port is selected over line 78 from the SC~ 50, value in the satellite selects counter 233' is decremented by one until it is zero, at which time no more selects are accepted for that scan.
This is achieved by the ~ND gate 254 having a first ~9-80-002 1 ~75~ ~
-'37-input connected through the inverter 252 to the output 251 of the zero detect 237', and having a second i~put connected to the select line 7~. As long as the satel-lite selects counter 233' has a non-zero value in it, every select signal on the line 78 will satisfy the AND
gate 25L~, since the zero output of the zero detect 237', will be inverted to a binary one value which is input to - the AND gate 254. The output of the AND gate on line 246 is connected to the write pointer 25~ o the receive 10 R~l 232, shown in Figure 27. When the SCM slot corre-sponding to the port is scanned in the SC~ 50, the contents of the RBB partition accessed over line 82 is transferred over line 44b and is loaded into the data portion of the register 230 and the corresponding contents of the RBB load memory G26 is loaded as the activity bit in the DAC portion of the register 230.
When the contents of the satellite selects counter 233' is zero, the output on line 251 from the zero detector 237' is a binary one which, when inverted by the inverter 20 252, disables the AND gate 254. Thus, when a next -select signal comes in over line 78, it will not be passed through the AND gate 254 and therefore, no enabling pulse is output over the line 246 to the receive R~ 232. Thus, in this position when the SCM
slot ~or the data poxt is encountered in the SC~-l 50, the contents of the correspondingly accessed partition in the RBB, accessed over line 82, (which should be empty) will not be loaded into the receive RAM 232 since the write pointer 256 is not incremented. This is illus- ~
trated in Table VII, frame 2 where the second channel was intentionally omitted from transmission by the sending station 1 and, by virtue of the synchronized operation of the receive pattern generator 244 with respect to the operation of the transmit pattern gener-35 ator 224, a receive pattern generator 244 inhibits the storage of an~ new in~ormation in the receive RAM 232.

~9-80-002 1 157~ 1 When thP value stored in the satellite selects counter 233' is not zero, the AND gate 254 is satisfied every.
time a select pulse is input on the line 78 and this is a circumstance which obtains in frames 1 and 3 of Table VII. In frame 1, both channels were intentionally sent from the transmitting station 1 to the receiving station 2 and thus the DAC bit indication loaded from the RBB
- load memory 226 into the DAC portion of the receive Pl~M
232 indicates that an active byte has been loaded and need not be replicated by the DAC logic 234 when read out on line 241. In frame 3, although the receive pattern ~enerator 244 indicates that data should have been received from the satellite transponder and loaded into the RBB 64, the RBB load memory 226 indicates that no information was in fact so loaded, as is signified by the DAC bit loaded over line 208 into the receive RAM
232, under the control of the receive pattern generator 244, by virtue of its enabling pulse over line 246 to the write pointer 256. The presence of the DAC bi' on line 236 cutput from the receive RAM 232 to the DAC .:
logic 234 will cause a replication of the last received byte in the last frame on the output line 241. This corresponds to the circumstance which obtains in frame 3 of Table VII for the 56 Kbps data port. In this frame, although two channels were supposed to have been re-ceived in the RBB 64, as is indicated by the receive pattern generator 244 with its enabling output on line 246 to the write pointer 256 of the receive ~M 232, instead two consecutive DAC values of one indicating n~ -reception are loaded from the RBB load memory 226 into the receive R~l 232. As is shown in Figure 27, when the receive RAM 232 is read out to the DAC register 240, the DAC bit is monitored. If the DAC bit is off indicatlng no replication is necessary, the DAC register 240.is loa~ed with the information If instead, the DAC bi- is on or a binary one, the D~C register 240 is not updated and the information that had been previouslY loaded in the DAC register 240 is repeated to the output register ~A9-80-002 1 157~

242.. This corresponds to frame 4 in Table VII. Ever~
reaccèss of the receive RAM 232 is followed by ~ write.`
cycle into the same location forcing the D~C bit on.
The state of the ~AC bit will be turned off into a binary zero position by new data being written ~rom the receive bus resister 230 into the receive RAM 232 from the digital switch 30. If the byte accessed has the DAC
bit Of L ~ it is transferred to the recipient data output over line 241 and the state of the DAC bit associated with that location in the receive RAM 232 is turned on so that when that location is read ayain, the DAC bit will be on if no new information was loaded from the digital switch 30, and the last byte received will be continuously loaded on the output li.ne 241 until new data is received.

In order to share the pattern generators 224 and 2~4 among the two ports supported by one digital data processor unit, it is necessary that the selects ~or the port 0 and the port 1 alternate as is shown in the ~
timing diagram of Figure 22. This allows one selects counter 233 to be used by both of the ports. Thus if only the zero port is operational then every select on line 78 is allowed to decrement the selects counter 233.
If both the port 0 and the port 1 are operational, the selects counter 233 is decremented by the port 1 select only .

Overview of the Elastic Buffer Function of the Data_Port The functional block diagram of the transmit side of the data port is shown in Figure 25 and a functional block diagram of the data port transmit buffer is shown in Fisure 26. A functional block diagram of the receive side of the data port is shown in Figure 27. In ~igure 25, two data input lines 194 and 194l can be serviced by the t~ansmit side of the data port with input shift register 195 havins ts input connected to input line ~'~9-80-002 1 1.~759 1 194 and the recei~e clock 193 and the lnput shi~t reglster 195' having its data input connected to line -194' ~nd its receive clock as 193'. As complete eight-bit bytes of information are received each respective input register 195 and 195', the~ are gated throush the select register 196 via the input line 198 to ~he transmit P~M 214. This is accomplished under cont~ol of the write pointer 258 for the input register 195 and the second write pointer 258' for the second input register 195'. Data in the transmit RAM 214 is read out of the transmit RP~ 214 into the transmit register 216 with each enabling pulse 227 from the transmit pattern generator 224. The operatio~ of the comparator 218 in conjunction with the transmit register 216 and the output register 220 has bee~ previously described. The logic is capable of handling two data streams and therefore a second output registe~ 220' is also con-nected in a similar fashion as is the output register 220, between the transmit register 216 and the output 20 line 44a to the digital switch 30. .~

The relationship between the read pointer 260 and the write poin~er 258 or both the transmit RA~ 214 and the receive RAM 232 is non-linear requiring that an o~fset between the pointers be introduced at the frame synchro-nization time. Table VI describes the transmissionpattern for all the rates supported, and Figure 24 describes a pattern for a 9.6 Kbps data port. Table VI
and Figure 24 show that the pattern repeats every 10 ~ ~
frames, or four times between the frame sync pulses at

9.6 Kbps. Figure 24 also shows that at the end of the 10th frame, the port will have developed a channel's worth of information for transmission, allowing the data to be loaded into the TBB 54 on frame 0. In a similar manner, the channel's worth of data will be developed at the end of the 39th frame to be loaded in the TBB 54 on the following frame. This implies that at the transmit frame synchronization pulse time, the transmit status ~9-80-002 register 229 and the selects counter 233 previously described, must be set to a value of one when the por~
is switched on/ SQ as to synchronize them to the value they ~lill have on the following transmit ~rame sync pulse. Since the digital switch 30 will increment the transmit RAM read pointer 260 by 60 bytes during frame 0 and the write ~ointer 25~ will be incremented by 12 bytes, an offset of 48 bytes is required. ~t a data rate of 2.4 Kbps, the offset would be 57 bytes. An offset of 64 bytes is required for all rates up to 224 Kbps. The offsets associated with the different rates are described in the Table VI. At every frame sync pulse, the relationship between the pointers is checked to verify that synchronization between the port and the digital switch is maintained.

On the receive side of the data port, the satellite status register 229' and the satellite selects counter 233' are synchronized at the satellite receive frame sync time and set to the same value as the transmit status register 229 and the transmit selects counter 233.

In addition to the read and write pointer offset de-scribed above, an additional offset is required to accoun~ for a slip between the external clock on input line 193 and the port clock as represented on input line 215 to the pattern generator 224. This offset is equal to eight bytes for rates below or equal to 19.2 Kbps and 16 bytes for rates between 56 Kbps and 224 Kbps.

With reference to Figure 25, data from the line 194 is accumulated in the input shift register 195 which generates a transmit RAM write request when full, and drops the shift register contents into the ~AM 214 when a write cycle beco~.es available. The appropriate write polnter 258 is then incremented. In addition to data and parity information, the entry to the transmit ~M

~A9-80-002 l 15759 l 214 defines the port identification associated with that entry as being either the æero or the one port on ~he D~PU and also the state of the receive line signal detect (~LSD) at the tlme the data byte W25 loaded into the transmit RA~ 214. The state of the RLSD is required by the digital switch 30 in multi-point operation. When the RLSD turns off, the input to the shift register 195 is set to mark hold insuring that the slip control loyic loads the transmit R~l 21~ with the mark hold. In addition, the slip counter 262 is se~ for a maximum elasticity. The effec~s of filling the transmit RP~I 214 with the mark hold indication after the RLSD turns off are to turn the D~C bit on and to set the transmit data circuit at the receive station 2 to mark hold.

Every select on the ir.put line 78 that is passed by the pattern generator 224 carries a read request to the transmit RP~1 214 and the appropriate read pointer 260 is then incremented.

Figure 26 is an illustration of the operation of the data port as in the elastic buffer. The elastic buffer feature is provided on the data port to synchronize data from modems that cannot be clocked by the SCC as well as to correct for phase shift variations in the txans-mission medium on the input line 1~4.

The transmit buffer 214 shown in Figure 26 incorporates the elasticity required to compensate for freauency - ~
variations between the external clock and the SCC clock in the following way.

At the system reset time, the slip counter 262 which is an up/down counter, is set to a binary value lOQ00 for a 32 byte elastic buffer or 01000 for a 16 byte elastic buffer.

1 l57~g l -103~
The external clock is a byte clock which is generated every time a byte cf external data is accumulated in ,~he input shift register 195. Every transition of the external clock causes:

A. The data to be loaded into the transmit RAM 214 at the address indicated by the write pointer 258.

3. The write pointer 258 is incremented to the next sequential location in the transmit buffer 214.

C. The slip counter 262 is incremented.

The port reference clock 215 is t~e SCC clock ayainst ~hich the external clock is measured and it decrements the slip counter 262 every transition. All e~ternal devices of the same data rate that attach to the SCC are measured a~ainst a port reference clock of the same nominal rate. The port refer~nce clock 215 determines the number of channels the digital switch will read from "~
the transmit RAM 214 in every frame.

If the external clock and the port reference clock 215 are in synchronism, the slip counter 252 remains constant and the relationship between the read pointer 260 and the write pointer 25~ is maintained.

If the external clock is slower than the port reference clock 215, the slip counter 262 will eventually reach .
the value of a binary 00000 indicating a slip of the elastic buffer. At this point, the write pointer 25~ is incremented by a value of 16 or eight depending on the elastic buffer size desired and the slip counter 262 is set to 10000 or 01000. Normal operaticn can now resume.

If the external clock is faster than the port reference 30 clock 215, the slip counter 2G2 will eventuall~ reach the binary value lllll indicating a slip of the elastic ~9-80-002 a~s7ss~

buffer. At this point, incrementation of the write pointer 258 and of the slip counter 262 are prevented so as to enable the port reference clock 215 to decrement the slip counter 262 until it reaches its sync value of 01000. At this point, the incrementation of the write pointer 258 and of the slip counter 262 are enabled and nor~al operation can resume.

Loss of the e~ternal clock, as would occur where the receive line signal detector associated with the ex-ternal modem turns off, does not prevent the writepointer 258 and read pointer 260 from maintaining synchronism, since loss of the external cloc~ would be equivalent to the situation described above where the e~ternal cloc~ is slower than the port reference cloc~

As is illustrated in Figure 27, data from t~ë receive bus 44b from the digital switch is loaded directly into the receive bus register 230 and the DAC bit is loaded from the line 208. For speeds below 32 Kbps, the bus is not allowed to load data into the receive bus register 230 at its basic scan rate of 32 ~bps, but only on the frame boundaries as shown in Table VI. The recei~e pattern generator 244 equalizes the rate at which data is written into the receive ~AM 232 with the rate at which data is fetched from the receive RAM 232 and directed to the destination external user. The write pointer 256 for the receive RAM 232 is incremented by selects on the input line 246 gated by the receive pattern generator 244 as described above, without regard for whether data is received in the RBB 64. The DAC bit is loaded with the data in the receive RAM 232. When reading the RAM 232, the DAC bit is monitored. If the DAC bit is off, the DAC register 240 is loaded with the new information. If the DAC bit is on, the DAC register 240 is not updated and the informa~ion that was previ-ously loaded in the DAC xegister 240 is repeated to the output shift register 242.

-- ll57~91 The receive ~l 232 operates as an elastic buffer to compensate for the differences in data rates be.tween the external destination for the data and the data port 1~.
The implementation is different from the transmit RAM
214 because the read pointer 264 in the receive RA~ 232 is shared by both ports serviced by the RAM, whereas in the transmit RP~l 214, each o~ the two input llnes 194 - and 194' has its own write pointer, 258 and 258', respectively. As is shown in Figure 27, a slip counter 266 is associated with the read pointer 264 for the first output line 194 and a second 51ip counter 266' is associated with the second output line 194'.

The slip counter 266 or 266' is used to calculate the effective read address so that the effective read ad-dress is equal to the read pointer value minus the slip counter value. The external byte clock decrements the slip counter 266 or 266'. The port reference clock increments the slip counter 266 or 266'. The read pointer 264 is incremented every port reference clock cycle. If the external clock is faster than the port reference clock, the slip counte~ 266 or 266' value approaches zero at which time the external clock is prevented from decrementing the slip counter and the port byte clock is allo~led to increment the slip counter until it reaches the value of eight or 16, depending upon the elastic buffer size. Then normal operation resumes. If the external -lock is slower than the poxt reference clock, the slip counter 266 or 266' value approaches the maximum, at which time the port byte clock is prevented from incrementing the slip counter until the slip counter is back to the value of eight or 16. Then normal operation resumes. The read pointer 264 is always incremented at the port reference clock rate thereby allowing the same receive RA~ 232 with the same read pointer 264 to be used by both of the output lines 194 an~ 194' operating asynchronously to each other. The effective read address for the two ports will be different.

~9-80-C02 1 .~5759I

O eration of the Data Port with Deferred Data P

In the deferrable data mode which applies to data rates accumuLatins less than one channel's worth of data per frame, the computation of the state of the DAC bit for the channel is determined by the port. This is achieved by storing the 60th b~te selected by the digital switch 30 in frame N and comparing it with the 60 bytes se-lected during frame tN+l). If no compare occurs during the (N+l) frame, the DAC bit is turned off and is not allowed to turn on a~ain until a compare occurs between the 60th byte of frame (NtP-l) and the first byte of frame (N+P) where P equals 2, 3, 4,...,X where X is a total number of frames transmitted during the call. The enqueue control ROS 88 need monitor only the DAC bit associated with the 60th byte of any given frame to determine whether or not that frame should be trans-mitted. `

At rates equal to or lower -than 19.2 Kbps, the transmit ~
pattern generator 224 is synchronized every 40 frames with the transmit frame sync signal. Forty frames is employed because the 2.4 Kbps pattern repeats every 40 frames and the 60 byte counter 217 will have a value of ~ero. The counter is reset to zero every 40 frames with the transmit frame sync pulse over line 91.

In the deferred mode, the management of the internodal write pointer differs from what it is in the normal mode because a transmitted channel of data can be received in more than one receive frame. Fiyure 24 illustrates the operation for 9.6 Kbps ports. Table VIII gives an example of a 9.6 Kbps data port operation. As was previously mentioned, the data port passes the same channel of data to the digital switcn in two consecutive frames for low speed data ports having rates of 19.2 Kbps or less. Thus, channel a in Figure 24 is loaded into the TBB on frames 0 and 1. l~he TBB 54 has the ~A9-80-002 115759~

option of transmitting this channel on transmit frames 1, 2, 3 or 4 ~hich means that the ~ort must be able to receive data on the corresponding receive frames. The internodal write pointer 256 instead of being incre-mented only on the receive frame Y01 as is normaliy thecase, is set to ~he value it had at the beginniny of -the frame Y01 for frames Y02, Y03 and Y04, in ~igure 24.
- Since data is actually transmitted only on one frame, the DAC bit accompanying the data received from the digital switch 30 in the receiving station will be off only on the receive rame corresponding to the one frame when data was transmitted. Thus i data was transmitted on the transmit f-ame X03, it will be received, that is (DAC bit off) on receive Y03, at which time data is written into the receive RAM 232. At the beginning of frame Yll, the internodal write pointer ~56 is allowed to operate in the next 60 byte section of the receive RAM 232. To take into account the additional delay introduced by deferring the transmission of data, an additional offset of 60 bytes is introduced between the internodal write pointer 256 and the read pointer 264 at the satellite frame sync time.

~9-80-002 1 1575~ l T~BEE VIII
9.6 Kbps _ Transmit 0 1 2 3 4 5 Frame _ Bytes ~ ! 60 18 36 54 72 30 48 Accumulated in Data Port Selects ¦¦ 60 60 60 60 60 60 60 Digital ll S itch !l ` I
Transmit l 1 0 0 0 1 0 0 Pattern Generator .
Channels ¦ Al...... .A60 A60.. A60 Output (B) to Digital Switch ¦ _ DAC Bitsjl 0.... .0 1... 1 1... 1 ¦ l.. l 1.... 1 1... 1 1... 1 I _ P.~5 Bits ¦¦ O 1 1 ¦ 1 1 1 1 I , _ TBB-A ¦¦ Al..... A60 ~ A60.. A~o TBB-B l l Al.. A60 A60.. A60 Enqueue i¦ YES YES N0 N0 .
_ Transmit ¦¦ DEFER DEFER BTuBBsA l N0 NO N0 .. ! -- __ Receive ~¦ 1 2 3 4 5 6 Frame ,1 ~ _ RBB ll Al... A60¦ EMPTY
l _ RBB I 1 1 0 ¦ 0 1 l l Loaded I l Bit I _ l _ _ _ Receive ¦¦ o o o ¦ 1 o o 1 Pattern l l Generator I I ! - -Receive 11 ¦ Al.. A60 A60.. A60 Data Port 11 I I
on Last 11 Available 11 I I
Frame 11 I I

~1A9-80-002 1 ~5759 1 Intranodal Operation On the receive side of the data port, the internodal and intranodal pattern generator are implemented. The operation of the pattern generators is as described above except that in the intranodal case, the intranodal status register 245 in Figure 20 is preset with the value in the transmit status register 229 at the trans-mit frame switch time plus 250 microseconds, labeled 91' in Figure 20. The signal in 91' opera~es the gate 2~3 which transfers the contents of the transmit status register 229 to the intranodal status register 245. The duration of 250 microseconds is the path delay for a byte traveling from the transmit side of the port ~la the intranodal buffer (I~B) 56 to the receive side of the data port. For the internodal pattern generatox, the 60 byte counter 217' is reset to zero every 40 frame times and the satellite status register 229' is preset with the value in the channel counter 219' every receive satellite frame switch time. The channel counter is then set to zero. The relationship between the transmit frame sync pulse and the satallite frame sync pulse is described with respect to Figure 23. The transmit frame sync pulse occurs every other superframe. The recei~Je frame sync pulse is synchronized to a byte time of the transmit frame.

The intranodal and internodal pattern generators are separately synchronized and independent from each other.
Li~ewise, the intranodal write pointer 256' in the Figure 27 is increment~d independently of the internodal write pointer 256. This enables the port to service an intranodal connection for one port and an internodal conr.ection for the other port. If both ports are par~
of the same type of connection, they will use the same write pointer in ~igure 27. The port ID which is presented to the port by the ~C~ 50 when the port is ~9-80-002 I 1 ~759 1 port 0 is the loca-tion 0 throu~h 225 of the receive P~M
232 and when the port is port 1 the corresponding lo-cations are 256 through 511 of the receive P~M 232. T~.eport ID represents the high order bit of the write address to the receive RAM 232.

Thus it is seen b~ synchronizing the transmission and reception pattern generators for all data ports operating at the same data rate throughout the entire TDI~A system, the necessity for bit stuffing to accornmodate non-integral multiple data rate data ports is eliminated andyet data activity compression operations can be carried out.

Integral Multiple Data Rate Feature The integral multiple data rate featuxe finds appli-cation in a TD~ communications controller having a plurality of inputjoutput ports for transferring ni channels of m data units each per TDMA frame from ,~
respective, local data users to a TDMA transmit burst communications link and transferring ni of the channels of data from a TD~ receive burst communication link to the respective local users on a time interleaved ~asis during periodic TD~A frames, each port operating at its own data rate Xi.

The digital switch 30 includes a transmit burst buffer 54 having a data input connected to a transmit bus 44a common to the data outputs of all of the ports 14, 16, 18 and 20 and a data output connected to the TDMA
transmit burst co~munication link. The transmit burst buffer has a plurality of addressable storage locations arranged into ro~s and m juxtaposed columns.

The digital switch further includes a receive burst buffer 64 having a data input connected to the TD~1A
receive burst communication lin~ S and a data output ~'~9-80-002 1 1575(~ 1 connected ~o a receive bus 44b co~mon to the data lnputs Oc all of the ports. The receive burst buffer has a plurality of addressable storage locations arranged into rows and m jux~aposed columns.

The digital switch invention further includes a scanner 70 having a periodic cycle of m scans per TDMA frame, there being a frame rate o f frames per second, with a scan count output 77 connected as a column address input to the transmit burst buffer and to the receive burst buffer.

The digital switch further includes a switch control memory 50 having an address input connected to a scan output 75 of the scanner, a port select output 78 con-nected to a control input to each of the ports and a stored address output 82 connected to a row address input to the transmit burst buffer and to the receive burst buffer. The switch control memory stores ni control words for each of the ports, each of the ni ~
control words for the i-th port issuing a port select signal to the i-th port and issuing a distinct row address to the transmit burst buffer and the receive burst buffer when scanned by the scanner. The value of ni is equal to Ri divided by m times f.

In this manner, geographically remote ports having a varlety of data rates can be serviced on a time inter-leaved basis.

The disital switch further includes an intranodal buffer 56 having a data input connected to the transmit bus and a data output connected to the receive bus, with a plurality of addressable storage locations arranged int~
rows and two juxtaposed columns. The intranodal buffer has a row address input connected to the stored address output 82 from the switch control memory and a column address input connected to the scan count output 77 from ~9~80-002 the scanner, for transerring data between the 'irst and second ones of the local ports. -A first and a second one of the local ports having thesame data rate Ri will have ni pairs of the control words in the switch control memory. Each of these pairs will have a first control word in the j-th pair issuing a port select sign~l to the first port and a row address to the p-th row in the intranodal buffer on even scans of the switch control memory and to the p~1 ~T row in the intranodal buffer during odd scans. A second control word in the j-th pair will issue a port select signal to the second port and a row address to the p+l ST row in the intranodal buffer in even scans of the switch control memory and to the. p-th row in the intranodal buffer during odd scans.

~uring even scans of the switch control memory a read access is made to a first one of the columns and a wrlte access is made to the second one of the columns in the intranodal buffer and during odd scans of the switch control memory a read access is made to the second one of the columns and a write access is made to the first one of the columns of the intranodal buffer.

The low order bit of the byte scan count 77 is input to the intranodal buffer 56, as shown in Figures 11 and 12, to alternate the row address access for paired locations in alternate SCM scans and to alternate the writing and reading into the A and B columns of locations in the I~B
56 in alternate SCM scans. For example, when the low order bit of the byte scan count 77 is zero, the low order bit of the row address 82 can be inverted so that the p-th I~B address stored in the SCM word is converted to the p+l ST location and the p+l ST location is con-verted to the p-th location. When the low order bit of the byte scan count 77 is a binary one, the low order bit of the row address 82 can pass unchanged to the row ~A9-~0-002 1157~1 address input of the intranodal buffer 56. In a similar manner, when the low order bit of the byte scan count 77 is a zero, the ~ column can be read and the B column can be written into in the INB 56. When the low order bit of the byte scan count 77 is a binary one, the A column can be written into and the B column can be read from in the INB 56.

The values of ni can be integral values so that data ports having integral multiple speeds of the basic TDM~
transmission rate correspondiny to a single SCM word in the SCM 50, can be accommodated.

Non-Inte ral Multiple Data Rate Feature g The non-integral multiple data rate feature finds application in a TD~A communications controller having a plurality of input/output ports for transerring ni channels of (qi+ai)m data units each per TD~ transmit frame from respectiv~ local data sources to a TDMA ~
transmit burst communication link on a time interleaved basis during periodic TDMA transmit frames. Each port operates at its own data rate Ri, where qi is a positive integer or zero, m is a positive integer and ai is a fraction bet~Jeen zero and one.

An input buffer 214 in one of the ports 14, 16 or 18 has an input connected to a respective local data source 10, for accumulating (qi+ai)m data units per TDMA transmit frame.

A mod m ~ransmit counter 217 in the one port has an input connected to the respective local data source, for counting the number of groups of m data units accumu-lated during each of the TD~ transmit frames.

~IA9-80-002 ~ 15759 1 The transmit output register 216 in the one port, has an input connected to the input buffer and an output -connected to the transmit bus, for gatably transferring consecutive data units from the input bufrer to the transmit bus.

The transmit burst buffer 54 has a data input connected to the transmit bus and a data output connected to the T~A transmit burst communication link, with a pluralit~
of addressable storage locations arranged into ro~ts and m juxtaposed columns.

The scanner 70 has a periodic cycle of m scans per TD~
transmit frame, there being a frame rate of f frames per second, with a scan count output 77 connected as a column address input to the transmit burst buffer.

The switch control memory 50 has an address input connected to a scan output 75 of the scanner, a port select output 78 connected to each of the ports, and a stored address output 82 connected to a row address input to the transmit burst buffer, for storing qi~l control words for the one port, each of the control words issuing a port select signal to the one port and issuing a distinct row address to the transmit burst buffer ~Jhen scanned by the scanner, whexe (qi~ai) =
Ri/mf -A transmit transfex gate 239 in the one port, has a datainput connected to the mod m transmit counter, a control input connected to the scan count output of the scanner and an output, for transferring the contents of the mod m transmit counter to the output for each of the m scan counts per TDMA transmit frame.

A transmit selects counter 233 in the one port, has a data input connected to the output of the transmit transfer gate and a control input connected to the port l 1575~ l select output of the switch control memory, for re-ceiving the contents of the mod m transmit counter for~
each of the m scan counts in a T~1A transmit frame and decrementing the received contents by one for every port select signal received from the switch control memor~
during any one of the scan counts.

- A transmit zero detector 237 in the one port, has an input connected to the said transmit selects counter and a control output 227 connected to a gate input of the transmit output register 216, for detecting when the contents of the transmit selects counter is not zero and sending an enabling signal to the transmit output register for transferring one of the data units from the input buffer to the transmit bus, the detector inhibiting the transfer through the transmit output register when the detected contents of the transmit selects counter is zero.

In this manner, data from a local data source having a data rate Ri which is not an integral multiple of the scan count rate mf of the scanner, can be transmitted.

The receive burst buffer 6~ has a data input connected to the TD~A receive burst communication link S and a data output connected to the receive bus, with a plu-rality of addressable storage locations arranged into rows and m juxtaposed columns, having a column address input connected to the scan count output of the scanner and a row address input connected to the stored address output of the switch control memory.

A receive output buffer 232 in the one port has a data input connected to the receive bus and an output con-nected to a respective local data sink 10, for gatably buffering consecutive data units in a data field re-ceived from the receive burst buffer for transfer on an output line 241 at the data rate Ri to the respective local data sink.

~'~9-80-002 1 .1~75~

An output clock 215 in the one port, counts the number (qi+ai) m of the data units per TDMA receive frame to.be transferred from the TDMA receive burst communication link to the respective local user.

A mod m receive counter 21t' in the one port, has an input connected to the output clock, for counting the number of groups of m data units which should be ac-cumulated in the receive output buffer from the TDMA
receive burst communication link during each of the TDMA
receive frames.

A receive transfer gate 239' in the one port, has a data input connected to the mod m receive counter, a control input connected to the scan count output of the scanner and an output, for transferring the contents of the mod m receive counter to the output for each of m scan counts per TDMA receive frame.

A receive selects counter 233' in the one port, has a .
data input connected to the output of the receive transfer gate and a control input connected to the port select output of the switch control memor~y, for re-ceiving the ~ontents of the mod m receive counter for each of the m scan counts in a TDMA receive frame and decrementing the received contents by one for every port select signal received from the switch control memory during any one of the scan counts.

A receive zero detector 237' in the one port has an input connected to the receive selects counter and a control output connected to a gate input of the receive output buffer, for detecting when the contents of the receive selects counter is not zero and sending an enabling signal to the receive output buffer for buffer-ing one of the data units transferred from the receive burst buffer over the receive bus, the recelve detector inhibiting the buffering in the receive output buffer ~hen the detected contents of the receive selects counter ls zero.

~A9-80-002 l l5759 ~

In this ~anner, data to be transferred to a local data sink ha~Jing a data rate Ri which is not an integral multiple of the scan coun~ ra~e mf of the scanner can be received.

~n intranodal buffer 5~, has a data input connected to the transmit b~s and a data output connected to the receive bus common to the data inputs of all of the ports, with a plurality of addressable storage locations arranged into rows and two juxtaposed columns, with a row address input connected to the s~ored address output from the switch control memory and a column address input connected to the scan count output 77 of the scarner, for transferring data between the first ports and a second port.

The port and khe second port have the same data rate Ri having qi+l pairs of the control words in the switch control memory, each of the pairs having a first control word in the j-th pair issulng a port select signal to the first port and a row address to the p-th row in the intranodal buffe-r in even scans of the switch control memory and to the p+l ST row in the intranodal buffer during odd scans and a second control ~lord in the j-th' pair issuing a port select signal to the second port and a row address to the p+l ST row in the intranodal buffer in even scans of the switch control memory and to the p-th row in the intranodal buffer during odd scans.

The scan count 77 connected to the column address input enabling a read access of the first one of-the columns of the intranodal buffer and a write access of a second one of the columns of the intranodal buffer during even numbered ones of the scans of the switch control memory and enabling a read access of the second one of the columns of the intranodal buffer and a ~rite access of the first one of the columns of the intranodal buffer during odd numbered ones of the scans of the switch control memory.

1 ~7591 A receive output buffer 232 in the second port has a data input connected to the receive bus and an output:
connected to a second respective local data sink, for gatably buffering consecutive data units in a data field received from the intranodal buffer for transfer on an output line at the data rate P~ to the second respective local data sink.

An output clock 215 in the second port, counts the number (~i+ai) m of the data units per TD~A intranodal frame to be transferred from the intranodal buffer to the second respective local user, the TD~ intranodal frame belng delayed by the period of one of the scan counts 77 with respect to the TDMA transmit frames.

A mod m intranodal counter 217 in the second port, has lS an input connected to the output cloc~, for counting the number of groups of m data units which should be ac-cumulated in the receive output buffer from the intra-nodal buffer during each of the TDMA intranodal frames. .

An intranodal transfer gate 248 in the second port, has a data input connected to the mod m intranodal counter,a control input connected to the scan count output of the scanner, and an output, for transferring the contents of the mod m intranodal counter to the output for each of m scan counts per TD~A intranodal frame.

An intranodal selects counter 249 in the second port, has a data input connected to the output of the intra-nodal transfer gate and a control input connected tc the port select output of the switch control memory, for receivin~ the contents of the mod m intranodal counter for each of the m scan counts in a TDMA intranodal frame and decrementing the received contents by one for every port select signal received rom the switch control memory during any one of the scan counts.

1 1575'3~
-119-.
An intranodal receive zero detector 250 in the second port has an input cannected to the lntranodal selects -counter and a control output'connected to a gate input to the receive output buffer, for detecting when the contents of the intranodal selects counter is not zero and sending an enabling 'sig'nal to the receive output buffer for buffering one of the'data units transferred from the intranodal buffer over the receive bus, the intranodal detector inhibiting the buffering in the receive output buffer when the detected con-tents of the intranodal selects counter is zero.

In this manner, data to be transferred to a second local data sink having a data rate Ri which is not an integral multiple of the scan count rate mf of the scanner can be received from another local port o~ the same data rate.

Although a specific embodiment of the invention has been disclosed~ it will be understood by ~hose with skill in the art that the foregoing and other changes in form and ,~
details ma~ be made therein without departing from the spirit and the scope of the invention.

~A9-80-002

Claims (3)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a time synchronized communication system containing a transmitting data port and a receiving data port for transferring channels of digital information of N bytes in length during each time frame, wherein the improve-ment comprises:

a storage means in the transmitting data port for storing the last byte in the present time frame transmitted to the receiving data port;

a comparison means connected to said storage means in said transmitting data port and connected to the input data source to the transmitting data port, for comparing the last byte transmitted in the present frame to each byte of data in the channel to be transmitted in the next frame;

data transmission switching means connected to said input data source and said comparison means for transmitting the channel of data in said next frame if said comparison means determines that said last byte in said storage means has not been replicated in every byte in said next channel and said switching means preventing the transmission of said next channel of data if said byte stored in said storage means is replicated by every byte of data in said next channel of said next frame;

a synchronization means connected to said transmitting data port and said receiving data port for synchronizing the operation of said transmitting port and said receiving data port;

a second storage means in said receiving data port for storing the last byte of data re-ceived from said transmitting data port in said present time frame;

replication means connected between said second storage means and the data destination connected to said receiving data port, and connected to said synchronization means, for generating M replicated bytes and trans-mitting them to said destination when no data is received from said transmission port in said next frame.

2. In a TDMA satellite communication system containing a transmitting data port at a first earth station and a receiving data port at a second earth station for transferring channels of digital information of N bytes in length during each time frame, wherein the improvement comprises:

a storage means in the transmitting data port for storing the last byte in the present time frame transmitted to the receiving data port;

a comparison means connected to said storage means in said transmitting data port and connected to the input data source to the transmitting data port, for comparing the last byte transmitted in the present frame to each byte of data in the channel to be transmitted in the next frame;

data transmission switching means connected to said input data source and said comparison means for transmitting the channel of data in said next frame if said comparison means determines that said last byte in said storage means has not been replicated in every byte in said next channel and said switching means preventing the transmission of said next channel of data if said byte stored in said storage means is replicated by every byte of data in said next channel of said next frame;

a synchronization means connected to said transmitting data port and communicating with said receiving data port for synchronizing the operation of said transmitting port and said receiving data port;

a second storage means in said receiving data port for storing the last byte of data re-ceived from said transmitting data port in said present time frame;

replication means connected between said second storage means and the data destination connected to said receiving data port, and communicating with said synchronization means, for generating N replicated bytes and transmitting them to said destination when no data is received from said transmission port in said next frame.

3. In a TDMA satellite communication system con-taining a transmitting data port at a first earth station and a receiving data port at a second earth station for transferring channels of digital information of N bytes in length during each time frame over a satellite com-munication link, wherein the improvement comprises:

a storage means at said first earth station for storing the last byte in the present time frame transmitted to the receiving data port;

a comparison means connected to said storage means at said first earth station and con-nected to the input data source to the trans-mitting data port, for comparing the last byte transmitted in the present frame to each byte of data in the channel to be transmitted in the next frame;

data transmission switching means connected to said input data source and said comparison means for transmitting the channel of data in said next frame if said comparison means determines that said last byte in said storage means has not been replicated in every byte in said next channel and said switching means preventing the transmission of said next channel of data if said byte stored in said storage means is replicated by every byte of data in said next channel of said next frame;

a synchronization means connected to said transmitting data port and communicating with said receiving data port for synchronizing the operation of said transmitting port and said receiving data port;

a second storage means at said second earth station for storing the last byte of data re-ceived from said transmitting data port in said present time frame;

replication means connected between said second storage means and the data destination connected to said receiving data port, and communicating with said synchronization means, for generating N replicated bytes and trans-mitting them to said destination when no data is received from said transmission port in said next frame.