CA1153122A - Data processing system with direct device-to-device data transfers - Google Patents

Abstract

ABSTRACT

Under the I/O protocol required by conventional computer architectures, peripheral devices communicate with each other via the CPU of a host computer. That requirement necessitates two separate data transfers and cuts the data transfer rate by one-half.
This invention discloses a data processing system having an architecture that will allow high-speed direct device-to-device data transfers independently of a computer memory. The system consists of a host computer interconnected with a remote signal processing subsystem. A Direct Device Access Bus and a plurality of data processing devices are provided. The supervisor includes means for subdividing the plurality of devices into several device sets by assigning a unique transaction code to the members of each set, a different code being used for each different set. A controller associated with a Signal Processing Subsystem supervisor, selectively interconnects desired ones of a set of data processing devices via the Direct Device Access Bus to provide direct communication between the selected devices of each of several device sets on a substantially concurrent basis.

Description

~;3~;~2 ~ 1-APPARATUS FO~ DI~ECT DEVICE-TO-D~'~ICE DATA T~AL~FEI~

l This invention discloses a novel aigital computer architecture desi~ned to process large blocks o~ ~a~a wherein the same operation or sequence of operations is performed on all of the elements which make up the data block.
Conventional, general-purpos~ computer systems typically include a memory, central processing unit (CPU) and one or more input-output (I/O) c'hannels with a plurality of peripheral devices. The central element in all data-processinu transactions is the memory. The CPU
communicates to and from the memory. Each periphera'l device com~unicates via its I/O channel to the memory. For example, to transfer the contents o~ a magnetic tape record to an array processor in order to perform certain arit~etic operations on the data, the recora from the magnetic tape must be transferrea to the com~uter memory and thence ~rom the computer memory to the array processor. ~'hat single transaction requ-lres two data transfers. ~he first trans~er results in a write to the computer memory from tape; tne second transfer results in a read ~rom memory to the array processor. In essence, the computer aata-trans~er 'bandwidth has been cut in half 'because o~ t'he two trans~ers required by a single transacton.
Typically, peripheral devic~s sucn as a magnetic tape drive, transfer data at a cons~ant rate. The I/O cnanr~e'l to which a device is connected and the me~ory to or from which data are being transferred must be prepared to transmi~ or receive aata at the rhte required 'by the aevice, otherwise, an overrun condition will occur. Devices exhibiting that characteristic are de~ined as "I/O ~ynchronous" devices. On the other hand, a rando~ access Du'lk storage memory that can tolerate a variab'le I/O transfer rate ~not to exceed its maximum cycle time of course) may be classi~ied as an "I/O
Asynchronous" device.
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1~531Z2 In conventional computer systems, the reason for routing all transactions through the computer memory is that typically both the source and receiver peripheral devices involved in a transaction, are of the I/O synchronous type.
The computer memory acts as a buffer between the source and receiver peripheral devices.
In the example given earlier, the array processor is a device which has its own memory and it therefore behaves as an I/O asynchronous peripheral device. Theoretically, as far as synchroni~ation of data transfer rates is concerned, data could be transferred directly from the magnetic tape drive to the array processor. In practice, known conventional computer architectures do not allow direct device-to-device transfers.
In signal processing in general and in seismic data processing in particular, large blocks of data are processed wherein the same operation is performed on all of the data elements that make up the data block. Therefore, only a relatively small amount of logic and control is required for a given block of computation that is to be performed on each of a very large number of data values. By contrast, business data processing, for which most general purpose computers are designed, requires relatively large amounts of logic and decision making for relatively small amounts of computation.
It is an object of this invention to provide a data processing system having novel architecture that will allow direct device-to-device data transfers without first detouring the data through memory.

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The invention relates to a data processing subsystem associated with a host computer, comprising: a supervisor for establishing communication between the host computer and the subsystem; a direct device access bus; a plurality of peripheral devices, all having equal priority and means for interfacing each device with the direct device access bus;
means associated with the supervisor for subdividing the plurality of peripheral devices into several device sets by use of several unique transaction codes and for assigning a different task to each device set; a bus controller inter-connected between the supervisor and the direct device access bus for opening and closing data pathways, over the direct device access bus, between the members of each device set to enable substantially concurrent data transfers between the members of the several device sets as required in the performance of the different tasks.
In a preferred embodiment of this invention, the improved data processing system includes a host computer having a CPU, associated memory modules, and peripheral devices such as mass storage media, all interconnected by appropriate data buses. A remote Signal Processing Subsystem is coupled to the host computer by a Signal Processing Subsystem Supervisor. A Direct Device Access Bus and a plurality of data processing devices are provided. A
controller associated with the Signal Processing Subsystem Super-visor, selectively interconnects desired ones of a set of data mg/'' - 2a -. ~

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1 processing devices via the Direct Device Access ~us to provide direct device-to-device communication between the selected devices of a set. One of the devices of a set is considered to be a source device and the other device or devices are considered to be a receiver device(s).
In accordance with an aspect of this invention the controller schedules concurrent parallel m~ltiple-task, direct device-to-device data transfers between the memkers of each set of a plurality of sets of devices ky dynamic time slot allocation.
In another aspect of this invention, either the source or the receiver device(s) of each set is an asynchronous device.
In accordance with another aspect of this invention, the Signal Processing System Supervisor enables transfer of data between a transmitter and a plurality of receivers in a parallel multiple-record transfer mcde.
In accordance with yet another aspect of this invention, serial split-record data transfers are enabled by a comnand/data chaining technique.
In accordance with a further aspect of this invention, means are provided for establishing a plurality of time slots.
The time slots are grouped into frames. m e width of a frame in terms of time slots is varied in accordance with the number of sets of devices currently being service In accordance with another aspect of this invention, each peripheral device of a set of such devices is connected to the Direct Device Access Bus by a General Purpose Device Adapter.
m e adapters are interconnected with the Signal Processing Subsystem Supervisor by a commandlcor~trol bus. In response to signals from the supervisor, a programmable micro-controller in each General Purpose Device Adapter activates its attached device and enables direct device-to-device data transfers between selected devices of a desired set.
In a ~urther aspect of this device, the General Purpose Device ~dapter includes an input/output data board for transferring data between the direct device access bus and the peripheral device connected to the Gen~ral Purpose Device Adapter. The data ~ 1~ii31Z2 1 board also includes a FIFO memory for a~sorbing minor variations in data transfer rates between devices and a data~word reformatting means.
ln yet another aspect of this invention, means are provided for assigning a transaction code to the General Purpose Device Ac'apters that are to participate in each one of a plurality of data transfers. Means are also provided for monitoring the available time slots for use in multiple data-transfer operatiorls. m e transaction codes are tabulated and indexed a~ainst the respective available time slots.
ln a further aspect of this invention the commanl protocol is separate and distinct from the data transfer protocol and operate asynchr~nously with respect to each other.
In yet another aspect of this invention, the host computer transmits groups of Supervisor Command Packets to the Signal PL~cessing Subsystem Supervisor. Each group of oommand packets ~efines a different transaction. Selected Supervisor Ccmmand Packets are transformed into Device Command Packets by the Supe~visor. In response to a group of active and pending SupeLvisor Command Packets the Supervisor establishes a p~urality of direct device-to-device data transfers independently of intervention ky the host ccmputer.
~ n another embodLment of this invention, the Signal Processing Subsystem Supervisor establishes direct data transfers bet~een a device in the Signal Processing Su~system and the host com~uter, independently of m~ltiple tasks that may be currently underway in the subsystem.
In another embod1ment o~ this invention, the Signal Processing Subsystem SupeLvisor establishes serial split-record 3~ data tra~sfers between a transmitter and a plurality of different receivers.
~ me benefits and features of this invention will better ; ke understocd by reference to the acoolpanying description and the drawnngs wherein:

~53122 1 Fig. 1 is a block diagram of the Large-Volume, High-Speed Data Processor;
Fig. 2 is a detailed drawing of the Direct Device Access Bus controller, Fig. 3 is a detailed shcwing of the General Purpose Device A~apter control koard;
Fig. 4 is a detailed diagram of t~e General Purpose Device A~apt~r data koard;
Fig. 5 is a timing diagram illustrating the timing of events invol~ing parallel m~ltiple device-to-device data transfe~s;
Fig. 6 shows the relationship ~etween a transmitter-receiver pair of GPDAs;
~ Fig. 7 is a simplified flow diagram of the sequence of events that t ~ e pl æ e in the trans~itter GPDA of Figure 6; and Fig. 8 is a simplified flow diagram of the sequence of events that take place in the receiver GPDA of Figure 6.

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~1~;3~22 1 ~eIerring now to Figure 1~ the Apparatus ~or Direc, Device-to-~evice Data i~rans~er consis~s of a host com~uter and a Signal Processing Subsystem (SPS) 12, shown enclosed by dashed lines. lhe host computer may be any conventional computer having a ~PU, large-capacity memory with the usual perip~leral devices such as a disc ~rive, ta~e drives, line printer, console terminal, card reader, etc. A
preferred compu~er system îs the VAuX 11/780 with at least 1.0 megabytes o~ memory, made ~y Digital Equipment Corporation o~ Maynard, ifassachusetts. VAX is a trademark of that corporation.
T~.e SPS is a special purpose data processing subsystem designed ~or e~Iicient handling oI ni~h volume, high density data. It achieves that purpose by ~eans o~ an internal high-speed, ~ime-multi-plexed data bus that enables parallel multiple direct device-to-device data transfers between a plurality of peripneral devices on a concurrent basis.
Si~nal Processing Subsystem 1~ consists or:
1. An SPS Supervisor (SPSS) 14;
~. A Direct Device Access Bus ~ontroller 16;
3. A Direct Device Access Bus (DDA Busj consistin~
o~ a set, 18, o~ thirty two ~ata lines, and a set, 20, of sixteen control lines including clocks, control, transaction-coae a~aress and parity lines;
4. A plurality of peripheral devices Z2-~8 such as magn~tic tape drives, disc drives, array processors, and demultiplexing ~emories;
5. A plurality of General Purpose ~evice ~dapters (GPDA) whîch interface the respectlve devlces to the DDA Bus and are the basic input/output controllers for the system. A GPDA COIISiStS o~ a data section such as 30-38 and a control section such as 40-48 that adayt, under rirmware control, a given GP~A to the device it is to service.
Fifteen or more such GPDAs may be employed although only four are snown;
6. A ~ontrol/Status line 50 ~or inteIIacing the SPSS
with the host computer;
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1 7. A Command/Control Bus (CCB) 52 for interfacing the SPSS with the devices via the GPnAs; and 8. A Data Interface Bus 54, for transferring data from the DDA Bus directly to host computer 10.
Fra~ hardware standpoint, SPS 12 is a stanl-alone system although within the overall framework it is contr~lled ~y the host computer 10. Control fram the host co~puter 10 is transmltted in the form of Transaction Command Packets (TCP~, to be discussed helcw, over Control~Status line 50, in serial ord~lr.
m e SPS Supervisor (SPSS) 14 functions as a data flow controller, controlling the data transfers on the DD~ Bus unler the supervision of the host computer. Its main function is to take Transaction Commanl Packets from the hos-t computer, transform them into individual Device CQmmand Packets fQr each of the various devices on the DDA Bus, and to route these commands to the correct device. The system i5 able to open and close data paths as required. It is also used to dcwn-load fir~ware into the DDA Bus Controller and the GPDAs.
A Transact~on Control Packet (TCP) consists of a ser_es of Supervisor Control Packets ~ ) that instruct the SPS
SupervisOr how to complete a transaction to do a desired quantitv of work. me Supervisor then transforms selected SCP-s into Device Command Packets ~DCP) that exe cise co~trol functions, through the GPD~s, over the peripheral devices.
Device Control PacXats æ e sent from the SPSS to the DDA
Bus Controller and GPDhs via CCB 52. Status messages from the devices are routed back to the SPS via the CCB.
m e Direct Device Access Bus Controller 16 iâ the link between Direct Device Access Bus 18, 20 and SPSS 14. Control information is passe to the DDA Bus Controller via the CCB.
The controller interprets this information and sets up or terminates a device-to-device data path on the DDA bus. The DDA Bus controller can also enable m~ltiple device-to-device transfers on a dynamic tim~-slot ailocation basis. Thus, the command protocol is separate and distinct from the data-transfer protocol and they function asynchronously wqth respect to each other.

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. . . - ~ ~ ~;, , ~53122 1 m e 48-bit wide Direct Device Access Bus contains a 32 bit wide data path, 18, with a 16-bit wide bus, 20, including byte p æ ity, clocks, control, and address lines. It is a time multiplexed ~us capable of muLtiple-device-to-device transfers at a mE~d~lm aggregate transfer rate of 40 megabytes of data per second.
With reg æ d to data transfers over the two sets of DDA
EhLs lines 18, 20, three terms must e defined: a time slot, a transaction aperture and a frame. A time slot is a lOOns period d~ring which a specific data transfer over the ~D~ Bus is permitted to take plaoe . A transaction aperture has a width equaL to the number of time slots required to ccmplete a transaction. A frame is the time periol between repetitions of any specific slot. If four muLtiplexed da~a transfers æ e taking place, the fxame wid~h will be 400ns and there will be four slots/frame. An unusual feature of the DD~ Bus is that data paths æ e only created when they æ e needed. The Bus Controller under command frcm the SPSS dynamically creates a time-multiplexed slot on the bus for every required data transfer.
m us if three ind~pendent data transfers are called or, ~he controller opens up three slots. If another transfer is r~quested then the number of slots/frame is increased to four. m us, the frames æ e of variable length. When any transfer termin3tes, its slot is removed. Due to the overlapped bus protocol, a minimum of two slots/frame are required.
A ne~c~NIm limit of fifteen attached devices plus the Dn~
Bus Controller has been æ bitr æ iLy established. However, ~he system is in no way limited to that number of peripheraLs. As is welL kncwn, a peripheral unit, such as one or more tape drives includes a dedicated controller for formattinq and scheduling incoming and outgoing data. For purposes of this disclosure, both the peripheral unit and its dedicated controller is considered to be a sinqle peripheral device. Since the peripherals always work in sets, i.e. there must be a data source and at least one destinatio~ The nE~u~mm normal effective ;

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g 1 frame widt~ ~or fi~teen devices is seven tîme slots. A ~ce-y feature oi the ~A Bus is tha~ it enables device-to-device transfers ana that these transfers are activated without any arbitration protocol from the host computer.
As its name implies, the General Purpose Device Adapters are designed to interface any peripheral device to the DDA Bus. Physically all of t'he GPDAs are identical.
The personali~y or characteristics o~ a giv~n' GPDA are determined by the firmware that is down-loaded from the SPS~
at system intialization time. 'rhe firmware provides each GPDA with all of the information that it needs to transfer data from the peripheral device to which it is connectea across the D~A Bus. I~ a GPDA is removed from one device and connected to another, it is a simple matter ~o reprogram the firmware.
The purpose of the Signal ProcessinO Subsystem is to perfor~ multiple tasks of usefu'i work with minimal intervention Dy the llOSt computer. A transac~n is defined as the performance of a desirea task. A typical transaction might consist of transferrin~ a multiplexe~ data stream ~rom a seismic magne~ic ïield tape to a demultiplexing memory and thence to store the demultiplexed data on a disc ~or furt~er processing.
A transaction is accomp'lished by sending a p'lurality of Supervisor Command Packets (SCP) from the host computer to the SPSS over the Control/Status ~us 50. An SCP con~ains all of the information required by the SPS to complete a requested action and a transaction contains all o~' t't~e S~Ps required to complete a single processing step, i.e. transfer o~ data irom tape to a demultiplexin~ memory. SCPs provide for data transfer operations, transaction modification, error recovery and status reportin~. ' Certain ~ypes of SCPs generate Device Command Pac'kets (DCP~ which are transmitte~ to the appro?riate ~PDA control modules over ~ommandlControl Bus 52. A DCP contains information that is both genPral (i.e. applicable to ~l'i ~evices) and device speci~ic. ~rnformatioll preserlt in a DCP
will ~e the source;
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31~2 1 destination transaction code, device camma~ds, byte count for the block of d~ta to be transferred, starting ~ress for the data transfer.
Normally, several data transfer operations are conducted concurrently. Accordingly, a queue of -~everal Transaction Ccmmand Packets is sent to SPS 12 frcm host ccmputer 10. The SPSS 14 then accepts the transaction command packets and allocates thè necessary resources to the various tasks:to be perfor~d in an orderly sequence. A resource is defined as a device such as a ~gnetic tape drive, a storage element such as a dem~lti~lexlng ~moryr or a data pathway such as a disc controller.
m e overa U operation of the system can be described, in a simplified w~.y, as follows. Assume that ten thousand bytes of data are to be transferred to an array processor fr~m a magnetic tape. An array processor, for purposes of this disclosure, is a device for performing a sequence of high-speed mllltiply/add operations for use in data correlation.
A TCP is sent from host ~omputer 10 to SPSS 14. The SPSS then alerts a tape drive over CCB 52, designating it as a source or transmitter, assigns to it a specified transacti~n code c~nl sets up a ~yte ccunter to a count of 10,000. m e SPSS also designates the aulay processor as a receiver, assigns to it the same transac~ion ccde as the tape drive and the same byte count.
At the same time, the SPSS tells the DD~ Bus Controller that it is to place the assigned transaction ccde on the address lines of DDA Bus 20 at the first available time slot within a frame.
In the meantime, the Gæc~s associated with the tape drive and the array process~r are looking for the transaction code to appear on the ad~ress lines of DDA Bus 20. During the first time slot, the transmitter recognizes his address; at the next time slot, if ready, he places his data in parallel on the DD~
Bus data line 18 and transmits a transmit-acknowledge signal, T~fK over one of the set of oommand lines 20. At the last time ' ~;

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~53iZ2 1 slot, the receiver, which has already reco~nized the trans&ction code, i~ ready, thereupon accepts the da~ ~rom the transmitter and transmits a receive acknowledge signal, ~A~K. ~ach time that transmitted data are receive~, the byte counter in the transmi~ter is decremented. When the byte count is e~hausted, the transmitter sends a si~nal ~
back to the SPSS over a status line in CCB 52 and the transaction is terminated.
T~le abov~ sequellce o~ events will be discussed in more 'detail below in the separate detailed descri~tions o~
each of the key elements of the system, name'ly the SPSS, the DDA Bus Controller, the GPDAs, the Co~and/~ontroi Bus and the Direct Device Access `~us.
Signa'l Processin~ Subsystem ~upervisor (SP~S) 14 may be a mini-computer such as the PDP 1'1/04 made by Di~ital Equipment Corporation, supra. PDP is a trademar~ o~ sald corporation. SPSS 14 communicates with t~le host computer over control/status line S0. ~asically, SPS i2 is controlled by commands ~rom SP5S which cause the ~D~ Bus Controller 16 to create or de'lete data patns on the DI)A '~us data lines 18. SPSS 14 also ~ends commands to tne GP~As over CCB 52 which allows the ~P~As to use ~nose ~atns.
Althou~h the SPS Supervisor '14 is pre~erably a st~nd-alone unit with respect to the host computer, the Supervisor may also be resident in the tlOSt computer as soitware, ~irmware, hardware or a comoination thereoI. ~'it that capability, in the event that SPS Supervisor 14 'malfunctions, subsystem 'i~ may still oper~ albeit less e~ficiently. Conversely, if the host computer malfunctions~
commands that wou'ld normally be downlo~de~ irom ~he ~IOst computer, may be en~ered directly into SPS Supervisor 14.
C~ 5~ is a 56-line ous to wllich the ~ ~u~
controller 16 and all o~ the ~PDAs are connected. ~equests to o~en and close data pattls are transmitted over this bu~.
The functions o~ these control lines are ~u'lly described ln U.S. ~atent No. 3,710,~4 an~ 3,815,~

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1 Interaction between the SPS Supervisor and the host computer as well as the management and allocation of resources is dependent on relatively slow, conventional programming logic. Once a set of devices (trans~itter-receiver oombina-tion) has been assigned by the program logic to perfonm a specified task, high-speed, mass data transfers can take place across the DDA Bus without further intervention by the SPS Supervisor until the task is oomplete. All devices in the Signal Processing Suhsystem have equal priority with respect to the CCB.
The host computer causes the SPS bo d~ useful wcrk, - in an orderly manner without further intervention, by means of Transaction Command Pa~kets. A Transaction 0ommand Packet (TCP), transmitted frcm host ccmputer 10 to SPSS 14 seriA1ly over command~status line 50, consists of at least four Supervisor Command Packets (SCP). There are fi~e types of SCP. A TCP consists of a type 1, type 3, type 4 and either a type 2 or type 5 SCP.
The functions of the five SCP types are as folJows:
Type 1 - Device Queue specification. This is the first SCP in a transaction. It specifies the deviee queues necessary for the entire tra~saction.
Type 2 - A type 2 SCP oontains the information necessary to perform the data transfers requested in a transaction. The type 2 SCP specifies the source (tran~tteri and destination (receiver) of the data and the parameters required by the devices. It is well to point out here that : more than one receiver may receive data from a given `~ transmitter at the same time. The byte count of the data to~e transferred is included as well as the byte count or address of the next SCP to be activated. An error termination routine is specified.

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1 Type 3 - A type 3 SCP is used to terminate a process and is activated by a type 4 SCP. A type 3 SCP gathers information about the transaction such as success, failure, error parameters etc., and transmits these data to the host computer.
Type 4 - A type 4 SCP provides instructions to the SPSS. m ere may be several kinds of Type 4 SCPs, depending upon the ~peration code. First is a use-count termination, ; i.e. execute a type 2 or a type 5 SCP a given nu~ker of times. For example, it might be required to transmit 5000 bytes of data from a source to a first destination and thereafter to transfer another 5000 bytes of data from that source to a second destination until the byte count is - exhausted.
Second is a status termination. That is, do a type 2 or type 5 SCP until a certain status is attained. For example to read records in a tape filel the tape ~culd be read until the End of File mark ~status) is detected.
Third is an error tenmination such as a termination due to excessive parity errors.
Fourth is a test termination. This code is used when a SCP type 2 or type 5 must activate another SCP type 2 or 5.
Type S - A type 5 SCP is used to perfonm single-device utility actions such as rewind a tape drive or initiate an array processor. Transactions that use multi-unit devices m~st begin with a type 4 SCP to verify not only that all the controllers needed æ e free, but also that the needed units on these controllers æ e not busy. Para~eters include usage count device specification, device parameters and status ~; (i.e. DONE, BUSY, ERR3R).
It is evident, of course, that when several ~` transactions are to be chained (to be discussed infra), then each SCP must bear a packet identification number.

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1 Of the five SCPs, only a type 2 or type 5 SCP
generate a Device Ccmmand Packet, now to be discussed.
m e Signal Prccessing System Supervisor includes a &CP to DCP tr~lsformer. The transformer converts SCPs that contain process specific parameters into DCPs that contain device specific mformation. The SCP to DCP
transformer also decodes the error fields of the SCP and sets the appropriate flags for the required error routines.
- A separate set of SPCs is necessary for each func ion that is require~ of a pair of devices in ordRr to ccmplete a transaction. Thus, to read data from a n~gnetic t~pe file, the tape = t be instructed to (1) adJance to beginnin~ of the file; ~2) read the header bytes and transfer to a tem~orary storage; (31 read the data until the end of file mark; (4) rewind tape and s'~op. For this operation four separate sets of SCPs are required. The two read sperations (2) and (31 require use of a type 2 SCP; oFerations (1) and (4) require a type 5 SCP.
As will b~ discussed later Wit~l respect to the GPDA
control bcard, the above listed sequ~nce of events may take place in pro~er se~ ence without inkervention by the host computer. ~le process descri~ed is term2d command/data chaining.
The ctandard ccmmand set ~or the GP~As is as follows:

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~ ~53~22 1 COMMAND OODE DE5C$IPTION
READ 0 Transfer Data out of the Device RITE 1 Trans~er Data into the Device SPFW 2 Space Forward 5 SPRV 3 Space Reverse ERAS 4 Erase WEOF 5 Write "En~ of File" Mark RWCL 6 Rewind on Line R~OF 7 Rewind off Line 10 ABRT 8 Immediate Stop of All Activity ST~P 9 Stop at the end of the current ~CP
LDAD 10 Load the GPDA Firmhare DI~G 11 Place the GPDA into a Diagnostic Mode 15 STRD 12 Read Status STWT 14 Write Status O~P~L 15 Take the Device off Line STRT 16 Start a Device FUNC 17 Device Dependent Fhnction 20 RSET 18 Reset the Device BOOT 19 Perform a Bootstrap Function NOOP 20 No Operation It should be noted that these commands appear only in the SCPs. The actual device dependent commands necessary to oEerate a given peripheral are generated via the SCP to DCP transformer.
CQmmands are delivered to the GPSAs via DCPs over CCB 52. All SPS I/O will be initiated by supplying the proper command value r t~ the appropriate GPDA register.
DCPs are the structures that allow the general purpose SCPs to control specific devices. All the information necessary for the co~plete control of any SPS peripheral is oon~ained within its associated DCP.
There are t~o ways of transferring the DCP from the SPSS
to a GæDA. For devices requiring a minimal-length DCP, the device adapter will have all of its registers directly mapped inbo the SPSS I/O address space. For devices which require a longer DCP, only the first four registers will be mapped into SPSS I/O address space. These registers will include a GPDA control/status register, a DCP bl ~k length register, a DCP block starting address register, and a DCP identification register. A direct memDry ,:

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1~53~LZ2 1 access operation will be performed using the information in these regis~ers to transfer the DCP.
Each GPDA will have allocated 64 bytes of address space in which to locate its registers. The use of this address space except for one word per GæDAr namely a oontrol word for activating the GæDA control ~oard, will ke determined ky the GPDA firmware.
The DCP will contain information that is koth general, applicable to all devices, and device spe~ific. The general information will be contained in the first partion of the DCP.
Any in~ormation that applies to the control of the GPDA itself will be contained in the first word or words of the DCP. The next words of the CDP will contain information to link a long DCP to the GæDA control word.
The final portion of the DCP will ke the control bits that are transferred directly from the GæDA to the device oontroller which is, for all practical purposes, a part of the ; device itself. It will appear in the DCP in the same order as i the addressing of the registers within the device controller.
This information will include data such as: device commands, k,yte count for the data transfer, start address for the data transfer, track and sector addressing for discs, tape rewind, read, write, etc.
m e Direct Device Access Bus (DDA Bus) 18, 20 is the main kus of the signal processing subsystem over which all peripheral data are transferred. Data transfers across the DDA
Bus are made only between those General Purpose Device Adap~er data koards that are enabled by the DDA Bus-Controller 16. All of the Gæn~s in the SPS have equal priority with respect to ` the DDA Bus. The DDA Bus consists of 48 lines assign~d as follows ; 30 wherein there is a set, 18, of 32 data lines and a set, 20, of 16 ccmmand lines:

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1 ~AME ~0 OF MNEMCNIC FUNCTICN
Ll:~:S
~ata 32 H~T DDA Bus Data Transfer ~d~ress 4 HADD To initiate a DDA Bus data transfer ~d~ress Parity 1 HADDP DDA Bus Address Parity Bit ~ata Clock High 1 DCLKH 100ns clock to synchronize data transfers ~ata Clock Low 1 DCLKL Data Clock Return Data Parity 4 HR~IP Data Byte Parity Transmit A~knowledge 1 T~CK Data Gool Verify to Receiver Receive Acknowledge 1 R~CK Data Received verify to Transmitter End of Data 1 HEN~T End of Data

2 SFares All lines go to all GPDAs in the subsystem 12. The address lines, address parity and data clock lines originate from 2a the DDA Bus Controller 16, and are unidirectional. All other lines are bidirectional, and do not go to the DDA Bus Controller.
Communication between any two GæQ~s such as 32 and 34 is synchronous with the DDA Bus data clock, and is initiated by the DDA Bus Controller 16 by placing a four-bit transactian 2~ code on the DDA Bus address lines. Both GæDAs~ one a transmitter ana one a receiver, recognize the same transaction code. The transmitter places data on the data lines and indicates data are good with qASK. The receiver receives the data and responds with ~:EC.

3~ A complete DDA Bus data transfer requires three, 100ns time slots. The DDA Bus Controller, however, only requires one time slot to place the transaction code on the address lines of the kus. During the second time slot, while the transmitter is placing data on the bus, the DDA Bus Controller may place another transaction code on the address lines of the bus to initiate a data transfer between another pair of GPDAs. ~y overlapping time slots in this manner, a 40 megabyte aggregate transfer rate over the DDA Bus is achieved, i.e. one 4-byte word transfer is possible every 100ns.

~1~;3122 1 A detailed description of the timing for DDA Bus data transfers will be discussed later.

The Direct Device A~ ess Bus controller 16 is the link between the Dl~ct Device Aa:ess 8us 18, 20 and SPS Supervisor 14. Control information is ~assed bO the DDA Bus Controller via the CCB 52. m e control~er interprets this infonmation and sets up a device-to-device data path on the DDA Bus. me C~ntroller can also control J~lltiple device-to-device transfers on a dynamic time-multiplexe~l basis. Device æ cess to the DDA
8us is implemented with dy ~ nic time slot allocation. me tenm "Dynamic Time Slot ~llocation" is defined to mean that te~hnique where~- data-transf~r time slots are created only when and where needed. The number of ~ata transfer slots per frame is under continual adjustment so that when a transaction is complete, the slot or slots allocated to that transaction are removed. As a new transaction is initiated, new slots are created. A specific device is not necessarily assigned to a specific ti~e slot or transaction code on a permanent basis. This technigue differs from conventional Time Division Multiplex ~TCM) svstems where the frame width is fi-~ed as are the number of time slots per frame and the allocation of a specific device to a specific time slot.
The operation of the Direct Device Access Bus is oontrolled by transaction codes supplie~ at a cv~le time of lOOns in a polling type sequence. m e source and destination devices respond, starting at the time slot allocated.
Communication with the CCB is preferably controlled by a microprocessor such as the 8x300, made by Signetics, Inc. of Sunnyvale, C~. It does the handshaking with the bus, then nterprets the ccmmand and E~Sses the needed information to the hardware.
ere are sixteen E~ssIble time slots with a transaction code and a slot flag associated with each one. The transaction codes are stored in t~o 16-by-4 RAMS. The slot flags æe : :~
,~ ~ : , , : ~ ' ~ii31Z2 , 9_ :L stored in two 8-bit addressable latches.
q~ne 8x300 loads transaction codes into the R~M and raises or lowers slot flags under comnands from the SPS
Supervisor 14. The hardware logic looks at the raised slot 5 fl~gs and puts the associated device address on the bus in a sequential manner.
Referring now to Figure ,2, there is illustrated :in detai L the c~onents that make up the Direct Device Access Bus Controller 16, Figure 1.
Address deccder 31 has inputs C2 and ~D.
SignaLs over line C2 determine whether ~ata are to be read fram or written into address 2ecoder 31. Line ADD
identifies the DDA Bus Controller 16 as being ~le recei~er of the corrl[and presently on the c~nand/data lines of the C~B. It 15 aLso defines the destination for the ccmnand/~ata words ~s being the status/control register 33 or the writable c,~ontrol-storage 35.
It should be understood at this poirlt, that the so-called ~ line does not necessarily carry data in the sense of 20 n~nerical data signals that are to be processe~ such as are transferred betwe~ devices over the DDA Bus. In the c~ntext of Figure 2 the DAlY~ lines trar~nit cnand, control and statuq - words such as system intialization parameters and Device C~
Packets .
Writable control-storage 35 ar~l mlcroprocessor ~.7 are : inert until they are activated ~y certain control bits in the status/control register 33. According'y, the first conn~nd word from SPS SuE~rvisor 14 over the D~TA Bus of CCB 52 must be directed bo status/control register 33. Status/ocntrol register 30 33 then activates writable control-storage 35 and microE~ocessor 37. When writable control-storage 35 has keen loaded, micro-processor 37 can then exercise the functions necessary to control and transfer da~a ketween devices over the DDA bus.

~3~22 1 Certain registers are connected to the ~icroprocess~r 37 over the inputJcutput Bus. Read/write enable deooder 51 sends read/write instructions to specific registers under the control of instructions from microprccessor 37.
Initially, ccmmand/data and addresses æ e presented to the D~ Bus Controller by the SPS Supervisor on a request/
acknowledge basis. Accordingly lines MSYN and SLSYN æe provided.
MSYN active to address decoder 31, says that data are present on the CCB 52. Upon receiving the data, address decoder 31 responds with SLSYN. After microprccessor 37 and writable control storage 35 have been activated, handshaking between Do~ Bus Controller 16 and CCB address space, for addresses defined by the microprogram in the writable control-storage 35, is oontrolled by control register 49.
The SPS SuFervisor 14 monitors the availability of resources needed for the respective transactions that are to take place. It assigns a specific transaction code and a specific time slot to each set of peripheral devices that will participate in a transaction. For that purpose, the Sup~rvisor decodes the unit address of the receiver GP~A and assigrs that address as a transaction code for both the transmitter GæDA and the receiver GæD~ The SPS Supervisor 14 tk~n requests from DD~ Bus Controller 16 the num~er of the next av~;lable time slot frcm time slot flag register 41. The Supervisor then sets t~e flag, corresponding to the designated time slot, in time slot flag register 41. At the same time, the transaction code i5 entered into transaction-code R~M 39, indexed according to the assigned time slot number. ~5 each time slot appears, if its flag is raised, the corresponding transaction code is placed on the address lines of the DDA Bus.
Address register 45, data register 47 and control register 49 provide intercommunication bet~een the input/cutput bus and Ccmmand Control Bus 52~ These registers are provided so that the ccmmands and status that were downloaded into status/control register 33, writable control-s~orage 35 and .
, . . .~ . ~

.
.., ~

i31Z2 1 microprocessor 37, can be read back for diagnostic verification.
They also provide areas for receiving and storing time slot and transaction-code allocations.
A General Purpose Device Adapter such as 32 serves as a common point for control signals to and ~rQm the SPS Supervisor 16, the data stream on the DDA Bus between devices and the control and data signals ~lowing to and from a device at a data port. Peripherals connect to thç SPS at a data port. m e GæDA
data port, under fLrmware control and sequential switching, can be made to be 8, 16 or 32 bits wide as will be discussed later.
- m e GæDA personality or characteristics are determined by thef~rmware down-loaded from the SPSS into a writable control-storage during the system initialization. m e GæDA supports command chaining to be described later herein and will respond to a standard oommand structure. A GæDA is required for every peripheral device connected to the DDA Bus.
The GæDA consists of two boards, a control board such as 42 and a data board such as 32 with a ccmmand-status interface such as 56 between the two koar~s. There are three interfaces to the GPDA as a whole, namely, the ~rR, the DDA Bus and the data p~rt.
m e control koard interfaces to the CCB, the data port ar~d the data board. The data board interfaces to the DDA Bus, t~e data port and the control board.
A data port is the communication path ketween a GPDA and ;~ 25 a peripheral de-~ice. It is not a bus, that is, only one device m~ly be connected to one GPDA at a time. However, since the pçripheral device may be one o~ many types, the data port includes 63 lines, to be discussed later, that are shared between ; t~le GPDA ocntrol bo æ d and the data bo æ d.
m e GPDA command-status interface 56 is the control link between the GPDA oontrol board and the GPDA data k~ard. It consists of nineteen unidirectional l mes, assigned as follows:

. ; .

~15312Z

LINES --FIFO Control Command 8 Control-Data Iines FIFO Control Status 8 Cont~ 1 Status Lines 5 Co~mand Enable 1 Enable to Load Command Register on Data Board Data Enable 1 Enable to Load and Raad Data Transfer Parameters Register on Data ~oard 10 Master Clock 1 Clock from ~ontrol Board The control-data lines are used to transfer control nformation f m m the GPDA control koard to the data bo æd. The ~ control status lines are used ky the Gæ~A control board to read status inormation from the data board. The other tbree l m es are used to control the transfer of this inlormation.
Referring to Fig~re 3, there is a detailed diagram of the GPDA control koard. The heart of the GæDA is a bipolar microprocessor 60 which is a 8x300 mLcroprocessor. This device and its associated control logic, interfaced to CCB 5~, co~pletel~
control the sequence of events within the tw~ koards such as 32, 42 comprising a complete GPnA. The main purpose of the GP~
control board is to act as an intelligent control interface between the CCB and a device to be controlled. It also h2ndles interrup~s from the device interfaces to minimize interruptions of the SPS
SupervisOr.
In many instances the control board will have, attached to its control/data port 86, an interface ~hat ~culd normally ccnnect directly to the CCB. It may in-these instances be used to store strings of commands to be executed by the peripheral device in a conventional fashion without employing the spec:ial features of the DDA Bus. Such action would primarily ~e diag~ostic in nature.
In so~e situations the GPD~ control board wQll be the control interface between SPS Supervisor 14 and the device controller itself. Such is the case ~th a tape system. ~hen connected to the tape system, the GPDA control board will issue co~mands to the tape formatter/controller and ~onitor status 1~53122 1 reported kack. It can then issue interrupts to the SPS
Supervisor under chosen conditions. It should be understcad that each device includes a dedicated controller/formatter that is an integral part of the device and it should not be confused with the GPnA control koard.
Besides sending the commands and ~ontrol parameters to the device (or device interface?, the GænA control b~ard also sends the data transfer commands and parameters to the data b~ard. m e data board interprets the commands, performs the requested operation, and rep~rts back status to the GPD~ control koard.
m e microprogram (firmware) for the GæDA is loaded inbo a writable control-storage ~WCS) 62 sometime ater power is applied to the system. The GænA control board 42 can do nothing until the finmware is loaded.
m e WCS is a random access memory aevice to store the-sequence of instructions making up the firmware. Changes in the firmware are easily m~de by reloading or mcdifying the data in the writable control-storage.
In addition to storing the 16-bit instructions for the 8x300, the writable oontrol-storage stores a seven-bit field that is used for enabling registers associated with the input/output - bus of the 8~300.
Each instruction includes a parity bit. Hardware in he oontrol board 42 checks parity for each instruction as it is executed to assure that odd parity is maintained in the instructlon worZ. If a parity error is detected, a bit in the status/control register 64 will be set, and will remain set until a system reset is applied or until the 8x300 itself is reset.
The writable control-storage 62 oonsists of 1024, twenty-four bit words of memory. To simplify the loading of firmware, the writable control-storage is treated as though the instructions are 32 bits wide, with the upper 8 bits always zero.

~31Z2 1 ~rit~ble control-storage 62 is loaded ~y the SPS Supervisor by first: enabling it into CCB I/0 space. This is done by setting the proper bit in status/control register 64. When enabled into CCB address space each instruction takes two consecutive words.
In order to conserve address space, only a portion (one fourth) of t~le writ~ble control-storage is enabled at a time. ~he block of w~itable control-storage to be enabled is selected by two bits in t~e status/control register. By enabling it in blocks, the - writ~ble control storage takes up only 512 ~ords of I/0 space.
The writable control storage 62 of only one GPDA can ke enabled at a time, kecause all of the writable control-storage mcdules in tne system share the same address space.
Each GPDA (excluding writable control-storage 62) is addressed with 32 words of consecutive CCB address space. With no firmware loaded in a GPDA control board, only the 16-bit status control register 64, is accessable within that GPQ~'s address space.
Sixteen different non overlapping regions of SPS
Supervisor address space are availAhle to the GP~A. Selection of the region to be used is selected by ~anually operated sixteen-position ID switch 66. This switch selects a unique address for eac~l GæDA in the system. The address decoding circuitry 70 on the control board furnishes the read and write strobes for the status control register and the writable control-storage. It also fur~lishes a logic signal, accessable by the firm~are, that indicates thal: an address is present on the CCB that falls within the unique ad~^ess region allocated to this particulæ GPDA.
The status/control register 64 receives all commands govl~rning the operation of the GPDA control koard hardware. It repl~rts back status pertaining to the hardware. Some of the bits in the status/control register are read or written by the firl~are.
m e low order eight bits in the register are read/write ccmmand bits. The upper eight bits are the status bits. The functions of the 16 bits are defined as follows:

,. . .

.
~ ., ~1~31Z2 1 b0: RUNH, active high. ~hen high, 8x300 is allowed to run. When low the 8x300 is halted.
bl: E~BLE INrERRUPTS, active high. When high, hard and soft interrupts to thR SPS Supervisor processor are normally enabled.
b2: ENABLE BUSES, active high. Must be high in order to enable any component other than the status/control register (SCR), ~rit~ writahle control-stcrage data onto the CCB, or control signals onto the Data Port.
b3: SEIECT MICR~, active lcw. When low the Writable Control Storage pWCS) is addressed by the 8x300. When high the WCS is maFped into the WCS portion of CCB I/O address cpace.
Also the 8x300 is reset whenever SELECT MICR~ is high.
b4: M~P SELECT bit 0. In conjunction with b5, a block 5 of the WCS is specified for maFping inbo CCB address space.
b5: M~P SELECT bit 1.
b6: GæFDIN~ General Purpose Firmware defined input.
m is bit can be sampled by the finmware at any time. It is a read/write bit in the SCR r~gister, but is read only bo the 0 firmware.
b7: GPFDIN. Same as b6.
b8: ID0: In Conjunction with b9, bl0 and bll, the GænA
unique address (0-15 set in a switch 66 in the GPD~) can be - read.
b9: IDl.
bl0: ID2.
bll: lD3.
bl2: Unused bl3: GPFDOUTl. Gen~ral purpose firmware defined outFut number one. miS bit is set and cleared by the firmware. It is a read-only bit in the status/control register.
bl4: GæFDouT2~ General purpose firmware defined output number two. This bit is set and cleared ky the firmhare. It is a read-only bit in the status/control register.

~1~i312Z

1 bls: WCS PARITY ERRDR. Indicates that a p æ ity error was detected in the writable control-storage. Reset by a CCB
RESET or by setting b3 in the status/control register high.
Control signals associated ~ith the inputJoutput LUS
and read/write enable deccder 76 define a source and destination for data that is to be manipulated. Data ~i~nipulation instru~ions executed by microprocessor 60 include source, dest;nation and operation code fields. Ftur clock cycle~ are required to periorm an instruction. m e first clock cycle defines a read opexation from the source; the second clock cycle defines the operation to be pexformed; the third clock cycle addresses the de~tination;
the fourth clock cycle defines a write oFeration to the destination device.
As mentioned e æliex, the GæDA control bo~rd 42 ~hrou~3h its firmware has control over up to sixty three signals ~hat can ke connected to the peripheral to be controlled. Interconnec1:ion between the GPDA control board and a pexipheral device is acccmplished across control board data port 86, Figuxes l and 3.
Methods of control over these lines vary from one type of dev:ice to another and are conventional. Accordingly their use can only be descriked in broad terms. Many of these lines are pri~3ri_y bypass links for diagnostic purposes.
1. Sixteen o~ these lines can be driven dir~ctly by the CCB data lines, or data can be loaded into a latch and enabled out onto these lines. Data can also ~e read from these lines for use in the pr~x3ram of the control board or the data can ~e ena`bled directly through to the CCB data lines.
2. There are eight other lines that can be used in t1ne same way except that instead of being driven directly by tne CCB
; data lines, they can ke driven directly by the least signific3nt six CCB address lines and C0 and Cl, read/write control, on the CCB. Data can also be enabled directly onto these CCB lines.

.
, . : : :
, .. ' ~: ~
, ~531Z2 1 3. Twelve of the lines can be driven directly only by the control board, read by the control board, or enabled onto the upper twelve ~A~6 - A17~ address lines of the CCB.

4. Twenty-one of the lines can only be read by the control board. m ese are not bidirectional signals.

5. Two lines can only be written to by the control koard. These are not bidirectional signals.

6. Three lines can ke read or written to by the control board. These are bidirectional signals.

7. One line is the reset line. It can bo set and reset by the control board.
Address decode logic 70, receives an address from ID
switch 66 and, when a block of command data appears on CCB 52, deoode logic 70 deccdes the address. If a matching address is seen, the data block is routed to either status/control register 64 or to writa~le control-storage 62 in accordance with command Cl. Ordinarily, of course, status/control register 64 m~st first be loaded in order to activate the GPDA control ~oard. m ese functions were earlier described in greater detail in conjunction with the de~cription of the D~A Bus Controller 16.
Command blocks are entered into writab~le control-storage 62. m e co~mand blocks contain a set of instructions to microprocessor 60 regarding control over the device to which the GæDA is connected. Unless the attached device is removed in favor of another, different device, the instructions are not changed, once the system has been initialized. Upon reguest over instruction address line 72, microprocessor 60 receives an instruction over ins~ruction line 74. Leaving writable control-storage 62, the instruction w~rds are 24 bits wide. Of th2se, 16 bits go to microprocessor 60 and 7 of the remaining 8 bits are decoded by read/write enable byte select decoder 76 to select the desired read/write enable byte. m e 8th bit is a parity bit. A 4-bit line 78 from microFrocessor 60 provides a control line for CLOCK ard S~TFCT.

~i312Z

1 m e GæDA control board 42 is interfaced with a c~ata koard 32 over interface 56. The interface includes a ccmmand/
data recJister 80 and a status register 82. Eight of the previouLsly~discussed interface lines lead to the status register from th~ GæDA data kDard 32, ten leave the oommand/data registeI and go to the data board and a master clock line sends clock pulses from the output Bus ~8 to the data board.
A working storage 84 is interfaced to the output Bus for use as a utility memory. It is here that ~CPs are stored 10 for use ~y a peripheral device under control of microprocessor 60. ;`
Data register 81, address register 83 and control signal register 85 are provided. These registers ccmmunicate bicirectionally between the input/output bus and the datar address and control lines. Under control of micrcprocessor 60 and reacl/write enable deooder 76, these registers may serve several purposes. Data signal register 81 provides means for transmitting device parameters to the device attached to the GænA. Typical commands ~ght be READ, RITE, WEOF, ERAS, STOP, RWOL. ~refer to the GæDA stanclard ccmmand table). m ese co~nE~; are transmitted via the control board data port 86 over one or more of the CCB command lines.
Address register 83 and data regis~er 81 provide means for reading b~ack commands loaded into ~Drking storage 84, and microprocessor 60 for error det~ction purposes. Data from the attachecl peripheral device can be read back for checking.
Additionally the three registers data, address and control, can be used for diagnostic system tests and de~ugging.
It should be pointed out here, as before, that the "data"
lines d~ not necessarily contain data that is to be processed such as is transferred between devices across the DCA Bus.
Command and status words may be manipulated like true data by the host ax~puter and the SPS Supervisor operating system, but except ~or diagnostic testing, actual data are not transmitted over that line.

' ~; ~

~i;312Z

1 The purpose of the GPDA data b~æ d 32, Fig. 4, is to transfer data at a high transfer rate between peripheral devices across the data p~rt and the Direct Device Access Bus. As pointed out kefore, the DDA Bus is a 32 bit wide data path capable of transferring data at an aggLegate rate of 40 mega~ytes per second. The peripheral device may have a data path 8 bits, 16 bits or 32 bits ~ide. m e control path of the device may have separate lines to the GæDA coni~ol board 42, or it may be time-multiplexed over the data lines. Physically, the data port is simply a connector to the OE~DA data board. Re-formatting of data words to or frGm 32-bit parallel format is done by data-port I/O registers 118, 120 in a manner later to be described.
In ger.eral, data transmission across th~ DDA Bus oc s between a GæDA transmitter, ard one or more GPDA receivers. m e SPS Supervisor sends to all GæDAs that are to participate in a particular DDA Bus data transmission, the same DDA Bus transaction code and assigns a time slot for this transaction code on the DDA Bus. The time slot assignment is programmed into the DDA
Bus Controller as previously described. When the DDA Bus Controller pU~5 a code on the DDA Bus address lines, the previously-downloaded GæDAs will recDgnize the transaction code and transfer data across the DD~ Bus. Additional time slots may be assigned for other transaction oodes, and for each time slot, a different code is downloaded into a GæDA trar~3mitter-receiver pair.
There æ e two im~ortan~ features attrikutahle to the GæDAs~ One is a multiple parallel data transfer process. Here, one transmitter can transfer data t~ several different devices in parallel.
~nother feature of the GæDA is the capability for reading a long record from a peripheral device, subaivide the record into parts, and send each part to a diff~rent destination as complete records. This is called a split-record transfer or multiple 1~L53~22 1 serl~l dest m ation transfer. To do a split-reoord transfer, for example to send parts of one record to two different destinations, one GæDA receiver is downloaded with DRA Bus transaction ccde A and a first byte count, another GPDA receiver is downloaded with DDA Bus transaction oode B and another byte count. The GP~ transmitter is downloaded with both transactio~
codes A and B and both byte counts. me GPDA transmitter first recognizes address A, and for each word transferred across the DDA Bus to the receiver with address A, the ~yte counter~ which is loaded with the first byte count is decremented by four (because there are fo~r 8-bit bytes per 32-~it word). ~hen the transmitt~r byte count reaches zero, the byte ccunt~r is loaded with the next kyte count, and the transmitter starts recognizin~
address B. Data is then transferred to the receiver with address B. The process just described in the transmitter GæDA is deined as co~mand chaining.
In the context of this disclosure, command chaining is the ability of the GPDA contr~l board to access and activate successive hardware command strucbures without supervisor interVentiOn.
Data chaining is the ability of the GæD~ control board bo reinitialize the byte count and the address register dynamically within a transfer without interrupting the physical record and without supervisor intervention.
The lines on the data port æ e shared by the GP~ control ~o æ d and the data board. A description of how the data p~rt lines are used by the oontrol board has been discussel earlier.
The data lines are connected to the data board although ce~tain oontrol lines also may be oonnected thereto depending on the particular device serviced. Some or all of the remaining control lines are oonnected to the GPDA control board.
The data koard uses the data port lines to transfer data information only to and from the peripheral device, under the control of the GPDA control koard. The data board connects to 8, 16 or 32 data lines as previously mentioned, depending on the ~1~i31Z2 1 data path width of the peripheral device to or f-om which data are to ke transferred. Communication across the GPDA data koard data port is asynchronous, i.e. every transfer takes place on a request-acknowledge basis. The data ko æ d receives data reguests, and responds with data acknowledge over ackncwledge line 123.
The GPDA data board consists of control/status registers, DDA Bus I/O registers, dataport I/O registers, memory and control to be described in connection with Figure 4.
The receivers 90, 92 receive signals from the eight control lines, the data enable, command enable, and master clock.
These lines fonm part of control-board data-bo æ d interface 56 and match with the corresponding lines of Fig~re 3.
Ccmmand register 94, is an 8-bit register used primarily to load and read the data trans~er parameters register 95, and to start and end a data transmission. It is also used to perform certain control functions which may be necessary while a data transfer is in progress.
Ccmmand bits in command register 94 have the following significance:
20 Bit Mnemonic Meaninq 0,1 CW0, CMl Command Word 0 ~ Reset 1 0 Load parameters ~ 1 Read para~eters 1 1 Data Transfer enable 2 LBK Last 64Kb block 3 SRR Reset status register 4 INP Load new parameters MR~ Multiple record transfer 30 6 CLN Set cleanup 7 LWD Set last word The data transfer parameters register 95 includes five registers, 96-104, an output driver 106 and an input multiplexer 108.

~lS3~2;2 1 Output driver 106 puts the par~umeters register on the status lines during a parameters-regis1~r read for error-checking purposes and to determine the numker of bytes read at the end of a data transfer operation. The data from ea~h register may be sequentially circulated through the status lines by mLltiplexer 108. Seven clock cycles are reg~L~red ~o ccmplete the circulati~n and to restore register 95 to its orgillal condition.
The control register 104 is used to set up the data b~ard prior to a data tr~nsmission. Such things as data port width, parity configuration an~ transmitter-receiver identification are specified by this register.
Control bits in ccntrol regist~r 104 have the following meanings:
Bit No. Mnemonic Meaning 15 ~, 1UW0, ~Wl Data port width 0 ~ 8 bits 0 1 Not used 1 0 16 bits 1 1 32 bits 20 2, 3 UP0 Data port parity control 1 1 32 bit parity 1 p Not used 0 1 16 bit parity 0 0 8 bit parity 25 4 TID Transmitter ID;
0 Transmitter 1 Receiver LSF Least Significant byte first 0 MSB first 1 LSB first Byte cc~mter 102 is loadea with the desired byte count of a record to be transferred, and with ~ach 32 bit ~ord input t~
the data boæ d, it is decremented k~ four. When the kyte counter ret~ches zero, dat~ transfer to the data board is finished.

~5312Z

1 m e address register 100 is loaded with the transaction code that the GPDA data ~oard is to rec~gnize on the Dl~ bus address lines for the current data transnuLssion.
Byte count register g8 contains the byte count for a su~sequent record of a split-rec~rd transfer. This byte count is transferred to byte counter 102 when that byte counter reaches zero in the presence of a split-reco~d transfer.
Reserve address register 96 contains the r~DA Bus transaction oode for the next record or a split-record transfer.
m is code is transferred to c~3dress register 100 ~hen the byte counter 102 reaches zero during the current trans-^er.
As soon as parameters from registers 38 and 96 have been ~oved to registers 102 and 100 respectively, new param~ters may be entered. By this means, a continuous series cf split-record transfers or command chaining operatio~s involvi~g device control functions, may be effected. The chaining ceases only when a STOP code issues.
Status register 110 relays data board status ~ck to the control board. m e information includes status kits definin~
p æ ity error status, whether the FIED is full or empty, when the byte counter reaches zero and when the last byte has heen transferred from the data board.
Status ~its in status register 110 have the follc~wing significance when true:

25 BitMne~onic Meanin~
0 TED Transmitter End Data 1 CHE Channel E~y 30 3 FMr FIF~ Empty 4 PE0 Parity error, output PEl Pariiy error, input 6 ZLC Zero long~ord count 7 AIN Status attention ~312Z

1 DDA Bus transaction~oode deccder 112 oomçares informaticn in the address register with information on the DDA Bus address lines. When there is a match, the DDA Bus co~trol is triggered to initiate a data transfer.
m ere æ e four, 32-bit wide I/O registers, 114-120 and a 4-bit parity regist OE (not shown). Included æe DDA Bus input register 114, DDA Bus output register 116 data-port input register 118 and data-p~rt output ~egister 120.
All data transfer paths within the GPDA data boæd æ a 32 bits wide plus parity. Inooming data across the data port may be

8, 16, or 32 bits wide. If the incoming data word is less than 32 bits wide, say only 8 bits, then the first 8-bit word of the incoming data are p æ allel loaded in the first of the 8-bit ; positions of data port input register 118. As the second 8-bit ward æ rives, data p~rt control 122 parallel loads the next 8-bit positions of the data port input register. The process is continued until all 32 bits have been loaded. m e reverse process occurs at data-port output regis~r 120, i.e. all 32 bits are parallel-load~ed into the register from the FIYO and are tra~smitted to the device 8 bits at a time.
~olding register 124 is a 36-bit register (32 bits plus - 4-bit parity) which accepts data from one of the input registers,and presents it to the FIFD. If the GæDA is a transmitter, the holding register gets data from the data port input register; if the Gæn~ is a receiver, the holding register gets data from the DC~ Bus input register. m e holding register is necessary for isolation between the data port and the FIFO because of the relative slowness of the FIFO. Data must be held static on the ~ FIFO inputs while data are keing transferred from the data port.
i 30 FIFO 126 is a 36-bit wide, 64-word deep first in, first out buffer memory. Its purpose is to synchronize irregularities in the data transfer rates of various peripheral devices. It accepts data frQm holding register 124, and passes it on to one of the ~utput registers. If the GæDA is a tr a tter, the FIFO

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~1~i31ZZ

1 transfers data to D~ Bus output register 116; if the GæDA is a receiver, the ~ U transfers data to the data port output register 120.
~he data-koard controllers include the data conLloller 128, the DDA Bus control 130 and the data-port control 122.
Data controller 128 accepts aolltrol information from command register 94, byte coun~Pr 102 and oontrol register 104.
Data Controller 128 controls the ~irection of data transfer through data ~oard 32, the loading of holding register 124 and the ~l~u 126 and reports status to the GæDA oontrol board 42. It also oontrols the loading and reading of the data transfer parameters register 95. It does not h3wever, control the loading of the oommand register 94; this is done directly by the control board 42, Figure 3.
DDA Bus control 130 accepts control information from t,he data controller 128 and from the DDA Bus transaction code decoder 112 in resp~nse to the transaction ccde appearing on DDA Bus control lines 20. It c~ntrols the loading of the DDA Bus I/O
registers 114, 116 and passes transmit or receive acknowledge ~ signals to the DDA Bus. It also passes status information kack to the data,controller 128.
Data port control 122 accepts control information from the data controller 128 ana from the data port. It controls the loading of the data port I/O registers 118, 120. It also passes : 25 status information back to the data controller 128.
Data is transfered etween devices during a 300ns transaction aperture. Master clock pulses at 10 MHz are provided ~y DDA Bus controller 16, Figure 1, providing lOOns time slots.
Referring no~w to Figures 1, 4 and 5, during the first time slot of a transaction aperture, DDA Bus oontroller 16 places a - transaction code on the address line of DDA cc~nQnd Bus 20.
, m e transmitter device and the receiver device~s) to which that transaction code was assigned receive and decode the transaction , ::
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-~3122 1 code in DDA address decoder 112. At the next time slot, the transmitter, if it is ready bo transmit, places a 32-bit data word fron DDA cutput register 116 on the data lines 18 of the DDA
Bus and drives transmit ackn~wledge (TACK) on the TACK oommand line in Bus 20. m e reoeiver GæDA(s) latch the data into the DDA
input register 114 and recognize TACX. At the last time slot, the receiver GæDA(s)~ if ready to receive data, releases receive ackncwledge (RACK). All of ~he receivers, if mDre than one release RACK. When ~11 of t~e receivers recognize RACK they transfer the data fm m DDA Bus input register 114 into hol~ing register 124. The GæDA tran~mitter recognizes R~CK and transfers the next data wDrd from FIFO 126 to DDA Bus cutput register 116.
m e timin~ relations are illustrated at the top four lines of Figure 5. m e first line 140 represents the lOOns time slots. The .ransaction code 6, assigned to a designated transmitter and receiver is transmitted at the first time slot as shown by pulse 142. During the next time slot 144, data and TACR
are transmitted. A~ the last time slot 146, I~CK is recognized, data are received and RACK i~ released. When R~CK goes true the data transfer is complete and the transmitter and all of the receivers, if mDre than one, ~ove data at the same time. If R~CR
does not go true, the receiv rs do not transfer data from their DD~ Bus input registers into their holding registers and the transmitter puts the same data on the Bus when the transaction ccde is again reoognized.
Multiple data transfers may take place concurrently as shown by the timing dia~rams corresponding to transaction codes

9, 7 and 2. Where data are to be transferred ~etween ~Dre than one pair of transmitter-receiver devices, DDA Bus controller 16 assigns a time slot and a transaction oode to each device pair.
It is to be understood of course, that the term "device pair"
may consist of a transmitter and one or more receivers, which, as a whole, constitute a set of devices. As soon as the transaction code for the first device pair such as 6 has ~een transmitted, ' ' ~;31Z2 1 another transaction c~de may be sent such as code 9, during the first time slot of transaction aperture 2 as shown in:the timing diagrams. m e process continues for transaction codes 7 and 2 during transaction apertures 3 and 4. A~cordingly, in the example of Figure 5, fcNLr transacti~ns are taking place concurrently. In this example~ the f a~e time is four time slots wide.
Transaction apertures, within a frame are numbered consecutively for convenience. T ~ t numbering should not be confused with the D~ Bus transacti~n codes for devices to be serviced during a particular time slot. For example, Ln Figure 5, it is seen that transaction apertures 1, 2, 3, 4 have assigned to them transaction codes 6, 9, 7, 2 respectively. A fra~e contains all of the time slots assigned by DDA Bus C~ntroller 16 at a particular point in time.
Time slot allocation is dynamic. m at is, they are prcgrammed into and are allocated by the DD~ Bus Controller as required. They may be added to or rem~vad rrom the frame as needed. m us the fram~ wllth is variable, 1~hereky making ~ore efficient use of the DDA Bus. For example, when all of the data in a transaction for transaction code 9 have keen transferred, time slot 2 is closed, m~king the frame three slots wnde.
The example of Figure 5 inv~lves da~a transfers between four separate device pairs. Data coul~ be transferred between a single pair of devices, of course, ky repeatedly placing the same transaction code on the address line for e~ery seoond time slot.
Because of the system protccol the min~mum frame width is two time slots.
A preferred mode of operation of th-e system is kest shown ky way of example. Assume that lO000 bytes of data are to be transferred frcm a 9-tra~k magnetic tape to an array processor.
The s~stem is first initialized ~y downloading the firmware to the inv~lved GP~s fron the host computer through the SPS Supervisor. A conventional utility program is employed for .

~1~;3~2Z

1 this purpose. The microprocessors 60 now have available instructions for operating the tape drive and array pr~cessor respectively.
A transaction command packet is r~ bo be enco~ed and presented to the host computer for trar~3mission to the SPS
Supervisor as follows:
PACKET VMSPID , ; Ccnç~lter process ID
37 ; 37 w~ds ln the packet SCP TYPE 1 1*245+1 ; ID ~rd for the first type 1 S~P
~ +APA ; Devices to use: MN~=tape, - APA--array processor MNA , Device to start SCP TYPE 2 1*256+2 ; m word ror first type 2 SCP
in the p~cket NOMDRE ; Only one type 2 SCP
NOCH~ ;
SCP4 ; Activate a Type 4 SCP
; Use count; SCP type 2 is used ; Only once NOERXOR ; . Igr,ore errors MN~*256+0 ; Use tape unit ~0 NOERROR ; Ignore errors

10,000 ; Transfer 1000~1 bytes 4 ; 4 bytes ~f pa~ameters; each Pæameter uses two bytes READ ; Read tape - 10000 ; Byte count APA*256+0 ; Use Array P ~essor 0 NOE~R ; IgrDre errors 0 ; There are no ~ytes to be ignore kefore starting to transfer 8 ; eight bytes o~ parameters RnM~ ; Receive data ln a direct memory acoess mode~DM~) 0 ; Start at loca'ion 0 in array :-processor 10,000 ; Byte count CTgL ; Control b ts for DM~

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1 SCP TYPE 4 1*256+4 ; ID wOra for first type 4 SCP
UCTER~ ; Terminate on use count for SCP2 ; th~c SCP type 2, SCP3 ; then activate a type 3 SCP
0 ; and use it only once so 1 ; terminate ~hen the use count of the ty~e 3 SCP is 1.
SCP TYPE 3 1*256+3 ; ID wori for the type 3 SCP
0 ; GO-NOGO code 8 ; Eight bytes of status MNA '; Tape status goes ~ ; Here APA ; APA status gces 0 ; Here The above transaction is sent to t~e SPS Supervisor 14 ~y host computer 10 using a conventional driver program.
If the SuEe$visor has roon in its transa~tion packet buffer for the 37 words of the TCP, the transaction pachet is accepted and awaits activation. During i~le time, an operating program in the SPS Supervisor scans the ~ransaction ku~fer for pendlng transactions that may be activated. In this case, ~he transaction may ke activated as soon as magnetic tape controlle~^, unit 0 and array processor controller, unit 0 æ e free.
Once the transaction has een cleared for activation, a set of device queues are set up for each of the t~o involv~d controllers. Two devices queues æe needed, one for the tape a~d one for the array pr wessor. The device queues include pQinters to the SCPs in the transaction packet kuffer that wi11 be invDlved in this transaction.
m e next step is to assign a time slot for the transaction and a DDA Bus transaction code. me SPS Supervisor 14 first requests frcm the DDA Bus controller 16 the numker o~
the next available time slot. Let us assume that time slot 7 is next available. m e transaction code may be arbitrarily assigned by the SPS Supervisor, kut from a practical standpoint, the unit address of the receiver as selected by ID switch 66, ~igure 3, is assigned as a tra~saction oode to b~th the magnetic tape unit and : .
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1 the array prccessor for a particular transaction. Note that, the device unit number is not necessarily the same as the GæDA unit address. m ere may ke, for example, several unit devices such as 0, 1, 2, 3, all connected through a device controller to a GæDA
whose unit address may be 6. In our example, let us assume that the GPDA connected to the receiving array processor has a unit address of 2. Accordingly SPS Supervisor assigns to the DDA
controller 16 a transaction code of 2 to ~e entered in address encoder 39, Figure 2. m is code will be activated at time slot 7 from R~M 39.
Once the DDA Bus controller is set up, the re~uired DCPs are generated by the SCP/DCP transformer resident in SPS
Supervisor 14. m e device queues are then sent to the working storage 84, Figure 3 over CCB 52. m e Device Command Packets are:

; DCP for tape 5000~ 0 ; Read command(5~0~) for unit 0 10,000 ; Byte count DCP for array 2 ; Do a DMA data-transfer pr~cessor write operation 0 ; to location 0 in the - array processor 250~ ; There æ e 2500 four-~yte words ; into the array processor 10001 ; m ese are cantrol bits.
Now, since each GPDA control board has all of the necess æ y parameters for conducting, the data transfer, the various registers in the GPDA data bo æds can be loaded.
GæDA control ~oard 42 places on the command~data lines a command to load the data transfer parameter register 95, and sends a ccmman~ strobe. m is loads the command into command ~ register 94.

:'' ~ ' ~i3122 1 TS~e GPDA control board then places seven bytes of data transfer parameters on the ccmmand/data lines, sending a data strobe with each byte. m e data transfer parameters include:
1. One byte containing control info ,.~tionf such as data port width ~8, 16, or 32 bits wlde); data port parity conf;guration and a transmitter identification bit ~hat tells the '~PDA data controller 128 that ~t is to transmit onto, or receive f-om the DDA Bus.
2. Iw~ bytes containing data byte count.
3. One byte containing the transaction code.
4. Two bytes containing the data kyte count for:a seco~d receiver, if any, and 5. One byte containing a transaction code for a second destination, if any.
The data transfer parameter register 95 may be read by ~he control koard 42 ky loading a read-parameters co~mand into the command register 94 and sending seven data strobes. The informatinn thus read may be compared with the information that was intended to be loaded. The data transfer parameters register 95 restores itself to the initial condition after the seventh data stro~e.
A command word is sent frcm the GæDA control koard 42 to the GPDA data board 32 to start a data transfer. For the GPoa rece~ver, that is the array processor, the following events take place:
1. Data controller 128 starts looking for its transaction code on the transaction ccde lines 21 fr~m D~ Bus 20.
2. Upon recognizing its transaction oode, data controller 128 l~ads a 32-bit word fro~ the DDA Bus data lines at the next clock cycle into its DDA Bus input register, and looks for TACK.
3. If TACK does not go true, the controller waits until it sees its oode again. If TACK does go true, it releases R~CK
and looXs for RACK to go true at the next clocX cycle. If RACX
does not go true (i.e. if another receiver does not release RACK

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1 to go true), it wait until it is addressed again by the assigned transaction code. If R~CK does go true, data are then transferred from the input register 114 to the holding register 124 where it is presented to the 64-word FIFO 126. Byte counter 102 is decremented by four, ~because the data word contains four bytes) and the controller starts looking for its transaction code on the DD~ Bus for the next word.
4. After FIFO 126 has accepted data from the holding register 124, it indicates to data controller 128 that ho~ding register 124 is empty.
5. Mear~hile, the first data word passes throu~h FIFO
126, and w'nen it appears on the F~F0 GUtpUts, data is loaded into the data port output register 120. FIEO 126 continues to fill up. When it is full, data c~-ntroller 128 signals the control board 42 that data are ready to be serit to the peripheral device.
Data controller 128 then starts lookirlg for master SYNC from the array processor, indicating that the clevice is ready to accept the first clata word.
6. I~x~n receiving master SYNC, the data control board sends the first 16 bit word and resFonds with slave SYNC. Upon receiving the second master SYNC, the data controller respcnds with slave SYNC, ar~ transfers th~ ne~ 32-bit data word from the FIFO outputs, if it is ready, to the data port output register.
7. Data is transfe red from t~ne DD~ Bus to the array processor in this manner until the byte counter 102 reaches zero, indicating the last w~rd is loaded in1 hoJding register 124. At this time c~ata controller 128 sto~s ri~oognizing its transaction ccde on the DDA Bus.
8. A last-word indicator bit is transferre~ to the FIFD
126 along with the last data word, a~l when this bit appears on the FIF~ outputs, it is used to set an end data flag when the last data word is loaded into the output register.
9. When the last ~ord of data in output register 120 is transferred to the peripheral, a channel empty-status bit is sent to the OE DA oontrol b~ard 42.

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~1~i3122 1 For the GæDA transmltter, that is the ma~netic tape, the following events take place:
1. Data controller 1~8 immediately star1s looking for its transaction code on the transaction code lines 21 of the DD~
Bus, but does not transfer any data since FIF0 1;'6 has not yet been written into, that is, the ~ransmitter is not ready.
2. The data controller starts looXing ft)r master SYNC
from the tape controller, indicating t~.e presence of data on the data port lines.
3. Upon recognizing master SYNC, d~ta a~ntroller 128 loads data into its data port input register 118, responds to the tape controller with slave SYNC, and ~crements k~te counter 102 ~y one, two, or four ~ytes, dependlng on the width of the data port which in this case is one ~yte.
4. When the data port input register has been loaded with four bytes of data, data are transferred from input register 118 to the holding register 124, i~ empty, where it is presented to the 64-w~rd FIFO inputs, and the da a controller 128, continues looking for master SYNC.
5. After FIFO 126 has accepted the data from the holding register, it indicates to data controller 128 that the holding register 124 is empty.
6. Meanwhlle, the first data word passes through the PIEO, and when it appears on the FIFO outputs, it is loc~ded into the Dn~ Bus output register 116, making the GPD~ transmitter ; ready to transmit data over the DD~ Bus 18.
7. Upon recognizing its transactionicodo on the transaction code lines, the controller places data from DR~ Bus output register 116 onto the DD~ Bus data lines 18, drives the TASK line true, and looks for R~Ll~ to go true at the next clock cycle.

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~53122 1 8. If RACK does not go true, controller 128 looks for the transaction code to again app~ar on the transaction code lines 21. IL RACK does go true, the controller 128 transfers the next word of data from t~le FIFO, if it is ready, to the DDA Bus output register, if it is empty, and continues looking for its transaction code on the transaction code lines. If FIFO 126 is not ready, t~R controller waits until it becomes ready, then transfers the next word from FIFO 126 to the DDA
Bus output register 116 and waits until it sees its transaction code again on the DDA Bus.
9. Data are transferred from the magnetic tape to the D~ Bus 18 in this manner until the byhe counter 102 reaches zero, indicating the last byte is loaded into the data port input register 118. Byte count zero status is sent to the GPDA control ~oard 42.
iO. When the ~yte count is zero, data are transferred from the data port input register 118 into the holding register 124, and the last word indicator bit is set, which is presented to the FIFO inputs along with th~ last word of data.

11. The last word indicator bit on the FIFD output causes the end-data flag to be set as the last word is loaded into the DDA Bus output register 116.

12. Channel-empty status is sent to the GæDA control b~ard 42 ~ the last word is transferred onto the Dn~ Bus.
Whe~ end of channel status is recei~ed from the data controller 128, the DDA Bus Conb oller 16 places a reset commsnd on the command~data lines, and sends a command strobe. m is resets the GPDA oontrol ~oard, and ends the data transmission.
When the entire transfer is complete, the GæDAs generate interrupts to the SPS Supervisor to inform it that the date transfer has keen ccmpleted. At that time, the type 4 SCP is decoded. Since a use count termination ~as selected and the !

~53~2Z

1 type 2 SCP was used once, the type 3 SCP is activated which sends a status rep~rt ~ack to the host ocmputer.
The preferred method d operation ma~ ke further ~ett~r understcod by reference to simplified flcw diagrams for programming the transmitter and receiver GP~ koards.
Figure 6 reviews the relationship between the tape (transmitter) GPDA 150 and the receiver (array Frocessor) Gæ~
152. Both units receive orders over CC~ 52 and ccmmLnicate directly with each other over the DDA Bus. In operation, th~
timing of events is such that the 64-wo d FIF0, such as 126, in transmitter GæDA 150 is always em~ty ~hile the oorresp~nding FIEO in the receiver GæDA 152 is always full. miS conditio~
furnishes a small amount of elasticity to the system. m e tcpe for example, transfers out data on a per byte basis. ~oweve~, the array processor receives data in 16~word blocks. Hence, the 64-word FIFO provides a means for accumulating a 16~ord block ~, without hindering the data transfers of the tape GP~.
~ Figure 7 is a flow diagram~of the sequence of events ; that take place in the transmitter GæDA lS0. In the IDT~ state ; 20 lS4 the GPDA is a~7aiting the arrival of a DCP. Upon receipt of a DCP and a start oommand at step 156, cc~nELnd register 94 (Figure 4) is loaded with a load commanl to load t]he data ~ transfer parameters register 95, by setting bit~s ~1 and ~0 ;~ to 01 at step 158. At step 160 register 95 is loaded wi~h tlle necessary tr~nsaction code, ~yte count and control bits. In step 162, LBR, last 64-Kbyte block, is set because only lO,OaO
bytes are to be transferred. The transfer is started by~setting '~ CWl, C~0 to 11. In step 164, the tape is started and data are transferred across DDA Bus 20 until CHE, channel empty, state occurs. Upon receipt of CHE from the status register, GæDA 150 is reset by setting ~.~1, CW0 to 00 in step 168. Finally in step 170, a signal is sent to the receiver over CCB 52 that the trans~itter is finished.

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~: ' i3~22 1 Fig~re 8 is a simplified flow diagram of the sequence of events that take place in the receiver GPD~ 152. Steps 172-180 correspond to steps 154-162 shown in Figure 7. At step 182, the receiver GæDA waits until the 64--word FIFO, such as 1~6, Figure 4, is full before starting the array processor assuming, of course that the transmitter is not finished, step 186. Once the FIFO is full, data transfers take place at step 184 until the XM~R finished signal is received from transmitter GPDA 150 over the DDA Ocmmanl Bus 20. It will be rememkered that the receiver FIF3 holds sLxty-fo~r ~ords and therefore it is still full after the transmitter finishes. Accordingly, steps 188-202 take place in order to empty the FIFO. Since the array processor receives data in 16 word blocks, the FIFO will be emptied at the fourth cycle and CHE will go true, causing the system to reset at step 204, whereupon both transmitter and receiver revert to the IDLE state.
Other madifications and e~odiments may be m~de by those skllled in the art without deaprting from the scope and teachings of this disclosure which is limited only by the appendel claIms.

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Claims (6)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A data processing subsystem associated with a host computer, comprising:
a supervisor for establishing communication between said host computer and said subsystem;
a direct device access bus;
a plurality of peripheral devices, all having equal priority and means for interfacing each device with said direct device access bus;
means associated with said supervisor for sub-dividing said plurality of peripheral devices into several device sets by use of several unique transaction codes and for assigning a different task to each said device set;
a bus controller interconnected between said super-visor and said direct device access bus for opening and closing data pathways, over said direct device access bus, between the members of each device set to enable substantially concurrent data transfers between the members of said several device sets as required in the performance of said different tasks.

2. The improved data processing subsystem as defined by claim 1 wherein:
one of the members of said set of peripheral devices is a transmitter device.

3. The improved data processing subsystem as defined by claim 2 comprising:
means associated with said supervisory means for transferring data directly between a transmitter device and a plurality of receiver devices in a parallel-multiple-record transfer mode.

4. The improved data processing subsystem as defined by claim 2 comprising:
means associated with said supervisory means for transferring data directly between a transmitter device and a plurality of receiver devices in a serial split-record transfer mode.

5. The improved data processing subsystem according to claim 4 comprising:
means for supporting command/data chaining to permit serial split-record data transfers independently of action by the supervisory means and the host computer.

6. The data processing subsystem according to claim 1 wherein:
said bus controller initiates a second data transfer over said direct device access bus before completion of an immediately previous transfer of data.