CA1150819A - Subscription television apparatus and methods - Google Patents

Abstract

ABSTRACT
Subscription apparatus and methods wherein an encoder begins inversion of a video signal during the last horizontal trace line of a randomly selected vertical interval and continues to invert trace lines in the following field of the video signal. The encoder also suppresses the amplitude of randomly selected horizontal blanking pulses only during fields of the video signal while maintaining unaltered the absolute amplitude differential between the horizontal blanking pulses and associated horizontal synchronization pulses. A decoder reinverts trace lines of the field following detection of an inverted last horizontal trace line of a vertical interval. The decoder also selectively rebiases the video signal to restore the horizontal blanking pulses upon detection of a suppressed amplitude during the front porch of a horizontal blanking pulse. Reinversion of the trace lines and rebiasing of the blanking pulses is achieved by selective reference biasing of a video modulator circuit in the decoder.

Description

1 ~0~9 Background of the Invention 1. Field of the Invention This application is a division of application Serial No. 338,851 filed October 31, 1979.
The present invention relates to apparatus and methods pertaining to the encoding and decoding of a television signal in a manner which deters unauthorized utilization of the signal.

rI. Description of the Prior Art Present day subscription television systems are based on the generally accepted fact that rendering a video picture unviewable in a normal television receiver is most easily and effectively accomplished by simply upsetting the horizontal synchronization of the receiver. It is known that horizontal synchronization can effectively be upset for standard NTSC receivers by simply removing the horizontal synchronization pulses or by suppressing the horizontal synchronization pulses below the average video level of the signal. This causes the television receiver to try to lock horizontally on random video peaks trans-mitted during the active or video trace line portions ofthe video signal rather than on the actual horizontal synchronization pulses. The fact that the horizontal synchronization pulses are no longer consistenly processed also destroys a receiver's ability to use a color reference burst associated with the horizontal synchronization signals, thereby causing inaccurate color reproduction.
However, known systems which employ removal or suppression of horizontal synchronization pulses, require employment of an encoding signal, such as a control code or keying signal, to allow a decoder to reconstruct the missing or suppressed horizontal synchronization pulses.
For example, the control ;' ' ' .
code or keying siqnal may take the form of negative going il encoding pulses inserted in selected locations of the 'l horizontal blanking pulses. In the ~lternative, a totally I independent signal, which contains the critical encoding ~¦ information needed to reconstruct the horizontal synchronization pulses may be sent by a separate communication medium, such as the audio portion of the television signal or a telephone land line.
,1 In addition to having the disadvantage of requiring ,I transmission of an encoding signal to reconstruct the missing ! or suppressed horizontal synchronization pulses, presently known systems, whlch employ horizontal synchronization pulse ; suppression or removal, generate pictures which during a I sequence with a stationary vertical (gray or black) line " will sometimes allow a normal receiver to horizontally lock j !, and display a recognizable picture, albeit with severë color distortion.
Some known subscription television systems employ j , circuitry to invert all or selected portions of the video ,, signal to prevent unauthorized demodulation of the video il signal content. For example, systems have been described " which transmit even number fields with a conventional polarity ~i and transmit odd number fields with reverse polarity with ', ', the resultant video signal generating a blank or washed-out ¦
I picture in a standard television receiver. Other systems ! randomly invert fields or individual lines of video to ~! establish a scrambled signal. To decode randomly inverted !i video, as is the case with decoding missing or suppressed horizontal synch pulses, known systems generally require the ;~

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~ SO~i9 generation and communication of an additional control code, keying signal, or encoding signal, to allow a decoder to correctly reinvert the randomly inverted portions of the scrambled signal.
While systems have been described which employ aspects of both horizontal synchronization modification and video signal polarity modification to generate a scrambled signal, such systems also require the further inefficient process of generating, communicating, and decoding of some form of encoding signal in addition to the scrambled video signal.
It is therefore an object of the present invention to economically and efficiently render the video portion of the television signal scrambled to the point of being effectively unwatchable when displayed on a standard television receiver.
Another object of the present invention is to provide a subscription television system in which the scrambling of the video signal is secure in that it becomes difficult and costly for an unauthorized viewer to reconstruct to an acceptable viewing level.
To this end the invention consists of an encoder for a video signal having fields with horizontal trace lines separated by horizontal blanking pulses having front porches followed by associated horizontal synchronization pulses and the video signal further having vertical intervals separating the fields containing vertical synchronization information followed by horizontal trace lines separated by horizontal blanking pulses, the encoder comprising: a) first means for randomly inverting the polarity of a video signal by inverting the polarity of a trace line of randomly selected vertical intervals and by liS08~9 inverting the trace lines of associated fields following said randomly selected vertical intervals; and b) second means for suppressing the amplitude of randomly selected horizontal blanking pulses during fields of said video signal while maintaining unaltered the absolute amplitude difference between said horizontal blanking pulses and associated horizontal synchronization pulses.
Other features of the apparatus described herein are claimed in the parent application and in divisional application Serial No. 405,945 filed June 24, 1982.
Brief Description of the Drawings The accompanying drawings, which are incorporated and constitute a part of the specification, illustrate a preferred embodiment of the invention and, together with the general description of the invention given above and the detailed description of the preferred embodiment given below, serve to explain the principles of the invention.
Fig. lA illustrates a portion of a video signal including a vertical interval between the end of an even field and the beginning of an odd field;
Fig. lB illustrates the portion of a video signal including the vertical interval between the end of an odd field and the beginning of an even field;
Figs. 2A and 2B illustrate inverting the polarity o~ a video signal in accordance with the teachings of the present invention;

11508~9 ,j F~g. 3 illustrateQ suppress~ng the ampiituae of a il rand~mly selected horizontal blanking pulse in accordance I¦ with the teachings of the present inyention;
jl Fig. 4 is a block diagram of a video encoder incorporating S ,I the teachings of the present invention;
Fig. 5 is a circuit diagram of a processing amplifier , incorporating the teachings of the present invention;
Fig. 6 is a block diagram of a transmitter exciter 'l incorporating the teachings of the present invention;
~ Fig. 7 is a schematic diagram of one example of employing il the teachings of the present inven~ion in a differential , gain driver as illustrated in Fig. 6;
, Fig. 8 is a schematic diagram of one example of incorporating i! the teachings of the present invention in a differential lS ~ phase corrector as illustrated in Fig. 6;
?l .. ... ...;
j Fi~. 9 is a circuit diagram of a timing networ~ employed .~ in an encoder in accordance with the teachings of the present , invention;
: Fig. 10 is a block diagram of decoder constructed in 20 i accordance with the teachings of the present invention; .
Fig. 11 is a circuit diagram of the synch and inversion contFol illustrated in Fi9. 10: ;, ,, Fig. 12 is a circuit diaqram of the synch comparator, :, . video comparator, synch gate, and video gate illustrated in ' Fig. 10;
Fig. 13 is a circuit diagram o.E one example of the i~ timing network illustrated in Fig. 10.
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! The above general description and the following detailed !, description are merely illustrative of the generic invention i and additional modes, advantaqes, an~ particulars of this ! inve~tion will be readily suggested to those skilled in the S ¦! art without departing from the spirit and scope of the inveation.
Description of the Preferred Embodiment Reference will now be made in detail to the present '1 preferred embodiment of the invention as illustrated in the 10 ~!~i accompanying drawings.
.j ~roadly, the present invention relates to a subscriber 'i televi~ion system and method for selectively communicating , a standard television video signal. Specifically, a standard ¦l television video siqnal may be defined as a composite video ' siqnal having fields with horizontal trace line~ separated ~, ....................................................... ... ... ;
by horizontal synchronization pulses and further having . jj vertical intervals separating the fields~ the vertical intervals containing vertical synchronization information followed by horizontal lines separated by horizontal blanking " pulses.
I; For example, as illustrated in Figs. la and lb, a I composite video signal comprises even fields 10 and odd ~' ,~ fields 12. As shown in Fiq. la, the end of each even field 'I
,~ 10 is separated from the beginning of each odd field 12 by a `!
~I verti¢al interval 14 whereas as illustrated in Fig. lb the 7 _ 11~08~9 !

end of each odd field 12 is separated from the beginning of ! each even field 10 by a vertical interval 15. Fields 10 and il 12 include horizontal trace lines, s~veral of which are ,¦ illustrated in Fig. la and lb by trace lines 16, 18, 20, 22, ' 24, 26, 28, and 30. In addition, the end of each odd field ¦ 12 and the beginning of each even field 10 contain half trace lines 32 and 34, respectively.
. The horizontal trace lines of fields 10 and 12 are each l; separated by horizontal blanking pulses 36. A horizontal 10 .~i blanking pulse 36 is illustrated, for example, in Fig. 3 as having a front porch 38 typically of approximately 2 microseconcl !I duration and a back porch 40 which typically carries on it a ~ color burst signal 42. Horizontal blan~ing pulses 36 each ,i further carry a horizontal synchronization pulse 44 followin~ ¦
. front porch 38 and preceding back porch 40. It is of course . i~ ...................................................... .......
to be understood that the present invention is also obviously :. applicable to composite video sig~als which exhibit the !l essential format in the above set out composite video signal, ¦
although such other composi~e video signals may exhibit ' additional features or minor modifications.
Vertical intervals 14 and 15 as illustratively shown in Fiqs. la and lb typically contain vertical synchron~zation;;
information comprising, for example, equalizing pulses 46 ' followed by a serrated vertical synchronization pulse 48 l 25 1i which in turn is followed by additional equal~zing pulses ~¦
~ 50. The vertical synchronization information is in turn ~.

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typically followed by horizontal trace lines 52 which are `I separated by horizontal blanking pulses 54 that contain horizontal synchronization pulses 56~ In additian, vertical j interval 15 which separates the end of odd fields 12 from il the be~inning of even fields 10, terminates in a ~.alf horizontal trace line 58.
In accordance with the present invention, a subscriber television system comprises video encoder means for randomly ' inverting the polarity of the video signal by inverting the polarity of a trace line of randomly selected vertical intervals and by inverting the trace lines cf associated ' fiel~s following said randomly selected vertical intervals, '~ the said encoder means further including mean~ for suppressina I the amplitude of randomly selected horizontal ~lanking ;, pulses during the fields of the video signal to form a .. .. . .. ... ..
scra~led video signal. I
In Figs. 2a and 2b, for example, a trace line 60 of ;I vertical intervals 62 is shown to have approximately a 75%
amplitude level which in the art is nDrmally ind~cative of a black or blan~ing level. In Fig. 2b, trace line 60 is shown . to have an inverted polarity such that an indication of black or blanking levQl is now represented by an approximately 10% amplitude signal. Accordingly, the video signal of Fig. ~!
,l 2b represents one illustrative and not limitinq example of a trace line of a vertical interval having an inverted polarity.
In Fig. 2a fields 64 follow and therefore may be said ij to be associated with vertical intervals 62. Associated ,¦ fields 64, as was explained above with respect to fields 10 I . , l .

_ 9 _ ' ¦
j, and 12 in Figs. la and lb, contain a series of trace lines 66 separated by horizontal blanking pulses 68. Trace lines 66 are represented in Fig. 2a to contain video information which information, in accordance with standard United States television practice, represents a white signal at 10% amplitude and a black signal at 75%
amplitude. In Fig. 2b, however, trace lines 66 have been inverted and therein represent a white signal at 75%
amplitude and a black signal at 10% amplitude signal.
Thus, while the video signal represented by Fig. 2a would result in a normal television picture in a standard television receiver, the video signal of Fig. 2b would res~lt in an inverted or "negative" television signal in a standard television receiver. The video signal of Fig. 2b therefore represents a partially scrambled video signal.
The subscri~er television system of the present invention further comprises a video encoder means including means for suppressing the amplitude of randomly selected horizontal blanking pulses during the fields of the video signal to form a scrambled video signal.
Again, for purposes of illustration and not limitation, attention is called to Fi~. 3 wherein a standard horizontal blanking pulse 36 of a field is illustrated. Blanking pulse 36 is illustrated as achieving approximately 75% amplitude for the entire time duration 70 of the blanking pulse. In addition, following front porch 38, a horizontal synchronization pulse 44 is shown mo~nted on horizontal blanking pulse 36. A
suppressed horizontal blanking pulse 72 is illustrated in ;
,i, -- 10 --1150~9 Fig. 3 as having a constant 25% level ampl'tude during the entire time duration 70. However, it should be noted that while suppressed horizontal blanking pulse 72 has a lower ; level amplitude than horizontal blan~ing pulse 36, the differential 74 between the level of horizontal ~lan~ing pulse 36 and the level of horizontal synchronization pulse 44 remains unaltered. Preferably, horizontal blan~ing puls~
36 is suppressed to a level such that horizontal synchronization ,I pulse 44 will fail to lock a s~andard television receiver i~ into hor~zontal synchronizat~ion.
In ~ig. 4 there is illustrated a block diagram of one example of video encoder incorporating the teachings of the j!
present invention to randomly invert a video signal as is 1' illustrated in Fiqs. 2a and 2b and to suppress randomly 15 , selected horizontal blan~ing pulses as is illustrated in Fig. 3. The decoder of Fig. 4 comprises a standard tëlevision camera 100 having a video output 102 coupled to the series combination of processing amplifier 104, transmitter exciter 106, transmitter 108, and antenna 110. As is well-known to 20 I those skilled in the art, processing amplifier 104 takes video output 102, which comprises a compos~te video signal, shapes and or reforms the color burst signal, controls the ;I gain and bandwidth of the video signals, and~or shapes "
!' and/or reforms the synchronization signals to create a 25 ' reconstituted composite video signal on output line 112 to exciter 106. As is also well-known to those skilled in art, tl exciter 106 continues to shape and form the reconstituted video signal ~or suitable applica~ion to transmitter 108 which radiates the video signal by means of antenna 110.
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The encoder of Fig. 4 further includes a random signal generator 114 and a timing network 116. As will be explained ,1 in greater detail below, a processin~ amplifier 104 is Il modified to operate in connection with timing network 116 to il randomly invert video output 102 by inverting the polarity 11 of a trace line of vertical intervals randomly selected by ., generator 114 and by inverting the trace lines of associated '~ fields following the randomly selected vertical intervals.
!i Furthermore, as will be explained in detail below, exciter 'I. 106 is modified to operate in conjunction with timing net-work 116 to suppress the amplitude of horizontal blanking !! pulses during fields, which blanking pulses are also, but 'j differently, randomly selected by generator 114. Thus, the ,1 output of exciter 106 includes a scrambled video signal lS , whose polarity is randomly inverted as, for example, is ï i illustratively shown in Fig. 2b and whose horizontal blanking .- l pulses are randomly suppressed as is illustratively shown ', in Fig. 3. -' Timing information from video output 102 is transmitted I from processing amplifier 104 to timing network 116 over ! line 118 while gating signals to randomly invert the video . signal are communicated from timing ne.twork 116 to processiny .
'I amplifier 104 over line 120 and gating signals to suppress ,I randomly selected horizontal blanking pulse are transmitted 'I from timinq network 116 to transmitter exciter 106 over line ¦
i~ 122. !
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In accordance with the pre ent invention, an encoder includes means for generating an audio subcarrier signal, ,¦ means for generating an audio signal~ and means for modulating ,I said audio subcarrier with said audio signal.
'! As also illustratively shown in Fig. 4, audio subcarrier ¦' generator 124 is coupled between microphone 126 and transmittel i exciter 106. Audio subcarrier 124 allows programmed audio to ~e transmitted on an audio s~bcarrier such as that used i¦ for "store cast" or background music transmission by FM
radio as is well-~nown to those s~illed 1n the art. Generator ' 124 may, for example, generate a 39.5 mhz subcarrier signal which is modulated by audio from microphone 126. ~he thus , modulated signal is in turn u~ed to modulate a 4.5 mhz ' oscillator in transmitter exciter 106.
15 !~ Further in accordance with the present invention an ï 1~ encode~ preferabiy includes ~eans for inserting data signals into additional selected trace lines of the vertical intervals.
As also illustratively shown in Fig. 4, data register 128 is coupled to data gate 130. In data register 128 data 20 ; information may, for example, comprise 24 bits and be sent ~! at approximately a 500 khz bit rate. The format may, for example, be 2 frame bits, 19 binary coded addres~ bits, one l , parity bit and two command data bits. The command data bits ;' may serve to set or reset a magnetically latching relay in a decoder which will either enable or disable the decoder operation, and which will remain in its assigned state even in the case of power interruption at the decoder as will be explained more fully below. ,1 `I

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Under control of timing network 116, data gate 130 !, operates to pass digital ~nformation from data register 128 to processing amplifier 104 during s~lected trace lines of ~I the vertical intervals of the video signal. For example, ,, three trace lines of each verti¢al signal may be employed to i~ transmit data information, and the information may be transmitted in digital form with an uninverted portion of a I trace line indicating a zero data bit and an inverted portion .' of a trace line indi¢ating a one data bit. A¢cordingly, the !' same mechanism utilized in processing amplifier 104 to ' randoml~ invert the polarity of the video s$gnal, as will be '. explained in detail below, can also be employed by data gate ' 130 to generate data information during trace lines of the ~i vertical intervals.
In Fig. 5 a circuit diagram is provided showing one .' example of processing amplifier 104. In Fig. 5 processing ' I amplifier 104 is illustrated as comprising diplexer 200, color burst processor 202, video processor 204, synch .
~ deteetor 206, synch processor 208, and combiner 210. As is 20 , well-known to those skilled in the art, diplexer 200 may 1 il operate to separate a color burst signal which is delivered ~¦
i by line 212 to color burst processor 202 from a video signal i;
which is delivered by line 214 to video processor 204.
i. Color burst processor 202 essentially reconstructs the color ~
25 ~I burst signal of the composite video received by diplexer ~.¦
~' 200, for example, by phase-locking a stable 3.58 mhz oscillator l; to the incoming color burst signal. Video processor 204 .1 !, , ., 'j ' ~

11~0819 , may, for example, control the gain and bandwidth of the !' video siqnal. It may also extend low or high frequency i components, or cut-off unwanted port~ons of the video signal ! to give control over the formation and shaping of the video T
5 ~I signal.
The video siq~al on line 214 from diplexer 200 is also communicated to synch detector 206 which, as is well-known in the art, separates horizontal and vertical synch information !I from the composite video signal introduced to diplexer 200.
10 ' The output of synch detector 206 i5 coupled to synch processor , 208 which, like color burst processor 202, essentiall~
operates to reconstruct the syn¢hronization ~ignals by ~! phase-lo~king an internal oscillator to the incoming syn-il chronization signals. Signal processor 208 thereby recon-15 i structs and shapes the synchronization signals of the ; composite video signal.
In a standard processing amplifier, such as Grass , Valley Group Processing Amplifier, model 3240, the reconstructed ¦
!' color burst signals, video signals, and synchronization ¦
signals are combined in a com~iner 210 to form a reconstituted , composite video signal. ,¦
As explained above, the subscriber television system of '? the present invention includes encoder means for randomly l~ invertin~ ~he polarity of a video signal. For the purposes , of illustration and not limitation, attention is called to , analog switch 216, resistors 218, 220, 222, and 224, and ¦ differential amplifier 226 in Fig. 5. The output of differential¦
;, amplifier 226 is shown in Fig. 5 coupled to the video input ; . .
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3~ - lS _ . ., . l llS08~9 ' ' of combiner 210. ~eedback resistor 224 couples the output ? of amplifier 226 to the negative input. The negative input of amplifier 226 is in turn coupled to incoming video from , video processor 204 through the series combination of first S I pole 228 of analog switch 216 and resistor 218. The positive I input of differential amplifier 226 is coupled to the video from video processor 204 through second pole 230 of analog switch 216. First pole 228 of analog switch 216 is closed .l upon receipt of a Q gating signal on line 120 from timing .I network 116 whereas second pole 230 is closed upon receipt , of a Q gating signal over line 120 from timing network 116.
In operation of processing amplifier 104 as illustrated in Fig. 5, a Q gating signal from timing network 116 over , line 120 closes second pole 230 of analog switch 216 and :l allows the video signal from video processor 204 to be ï ~i transferred uninverted through differential amplifier 226 to . ;~ combiner 210. Accordingly, a normal reconstituted composite video signal is generated ~y processing amplifier 104 when a , Q gating signal appears on line 120. However, when a Q .¦
~ gatins signal appears on line 120 second pole 230 is opened and first pole 228 is closed communicating the video signal from video processor 204 to the negative input of differential , amplifier 226 and thereby causing inversion of the video .
j~ signal resulting in a reconstituted composition video signal 25 ¦' with an inverted video portion. ;

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1~508~9 i '.
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~i It should be noted that since the reconstituted synchros~Lzatio~
~ components of the video signal are inserted into the composit^
,I video signal by operation of synch d~tector 206 and synch ~! processor 208, the inversion of the video signal from line ~ 204 before introduction to com~iner 210 has no effect on the ~i polarity oE the synchronization signals. Accordingly, first '! pole 228 of analog switch 216 may be closed at the beginning j of the last full trace line of a vertical interval and ;l I
,~ remain closed throughout the subsequent fieid until the : beginning of the next vertical lnt~rval without in any way invertin~
" or otherwise affect~ng the shape of the synchronization t signals of the reconstituted composite video output from ', processing amplifier 104. ~hus, all that is required to , achieve a desired random inverting of the polarity of a , video signal introduced to processing amplifier 204 is a ¦ ' ~ating signal Q on line 120 which begins at the beginning of a selected trace line of a randomly selected vertical interval and,continues throushout the succeeding field until the beginning of the next vertical inter~al.
It should of course be understood that random inverting l . of the polarity of a video signal by inverting the polarity !
of a trace line of randomly selected vertical intervals and : ~y inverting the t,race lines of associated fields following ';
, the randomly selected vertical intervals can ~e achieved in ,. a number of alternative manners consistent with the spirit and scope of the present invention. For example, an inverter .¦
., , ., 17 - ~
, '~ ~' 'i i ~ay be inserted in the composite video signal path and tr~qgered durin~ a selected trace l~ne of randomly selected vertical intervals and triggered during the trace lines of , associated fields following the rand~mly selected vertical S ~ intervals. This method of inverting the polarity of the video signal, however, requires a gating signal which disables the inverter during horizontal synchronization signals which is not required in the processing amplifier il 104 illustrated in Fig. 5.
10 1l As mentioned a~ove, the video encoder means of the sub~ect invention further includes means for suppressing the amplitude of randomly selected horizontal blan~ing pulses during the fields of said video signal to, in con junction with the randomly inverted video signal, form a scrambled video signal. For purposes of illustration and not limitation attention is called t~ Fig. 6 wherein there is disclosed a ;l block diagram of a transmitter exciter incorporatlng the teachings of the present invention. ¦
The example of exciter 106 shown in ~ig. 6 comprises , the series combination of differential amplifier 300, video gain control 302, driver amplifier 304, differential gain i ~r~ver 306 differentLal gain corrector; 308 differential ;I phase drive 310, and differential phase correc~or 312. ;!
I Differential gain drive.r 306 is li~ited during horizontal I synchronization pulses by operation of video clamp amplifier 314 which is in turn controlled by clamp pulse generator 316 and by differential phase corrector 312 over line 318.

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~ 18 - , ;, `, Ij i 1i50819 Exciter 106 of Fig. 6 represents the basic design of an RCA Exciter Model No. TTUE-4A. It is of course intended that any comparable form of exciter may be employed in con~ection with the teachings of the present invention.
Any suitable point may be chosen along the video path including differential amplifier 300, video gain control 302, driver amplifier 304, differential gain driver 306, differential gain corrector 308, differential phase driver 310 and differential phase corrector 312 to suppress horizontal blanking pulses in response to a gating siqnal from timing network 116 of Fig. 4. For example, in Fig. 6 a gating signal Q from line 122 of timing network 116 is shown coupled to differential gain driver 306. Gating signal Q, as will be explained below, appears during randomly selected horizontal blanking pulses and operates to alter the bias of differential gain driver 306 by a fixed amount during such randomly selected horizontal synchronization pulses. Furthermore, since video clamp amplifier 314 attempts to clamp the horizontal synchronization pulses at a fixed level, it is necessary to also introduce gating signal Q to differential phase corrector 312 during the randomly selected horizontal blanking pulses to effectively prevent the operation of video clamp amplifier 314 from attempting to rebias the suppressed horizontal blanking pulses to their normal unbiased level.

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ii 1~508~g F$g. 7 is a schematic diagram of one example of a i portion of differential gain driver 306 employing the teachings i of the present invention. Specifica~ly, Fig. 7 illustrates '¦ a simple differential amplifier comprising transistors 320 5 ! and 322 with video input coupled to the base of transistor '! 320 and video output taken from the collector of transistor il 320. The video output, as can be fully appreciated by one skilled in the art, reflects the biasing level applied to j the base of transistor 322. Accordingly, the video output o i! from transistor 320 can be selectively biased by the employment 'I of an analog switch 324 in series with variable resistor ,1 326 connected between the base of transistor 322 and a B+
¦ voltage supply. The value of resistor 326 is chosen such ,¦ that upon closure of analog switch 324 by gating signal Q
the video output from transistor 320 is biased a fixed t '~ amount from normal biasing levels. For example, with j reference to Fig. 3, the value of resistor 326 may be chosen , such that upon closure of analog switch 324 during a horizontal !, blanking interval, the level of the horizon~al blan~ing 20 !' pulse is reduced from approximately 75% amplitude to 25%
jl amplitude.
An example of a portion of differential phase corrector 312 is illustrated in Fig. 8. Specifically, a buffer ampliier Il which forms the output of differenti~l phase corrector 312 1l is illustrated in Fig. 8 as comprisin~ transistors 328 and ¦ 330 series coupled between a B+ and a ~- voltage supply by !! resistors 332 and 334. The base of transistor 330 is il .
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~¦ coupled to the B+ supply by diode 336 and resistor 332 and ! is coupled to the B- supply by resistor 337. The base of il transistor 328 is coupled to receive the video input whereas ,I buffered video output is provided to'transmitter 108 of Fig.
~¦ 4 through resistor 338 coupled to the junction of the emitter of transistor 328 and the collector of transistor . 330. A controlled video feedback is provided to video clamp ~, amplifier 314 of Fig. 6 through resistor 340 which is also ;' coupled to the junction of the emitter of transistor 328 and o ! the collector of transistor 330.
Il ~o prevent operation of video clamp amplifier 314 from cl~mping the video signal in differential gain driver 306 of . Pig. 6 to the normal bias level of a horizontal synchronization , pulse during randomly selected suppressed horizontal blanking ~ pulses, the video output from resistor 340 in Fig. 8 is selectively coupled to the B- bias by the series combination .~ ' of analog switch 342 and variable resistor 344. Analog ,.
" switch 342 is controlled by the ~ gating signal from line 122 of timing network 116 to close analog switch 342 during i each randomly selected horizontal blanking pulse to effectively trick video clamp amplifier 314 into believing that a normal horizontal blanking pulse is present. In this manner, the video output from resistor 33B of differential phase correc~or ~!
1! 312 will pass randomly selected horizontal blanking pulses ~¦ of suppressed amplitude.
It should of course be understood that the suppression j of randomly selected horizontal blanking pulses can be 'l achieved in accordance with the teachings and spirit of the ~1 . .

\~ _21 _ ~i present invention in many alternative manne,r-~ and that the ! specific circuits of Figs. 6, 7 and 8 are set out to illustrate ! a single example of how suppression of the amplitude of Ij randomly selected horizontal blankin~ pulses may be achieved.
S '! Fiq. 9 provides a circuit diagram of one illustrative, but non-limiting example of timing network 116 of Fig. 4.
' ln Fig. 9, a video signal is provided on line 118 from processing amplifier 104 in Fig. 4. The video signal on il line 118 is shown ¢oupled to the video input of tuner and '~ master oscillator 400. Tuner and master oscillator 400 is ;I known to those skilled in the art having a standard TV tuner I and an internal oscillator which is locked to horizontal ,' syn¢hronization sisnals, either the horizontal blan~ing '~ signals or the horizontal synchronization pulses. Specifically, master oscillator 400 may comprise an Ml ~lodule of Zenith , Corporation which is presently employed in many commercially ,. ' available Zenith televisions. The Ml ~lodule employs a 503.5 kHz master scan oscillator which is phased-locked to 32 times the horizontal rate of a video signal received by the 20 ! tuner section. A master clock output of the oscillator 400 ¦
is coupled by line 402 to synch signal generator 404. When ,¦
master oscillator 400 is an Ml Module, line 402 is coupled ', to terminal B4.
I' Synch signal generator 404, as is well-known to those I skilled in the axt, provides horizontal drive pulses and I vertical blanking synchronization pulses in response to 1', receipt of a master clock signal and a composite synchronization signal. Synch signal generator 404 may, for example, comprise a Zenith 221-103 chip which is also presently employed in commercially availa~le Zenith televisions.

1150~19 j 'A composite synchronization signal,is provided to synch signal generator 404 from line 406 coupled to master oscillator ! 400 A composite synchronization si~nal merely comprises I the horizontal and vertical synchronization signals from the S tj video signal on line 118. For example, a suitabie composite l synchronization signal can be received from terminal B2 of i a Zenith Ml Module.
~orizontal drive pulses are generated by synch signal ' I generator 404 in response to the master clock signal on line 1 402 and the composite synchronization signal on line 406.
Horizontal drive pulses are defined with respect to timing network 116 as a square wave locked to the horizontal ' synchronization rate which passes from negative to positive l~ at or slightly before the beginning of each horizontal ~ U anking pulse. Vertical blanking synchronization pulses I ' from synch signal generator 404 are defined with respect to ' timing network 116 as a signal which is negative going half- , 'l way,through the vertical synchronization pulse of a video ,¦
; signal and remains negative going un~il termination of the '¦
' vertical interval.
! In Fig. 9, with horizontal synchronization generator ; 404 representing a Zenith 221-103 chip, output terminal 11 of synch signal generator 404 is coupled to the cloc~ed , input of flip-flop 408. In addition, the master clock ' signal on line 402 is coupled through inverter 410 to the input of counter 412, while a reset signal is supplied to ', counter 412 from the horizontal drive pulses of output terminal 11 of synch siqnal generàtor 404 through inverter _ 23 -.' '' ' '~

li5~8~9 '~ 414. Upon the beginning of each horizontal drive pulse counter 412 is enabled to provide an output upon receipt of six ma~ter clock signals to reset flipflop 408. The Q
' output of flip-f}op 408, namely flybick pulses, are coupled S jl from flipflop 408 by line 416 to the Bl terminal of master oscillator 400. This interconnection of master oscillator 400, synch signal generator 4~4, counter 412 and flip-flip ' 4.08 assures that the flybac~ pulscs on line 416 are centered , on the horizontal synchronizati~n signals of the video I sig~aal and have a duration of six of the 32 oscillations of master oscillator 400 which occur for each video line.
, Acco~dingly, the flybac~ pulses~on line 416 begin just slightly before the beginning of each horizontal blanking ~ll pulse ar;td terminate just slightly after the termination of ' each horizontal blanking pulse.
The timing networ~ illustrated in Fig. 9 further includes . inteqrating network 418, differential amplifier 420, flip-flops 422 and 424 and counter 426. Integrating network 418 is co~pled to receive the composite synchronization.signal ¦
on l~ne 406 and is designed to provide as an output vertical synchtro~ization signal to pin 12 of synch signal generator 404 and to the ne~ative input to comparator 420. The ,!
~! application of vertical synchronization pulses to pin 12 of :I synch signal generator 404 assures generation of vertical ~¦ blanking synchronization pulses at pin 7 of generator 404 as is known to those skilled in the art. In addition, the application of vertical synchronization to the negative ¦
, input of comparator 420 with the positive input. of comparator 420 coupled to a reference point will generate at the output , ' of comparator 420 a signal pulse with positive transition after "
,j ''~.
4 _ ~

1150~19 ., .

~¦ tho trailing edge of the vertical synchronization pulse if a .
il vertical synchronization pulse is in fact present in the ,', composite video signal.
'j ~he output of differential ampllfier 420 is coupled to S ! the clock input of flip-flop 422 which has a data input ,¦ coupled to receive the vertical blan~ing synch pulsés from pin 7 of synch signal generator 404- Since flip-flop 422 is clocked by the positive transition signal from differential ¦i amplifier 420 if a vertical synchronization pulse is present 11 in the video signal, the output of the flip-flop 422 will go ~! high and stay high when the vertical blanXing synch pulses from generator 404 are properly phase-locked to the incoming _ ~; video signal. The Q output of flip-flop 422 is coupled to ! the data input of flip-flop 424 whereas the vertical blanXing synchronization pulses are coupled to the clock input of - . ......................................................... . . - :1 flip-fiop 424. The reset of flip-flop 424 is coupled to the ,~ output of counter 426 which, in turn, has as an input the 'I inverted horizontal drive pulses from inverter 414 and has :¦
. a reset coupled to the Q output of flip-flop 424. Counter l 426 is designed to provide a short end of field pulse at the ¦
,I start of each vertical interval. Since flip-flop 424 is '¦
clocked at the end of each vertical interval and is reset at ;, ~ the end of each field, the Q output of flip-flop 424 generates ¦
,; a vertical interval signal which is high during the vertical `j ~ interv~l and low during the fields between vertical intervals. `¦
The timing network of Fig. 9 further comprises coun~er 1 ,l 428, OR gate 429, and flip-flops 430 and 432. Counter 428 .¦
,j is coupled to receive the horizontal drive pulses from synch ¦
1' 1 1 ! ;~
. -25 _ .,~ ' i llSO~9 !' signal generator 404 as an input and to receive the vertical blanking synch pulses from generator 404 as a reset signal.
,Counter 428 therefore begins countin~ half way through the ~i vertical synchronization pulse of a vertical interval and ll continues to count horizontal drive pulses until the beginning of a chosen trace line of the vertical interval, preferably the last complete trace line of the vertical interval.
The output of counter 428 is coupled to the clock input '¦ of flip-flop 432 whereas the data input of flip-flop 432 is I coupled to random signal generator 114. Random signal ' generator 114 may, for example, co~prise two separate random signal generator~ namely synch random signal generator 434 ' and video random signal geneator 436. In that case, the 1 data input to flipflop 432 is coupled to video random lS ~! signal generator 436. ~he reset of flip-flop 432 is coupled to the output of counter 426. Accordingly, flip-flop'432 ,. , operates to provide a high output at the Q terminal during j the last line trace of randomly selected vertical intervals and to continue a high Q output during the field which follows the randomly selected vertical interval. ~The output ,l of flip-flop 432 is coupled over line 120 to processing ~ amplifier 104 of Fig. 4, and speciflcally is coupled to ', analog switch 216 of Pig. 5 as described above. , ;~ Flip-flop 430 has a clock input.coupled to receive l flyback pulses from line 416 and a data input coupled to synch random signal generator 434. OR gate 429 is coupled to ~1 ,; receive at a first input terminal the inverse of flyback pulses ,¦
. ' ' ., , '~

' _ 26 _ , ;l ~1508~9 ,j .

,l~ on line ~16 from the Q outpu~ of flip-flop 408., OR gate ij 429 is also coupled to receive at a second input the vertical !~ interval signals from the Q output o~ flip-flop i24. The~-tl output of OR gate 429 is coupled to the reset terminal of S ~¦ flip-flop 430. Flip-flop 430 accordingly operates to il provide a high output or Q gating siqnal at line 118 during randomly selected horizontal synchronization pulses since, j when synch random signal generator 434 is high at the , ~eg$nning of a flyba¢~ pulse on line 416, a high output is .! ge~erated at the Q output of flip-flop 430 until flip-flop '~ 430 is reset slightly after the end of the horizontal blanking ~' signal by the Q output of flip-flop 408 through OR gate 429.
ii In addition, flip-flop 430 is disabled durinq vert~cal intervals by the operation of the vertical interval signal l of flip-flop 424 applied to the second input of OR ga~e 429 ,' who~e output in turn drives the reset terminal of flip-flop , 430.
In summary, the output on lines 120 from flip-flop 432 Il in Fig. 9 is coupled to processing amplifier 401 of Fig. 4 ~¦ and provides inversion of the polarity of a trace line of , randomly selected vertical intervals and inversion of trace il lines of the field following the randomly selected vertical interval~. The output on line 118 of flip-flop 430 in Fig. 9~¦
~s coupled to transmitter exciter 106 in Fig. 4 and provides ! suppression of the amplitude of randomly selected,hor~zontal ~,¦
'¦ blan~ing pulses during fields of the video si~nals. The j combination of the random inversion of the polarity of the ¦
li video signal and the suppression of randomly selected horizontal ~¦
ii blanking pulses provides a scrambled video signal to transmitter`~¦
108 of Fig. 4 which signal is unintelligible at a normal television r.eceiver. il 1 ! 27 ~

'¦ In accordance with the subscriber television system of the present invention, the system further comprises a decoder means responsive to the polarity of ~e trace line of the ,I vert~cal intervals for detecting the!polarity of the trace 5 11 lines of said associated fields, the detector ~eans being il further responsive to the a~plitude of the scrambled video ! signal during selected time intervals for detecting the i~ suppression of the randomly selected horizontal blanking ¦ pulses, and decoder means respons~ve to the detector means !I for unscrambling the scrambled video signal.
, As applicable to the specific waveformQ illustrated in '~ Figs. 2b and 3, a specific embodiment of the present invention may, for example, include a decodex which is responsive to ,¦ the polarity of trace line 60 of each vertical interval 62 ~; for detecting the polarity of the trace lines 66 of associated .. 1 - I fields 64. For the specific illustrative waveforms shown in ' Figs. 2b and 3, an example of a detector of the present !~ invention is further responsive to the amplitude of the '' ;
scrambled video signal during time period 70 of Fig. 3 which , is the time period of horizontal blanking pulses, for detecting ~l ~¦ the amplitude of the horizontal blanking pulses. Preferably the detect~on occurs during the period of front porch 38 to detect the suppression of randomly selected horizontal ', blanking pulses. In this specific example, a decoder is l also provided which is responsive to detection of an inverted trace line 60 of Fig. 2~ and responsive to detection of a suppressed horizontal blanking pulse during front porch 38 il as shown in Fig. 3 for unscrambling the scra~bled video , signal.
,1 ~
-28 - ~

, i~ I

1~508~9 More specifically, a television decoder in accordance - with the present invention preferably comprises a detector generating a video signal from the received composite video signal. In the specific example o a decoder illustrated in Fig. 10, antenna 500, UHF tuner 502, IF amplifier 504, tuning and automatic frequency control 506, automatic gain control 508, and video and audio detector 510 provide a video signal on line 512 from a received composite video signal at antenna 500. More specifically, as is well-known to those skilled in the art, UHF tuner 502 may, for example, convert a received composite video signal to a standard 45.75 MHz television intermediate frequency whereupon it is amplified and band-limited by intermediate frequency amplifier 504. Tuning and automatic frequency control 506 is coupled from intermediate fre~uency amplifier 504 to UHF tuner 502 to set the tuner at a specific received frequency which is preferably set at the manufacturing facilities and not accessible to the viewing public. The signal from intermediate amplifier 504 is then demodulated to composite base band video by video and audio detector 510 again as is well-known to those skilled in the art. Video and audio detector 510 generates a standard automatic gain control signal to automatic gain control 508 in order to keep the operation of UHF tuner 502 and the operation of intermediate frequency amplifier 504 at the proper level.
In accordance with the present invention, the decoder preferably further comprises a video modulator, the modulator having a first input terminal for the video signal and a . - 29 -~1508~9 .j . 1.
~i !
,second input terminal for a refQrence level signal, the modulator operable to generate a modulated television signal respons$ve to the difference betweea~the video and reference l level signals at the first and second terminals.
jj In the specific example illustrated in Fig. 10 a video and audio modulator 514 is shown having a first input terminal 516 and a second input terminal 518. Video and audio modula~or ~ 514 may, for example, comprise video modulator chip number .; LM 1889N which is normally currently found employed in video games to impress a video signal on a radio frequency carrier.
~he output of modulator 514 is coupled to television receiver 532 and comprises a video signal proportion~l to the differential ~l between the signal appearing at first term~nal 516 and ' second terminal 518.
. 15 . In accordance with the present in~ention, the decoder ... ....' ; prefera~ly further comprises bissing means for establishing ! first, second, and third differential signals between the first and second terminals upon receipt of first, second, ~ and third control signals, respectively, the difference jl signals comprising the difference between the video and 'i reference level signals, the first differential s~gnal ,~ biasing the first and second terminals sufficiently for the . ~.
- modulator to generate a normal modulated signal from the 'j video signal, the second d~fferential signal biasing the ! first and second terminals the same as the first differential I signal but the video and xeference level signals interchanged at the input terminals, whereby said modulator gener~tes an .

,i ~iS0~9 ,l inverted modulated television signal, and the third differential ;I signal biasing said first and second terminalQ sufficiently i for the modulator to generate a modu~ated television signal .¦ at a fixed level from the normaI mod~lated ~ignal.
S ¦ In the specific example of a decoder illustrated in Fig. 10, synch and inversion control 520 is shown having one i output 517 coupled to first input terminal 516 of vid~o and audio modulator 514 and another output 519 coupled to second ! input terminal 518 of modulator 514. As wlll be explained j in qreater detail below, synch and inversion control 520 operates in response to first, second, and th$rd internal contr.ol . signals to provide differential signals between first and . second terminals 516 and 518 of video and audio modulator ~l 514.
.. Further in accordance with the present invention the ; decoder also comprises first means for detecting the polarity -¦
of a selected trace line of vertical intervals of the video signal, and second means for detecting the amplitude of the video signal during the initial port~on of horizontal 20 : blanking pulses during the fields of the video signal. In I the specific example of the decoder illustrated in Fig. 10, a video comparator 522 continuously detects the polarity of ! the video signal appearing on line 512 and synch comparator ,.i j 524 continuously detects the amplitude of the video signal j appeari~g on line 512.
., ij i~ '.

. '!
~s , - 31 - 1 i~ !! ` `I

? 1150819 . .
ii .
¦~ The detector illustrated in Fig. 10 further comprises a jl timing network 526, a synch gate 528, and a video gate 530.
¦ Tim~ng network 526 received an input~signal from-video and " audio detector S10 and generates gating signalq to synch S ,I g te 528 and video gate 530. Video gate 530 $s coupled.
I between video comparator 522 and synch and inversion control ; 520 whereas synch gate 528 is coupled between synch comparator jj 524 and synch and inversion control 520. Timing networ~ 526 Il operates, as will be explained below, to pass the output of 1~ video comparator 522 through v$deo gate 530 during a selected I trace line of vertical intervals of a video s$gnal. As will ,1 also be explained below, tim~ng network 526 operates to pass. 1.
,, the output of synch compar~ator 524 through synch gate 528 ,~ during an initial portion of horizontal blan~ing pu~ses .. 15 ~'j .during the fields of the v$deo s$gnal. .. ... ...
!I Further in accordance with the present $nvention, the decoder includes control means for normally coupling the first control signal to the biasing means, the control means , being responsive to detection by the first means of the ,j selected trace line of a vert$cal interval having an inverted ' '~ polar~ty to couple the.second control signal to the biasing ;!
j means during the line traces of an assoc$ate f~eld following .¦
'i the vertical interval, and the control means being responsive ¦
to detection by the second means of the initial portion of ! horizontal blank$ng pulses having an amplitude below a .i predetermined level to couple the third control ~ignal to the biasing means during the portion of the horizontal , blanking pulse following the initial portion. !¦

32 _ s~ `I
~ ! l ` 11508~9 ;' i '; As will be expla$ne~ below with respect to the specific I example of the decoder generally illustrated in Fig. 10, ,i synch and inversion control 520 oper~tes to normally generate a first control signal which operates to establish a first i differential signal biasing first and second terminals 516 ;j and 518 of video and audio modulator 514 sufficiently for modulator 514 to generate a normal modulated television signal from the video signal on line 512. In addition, it , will be explained ~elow how synch and inversion control 520 ~ generates a second control signal upon the detect~on by video comparator 522, in con~unction with video gate 530 and timing network 526, of a selected trace line of a vertical inter~al having an inverted polarity and in response to the ,I second control signal generates a second differential signal biasing first and second termi~al~ 516 and 518 the same as .. , i ; upon qeneration of the first control signal but with the video and reference level signals interchanged at ~nput I terminals 516 and 518, whereby modulator 514 generates an ~nverted modulated television signal .to television receiver 20 ;l 532.
!I Finally, as will be explained below, synch and inversion control 520 is responsive to detection by synch comparator ¦ 524 and synch gate 528 of an initial portion of a hor~zontal ;
' blanking pulse having an amplitude below a predetermined 25 ~! level to generate a third control signal which results in ~I
jl coupling of a third differential signal to first and second ¦
terminals 516 and 518 sufficiently for modulator 514 to ¦
I generate a modulated television signal at a fixed video !
! level above the normal video signal to thereby effectively ~, re-establish the correct level of the suppressed horizontal blanking pulses for the period followi~g the initial period.
_ 33 _ . . .

¦ It is also preferred that the decoder of the present ,l invention include means for detecting a received audio i subcarrier signal, means for demodul~ting said subcarrier ! signal to generate an audio signal in response to detecting i said aud~o subcarrier signal, means for coupling said audio signal to said second input terminal of said modulator, and said modulator operable to generate a modulated tele~ision i signal with audio.
,l In the specific example of the decoder illustrated in 10, Fig. 10, audio output from video and audio detector 510 is j! provided, as is wellknown to those s~illed in the art, on '¦ line 534- The audio on line 534 is coupled to audio switch 'I 536, audio carrier decoder 538, and audio carrier detector 1, 540. Audio carrier detector 540 may, for example, comprise 1 a Decoder ~umber LM567CN, tuned by adjustment well-known to .. ~i .. ........
j those s~illed in the art to a 39 kHz audio subcarrier signal.
., Audio carrier detector 540 operates to generate A control signal to audio switch 536 upon detection of the audio ~ subcarrier. Audio carrier decoder 53.8 operate~ to demodulate i the audio subcarrier to provide demodulated audio to audio switch S36 which is passed through audio switch 536 upon .¦
operation of deteetor 540. ~owever, upon failure of detector 540 to indicate the presence of an audio subcarrier, the ,j , audio signal on line 534 is passed directly through audio 25~ switch 536. The output of audio swltch 536 is coupled to seco~d input 518 of video and audio modulator 514.
! In accordance with the present invention, the decoder il further comprises means responsive to data signals appearing ,¦

:, ;l ! '.
j _34 _ .s liS08~9 .j , .

in the received composite video s~gnal during selected trace lines of the vertical intervals to selectively enable or l disable the modulator. The specific~example of the decoder '1 illustrated in Fig. 10 includes a data gate 542 shift registcr S ,1 544, address comparator 546, storage 548, and term~nal on/off memory 550. The input of data gate 542 is coupled to ,, the output of video comparator 522 whereas the output of li data gate 542 is coupled to shift reg~ster 544. Data gate l~ 542 is opened by operat~on of timing networ~ 526 to pass the ,; output from video comparator 522 during selected trace lines ~! f vertical intervals of the video signal appearing on line 512. Data on these selected trace lines is sequentially ~ loaded into shift register 544. As was explained above, the ¦ data may preferably take the form of 24 blts of d~gital ij information. The first two bits are frame bits, foll,owed by , ....
19 binary coded address bits. The next two bits are data j bits which are used to enable or disable the decoder. The ,j last bit is a parity bit which relates to odd par~ty of the ¦
, 19 address bits only, not the frame bits or the data bits. ,, ,j Address data is preset into the decoder storage 548 and the ~' preset address is compared against the rece~ved address in shift register 544 by address comparator 546. When the address preset into storage 548 matches the address which is ~l !i loaded into shift register 544, the two data bits loaded ; into shift register 544 are examined by terminal on/o~f jj memory 550. If both data bits are low, the output of terminal !
,1 i , ' .

~ j _ 35 _ 1 , ,, ~I . I

1~50819 on/off memory 550 enableQ video and audio modulator 514.
However, if both data bit-~ are high, the output of terminal on/off memory 550 disables video and~audio modulator 514.
~I No change is made in the prev~ous setting of terminal on/off ~I memory for any other combination.
,! The enable or disable signal from terminal on~off ~ memory 550 is preferably accomplished by a pulse of appEoxima~ely.
I 1 mill$second duration to either set or reset terminals of a ,1 magnetic latching reed relay used in memory 550 to switch ! power to video and audio modulator 514. ~f the memory is , commanded to the reset or disabie state, voitage is removed ; from modulator 514 such that no siqnals, video or sound, i scrambled or unscrambled, are delivered to television recei~e~
~ 532. Since the relay is magnetlcally latching in either -I mode, as is the case for example with latohing Reed Relay ' model number 961A12Yl~ manufactured by the C. P. Clare .. Company, disconnecting power to the decoder in general, for either short or long periods, will not affect the setting of ~ the relay and therefore will not affect the enable or disable setting of memory 550.
~li In operational practice, it is anticipated that all decoders will initially be set in the enable state before "
! installation and that a disabling signal will be sent to the ;j Il appropriate decoders on a rotationally continuing basis at ,,¦ least during the transmission of scrambled programs. Since ! only the power to the ~odulator 514 is affected ~y memory 550, address comparator 546 is operable at all times when , X ' _ 36 _ 1 ; 1150~19 i~ there is power to the decoder. Thus, any unauthori2ed ~ decoder attempting to receive scrambled programs can be ;, disabled. Enabling of a decoder may~occur any time thereafter, jj but typically will be dons prior to scrambled program I transm~ssion.
In operation of the decoder ~llustrated in Fig. 10, ! audio and video signals appear on lines 534 and 512 from video and audio detector 510 upon receipt of a composite ¦ television signal at antenna S00. If the audio signal il contains an audio subcarrier, audio subcarrier detector 540 operates to switch audio switch 536 such that the detected audio from decoder 538 is passed through audio switch 536 to second input terminal 518 of modulator 514. However, if an audio su~carrier is not detected, audio switch 536 operates lS to pass audio directly from video and audio detector 510 onto second input 518 of modulator 514.
The video signal on line 512 is coupled to first i~put 516 of video and audio modulator 514 through synch and inversion , control 520 for normal operation. As will be explained below, synch and inversion eontrol 520 normally sets a ! reference differential between terminals 516 and 518 such that modulator 514 generates a normal modulated television ;, " signal to receiver 532.
I Video comparator 522 also receives video signal from 25 ~ line 512 and compares the magnitude of that v~deo siqnal .
against the magnitude of an uninverted black signal. ~he ~! output of video comparator 522 is gated by video gate 530 to j '.

!', !
k ~' 37_ :1 .` ~j i ., .

11508~9 !

1 pass to synch and inversion control 520 only during a selected ! trace l~ne of vertical intervals For example, the output of video comparator 522 may be passe~ to synch and inversion '¦ control 520 only during the last complete trace line of a ~, vertical interval. If the magn~tude of the v~deo during 'I such last complete trace line indicates an uninverted ~lack j, level, synch and inversion control 520 will continue to ,' maintain normal operation of modulator 514. However, if !! video comparator 522 detects that the last complete trace ll line of a vertical interval is below the uninverted ~lac~
~ level, synch and inversion control 520 will operate to bias " inputs 516 and 518 and interchanqe the video signal and ¦ reference level inputs such that the video signal appearing ,i on line 512 is inverted by video and audio modulator 514 durinq the line traces of the subsequent field. In this .. .. ~ .
~' manner, a randomly ~nverted vi~eo field is restored to ,'l normal without the necessity of employing control codes, ! keying signals, or other encoding signals independent from ¦ the actual inversion of the video signal. In the decoder of j Fig. 10 it is the inversion of the video signal itself 'I without additional encoding signals which is detected and ~tilized to reinvert randomly inverted selected fields.
' Synch comparator 524 operates to continuou~ly monitor ~l ~i the level of the video signal to determine when that level i ,I falls below the level of a standard horizontal ~lanking pulse. Synch gate 520 is operated to transmit the output of ¦¦ synch comparator 524 to synch and inversion control 520 ! ¦
,, !' ,I ,i s,~ 38_ liS0~9 ;' .
, , during ~he initial or front porch perio~ of each horizontal ~ ~lanking pulse during a field. Upon detection of a subnormal i! init~al period.or front porch portio~ of a horizontal blanking ~¦ pulse, synch and inversion control 520 immediately operates ~! to rebias first and second inputs 516 and 518 to a level ,j which assures that the remaining portion of the horizontal blanking pulse will be restored to normal level. Furthermore, jj a signal from synch and inversion control 520 is transmitted ,¦ upon detection of a suppressed horizontal blanking pulse to ~l automat~c gain control 508 to rebias the automatic gain .; .
control in a manner which avoids adverse effect on the automatic gain control by the remaining portion of the suppressed horizontal blan~ing pulse. It is this rebiasing . of automatic gain control 508 which allows timing network lS 526 to continually and accura.tely determine the expected . ...
. location of the next horizontal blanking pulse.
Turning now to Fig. 11 there is disclosed illustrative ., but non-limiting examples of terminal on/off memory 550, I video and audio modulator 514, and synch and inversion I control 520.
I In F~g. 11, an example of vide~ and audio modulator 514 is shown to comprise a video modulator chip 600. ~s was ,~ expiained above, video modulation chips 600 preferably ,¦
comprises semiconductor chip LM1889N which is typically ,.l presently found in video games. Chip 600 has a first input ,l 602 at pin 12 and a second input terminal 604 at pin 13.

,' !' l! `I
.~ ~ j `. I

," ; 1 11508~9 . ` , i ! First terminal 602 is coupled to a tap point of variable 'I resistor 603 which is coupled between bias terminal 618 of memory~
'¦ 550 and ground. Second terminal 604~is coupled to receive jl audio through a circu~t compr~sing ros~stors 606, 608, 610, il and 611, inductor 612, capacitors 614 and 615, and varactor diode 616. Specifically, resistors 606 and 608 are coupled between terminal 618 of memory 550 and ground. The anode of ., i ! diode 616 is coupled to the ~unction of resistors 606 and ,¦ 608 while inductor 612 is coupled between bias terminal 618 ¦
10 !1 and the cathode of diode 616. Both capac$tor 614 and resistor 610 are coupled in parallel with inductor 616. The cathode of diode 616 is also coupled through the series combination oE
capacitor 615 and resistor 611 to input 604 of chip 600.
The circuit comprising resistors 606, 608, and 610, inductor il 612 capacitor 614, And varac~or d~ode 616 operates to match ¦
ï ~ audio which appears at the ~unct~on of resistors 606 and 608 ,~ to a standard television fre~uency of modulation for receipt at inPut terminal 604 of chip 600.
I The output of chip 600 is coupled through a Rurface acoustic wave filter 620 which removes lower si~le bands of ,j , ii modulation from chip 600 as w~ll be readily apparent to ;j those skilled in the art. Filter 620 may, for example, ~o~prise a monolithic crystal filter number CI155B from Crystal Technology, In~. The output of filter 620 is .i '¦ transmitted to a standard teievision rece~ve,-.
~ Terminal on/off memory 550 is shown in Fig . 11 as ````I! comprising transistors 622 and 624, voltage regulator 626, ! and a latching relay 6~8 which comprises coils 630 and 632 .1 i !! 1 " 'I

I --40 _ ;
,` ,j il i~ !

~ ~508~9 ~ and switch fi34. Voltage regulator 626 a.~.ld ~witch 634 are ! coupled ~n series between a sourcç of ~ C voltage a~d ,, terminal 618. Coil 630 is co~pled in series with the emitter-J coll~ctor path of transistor 622 between the D.C. source and ll ground while coi.l 632 and the emitter-collector path of ' transist~r G24 are coup-~id in s~ries b~twaen the D.C. source and g.round. The ~ase of tran~is:~r 622 is coupled to receive a disa~le signal from addre~n comparato~ 546 whereag the bas~ o transistor 624 is coupled to rec~ive an ena~
,. signal from addrcss comparator 546 oE Fig. 10. Thuu, upon receip~.t~f a disable signal transistor 622 temporarily conducts causing opening ~f switch 634 and removal of any I power to terminal 618. On the other hsnd rece~pt of an ,; enable signal at the base of transistor 6~ ~loses switch.
! 634 and provides for power at terminal 618 through vo;tage j regulator 626. ............................................. ... ....
. ; Synch and inversion control 520 is illustrated in Fig.
11 as comprising an analog switch 636 having normally open first, second, th~rd, and fourth ~nternal switches 6~8, 640, 642 ~nd 644.
Switch 638 is coupled in series with resistor 645 between 1 a p~ck-off point of resistor 646 and second input terminal ;.
; 604 of chip 600. Switch 640 is coupled between video line ,, 512 and first input terminal 602 of ChiP 600. Switch 642 is 2S ~! coupled in series with resistor 645 between video l~ne 512 and input term~nal 604. One side of switch 644 is coupled to !¦ ground through variable resistor 656 while the other side of ;, switch 644 is coupled to a b~as point in automatic gate ~ l control 508. Resistors 646 and 649 are series-coupled 'I between terminal 618 of memory 550 and ground and the junction ,;
, of resistors 646 and 649 is coupled through resistor 645 to second input terminal 604.
~ ! - 41 -1~508~9 i;
j The operation of switch 640 is ~overned by receipt of a I f~rst control signal on line 650, the operation of switch ,i 642 is governed by a second control ~ignal on line 652, and ,, the operation of switches 638 and 644 is governed by a third S !, control signal appearing on line 654. Analog switch 636 ,j may, for example, comprise semiconductor chip number 4066B.
~! Upon receipt o~ a first control si~nal on line 650, sw~tch 640 is closed providing input 602 of video modulation ,~ chip 600 with a video signal from line 512 while input 604 ,~ is provided with a bias determined ~y the ~oltage drop across resistor 649. This bias i~ selected to result in a normal mcdulated televiQion signal senerated by chip 600 responsive to the video signal Appearing at terminal 602 and . the audio signal appearing at 604.
However, upon receipt of a second control signal on line 652 which closes switch 642, switch 640 is opened and the video from line $R is applied to second terminal 604 of chip 600 and terminal 602 is provided a bias determined by the setting of the pick-off point of.resistor 603 which . creates a reference differential between input 602 and 604 il which ~s equal in magnitude snd opposite in polarity to the .;
;; differential created upon receipt of the f~rst control .j s~gnal on line 650. This new blas and change of video input ' on pins 602 and 604 results in a modulated television ;j signal at the output of chip 600 in which the video portion 1 is înverted.

.
., ,~
!l ,, -- 4 2 .; I

11508~9 , .
~; Upon receipt of ~ third control ~ignal on line 654, switches 638 and 644 are closed, sw~tch 642 is opened and Il switch 640 is closed. Closure of sw~tch 638 causes a bias ¦¦ to appear at pin 604 equal to the voltage drop across a S , portion of resistor 646 and across the whole of resistor 649 i! Th~ s ~ias results in an increase in the level of the video j port~on of the modulated television signal generated by chip 600 which increase is designed ~y setting a variable resistor ~! 649 to precisely offset the amount of suppre sion introduced ~ by the encoder to randomly selected horizontal ~lan~ing pulses. In addltion, upon receipt of the third control signal on line 654, closure of switch 644 generates a bias signal from resistor 656 to automatic gain control 508.
, Thus, if the third control signal is received on line 654 during the initial or front porch portion of a suppressed horizontal synchronization pulse, the signal to automatic ' ! gain control 508 from resistor 656 will assure that the ! automatic gain control will re~ia~ the suppressed horizontal blan~ing pulse to a normal blan~ing pulse level thereby ,~ allowing for normal operation of the automatic gain control. 'i Generation of first, second and third control signals on lines 650, 6S2 and 6S4 is achieved by operation of inverter ! 660, NAND Gate 664, and NOR gates 666, 668, 672, and 674. Invert~
Il 660 is coupled to receive horizontal flyback pulses from 1¦ timing network 526 of Fig. 10, one input of NO~ gate 666 is `
!i designed to receive a synch compare signal from synch ga~e ! 528 of Fig. 10, one input of NAND gate 664 is designed to .

~" ll _43 -1150~19 ! receive a vertical interval s~gnal from timing network 526 ¦ of Fig. 10, and the other input of NAND 664 is des~igned to ! receive a video compare signal from ~ideo gate 530 of Fig.
¦ 10. ~he output of inverter 660 is coupled to a second input ~ of NOR gate 666, and to both inputs of NOR gate 668. The ! output of NAND gate 664 is coupled to the first input of NOR
,I gate 672. The output of NOR gate 668 is coupled to a second input of NOR gate 672. The output of NOR gate 672 is coupled ,I to both inputs of NOR gate 674.
~i As will be explained in detail below, the horizontal flyback pulses delivered to the inpu~ of inverter 660 go positive slightly after the initiation of each horizontal blanking pulse of a field and remain positive for the I duration of each horizontal blanking pulse. The vertical interval signal appearing at the first input of N~D gate ,~ 664 is low during each vertical interval. In addition, a synch compare signal is defined as a signal whlch begins during the inital portion or front porch portion of each supp~essed horizontal blanking pulse and continues for the l, durat~on of each such pulse. A video compare signal is ~! defined as a signal which goes positive during a selected ~', ' trace line of each vertical interval wherein the trace line ' is inverted in polar'ity and remains positive for the duration , of the succeeding field.
!l ,1 .i 11 ' I! ,.
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'I In accordance with standard logic, a flrst control t `~'t signal from the output of NOR gate 674 is normally present ~¦ on line 650. A second control signal from the output of Il NOR gate 672 appears during trace lines of a field following 5 l! a vertical interval in which the selected line trace exhibits jl a reverse polarity. A third control signal appears from the ! output of NOR gate 666 following the initial or front porch period of each suppressed horizontal synchronization pulse ,, and continues for the duration of each such pulse. Synch 10 ~¦ and inversion control 520 therefore operates to reestablish the correct polarity of randomly inverted video signals and the correct biasing of randomly selQcted suppressed horizontal ,I blanking pulses and achieves this end without the employment il f any control codes, keying sig~als, or encoding signals 15 j, independent of the actual scrambled video signal itself.
j, Turninq to Fig. 12 there is disclosed a circu$t diagram ' i of one example of synch comparator 524, video comparator , 522, synch gate 528, and video gate 530. ln Fig. 12, synch comparator 524 is shown to comprise resistors 700 and 702 ' and differential amplifier 704. Resistors 700 and 702 are ,¦
'l series-connected between a positive supply of voltage and ¦
ground and their junction point is coupled to the positive input of differential amplifier 704. The negative input of ~, ~ differential amplifier 704 is provid~d with a video signal Ij from line 512 of Fig. 10. The bias provided by resistor 700 ' and 702 is preferably set ~ust above the black level, typically ¦ at approximately 3 1/2 volts. Accordingly, when a suppressed ', ~
.j , :

, _45 _ ~i ~

., ¦ horizontal blanking pulse appears at the negative terminal of amplifier 704, a negative signal is generated at the output whereas, if a normal pedestal~is received, a positive ,l signal is generated at the output of the amplifer 704.
I The output of amplifier 704 is coupled to synch gate ! 528 which in Fig. 12 is illustrated as comprising a flip-flop 706. Specifically, the output of amplifier 704 is I coupled to the data ~nput of flip-flop 706. The cloc~ input `
i¦ f flip-flop 706 is coupled to receive horizontal flySack I pulses from timing network 526 and the set terminal of flip-j' flop 706 is coupled to receive a vertical interval signal 1, from timing network 526. If a negative output is received ! from amplifier 704 at t~e beginning of a horizontal flyback 1 pulse indicating existence of a suppressed amplitude horizontal blanking pulse, a low synch compare signal is generated at 3; . .
the Q output of flip-flop 706. However, in the event of a normal amplitude horizontal blanking pulse be~ng received at the beginning of a horizontal flyback pulse and at all times ,j during the vertical interval, the Q output of flip-flop 706 ' remains high.
i! Video comparator 522 is illustrated in Fig. 12 as co~prising resistors 708 and 710 and differential amplifier ;!
712. Resistors 708 and 710 are coupled in series between a `.
~I positive source of D.C. voltage and ground. The junction of I resistors 708 and 710 is coupled to the posit~ve input of differential amplifier 712. The negative input of amplifier ~! 712 is coupled to receive video from line 512 of F~g. 10.
The bias provided by resistors 708 and 710 is preferably se~

, _ 46 _ :~ " ' ;, ., .

at approximately half way between blacX and white level in a video signal or approximately 37 1/2% amplitude. Typically, ! this level may be in the order of 5 ~/2 voltæ. ~hen the ~¦ video is black or approximately 3 volts, the comparison is S ll positive and a positive output is generated from amplifier 712. However, when the video is white the comparison in negative and a negative output is generated by amplifier 702.
I The output of amplifer 712 is coupled to video gate 530 10 ' whi¢h, in Fig. 12, is illustratively shown to comprise ¦ inverter 714, counter 718, AND gate 720, and flip-flop 722.
,~ The output of amplifier 712 is coupled through inverter 714 il to one input of AND gate 720. Horizontal drive pulses are il defi~ed as with respect to timing network 526 a square wave ~¦ locked to the horizontal synch rate slightly after the ! I beginning of each horizontal blan~ing pulse. These horizontai ''j drive pulses are coupled from timing networ~ 526 to the input of counter 718. The reset of counter 718 is coupled ' to a vertical blanking synch signal ~rom timing network 526 ¦
!¦ which is defined as a signal which goes negative half-way ¦¦ through a vertical synchronization pulse and goes positive ; at the termination of the vertical ~nterval. Counter 718 is therefore reset half way through each vertical synchronization ' pulse and is designed to count horizontal drive pulses until 1 a seiected trace line of the vertical interval is reached.
'j Preferably the selected trace line is the last complete 'I trace line of each vertical interval.

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!' The ou~put of coun~er 718 is coupled to a second input of AND gate 720. The output of AND gate 720 is coupled to I¦ the clock terminal of flip-flip 722.~ AND gate 7ao accordingly il provides to the clock terminal of fliip-flop 722 a positive ,, going signal during the selected trace line of a vertical interval whenever a selected trace line is inverted.
~ The data terminal of flip-flip 722 is coupled to a j constant positive signal source. The reset of flip-flop ¦ 722 is coupled to receive end o~ field pulses from timing '~ network 526 which end of field pulses are designed to occur at the end of each field of the video signal. Since counter 718 can provide a positive input to the AND gate 720 only during the selected line trace of each vertical interval, i flip-flop 722 provides a positive going video compare signal at output terminal Q only when the selected v~deo line trace ' of a vertical interval is inverted. ~he video compar- i ~ignal, as a result of end of field pulses supplied to the , reset terminal of flip-flop 722, continues throughout the subsequent field. .
; In Fig. 13 there is illustrated a circuit diagram of ~l one example of timing network 526. This example of timing network 526 is essentially the same as the example of timing network 116 illustrated in Fig. 9 above. Specifically, ~, timing networ~ 526, as illustrated in Fig. 13, is provided with a video signal on line 800 from antenna 802. The video !
'j signal on lin~ 800 is shown coupled ~o tuner and master ,l oscillator 804. Tuner and master oscillator 804 is ~nown to ., i jl i ' s :, -- 48 --"..... ,,, .

11508~9 ! I .
those skilled in the art as having a standard TV tuner and an internal oscillator which is locked to the horizontal synchronization signals of the recei~ed video signal.
,I Specifically, master oscillator 804 may comprise a Ml Module I of Zenith Corporation which, as was explained above, employs a 503.5 ~Hz master scan oscillator which is phased-locked to , 32 times the horizontal rate of a video signal received by a I tuner section. The output of master scan oscillator 804 ,~ includes an audio signal suitable for use on line S34 of I Fig. 10 and a video signal suitable for use on line 512 of Fig. 10 as is well-known to those skilled in the art. A
, master clock output of oscillator 804 is coupled by line 806 ! to synch signal generator 808. When master oscillator 804 ', is an Ml Module, line 806 is coupled to terminal B4.
I Synch signal generator 808, as is well-known to those ; skilled in the art, provides horizontal drive pulses and i verticle blanking synchronization pulses in response to ; receipt of a master clock signal and a composition synchronizatio~
I signal. Synch signal generator 804 may, as was explained ! above, comprise a Zenith 221-103 chip. A composite synchronization .j signal is provided to synch signal generator 808 from line 810 coupled to master oscillator 804. A composition synchronization signal as explained above merely comprises the horizontal ~' and vertical synchronization signals-from the video s~gnal on line 800. For example, a suitable composite synchronization .I signal can be received from terminal B2 of a Zenith Ml Module as would be perfectly apparent to one sk~lled in this ,l art.

.1.

11508~9 !~ The timing nett~ork illustrated in Fig. 13 further comprises an inverter 812 which corresponds to inverter 410 ~i of Fig. 9, a counter 814 which corre~ponds to counter 412 of ,I Fig. 9, a flip-flop 816 which ~orresponds to flip-flop 408 ,j of Fig. 9, an inverter 818 which corresponds to inverter 414 . of Fig. 9, an integrating network 820 which corresponds to integrating network 418 of Fig. 9, a differential ~mplifier ,l 822 which corresponds to differential amplifier 420 of Fig.
,. 9, flip-flops 824 and 826 which correspond to flip-flops 422 ~, and 424 of Fig. 9, and a counter 828 which corresponds to counter 426 of Fig. 9.
,' Each of the above-identified elements of the timing ' network of Fig. 13 is connected in the same manner as the ~! corresponding element of the timing network in Fig. 9. The : primary difference between these elements reisides in the fact that counter 814 of Fig. 13 is reset to provide an ,. output upon receipt of only five master clock signals to reset flip-flop 816 as oppose,d to the six master clock :¦
~ignals employed in counter 412 to reset flip-flop 408. As'¦
l a result of employing only five master clocX signals, the Q ' output of flip-flop 816, namely flyback pulse-~, is centered on horizontal synchronization signals of the video signal ; and has a duration of only five of the'32 oscillations of'j master oscillator 804 which occur for each video line.
25 ,j Accordingly, the flyback pulses from flip-flop 816 begin ~i just slightly after the beginning of each horizontal blanking . . I

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i pulse and terminate slightly before the ter~ination of each ¦ horizontal blanking pulse. Thus, the horizontal flyback , pulses from flip-flop 816 can be employed, as discussed with ,i respect to Fig. 12, to assure compar~son of the ievel of S ,¦ each horizontal ~lanXing pulse slightly after the beginning ~! f each horizontal blanking pusle, for example, during the ~I front porch of each horizontal blanking pulse.
', The additional outputs of timing network 526 illustrated jl in Fig. 13 include horizontal drive pulses from synch signal i¦ generator 808, vertical blanking synch pulses from synch 'I signal generator 808, end of field pulses from counter 828, and vertical interval signals from the Q output of flip-flop ~1 826. The horizontal drive pulses from sy~ch signal generator ¦ 808 are defined with respect to timing network 526 as a ,~ squarè wave loc~ed to the horizontal synchronization rate I which, because of counter 814 being set to only 5 rat~er -j ! than 6 master clock counts passes from negative to positive at or slightly after the beginning of each horizontal ', blanking pulse. The vertical blanking synchronization pulses from synch signal generator 808 are defined with Il respect t,o timing network 526 the same as with respect to ! timing network 116, namely as a signal which is negative .:
going half-way through the vertical synchronization pulse of !i a video signal and remains negative until termination of the .
il vertical interval signal. The vertical interval signals 'I from flip-flop 826 are the same as the vertical interval jl signals from flip-flop 424 Fig. 9, namely, they are signals .1 ' li .1 . .

51 _ ~o~9 j which are high during the vertical interval and low during I the fields between vertical int~rvals. Finally, the end of i field pulses from the output of counter 828, like counter 426 of Fig. 9, are designed to provide a short end of field ~ pulse at the start of each vertical interval.
i The horizontal drive pulses, horizontal flyback pulses, vertical interval signals, end of field pulses, and vertical blanking synch pulses from timing networ~ of 526 of Fig. 13 l are coupled to synch gate 528 and video gate 530 as illustrated ~1 in Fig. 12 and operate as explained above. Furthermore, the horizontal flyback pulses and vertical interval signals from timing network 526 illustrated in Fig. 13 are coupled to synch and inversion control 520 as illustrated in Fig. 11 , and operate as explained above.
'! The above-described subscription system is uniquely j ~I suitable for use with a standard television transmitter for . ' several reasons. ~irst, no transmitter power reduction is required since the picture video is transmitted at exactly the same level as in normal NTSC transmissions, the only 20 1i difference being that the actual video is sometimes reversed !l to provide the equivalent of a negative lmage, and some horizontal blanking pulses are suppressed preferably ap-~l proximately 6db. Second, no change whatsoever is required ;
ll or desirable in the setting of predistortion circuits of a i! transmitter over that used for standard NTSC transmission.
I Even during horizontal blanking pulse suppression, the pulse Ij ~

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`' 11508~9 is being transmitted in the predistorted and linearized ~, portion of the transmitter characteristic. Accordingly, ~l only one exciter tuned for standard ~TSC transmission is ~ required. All the modifications to the signal are done in ' the video domain and consist of simply a blanking pulse , offset and a signal inversion on a controlled basis. No gain change is introduced into the transmission system at any time. Even the blanking pulse suppression is accomplished ,I with a simple bias level offset, as opposed to gain change, I thereby preserving the transmitted fidelity and linearity of '! the pulse.
In the decoder, the signal is restored to its original state, before modulation onto an output carrier by a series i~ of switching controlled bias changes at a modulator. The ~ decoder simply follows the random suppression format by j ,, sampling each horizontal blanking pulse during the ~front ' ! porch" in order to determine its level. If it is below blanking level, the decoder automatic~lly switches in the , correct bias level to bring the pulse back to its original ~ state. Conversely, if the pulse is at a blanking level, it is deemed normal and no change is required. ~ ¦
Video inversion is accomplished on a random field by !
~i field basis. The decoder simply samples a particular line ~' Il in the vertical interval of each field to determine whether I that line is at the black or white level. If that line is !l I
Il l ., `I
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I _ 53 _ ~ i !

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¦ at the white level, the decoder assumes video ~nversion from ~1 the subsequent field and will invert each active video il portion of every line of the followi~g field. Conversely, ,¦ if the line is at the black level, normal vidso is assumed 5 il and no inversion is required. Thus, the decoder may be said to be format agile in that it changes to suit whatever format is transmitted.
It should be noted that the starting point and reference I for the decoder is the vertical interval in each field i' wherein initial synchronization and timing are established since the format during this interval is always known.
Another important feature of the described system is that, since the decoder is format agile, no signal is required to switch the video from scrambled to standard NTSC broadcast.
~owever, since it is desirable to switch the sound, the j 1 presence of the audio æubcarrier signal will cause the sound to switch from normal base-band audio to subcarr~er audio during scrambled transmission, and can also be used to switch the video scrambling circuits.
2n !' Even though it is possible to alter the video inversion 1 and synchronization suppression formats at random and at any ! '.
order, in practice, standard non-inver~ed video preferably ;
will not be sent unless synchronization suppression is in ' ' effect. This assures that one form of scramblin~ is present at all t1mes.

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_ 54 -,, 1~5V819 "
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The suggested rate of change for video inversion is approximately 3 consecutive but randomly chosen fields of standard or non-inverted video out o~ every 100 fields. The ll~ rate of change for suppressed synchronization should be ~l approximately one field of non-suppressed synchronization, randomly chosen (but never corresponding to a field of non-; in~erted video) out of every 60 fields of suppressed synchronizatiO~
~ No two fields of unsuppressed synchronization should be 1 consecutive. The preferred operational cQmbinat~on will , tend to give the scrambled picture a flashing effect whichis quite annoying. It will also tend to produce the same interruption of the picture for unauthorized or "bootleg decoders" which are not quite sophistic~ated enough to handle the full format agil~ty required in the subject system. The , two interacting forms of scrambling plus the random v~riations ! produce a very effective form of scrambling and produce a high degree of security. ¦
Additional advantages and modifications will readily , occu. to those skilled in the art. The invention in its 20 ll broader aspects is therefore not limited to the specific j details, representative apparatus, ~nd illustrative examples ,I shown and described. ~ccordingly, departures may be made from such details without departing from the spirit or scope of applicant's general inventive concept.

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~' I 55 _ . j

Claims (5)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An encoder for a video signal having fields with horizontal trace lines separated by horizontal blanking pulses having front porches followed by associated horizontal synchronization pulses and the video signal further having vertical intervals separating the fields containing vertical synchronization information followed by horizontal trace lines separated by horizontal blanking pulses, the encoder comprising:
a) first means for randomly inverting the polarity of a video signal by inverting the polarity of a trace line of randomly selected vertical intervals and by inverting the trace lines of associated fields following said randomly selected vertical intervals; and b) second means for suppressing the amplitude of randomly selected horizontal blanking pulses during fields of said video signal while maintaining unaltered the absolute amplitude difference between said horizontal blanking pulses and associated horizontal synchronization pulses.

2. The encoder of claim 1 wherein said first means includes third means for limiting said inverting to only the trace lines of said associated fields.

3. The encoder of claim 1 wherein said second means comprises means for biasing said horizontal blanking pulses to effectively suppress said amplitude of said randomly selected horizontal blanking pulses.

4. The encoder of claim 3 wherein said means for biasing establishes said biasing at a predetermined level and said level is held constant throughout said randomly selected horizontal blanking pulses.

5. The encoder of claim 1 wherein said first means includes a timing network coupled to commence said inverting upon the beginning of the last video line in said vertical intervals and to terminate said inverting upon completion of inverting the last trace line of the field following said vertical intervals.