CA1148247A - Ground fault circuit interrupter with grounded neutral protection - Google Patents
Ground fault circuit interrupter with grounded neutral protectionInfo
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- CA1148247A CA1148247A CA000396020A CA396020A CA1148247A CA 1148247 A CA1148247 A CA 1148247A CA 000396020 A CA000396020 A CA 000396020A CA 396020 A CA396020 A CA 396020A CA 1148247 A CA1148247 A CA 1148247A
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Abstract
46,960 GROUND FAULT CIRCUIT INTERRUPTER WITH
GROUNDED NEUTRAL PROTECTION
ABSTRACT OF THE DISCLOSURE
A ground fault circuit interrupter includes a differential current transformer sensing winding supplying input to an integrator which is reset to zero at the end of each half-cycle of AC line current. A line-to-ground fault current will cause the integrator output to exceed a pre-determined limit value and produce a trip indication. A
saturable neutral transformer supplies a voltage to the neutral line and a reference current proportional to the neutral voltage to a comparator. The peak value of the reference current is compared to the peak value of the sensing winding output. A low resistance neutral-to-ground path causes the sensing winding output to exceed the refer-ence current and a signal to be added to the integrator input, thereby producing a trip indication which energizes an SCR to activate a solenoid. Means are provided to pro-duce a positive feedback signal to insure a "hard" turn-on of the SCR upon receipt of a trip indication, the feedback means also including capability to "remember" a trip indica-tion at the end of a half-cycle near current zero, and to produce the positive feedback signal at the beginning of the next succeeding half cycle.
GROUNDED NEUTRAL PROTECTION
ABSTRACT OF THE DISCLOSURE
A ground fault circuit interrupter includes a differential current transformer sensing winding supplying input to an integrator which is reset to zero at the end of each half-cycle of AC line current. A line-to-ground fault current will cause the integrator output to exceed a pre-determined limit value and produce a trip indication. A
saturable neutral transformer supplies a voltage to the neutral line and a reference current proportional to the neutral voltage to a comparator. The peak value of the reference current is compared to the peak value of the sensing winding output. A low resistance neutral-to-ground path causes the sensing winding output to exceed the refer-ence current and a signal to be added to the integrator input, thereby producing a trip indication which energizes an SCR to activate a solenoid. Means are provided to pro-duce a positive feedback signal to insure a "hard" turn-on of the SCR upon receipt of a trip indication, the feedback means also including capability to "remember" a trip indica-tion at the end of a half-cycle near current zero, and to produce the positive feedback signal at the beginning of the next succeeding half cycle.
Description
BACKGROUND OF THE INVENTION
: The inventlon relates generally to ground fault circuit interrupters and, more particularly, to ground fault circuit interrupters providing protection against grounded - neutral conductors.
Conventional electrical circuits such as fuses and ,. ) , 46,~
3~ 7 circuit breakers protect circuit conductors from thermal damage due to severe overload currents, thereby greatly reducing the danger of fire and explosion. However, such conventional circuit interrupters do not eliminate the danger of electrical shock to a person accidentally coming into simultaneous contact with a live conductor and an object at ground potential. The resulting current flow through the person, while only a fraction of an ampere, can cause serious in~ury or death.
Ground fault circuit interrupters (hereinafter referred to as GFCI r S ) combine the capabilities of conven-tional circuit breakers with sensitive means for detecting current flow between line conductors and ground at current levels much below the overload current levels required to trip conventional circuit breakers. Upon detection of such a ground fault current the contacts of the GFCI are opened to deenergize the circuit.
A differential current transformer is normally used to sense these ground fault currents, the transformer having as its primary windlngs the conductors of the dis-tribution s~stem being protected. During normal conditions, all current flowing in one direction through one of the con-ductors will return in the opposite direction on another of the conductors, thus producing a net current flow of zero through the transformer. However, if a fault (that is, a leakage path) is established between one of the conductors and ground, return current will bypass the transformer and flow through the ground back to the grounded side of the source supplying the circuit. Thus, more current will be ~lowing in one direction through the transformer than through '~6, g~
8~4~7 the other, producing a current imbalance.
A sensing winding detects this imbalance and provides an output signal used in various ways for the common purpose of tripping a clrcuit breaker mechanism when the sensed signal is of sufficient magnitude. One method of utilizing the signal of the sensing winding to produce a trip indication is described in U.S. Patent No. 3,852,642 ~G~s~ f~ issued December 3, 1974 to the present inventor and others and assigned to the assignee of the present invention. The device disclosed therein responds primarily in accordance- with the peak value of the sensing winding signal.
Such circuits resulted in generally satisfactory operation. However, performance standards for GFCI's as established by Underwriter's Laboratories have been in-creased to specify a trip level of 5ma. ~ 20% for all ambi-ent and load conditions. The trip levels of some prior art GFCI's were dependent upon normal load currents to the extent that the tightened specifications resulted in an increase in unnecessary trip lndications, often referred to as "nuisance tripping". It is believed that this effect is caused primarily by a false output from the differential current transformer at a frequency equal to twice the line voltage frequency; that is, 120 Hz on a 60 Hz system. The false 120 Hz output, when added to the actual 60 Hz output, results in a composite output current the peak value of hich is a runction of load current. This false output is believed to be caused by stray magnetic fields existing in the vicinity of the current transformer caused by difficult to control ~ariables such as the exact location of current ~ 7 4~
carrying conductors near the trarlsformer within the circuit breaker, input offset voltage for the sense amplifier, residual flux in the core, and others. A direct solution to this problem would include shielding the transformer and using more symmetrical lead routing. Unfortunately, the size and space restrictions within the housings of GFCI's do not always permit such shielding, and the conductor loca-tions are dictated by manufacturing considerations.
A method for alleviating the problems caused by 120 Hz false current is to make the trip indication depend-ent upon an integral of the current transformer output. An eYample of this approach is the device described in U.S.
Patent No. 3,953,767 (-~&~s-~f~ issued April 27, 1976 to Ahmed. This device sums the sensed signal over a period of at least a full cycle of line voltage primarily for the purpose of distinguishing between resistive ground faults and capacitive ground faults. This has the incidental benefit of reducing any 120 Hz signal which may be present, ; since over each half cycle of power line frequency the integral of a 120 Hz will be zero.
There are, however, other requirements for a commercially practical GFCI. Underwriter's Laboratories specifies that a GFCI must also trip upon occurrence of a low-impedance leaka~e path from the neutral conductor to ground. Such a path on the load side of the differential current transformer does not in itself produce a shock hazard; however, the occurrence of a grounded neutral at the same time as a ground fault on a line conductor will cause the GFCI to be less sensitive in detecting ground fault current from the line conductor.
r~4~ 6 ~ ~60 ~ rarious means have been successfull~ emplo~yed to detect a grounded neu~ral conductor, including the device described in U.S. Patent 3,959,693 issued ~ay 25, 1976 to Coley and Misencik and assigned to the assignee of the present invention. The device disclosed therein employs an additional transformer having a primary winding con-nected bet~teen the line and neutral conductors, with the neutral conductor serving as a secondary ~nding. The core of this neutral transformer is designed to saturate early in each half cycle of the power line frequency. m e transformer thus induces a voltage pulse on the neutral conductor on each half cycle, producing a current flo~r on the neutral conductor if there is a path from it to ground near the load. Since this current returns through the ground3 a current imbalance will result ~rhich ~11 be de-tected in a manner similar to a ground fault by the differ-ential current transformer to produce an output from the sense ~rinding.
Another means for detecting a grounded neutral conductor employs a pulse generator inducing high frequency voltage pulses upon the neutral conductor. This method is described in U.S. Patent No. 3,611,035 issued October 12, 1971 to Douglas.
` Both of the foregoing techniques are generally effective to detect leakage paths from neutral ~o ground.
Ho~iever, both produce a ground current having a fairly large peak value but a very limited average value over one cycle of the polrer line frequency. Thus, these techniques as previously utilized are not directly applicable to apparatus employing an integration technique~ such as the device described in the a~orementioned U.S. Patent No 3,9~3,767, since the pulses provided by the grounded neutral detection system would be cancelled by integration.
A ground fault detection system providing grounded neutral protection and utilizing an integrator is described in U.S. Patent No, 3,963,963 tCla~s ~17/'~D) issued June 15, 1976 to Schade. This system employs two synchronous switches, one operating at line frequency and the other operating at the frequency of the oscillator generating the neutral conductor pulses, to activate the integrator only at such time as the positive neutral pulses are occurring. Various problems still remain, however~ such as the dependence of trip level on load current.
It would be desirable to provide a GFCI having grounded neutral protection whlch meets current Underwriter's Laboratories requirements as established in Bulletin 943 which call for a 5ma. trip level + 20%. In addition, the device must be sufficiently compact to ~it in existing circuit interrupter housings and must minimize the volume and number of parts required. It would be especially desir-able to provide a ~FCI which can be adapted for operation using an integrated circuit.
SUMMARY OF THE I~ENTION
-In accordance with a preferred embodiment of the present invention there is provided ground fault protective apparatus for use on an AC electrical circuit having a line conductor and a neutral conductor. The apparatus comprises means for sensing current imbalance on the conductors and for providing an output signal proportional to the current imbalance. Means are also provided for integrating the ~8~2~7 output signal o~rer a period of one half cycle of li-ne current and for providing a trip indication whenever the signal integration exceeds a predetermined reference.
Grounded neutral detection capability is provided by a saturable transformer inducing a test voltage on the neutral conductor to produce a current irnbalance between the line and neutral conductors which is proportional to the neutral to ground resistance. The transforrner also provides a reference current proportional to the neutral conductor test voltage. This reference current is compared to the output of the sensing means and supplies a signal current to the input of the integrator whenever the output of the sensing means rises above the reference current, indicating a low resistance neutral-to-ground path. The amplitude of this signal current is sufficient to cause the integrator to rise above the trip current level bef`ore the end of the present half cycle, thereby producing a trip indication.
An SCR is responsive to the trip indication to energize a solenoid, thereby operating the circuit breaker contacts to deenergize the circuit being protected. Means responsive to the trip indication of the integrator are provided to supply a feedback signal to the input of the integrator which is additive to the output signal of the sensing means. This feedback signal is of sufficient magni-tude to cause a trip indication, thereby providing~a "hard"
turn-on for the SCR. In addition, a memory circuit respon-sive to a trip indication is provided, so that a trip indi-cation which is produced at the end of a half cycle near current zero (during which time the SCR may not be acti-vated~ ,lill result in a trip indication being generated ~ '7 ~6~g~
early in the next succeed;ng half cycle during 7,Jhich t~neSCR turn-on is insured.
BRIEF DESCRIPTION OF THE DRAl,'~NG
Figure 1 is a functional block diagram of a ground ~ault circuit interrupter constructed in accordance ~Jith the present invention;
Figure 2 is a set of curves showing wave forms pertinent to the operation of the apparatus shown in Figures . 1 and 3-5;
Figure 3 is a detailed schematic diagram of the present invention in accordance ~th one speclfic embodi-ment;
Figure 4 ls a schematic diagram of the present invention as embodied in a receptacle; and Figure 5 is a schematic diagrams of the large-scale integrated circult device of Figs~ 3 and DESCRIPTION OF THE P~EFERRED EMBODIMENT
A GFCI constructed according to the teachings of the present in~ention is shown in Figure lo A line conduc-tor 10 and neutral conductor 12 pass through a differentialcurrent transformer lgo The neutral conductor 12 is grounded at the point 16. A sensing l~nding 22 provides input iin to an amplifier 30 hav~ng t~ro outputs, the first of which ~ iin, is supplied through a summer 42 to an integrator 36. The integrator 36 i5 reset at the end of each half cycle of line voltage by the lead 4~. The output of the integrator 36 is fed to a comparator 1~6 which compares the integrator output to a reference 47 (the value Or which is speci~ied by the desired tripping current level) and supplies a signal through anti phasing circuitry 50 (to be more completely described 7 ~7960 hereina~ter) to a silicon controlled rect~fier ~SCR) 52 which controls a solenoid 24 and interrupter contacts 26.
Upon occu~rence o~ a ground ~ault between ~he conductor 10 and ground, as at 28, a portion of the current flowlng from the ~ource through conductors 10 and 12 wlll re~urn to the source throu~h the ground and wlll not pass through the tr~nsformer 18. A current ~mbal~nce thus occ~rs between the conductors 10 and 12 producing an output signal iin from the ~ensi~g w~nding 22. mis sign~l is amplified by ~he amplifier 30 and supplied through the summer 42 to the integrator 36. Ground fault current above the predeter-mlned tripping current l~vel wlll cause the ou~put of the lntegrator 36 to rise above the re~erence a~ supplied by 47 to activate the SCR 52, th~reby energizing the solenoid 24 and the contacts 26 to interrupt current flow through the load 14.
Detect~on of low resistance paths between the neutral conductor 12 and ground i8 prov~ded by a saturable transformer 54 as is described in the aforementioned U.S.
Patent No. 3,959, 693. m e trans~ormer 54 has a primary ~nding connected between the llne conductor 10 and the neutral oonductor 12, and has the neutral conductor 12 serving a~ a secondary winding. The core of the tr~nsformer 54 is de~igned to ~aturate wlthin a brief portion of each half cycle of power line frequency~ Until ~aturation, the tr~ns~ormer induces a voltage pul~e VN on the neutral con-ductor 12 which will, under normal conditlons, result in no current n ow since no complete c1rcuit exists. Howevert if there i8 a low resi~tance path to ground from the neutral conductor near the load, the voltage will cause an imbal-_9_ ,.. .
4~,g6~
anced current detectable by the differential curren~ tran~-former 18. Such a path is indicated at 48 and ~ill result in current flow in the circuit de~ined by ~he conductor 12, the ground path 48, the ground 49 ltself, and the ground connection 16. The current pulse so produced, while hav~ng a relatively high peak value, has a very low avsrage value.
Thus, in the prior art such a current pulse was not easily detected ~y integration7 especially over a perisd a~ short as sne hal~ a cycle.
Since ~ntegration over a hali cycle wlth a reset pulse occurring at the end th~reo~ ls desira~le~ additional mean3 are prov~ded in the present inventlon to detect low resi~tance neutral-to-ground paths. Speci~ically, mean~ 57 produce a re~erence current which i~ proportlonal to the voltage induced upon the neut~al conductor 12. This re~-erence current (indicated ln Figures 1 and 2 by ire~) ls supplied to a comparator 58. The ampl~fier 30~ in addition to supplying the ou~put ~i~n to the summer 42, produces a ~econd output Kiin which is suppl-ied to the comparator 58.
The peak value~ of Kiin and ire~ ar~ coDpared to establi~h the Yalue o~ output current iad~ ~hich is supplied to the summer 42. The summation i~um of curr~nts ~iin and iadd~
i~ ~hen ~upplled to the lntegrator~ During normal condi-tions ha~ing no low resist~nce neutral-to-ground path~, iref i~ 8reater than Kiin, the ~alue of iadd is , sum iin. I~ a path such as is indicated at 48 should occur, howe~er, the re~ulting current imbalance will be detected by ~he sen~ing windlng 22 and ~lif~ed by the amplifier ~0 to produce a larger value o~ Kiin. This value will be greater th~n iref and will produce a value of iadd equal to Kiin, 4 ~
and a value of iSum equal to ~iin plus Kiin. This input tc the integrator 36 is sufficient to raise the integrator output above the value produced by reference 47, thereby producing a t,rip indication. Thus, neutral-to-ground paths are detected by combining a peak sensing function performed at the comparator 58 with an integration function performed by the integrator 36 to provide adequate sensitivity to trip upon low resistance neutral-to-ground paths.
For ground fault currents just slightly above the the trip level~ the output of the integrator 36 will rise above the reference level at the end of the half cycle.
Unfortunately, the instantaneous value of line voltage at this time in the cycle may ~e too small to trip the solenoid 24 when the SCR 52 is triggered. Since the integrator is reset at the end of a half cycle and will start out from zero at the beginning of the next half cycle, the possibil-ity exists that a trip indication toward the end of the half cycle will be lost.
This possibility is eliminated by means of an ; 20 anti-phasing system indicated at 50. The trlp output of the , comparator 46 is fed to the system 50 which contains a capacitive "memory". The capacitor "remembers" that it had received a trip signal at the end of the preceding half cycle and produces positive feedback current (indicated by the path 51 of Figure 1) to the input amplifier 3,0 early in the half cycle succeeding the trip condition~ thereby produc-ing a large value of ~iin which is processed by the integra-tor 36 to quickly produce a trip indication early in the half cycle and energize the solenoid 24 to separate the contacts 26. The positive feedback thus produces a latching ~ ~ 8 2 ~ 7 l~h, g6~
type turn-on function ~Jhich eliminates the phasing problem, In addition, the latching process coupled ~th other circult features to be hereinafter described make~ it possible to operate the circuit at a line voltage of as low as 50 volts AC, The TEST button operates by deliberately establish-ing a ground fault current of a known le~rel between the line conductor and ground through resistor ~6. If the apparatus is operating properly9 a trip action ~nll occur.
Operation of ~he apparatus of Figure 1 m~y be more clearly understood by reference to the waveforms of Figure 2.
'~aveform A of Figure 2 sho~Js the voltage VLN between the line conductor 10 and the neutral conductor 120 Also sho~m is the voltage VN produced by the neutral transformer 54 on the neutral conductor 12~ As can be seen, the neutral voltage is a short pulse due to the saturating properties of the transformer 5~g A reference current ire~ is produced by the circuit 57 and has a peak value proportion.~l to the neutral voltage VN~ The edges of the current pulse iref have been shaped as shown in waveform B to provide more consistent op-eration., The value of Kiin generated by normal leakage conditions belo~r the ground f~ult trip level is sho~Jn in aveform C of Figure 2. Superimposed upon this current is the neutral reference current iref . Since Kiin,is less than iref~ iadd equals zero and iSum equals cc iin~ It can be seen in wa~reform D that the integrator output produced by this normal line-to-ground current over the period of one half cycle is less than the trlp cu~rent level. Also, the action of the reset signal upon the integrator 36 is sho~m in ~aveform ~ as it ~ '7 k6,9~
reduces the value of the integral to zero just prior to the end of the half cycle.
The value of Kiin generated by normal neutral-to-ground current is shown in ~aveform E of F~gure 2. It can be seen that during normal operation, this value of Kiin is also less than the peak value of the neutral reference current iref. Thus, iadd equals zero9 iSum equals c~ i~n~ and the output of the integrator 36 remains below the tripping cur-rent level as sho~m in waveform F~
Upon occurrence of a fault bet~een the line con-ductor 10 and ground7 as at 2~ of Figure 19 a current im~
balance is produced between the conductors 10 and 12 result-ing in a higher output from the sensing winding 22~ Under these conditions the peak value of Kiin may or may not be greater than iref However~ the value of~ n alone is sufficient to cause trip indication as shown in waveform H
of Figure 2, wherein it can be seen that the ~alue of the integral rises to the trip level befora the end of the half cycle. Thus, the solenoid 2~ will be activated to separate the contacts 26 and de-energize the load 1~. .
A low resistance neutral-to-ground path 4~ (Figure 1) results in a neutral-to-ground current producing an output Kiin from amplifier 30. Since Kiin is greater than the ~eutral reference current iref (waveform I), a value of iadd equal ko Kiin is added to ~ iin, producing an inte~
grator output as sho~ in waveform J. This out~ut rapidly rises above the trip level to produce a tripping operation as described above~
An electronic circuit embodying the principals of the present invention is sho~m schematically in Figure 3, ~ ,, 46,960 and will be described in sections.
BREAKER CIRCUIT
The breaker version of the present invention is shown in Figure 3. As can be seen, the main circuit element is an integrated circuit, or chip 75, the internal design details of which will be discussed in the following sec-tions. At this tlme it will be treated as a simple seven terminal circuit element.
The chip 75 ~s powered by a ~e dropping resis-tor, R4, which supplies a nearly sinusoidal bias current ofslightly more than 2 ma RMS from the 120V ac supply. The bias resistor dissipates 0.15 watts at 132V ac line voltage.
The voltage from B to GND is a square wave with a value of 14 volts during the positive half cycle of the supply and 0 volts during the negative half cycle. The chip can function only when the B terminal is positive, and thus the unit operates in a half wave manner. -`
The secondary winding 22 of the differential current transformer 18 is connected directly to the IN.
terminal. The polarity is such that normal line-to-ground current produces a current iin out of the IN terminal. The chip 75, by means of internal voltage feedback, maintains the IN terminal near virtual ground. The capacitor C2 is used as an RF filter.
The current flow out of the IN terminal flows from the B supply throv.gh C3 into the CAP termlnal. The voltage drop across C3 thus represents the integral of the current lin. At th~ end of the positive half cycle the voltage at the B terminal drops below lll volts which energizes cir-cuitry within the chip 75 to reset the capacitor C3 to zero.
--11~--7 '9 At the beginn~ng OI the next positive half cycle the reset circuit is turned oî~, and the capacitor C3 starts to be charged again. me voltage across the capacitor C3 at t~e en~ of each cycle thus represents the half cycle integral o~
the current iin wh~ch is proportional to half cycle average current of the 60 Hz ground current.
A voltage comparator on the chip 75 co~pares the voltage across C~ to a voll;age refere~ce OI about 1.6 volts.
When the capacltor voltage exceeds the reIerence7 current begins to flow ~rom the OUT terminal ~nto t~e capaoitor C4.
An exte~nal resistor R3 can ~e used to ad~ust the reIerenc~
voltage to calibrate the circuit. Inte~al posit~ve feed-back on the chip 75 produces rapid char~ng of ~3 which cause~ C4 to charge to the gate conductlon voltage of the SCR 52, t;uxning on the SCR~
For ground currents which barely exceed ~he trip level, the 5CR turn~ on at the e2~d OI th~ half cycle.
Capacitsr C4 i~ the memory element OI the '1anti-phaslng'l circuit 50~ me capacitor C4 retains its charge during the next negati~re hal~ cycle of the llne voltage ~o that the positlve ~eedback circu~t is still energized at the begin-nlng o~ the next positive hal~ cycle. The SCR is thus turned on hard at the ~eginning o~ the cycle eliminatlng phas$ng problems ~nd po~sible sole~oid "chattering"~ This feature makes it possible for the circuit to ~unction nor-m~lly with a llne vcltage a~ low as 50 volts RMS. Another important function o~ the gate capacitor C4 i~ to provide a low ac gate-to-cathode impedance which greatly improves the d~/dt capability of the SCR.
A neutral-to-ground resistance oi less than ~ 7 l~67960
: The inventlon relates generally to ground fault circuit interrupters and, more particularly, to ground fault circuit interrupters providing protection against grounded - neutral conductors.
Conventional electrical circuits such as fuses and ,. ) , 46,~
3~ 7 circuit breakers protect circuit conductors from thermal damage due to severe overload currents, thereby greatly reducing the danger of fire and explosion. However, such conventional circuit interrupters do not eliminate the danger of electrical shock to a person accidentally coming into simultaneous contact with a live conductor and an object at ground potential. The resulting current flow through the person, while only a fraction of an ampere, can cause serious in~ury or death.
Ground fault circuit interrupters (hereinafter referred to as GFCI r S ) combine the capabilities of conven-tional circuit breakers with sensitive means for detecting current flow between line conductors and ground at current levels much below the overload current levels required to trip conventional circuit breakers. Upon detection of such a ground fault current the contacts of the GFCI are opened to deenergize the circuit.
A differential current transformer is normally used to sense these ground fault currents, the transformer having as its primary windlngs the conductors of the dis-tribution s~stem being protected. During normal conditions, all current flowing in one direction through one of the con-ductors will return in the opposite direction on another of the conductors, thus producing a net current flow of zero through the transformer. However, if a fault (that is, a leakage path) is established between one of the conductors and ground, return current will bypass the transformer and flow through the ground back to the grounded side of the source supplying the circuit. Thus, more current will be ~lowing in one direction through the transformer than through '~6, g~
8~4~7 the other, producing a current imbalance.
A sensing winding detects this imbalance and provides an output signal used in various ways for the common purpose of tripping a clrcuit breaker mechanism when the sensed signal is of sufficient magnitude. One method of utilizing the signal of the sensing winding to produce a trip indication is described in U.S. Patent No. 3,852,642 ~G~s~ f~ issued December 3, 1974 to the present inventor and others and assigned to the assignee of the present invention. The device disclosed therein responds primarily in accordance- with the peak value of the sensing winding signal.
Such circuits resulted in generally satisfactory operation. However, performance standards for GFCI's as established by Underwriter's Laboratories have been in-creased to specify a trip level of 5ma. ~ 20% for all ambi-ent and load conditions. The trip levels of some prior art GFCI's were dependent upon normal load currents to the extent that the tightened specifications resulted in an increase in unnecessary trip lndications, often referred to as "nuisance tripping". It is believed that this effect is caused primarily by a false output from the differential current transformer at a frequency equal to twice the line voltage frequency; that is, 120 Hz on a 60 Hz system. The false 120 Hz output, when added to the actual 60 Hz output, results in a composite output current the peak value of hich is a runction of load current. This false output is believed to be caused by stray magnetic fields existing in the vicinity of the current transformer caused by difficult to control ~ariables such as the exact location of current ~ 7 4~
carrying conductors near the trarlsformer within the circuit breaker, input offset voltage for the sense amplifier, residual flux in the core, and others. A direct solution to this problem would include shielding the transformer and using more symmetrical lead routing. Unfortunately, the size and space restrictions within the housings of GFCI's do not always permit such shielding, and the conductor loca-tions are dictated by manufacturing considerations.
A method for alleviating the problems caused by 120 Hz false current is to make the trip indication depend-ent upon an integral of the current transformer output. An eYample of this approach is the device described in U.S.
Patent No. 3,953,767 (-~&~s-~f~ issued April 27, 1976 to Ahmed. This device sums the sensed signal over a period of at least a full cycle of line voltage primarily for the purpose of distinguishing between resistive ground faults and capacitive ground faults. This has the incidental benefit of reducing any 120 Hz signal which may be present, ; since over each half cycle of power line frequency the integral of a 120 Hz will be zero.
There are, however, other requirements for a commercially practical GFCI. Underwriter's Laboratories specifies that a GFCI must also trip upon occurrence of a low-impedance leaka~e path from the neutral conductor to ground. Such a path on the load side of the differential current transformer does not in itself produce a shock hazard; however, the occurrence of a grounded neutral at the same time as a ground fault on a line conductor will cause the GFCI to be less sensitive in detecting ground fault current from the line conductor.
r~4~ 6 ~ ~60 ~ rarious means have been successfull~ emplo~yed to detect a grounded neu~ral conductor, including the device described in U.S. Patent 3,959,693 issued ~ay 25, 1976 to Coley and Misencik and assigned to the assignee of the present invention. The device disclosed therein employs an additional transformer having a primary winding con-nected bet~teen the line and neutral conductors, with the neutral conductor serving as a secondary ~nding. The core of this neutral transformer is designed to saturate early in each half cycle of the power line frequency. m e transformer thus induces a voltage pulse on the neutral conductor on each half cycle, producing a current flo~r on the neutral conductor if there is a path from it to ground near the load. Since this current returns through the ground3 a current imbalance will result ~rhich ~11 be de-tected in a manner similar to a ground fault by the differ-ential current transformer to produce an output from the sense ~rinding.
Another means for detecting a grounded neutral conductor employs a pulse generator inducing high frequency voltage pulses upon the neutral conductor. This method is described in U.S. Patent No. 3,611,035 issued October 12, 1971 to Douglas.
` Both of the foregoing techniques are generally effective to detect leakage paths from neutral ~o ground.
Ho~iever, both produce a ground current having a fairly large peak value but a very limited average value over one cycle of the polrer line frequency. Thus, these techniques as previously utilized are not directly applicable to apparatus employing an integration technique~ such as the device described in the a~orementioned U.S. Patent No 3,9~3,767, since the pulses provided by the grounded neutral detection system would be cancelled by integration.
A ground fault detection system providing grounded neutral protection and utilizing an integrator is described in U.S. Patent No, 3,963,963 tCla~s ~17/'~D) issued June 15, 1976 to Schade. This system employs two synchronous switches, one operating at line frequency and the other operating at the frequency of the oscillator generating the neutral conductor pulses, to activate the integrator only at such time as the positive neutral pulses are occurring. Various problems still remain, however~ such as the dependence of trip level on load current.
It would be desirable to provide a GFCI having grounded neutral protection whlch meets current Underwriter's Laboratories requirements as established in Bulletin 943 which call for a 5ma. trip level + 20%. In addition, the device must be sufficiently compact to ~it in existing circuit interrupter housings and must minimize the volume and number of parts required. It would be especially desir-able to provide a ~FCI which can be adapted for operation using an integrated circuit.
SUMMARY OF THE I~ENTION
-In accordance with a preferred embodiment of the present invention there is provided ground fault protective apparatus for use on an AC electrical circuit having a line conductor and a neutral conductor. The apparatus comprises means for sensing current imbalance on the conductors and for providing an output signal proportional to the current imbalance. Means are also provided for integrating the ~8~2~7 output signal o~rer a period of one half cycle of li-ne current and for providing a trip indication whenever the signal integration exceeds a predetermined reference.
Grounded neutral detection capability is provided by a saturable transformer inducing a test voltage on the neutral conductor to produce a current irnbalance between the line and neutral conductors which is proportional to the neutral to ground resistance. The transforrner also provides a reference current proportional to the neutral conductor test voltage. This reference current is compared to the output of the sensing means and supplies a signal current to the input of the integrator whenever the output of the sensing means rises above the reference current, indicating a low resistance neutral-to-ground path. The amplitude of this signal current is sufficient to cause the integrator to rise above the trip current level bef`ore the end of the present half cycle, thereby producing a trip indication.
An SCR is responsive to the trip indication to energize a solenoid, thereby operating the circuit breaker contacts to deenergize the circuit being protected. Means responsive to the trip indication of the integrator are provided to supply a feedback signal to the input of the integrator which is additive to the output signal of the sensing means. This feedback signal is of sufficient magni-tude to cause a trip indication, thereby providing~a "hard"
turn-on for the SCR. In addition, a memory circuit respon-sive to a trip indication is provided, so that a trip indi-cation which is produced at the end of a half cycle near current zero (during which time the SCR may not be acti-vated~ ,lill result in a trip indication being generated ~ '7 ~6~g~
early in the next succeed;ng half cycle during 7,Jhich t~neSCR turn-on is insured.
BRIEF DESCRIPTION OF THE DRAl,'~NG
Figure 1 is a functional block diagram of a ground ~ault circuit interrupter constructed in accordance ~Jith the present invention;
Figure 2 is a set of curves showing wave forms pertinent to the operation of the apparatus shown in Figures . 1 and 3-5;
Figure 3 is a detailed schematic diagram of the present invention in accordance ~th one speclfic embodi-ment;
Figure 4 ls a schematic diagram of the present invention as embodied in a receptacle; and Figure 5 is a schematic diagrams of the large-scale integrated circult device of Figs~ 3 and DESCRIPTION OF THE P~EFERRED EMBODIMENT
A GFCI constructed according to the teachings of the present in~ention is shown in Figure lo A line conduc-tor 10 and neutral conductor 12 pass through a differentialcurrent transformer lgo The neutral conductor 12 is grounded at the point 16. A sensing l~nding 22 provides input iin to an amplifier 30 hav~ng t~ro outputs, the first of which ~ iin, is supplied through a summer 42 to an integrator 36. The integrator 36 i5 reset at the end of each half cycle of line voltage by the lead 4~. The output of the integrator 36 is fed to a comparator 1~6 which compares the integrator output to a reference 47 (the value Or which is speci~ied by the desired tripping current level) and supplies a signal through anti phasing circuitry 50 (to be more completely described 7 ~7960 hereina~ter) to a silicon controlled rect~fier ~SCR) 52 which controls a solenoid 24 and interrupter contacts 26.
Upon occu~rence o~ a ground ~ault between ~he conductor 10 and ground, as at 28, a portion of the current flowlng from the ~ource through conductors 10 and 12 wlll re~urn to the source throu~h the ground and wlll not pass through the tr~nsformer 18. A current ~mbal~nce thus occ~rs between the conductors 10 and 12 producing an output signal iin from the ~ensi~g w~nding 22. mis sign~l is amplified by ~he amplifier 30 and supplied through the summer 42 to the integrator 36. Ground fault current above the predeter-mlned tripping current l~vel wlll cause the ou~put of the lntegrator 36 to rise above the re~erence a~ supplied by 47 to activate the SCR 52, th~reby energizing the solenoid 24 and the contacts 26 to interrupt current flow through the load 14.
Detect~on of low resistance paths between the neutral conductor 12 and ground i8 prov~ded by a saturable transformer 54 as is described in the aforementioned U.S.
Patent No. 3,959, 693. m e trans~ormer 54 has a primary ~nding connected between the llne conductor 10 and the neutral oonductor 12, and has the neutral conductor 12 serving a~ a secondary winding. The core of the tr~nsformer 54 is de~igned to ~aturate wlthin a brief portion of each half cycle of power line frequency~ Until ~aturation, the tr~ns~ormer induces a voltage pul~e VN on the neutral con-ductor 12 which will, under normal conditlons, result in no current n ow since no complete c1rcuit exists. Howevert if there i8 a low resi~tance path to ground from the neutral conductor near the load, the voltage will cause an imbal-_9_ ,.. .
4~,g6~
anced current detectable by the differential curren~ tran~-former 18. Such a path is indicated at 48 and ~ill result in current flow in the circuit de~ined by ~he conductor 12, the ground path 48, the ground 49 ltself, and the ground connection 16. The current pulse so produced, while hav~ng a relatively high peak value, has a very low avsrage value.
Thus, in the prior art such a current pulse was not easily detected ~y integration7 especially over a perisd a~ short as sne hal~ a cycle.
Since ~ntegration over a hali cycle wlth a reset pulse occurring at the end th~reo~ ls desira~le~ additional mean3 are prov~ded in the present inventlon to detect low resi~tance neutral-to-ground paths. Speci~ically, mean~ 57 produce a re~erence current which i~ proportlonal to the voltage induced upon the neut~al conductor 12. This re~-erence current (indicated ln Figures 1 and 2 by ire~) ls supplied to a comparator 58. The ampl~fier 30~ in addition to supplying the ou~put ~i~n to the summer 42, produces a ~econd output Kiin which is suppl-ied to the comparator 58.
The peak value~ of Kiin and ire~ ar~ coDpared to establi~h the Yalue o~ output current iad~ ~hich is supplied to the summer 42. The summation i~um of curr~nts ~iin and iadd~
i~ ~hen ~upplled to the lntegrator~ During normal condi-tions ha~ing no low resist~nce neutral-to-ground path~, iref i~ 8reater than Kiin, the ~alue of iadd is , sum iin. I~ a path such as is indicated at 48 should occur, howe~er, the re~ulting current imbalance will be detected by ~he sen~ing windlng 22 and ~lif~ed by the amplifier ~0 to produce a larger value o~ Kiin. This value will be greater th~n iref and will produce a value of iadd equal to Kiin, 4 ~
and a value of iSum equal to ~iin plus Kiin. This input tc the integrator 36 is sufficient to raise the integrator output above the value produced by reference 47, thereby producing a t,rip indication. Thus, neutral-to-ground paths are detected by combining a peak sensing function performed at the comparator 58 with an integration function performed by the integrator 36 to provide adequate sensitivity to trip upon low resistance neutral-to-ground paths.
For ground fault currents just slightly above the the trip level~ the output of the integrator 36 will rise above the reference level at the end of the half cycle.
Unfortunately, the instantaneous value of line voltage at this time in the cycle may ~e too small to trip the solenoid 24 when the SCR 52 is triggered. Since the integrator is reset at the end of a half cycle and will start out from zero at the beginning of the next half cycle, the possibil-ity exists that a trip indication toward the end of the half cycle will be lost.
This possibility is eliminated by means of an ; 20 anti-phasing system indicated at 50. The trlp output of the , comparator 46 is fed to the system 50 which contains a capacitive "memory". The capacitor "remembers" that it had received a trip signal at the end of the preceding half cycle and produces positive feedback current (indicated by the path 51 of Figure 1) to the input amplifier 3,0 early in the half cycle succeeding the trip condition~ thereby produc-ing a large value of ~iin which is processed by the integra-tor 36 to quickly produce a trip indication early in the half cycle and energize the solenoid 24 to separate the contacts 26. The positive feedback thus produces a latching ~ ~ 8 2 ~ 7 l~h, g6~
type turn-on function ~Jhich eliminates the phasing problem, In addition, the latching process coupled ~th other circult features to be hereinafter described make~ it possible to operate the circuit at a line voltage of as low as 50 volts AC, The TEST button operates by deliberately establish-ing a ground fault current of a known le~rel between the line conductor and ground through resistor ~6. If the apparatus is operating properly9 a trip action ~nll occur.
Operation of ~he apparatus of Figure 1 m~y be more clearly understood by reference to the waveforms of Figure 2.
'~aveform A of Figure 2 sho~Js the voltage VLN between the line conductor 10 and the neutral conductor 120 Also sho~m is the voltage VN produced by the neutral transformer 54 on the neutral conductor 12~ As can be seen, the neutral voltage is a short pulse due to the saturating properties of the transformer 5~g A reference current ire~ is produced by the circuit 57 and has a peak value proportion.~l to the neutral voltage VN~ The edges of the current pulse iref have been shaped as shown in waveform B to provide more consistent op-eration., The value of Kiin generated by normal leakage conditions belo~r the ground f~ult trip level is sho~Jn in aveform C of Figure 2. Superimposed upon this current is the neutral reference current iref . Since Kiin,is less than iref~ iadd equals zero and iSum equals cc iin~ It can be seen in wa~reform D that the integrator output produced by this normal line-to-ground current over the period of one half cycle is less than the trlp cu~rent level. Also, the action of the reset signal upon the integrator 36 is sho~m in ~aveform ~ as it ~ '7 k6,9~
reduces the value of the integral to zero just prior to the end of the half cycle.
The value of Kiin generated by normal neutral-to-ground current is shown in ~aveform E of F~gure 2. It can be seen that during normal operation, this value of Kiin is also less than the peak value of the neutral reference current iref. Thus, iadd equals zero9 iSum equals c~ i~n~ and the output of the integrator 36 remains below the tripping cur-rent level as sho~m in waveform F~
Upon occurrence of a fault bet~een the line con-ductor 10 and ground7 as at 2~ of Figure 19 a current im~
balance is produced between the conductors 10 and 12 result-ing in a higher output from the sensing winding 22~ Under these conditions the peak value of Kiin may or may not be greater than iref However~ the value of~ n alone is sufficient to cause trip indication as shown in waveform H
of Figure 2, wherein it can be seen that the ~alue of the integral rises to the trip level befora the end of the half cycle. Thus, the solenoid 2~ will be activated to separate the contacts 26 and de-energize the load 1~. .
A low resistance neutral-to-ground path 4~ (Figure 1) results in a neutral-to-ground current producing an output Kiin from amplifier 30. Since Kiin is greater than the ~eutral reference current iref (waveform I), a value of iadd equal ko Kiin is added to ~ iin, producing an inte~
grator output as sho~ in waveform J. This out~ut rapidly rises above the trip level to produce a tripping operation as described above~
An electronic circuit embodying the principals of the present invention is sho~m schematically in Figure 3, ~ ,, 46,960 and will be described in sections.
BREAKER CIRCUIT
The breaker version of the present invention is shown in Figure 3. As can be seen, the main circuit element is an integrated circuit, or chip 75, the internal design details of which will be discussed in the following sec-tions. At this tlme it will be treated as a simple seven terminal circuit element.
The chip 75 ~s powered by a ~e dropping resis-tor, R4, which supplies a nearly sinusoidal bias current ofslightly more than 2 ma RMS from the 120V ac supply. The bias resistor dissipates 0.15 watts at 132V ac line voltage.
The voltage from B to GND is a square wave with a value of 14 volts during the positive half cycle of the supply and 0 volts during the negative half cycle. The chip can function only when the B terminal is positive, and thus the unit operates in a half wave manner. -`
The secondary winding 22 of the differential current transformer 18 is connected directly to the IN.
terminal. The polarity is such that normal line-to-ground current produces a current iin out of the IN terminal. The chip 75, by means of internal voltage feedback, maintains the IN terminal near virtual ground. The capacitor C2 is used as an RF filter.
The current flow out of the IN terminal flows from the B supply throv.gh C3 into the CAP termlnal. The voltage drop across C3 thus represents the integral of the current lin. At th~ end of the positive half cycle the voltage at the B terminal drops below lll volts which energizes cir-cuitry within the chip 75 to reset the capacitor C3 to zero.
--11~--7 '9 At the beginn~ng OI the next positive half cycle the reset circuit is turned oî~, and the capacitor C3 starts to be charged again. me voltage across the capacitor C3 at t~e en~ of each cycle thus represents the half cycle integral o~
the current iin wh~ch is proportional to half cycle average current of the 60 Hz ground current.
A voltage comparator on the chip 75 co~pares the voltage across C~ to a voll;age refere~ce OI about 1.6 volts.
When the capacltor voltage exceeds the reIerence7 current begins to flow ~rom the OUT terminal ~nto t~e capaoitor C4.
An exte~nal resistor R3 can ~e used to ad~ust the reIerenc~
voltage to calibrate the circuit. Inte~al posit~ve feed-back on the chip 75 produces rapid char~ng of ~3 which cause~ C4 to charge to the gate conductlon voltage of the SCR 52, t;uxning on the SCR~
For ground currents which barely exceed ~he trip level, the 5CR turn~ on at the e2~d OI th~ half cycle.
Capacitsr C4 i~ the memory element OI the '1anti-phaslng'l circuit 50~ me capacitor C4 retains its charge during the next negati~re hal~ cycle of the llne voltage ~o that the positlve ~eedback circu~t is still energized at the begin-nlng o~ the next positive hal~ cycle. The SCR is thus turned on hard at the ~eginning o~ the cycle eliminatlng phas$ng problems ~nd po~sible sole~oid "chattering"~ This feature makes it possible for the circuit to ~unction nor-m~lly with a llne vcltage a~ low as 50 volts RMS. Another important function o~ the gate capacitor C4 i~ to provide a low ac gate-to-cathode impedance which greatly improves the d~/dt capability of the SCR.
A neutral-to-ground resistance oi less than ~ 7 l~67960
2 ohms causes an internal current on the chip 75 (one o~ t~ro outputs of the input ampllfier 30) to exceed the neutral reference current iref produced by current i~l flowing into terminal NT through R2. (Current iN is caused by input to the neutral transformer 511.) The current iSum then flows into capacitor c3 which causes it to rapidly charge to the trip level turning on the SCR 52.
Input Am~ifier The circuitry of the chip 75, including input amplifier 30 with its two outputs ~iin, and Kiin, is shown in Figure ~. The output of transformer 18 produces a cur-rent iin flowing from pin IN. Input transistor Q25 is operated in a common base configuration which, by means of voltage feedback, maintains the IN terminal at a near vir-tual ground. This is achieved by means of the quad PNP
configuration of Q3 through Q6. The bias curre~t of about 14 ~a fed into the quad network splits evenly because of the transistor mirror configuration of Q7 and Q8 into two 7 ~a values. The base of Q3 is grounded through a 40K pinch resistor; the ~uad network tries by feedback to maintain the oase of Q6 near t~-ground. Balance is actually achieved when the base of Q6 is approximately 5 mv below ground.
Since the base of Q6 is tied to the input-terminal IN
through a 7.2K resistor, at balance terminal IN has a -5 mv offset.
Should the current iin exceed the emitter current of Q25, the excess will flow from the base of Q6. This turns Q5 on harder while decreasing the collector current of Q8. The e~cess collector current is forced into the base o~
Q~5 turning the transistor on harder, thereby lncreasing the ~ 4~7 ~6,960 current ~low into the IN terminal. me negative fe~dbackprocess will continue until the emitter current oi Q25 once again equals i~n.
The collector output current of Q25,~ i~n~ is slightly le~ than the input current because o~ the ~inite beta o~ Q25. A second ou~put current Ki~n iS produced by translstor Q26 which has a current outpu~ slightly less than ten t~mes the input, This current i~ ~ed to the grounded n~utral circultry a~ will be explained belo~r.
me 36K reæistor from IN to ground serves two purposes. First, it supplie3 a dc path for the base current o~ Q6 which, when added to the 7.2K ohm series resi~tance, approximately balances the 40K ohm base to-ground resistance o~ Q3. The second purpose of the 36K ohm resistor is to provide a di~charge path for the magnetizing current o~ t~e trans~ormer 18~ The 36K value is a compromise between the low v~lue desired for the base current and the large value desired ~or resetting the magnetizing current. A value signi~icantly le~s than this connected across winding 22 can result in a dc bi3s current being established in the wlnding 22 whlch would make the trip level a fu~tion of the mag-netiæing inductance~ This in turn would make the trip level a function o~ temperature, as the magnetiæing inductance is : temperature dependent.
- Po~lti~e feedback is provided to the base of Q3 from the out terminal of the chlp. Thi~ forms the "ant~-phasing" network which causes the circuit to latch once it tries to trip. The base of Q3 is raised to about 2 volts b~
the feedback æignal and held there by the SCR gate-t~-cathode capacitor. By normal feedback action, t~e base of ~ 7 4&,96 Q6 is also dri~en toward3 2 volts ~thich turns Q25 ~ully oncausing a trlp~
Tran~istors ~9 and Q10 and Schottky diode3 D1 and D2 form an overcurrent protection network for the chip. The circuit is designed to trip with a 5 ma primary current in the transformer 18. The 3600 turns yield an output current o~ 1.4~a which i~ the design level for the circuit.
During high "bolted" ground fault ~-urrent conditions of, ~or example, 5000 amperes, the output of winding 22 would become 1.4 amperes. Satur~tion o~ the tran3former core limits the output current below thi~ value; however, a large pul~e current may result. me transistors Q9 and Q10 are large area, diode-connected, de~ices ~thlch bypass the large tran~ormer output current while limiting the ~oltage at the IN termin~l -to ~lV. Diodes D1 and D2, ln combination with the 7.2K ohm resiætor, ~urther limit the voltage at the base of Q6 to a value o~ ~bout +o74v which ensures that ~ubstrate dlodes assoclated with Q6 are not activated.
The output ~iin of the input ampllfier 30 feed~ an integrator 36 which integrates the input current ea~h half cycle. m e integrated value is proportional to ~he hal~
cycle a~erags value o~ the ground current and iB independent o~ any 120 HZ signal present. External capacitor C3, con-nected from termin~l B~ to CAP performs ~he integration, since the voltage acros3 a capacltor is pr~portional to the integral of the current through it. The ~oltage across C3 is detected by means o~ the darlington-connected emltter ~ollower Q23 and Q24 which produces an output current proportion~1 to the integral o~ iin over one half cycle , .
~ 46~g6~
Diode-connected transistors Q21 and Q22 are used to ~al~nce the base emitter drops of Q23 and Q2~.
Tne capacitor is reset at the beginning of each half cycle by means of Q17. The reset circuit ~rks in combination ~th B+ power supply formed by passing an ac supply current of about 2 ma into the B~ terminal. The sup~ly current is obtained by means of the 56K ohm resistor R~ (Fig. 3) connected to the line conductor 10. The current entering the B~ terminal ~lows to ground through diode-connected Q33, Zener-connected Ql~ and Q19 (base~to-emitter Zener voltage o~ about 6.3 volts)9 and the diode-connected Q20. The B~ voltage is established at about 14 volts~ The temperature coefficient of the Zener of a~out ~2mV/C cancels the dlodes coefficient of about -2mV~ C.
A current '~irror" ls formed by Q33 and Q16 such that the schottky-clamped transistor Q16 is on whenever the value of current through the B~ terminal exceeds a threshold large enough to cause Q33 to conduct. With Q16 on9 tr~n-sistor Q17 is off as the 14~ a bias curren~ is diYerted from the base of Q17. At the beginning of each half cycle, however, the current through B~ is belo~/ threshold and Q16 is off. The bias current then flo~Js from the base of Q17 ~ ich turns Q17 on thus discharging C3. The capacitor thus starts each hal~ cycle in a discharged condition.
Diode-connected transistors Q33, Q34~ ,Q4~, Q~6, and Q~7 are used to cli~ the capacitor current during a very ~ 8~ ~7 46,960 large ground current. Without such a Clamp7 a po~s~bility exlsts that Q23 could saturate, a condition not permltted i~
integrated circuit design.
Bias Current Generator As shown in Figure 5, the supply current ~hrough B+ n ows through diode-connected transistor Q20 during the po3iti~e half cycle of the line ~oltage. m e 56K ohm supply re~istor R4 (Fig. 3) produce~ an average curre~t of about 2 ma. A mirror arrangement o~ four transistors (Q1~, Q15, Q39, and Q40~, with a common emitter resistor, is used to generate the required bias currents of about 1~a. The bias curr~nt is about 3 decade~ smaller ~han the ~upply current whlch, when c~upled with 65 mv/decade characteris-tics o~ the base-emitter voltage ver us log emitter current curve, indicates that the base-emitter drop o~ the mirror tran~istors will be about 97 m~ les~ ~han the drop across Q20. The 200 mV appears acroæs the common emitter res~stor which, to produce 4 x 14~ a of current, should be a 1.8K
resistor.
Grru~e~ ~otr~l c~rcu~-r/
A~ dlscu~sed previously, the circult is designed to trip on ~he peak value oi neutral-to-ground current i~
the ground resistance is less than 2 ohms. To do this, a reference cu~rent ire~, proportional to the neutral voltage, i8 generated on the chip. The circult ~or doing th$s is shown in Figure 5. A current iN~ proportlonal to ~he ~eutral transformer voltage, is fed ~hrough an external reaistor R~ into terminal NT. If ~his current is les~ than the current in Q40, lt i~ sh~nted to ground by Q40 which p turns Q38 of~, When iN exceeds the collector current of Q40 L~, g~J
the dif'ference current is shunted to ground through Q43which also turns Q38 on. The collector current of Q41 is summed with the collector of Q38 to form the current iref.
The three transistor current mirror Q35, Q35, and Q37 is used to produce a Q35 collector current equal to iref~ If Kiin~ iref~ the difference flows into Schottky diode D3. The cathode of D3 is biased one P-N Junction below B by means of Q33, and the anode of D3 is about 0.2 volts below B .
Transistor Q32 is off. The collector current of Q36 is diverted through D4.
~hen Kiin> iref~ the difference flows through diode clamps Q33 and Q34 which turns Q32 on. Its collector current iref flows ~nto Q31 which is mirrored b~ Q30 into the integrating capacitor. The value of K is about 10. The integrating capacitor current is more than 10 times (K~l) the value which it would be if the comparator circuit was not used. The resulting current is capable of charging the capacitor to the trip level during the short neutral pulse period.
The edge shaping of iN to form iref is done to ensure that the grounded neutral circuitry does not effect the trip level during normal operation.
Output and Reference Circuitry The integral of the input current appears across C3. The darlington emitter follower amplifier causes the capacitor voltage to appear across the 5.4K ohm emitter resistor of Q24. The emitter resistor voltage is amplified by the collector resistor by a factor of 24.3/5.4 4.5. The amplified value appears at the base of Q283 the external CAL
terminal. l,~Jhen this value reaches a value of about 7.4 >~ 45,g6~
volts (base-emitter voltage of Q2g plus Zener voltage of Q29), current ~ill begin to flo~7 through Q2~ and Q29 into the l~OK base reslstor of Q3. The 7.4 volt value is temper-ature compensated, the -2mV/C base-emitter characterlstic being balanced by the ~2mV/C Zener characteristic. The voltage rlse across the 40K res1stor represents pos~tive feedback at the input which further increases the charging current of C3. This further increases the turn-on o~ ~2 l~hen the voltage drop across the ~OK resistor reaches about 0.7 volts, Q44 begins to conduct ~nd Cl; s~arts to charge. ~en the gate-cathode threshold of the SCR 52 is reached, the SCR 52 turns on and the breaker is ~ripped.
The "anti-phasing'1 feature is achieved by C~. ~t a curren~
just above threshold, the SGR 52 turns on at the end of the half cycle ~rhen the instantaneous line voltage is too small to trip the breaker~ During the next negati~e half cycle of the line voltage, capacitor CJ~ is discharged through D7 and the 40 K resistors~ The R-C time constant is such that at the beginning of the next positive half cycle, positive voltage feedback still exists at the base of Q3 which results in a very rapid charging of C3. The SCR is then turned on early in the cycle.
The "anti-phasing" circuit makes it possible to operate the circuit down to a line voltage of less than 50V
P~S.
-~ 7 46,g60 The receptacle unit i5 designed to trip for both polarities of line voltage since if the receptacle input po~er leads are reversed, the polarity of the output voltage must be reversed to produce the same polarity of current iin, from the sensing winding 22. As mentioned earlier, the electronic circuit responds to only one polarity of iin, and thus the circuit must be able to trip for both positive and negative line-to-ground voltage. A full ~Jave bridge 77 is used to achieve this, as shown in Fig. ~.
The circuit includes the s~me integrated circuit chip 75 and responds to normal ground currents in the same manner as the breaker versionO A possible problem does exist, however, because of the full ~ave operation of the chip. The chip is energized continuously, except near line voltage zero each half cycle; and thus any dc offset at terminal IN appears as a battery across the output of winding ~6,~
~ 7 22. If the offset is a positive value of, for example, 4 mv, a linearly increasing current will flow fror~ the chip 75, out of termlnal IN, lnto tne winding 22. The rate of current increase will be governed by the magnetizing induc-tance LM of the transformer 18, approximately 100 henries, and the equation di/dt = Eo S~LM ~.04 ~A/ms. At zero line voltage the chip 75 ~s turned off and the current no longer increases. The current trapped in the magnetizlng inductance continues to flow, however, as a 36K resistor within the chip 75 from IN to ~ND provides a closed path. The circuit now becomes a simple L-R series loop which results in an exponentially decaying magnetizing current with an L/R time constant of about 3 ms. The current has little time to decay during the short zero crossing interval, and thus it will continue to increase each half cycle until the value of iin reaches the trip level of the circuit. It should be noted that this problem does not exist in the breaker ver-sion as the core has nearly 9 ms, or three times constants, to reset during each negative half cycle of the line voltage.
The cause Or the problem is the existence of a positive voltage offset at the IN terminal. A negative offset produces no problem as the input amplifier cannot sink current. Since current cannot flow into the IN term-inal, the magnetizing current is zero. The problem is thus eliminated by designing the chip so that the input ampli-fiers offset is -5 mv nominal with an expected distribution of no more than + 4 mv from nominal.
The grounded neutral system also functions slightly differently in a receptacle version because of the existence of two "grounds" caused by the bridge 77. The neutral -2l~-~ 4~7 4~,g~
transformer 54 must be fed from an ac supply ~,Jhile the electronic circuit is fed from a dc source. This results in there being no common connection between 54 and the GND
terminal of the chip 75. The current flow through R2 into the NT terminal is, thus, not proportional to the voltage across 54 during the negative half cycle. However, during the positive half cycle the current is proportional, and the grounded neutral system thus trips in the positive half cycle in the same manner as the breaker version.
The present invention provides a 5FCI employing an integrator which approaches the performance of an ideal integrator, performing integration over a period of one half cycle. Thus, 120 Hz false currents produced by stray mag-netic fields are effectively cancelled, reducing the depend-ence of the trip level current upon load current. Means are also provided to detect a grounded neutral condition through the use of a saturable transformer to induc~ a voltage pulse upon the neutral conductor. The saturable transformer method allows a reduction in the size and complexity of circuitry needed to provide grounded neutral protection. In addition, the problems associated with energizing an SCR at the end of a half cycle in the vicinity of current ~ero are alleviated through the use of the memory circuit to provide - a positive firing signal at the beginning of the next succeed-ing half cycle ~ It can be seen therefore that the present inven-- tion provides a ground fault circuit interrupter having improved performance, greater reliability, and decreased cost over the prior art.
Input Am~ifier The circuitry of the chip 75, including input amplifier 30 with its two outputs ~iin, and Kiin, is shown in Figure ~. The output of transformer 18 produces a cur-rent iin flowing from pin IN. Input transistor Q25 is operated in a common base configuration which, by means of voltage feedback, maintains the IN terminal at a near vir-tual ground. This is achieved by means of the quad PNP
configuration of Q3 through Q6. The bias curre~t of about 14 ~a fed into the quad network splits evenly because of the transistor mirror configuration of Q7 and Q8 into two 7 ~a values. The base of Q3 is grounded through a 40K pinch resistor; the ~uad network tries by feedback to maintain the oase of Q6 near t~-ground. Balance is actually achieved when the base of Q6 is approximately 5 mv below ground.
Since the base of Q6 is tied to the input-terminal IN
through a 7.2K resistor, at balance terminal IN has a -5 mv offset.
Should the current iin exceed the emitter current of Q25, the excess will flow from the base of Q6. This turns Q5 on harder while decreasing the collector current of Q8. The e~cess collector current is forced into the base o~
Q~5 turning the transistor on harder, thereby lncreasing the ~ 4~7 ~6,960 current ~low into the IN terminal. me negative fe~dbackprocess will continue until the emitter current oi Q25 once again equals i~n.
The collector output current of Q25,~ i~n~ is slightly le~ than the input current because o~ the ~inite beta o~ Q25. A second ou~put current Ki~n iS produced by translstor Q26 which has a current outpu~ slightly less than ten t~mes the input, This current i~ ~ed to the grounded n~utral circultry a~ will be explained belo~r.
me 36K reæistor from IN to ground serves two purposes. First, it supplie3 a dc path for the base current o~ Q6 which, when added to the 7.2K ohm series resi~tance, approximately balances the 40K ohm base to-ground resistance o~ Q3. The second purpose of the 36K ohm resistor is to provide a di~charge path for the magnetizing current o~ t~e trans~ormer 18~ The 36K value is a compromise between the low v~lue desired for the base current and the large value desired ~or resetting the magnetizing current. A value signi~icantly le~s than this connected across winding 22 can result in a dc bi3s current being established in the wlnding 22 whlch would make the trip level a fu~tion of the mag-netiæing inductance~ This in turn would make the trip level a function o~ temperature, as the magnetiæing inductance is : temperature dependent.
- Po~lti~e feedback is provided to the base of Q3 from the out terminal of the chlp. Thi~ forms the "ant~-phasing" network which causes the circuit to latch once it tries to trip. The base of Q3 is raised to about 2 volts b~
the feedback æignal and held there by the SCR gate-t~-cathode capacitor. By normal feedback action, t~e base of ~ 7 4&,96 Q6 is also dri~en toward3 2 volts ~thich turns Q25 ~ully oncausing a trlp~
Tran~istors ~9 and Q10 and Schottky diode3 D1 and D2 form an overcurrent protection network for the chip. The circuit is designed to trip with a 5 ma primary current in the transformer 18. The 3600 turns yield an output current o~ 1.4~a which i~ the design level for the circuit.
During high "bolted" ground fault ~-urrent conditions of, ~or example, 5000 amperes, the output of winding 22 would become 1.4 amperes. Satur~tion o~ the tran3former core limits the output current below thi~ value; however, a large pul~e current may result. me transistors Q9 and Q10 are large area, diode-connected, de~ices ~thlch bypass the large tran~ormer output current while limiting the ~oltage at the IN termin~l -to ~lV. Diodes D1 and D2, ln combination with the 7.2K ohm resiætor, ~urther limit the voltage at the base of Q6 to a value o~ ~bout +o74v which ensures that ~ubstrate dlodes assoclated with Q6 are not activated.
The output ~iin of the input ampllfier 30 feed~ an integrator 36 which integrates the input current ea~h half cycle. m e integrated value is proportional to ~he hal~
cycle a~erags value o~ the ground current and iB independent o~ any 120 HZ signal present. External capacitor C3, con-nected from termin~l B~ to CAP performs ~he integration, since the voltage acros3 a capacltor is pr~portional to the integral of the current through it. The ~oltage across C3 is detected by means o~ the darlington-connected emltter ~ollower Q23 and Q24 which produces an output current proportion~1 to the integral o~ iin over one half cycle , .
~ 46~g6~
Diode-connected transistors Q21 and Q22 are used to ~al~nce the base emitter drops of Q23 and Q2~.
Tne capacitor is reset at the beginning of each half cycle by means of Q17. The reset circuit ~rks in combination ~th B+ power supply formed by passing an ac supply current of about 2 ma into the B~ terminal. The sup~ly current is obtained by means of the 56K ohm resistor R~ (Fig. 3) connected to the line conductor 10. The current entering the B~ terminal ~lows to ground through diode-connected Q33, Zener-connected Ql~ and Q19 (base~to-emitter Zener voltage o~ about 6.3 volts)9 and the diode-connected Q20. The B~ voltage is established at about 14 volts~ The temperature coefficient of the Zener of a~out ~2mV/C cancels the dlodes coefficient of about -2mV~ C.
A current '~irror" ls formed by Q33 and Q16 such that the schottky-clamped transistor Q16 is on whenever the value of current through the B~ terminal exceeds a threshold large enough to cause Q33 to conduct. With Q16 on9 tr~n-sistor Q17 is off as the 14~ a bias curren~ is diYerted from the base of Q17. At the beginning of each half cycle, however, the current through B~ is belo~/ threshold and Q16 is off. The bias current then flo~Js from the base of Q17 ~ ich turns Q17 on thus discharging C3. The capacitor thus starts each hal~ cycle in a discharged condition.
Diode-connected transistors Q33, Q34~ ,Q4~, Q~6, and Q~7 are used to cli~ the capacitor current during a very ~ 8~ ~7 46,960 large ground current. Without such a Clamp7 a po~s~bility exlsts that Q23 could saturate, a condition not permltted i~
integrated circuit design.
Bias Current Generator As shown in Figure 5, the supply current ~hrough B+ n ows through diode-connected transistor Q20 during the po3iti~e half cycle of the line ~oltage. m e 56K ohm supply re~istor R4 (Fig. 3) produce~ an average curre~t of about 2 ma. A mirror arrangement o~ four transistors (Q1~, Q15, Q39, and Q40~, with a common emitter resistor, is used to generate the required bias currents of about 1~a. The bias curr~nt is about 3 decade~ smaller ~han the ~upply current whlch, when c~upled with 65 mv/decade characteris-tics o~ the base-emitter voltage ver us log emitter current curve, indicates that the base-emitter drop o~ the mirror tran~istors will be about 97 m~ les~ ~han the drop across Q20. The 200 mV appears acroæs the common emitter res~stor which, to produce 4 x 14~ a of current, should be a 1.8K
resistor.
Grru~e~ ~otr~l c~rcu~-r/
A~ dlscu~sed previously, the circult is designed to trip on ~he peak value oi neutral-to-ground current i~
the ground resistance is less than 2 ohms. To do this, a reference cu~rent ire~, proportional to the neutral voltage, i8 generated on the chip. The circult ~or doing th$s is shown in Figure 5. A current iN~ proportlonal to ~he ~eutral transformer voltage, is fed ~hrough an external reaistor R~ into terminal NT. If ~his current is les~ than the current in Q40, lt i~ sh~nted to ground by Q40 which p turns Q38 of~, When iN exceeds the collector current of Q40 L~, g~J
the dif'ference current is shunted to ground through Q43which also turns Q38 on. The collector current of Q41 is summed with the collector of Q38 to form the current iref.
The three transistor current mirror Q35, Q35, and Q37 is used to produce a Q35 collector current equal to iref~ If Kiin~ iref~ the difference flows into Schottky diode D3. The cathode of D3 is biased one P-N Junction below B by means of Q33, and the anode of D3 is about 0.2 volts below B .
Transistor Q32 is off. The collector current of Q36 is diverted through D4.
~hen Kiin> iref~ the difference flows through diode clamps Q33 and Q34 which turns Q32 on. Its collector current iref flows ~nto Q31 which is mirrored b~ Q30 into the integrating capacitor. The value of K is about 10. The integrating capacitor current is more than 10 times (K~l) the value which it would be if the comparator circuit was not used. The resulting current is capable of charging the capacitor to the trip level during the short neutral pulse period.
The edge shaping of iN to form iref is done to ensure that the grounded neutral circuitry does not effect the trip level during normal operation.
Output and Reference Circuitry The integral of the input current appears across C3. The darlington emitter follower amplifier causes the capacitor voltage to appear across the 5.4K ohm emitter resistor of Q24. The emitter resistor voltage is amplified by the collector resistor by a factor of 24.3/5.4 4.5. The amplified value appears at the base of Q283 the external CAL
terminal. l,~Jhen this value reaches a value of about 7.4 >~ 45,g6~
volts (base-emitter voltage of Q2g plus Zener voltage of Q29), current ~ill begin to flo~7 through Q2~ and Q29 into the l~OK base reslstor of Q3. The 7.4 volt value is temper-ature compensated, the -2mV/C base-emitter characterlstic being balanced by the ~2mV/C Zener characteristic. The voltage rlse across the 40K res1stor represents pos~tive feedback at the input which further increases the charging current of C3. This further increases the turn-on o~ ~2 l~hen the voltage drop across the ~OK resistor reaches about 0.7 volts, Q44 begins to conduct ~nd Cl; s~arts to charge. ~en the gate-cathode threshold of the SCR 52 is reached, the SCR 52 turns on and the breaker is ~ripped.
The "anti-phasing'1 feature is achieved by C~. ~t a curren~
just above threshold, the SGR 52 turns on at the end of the half cycle ~rhen the instantaneous line voltage is too small to trip the breaker~ During the next negati~e half cycle of the line voltage, capacitor CJ~ is discharged through D7 and the 40 K resistors~ The R-C time constant is such that at the beginning of the next positive half cycle, positive voltage feedback still exists at the base of Q3 which results in a very rapid charging of C3. The SCR is then turned on early in the cycle.
The "anti-phasing" circuit makes it possible to operate the circuit down to a line voltage of less than 50V
P~S.
-~ 7 46,g60 The receptacle unit i5 designed to trip for both polarities of line voltage since if the receptacle input po~er leads are reversed, the polarity of the output voltage must be reversed to produce the same polarity of current iin, from the sensing winding 22. As mentioned earlier, the electronic circuit responds to only one polarity of iin, and thus the circuit must be able to trip for both positive and negative line-to-ground voltage. A full ~Jave bridge 77 is used to achieve this, as shown in Fig. ~.
The circuit includes the s~me integrated circuit chip 75 and responds to normal ground currents in the same manner as the breaker versionO A possible problem does exist, however, because of the full ~ave operation of the chip. The chip is energized continuously, except near line voltage zero each half cycle; and thus any dc offset at terminal IN appears as a battery across the output of winding ~6,~
~ 7 22. If the offset is a positive value of, for example, 4 mv, a linearly increasing current will flow fror~ the chip 75, out of termlnal IN, lnto tne winding 22. The rate of current increase will be governed by the magnetizing induc-tance LM of the transformer 18, approximately 100 henries, and the equation di/dt = Eo S~LM ~.04 ~A/ms. At zero line voltage the chip 75 ~s turned off and the current no longer increases. The current trapped in the magnetizlng inductance continues to flow, however, as a 36K resistor within the chip 75 from IN to ~ND provides a closed path. The circuit now becomes a simple L-R series loop which results in an exponentially decaying magnetizing current with an L/R time constant of about 3 ms. The current has little time to decay during the short zero crossing interval, and thus it will continue to increase each half cycle until the value of iin reaches the trip level of the circuit. It should be noted that this problem does not exist in the breaker ver-sion as the core has nearly 9 ms, or three times constants, to reset during each negative half cycle of the line voltage.
The cause Or the problem is the existence of a positive voltage offset at the IN terminal. A negative offset produces no problem as the input amplifier cannot sink current. Since current cannot flow into the IN term-inal, the magnetizing current is zero. The problem is thus eliminated by designing the chip so that the input ampli-fiers offset is -5 mv nominal with an expected distribution of no more than + 4 mv from nominal.
The grounded neutral system also functions slightly differently in a receptacle version because of the existence of two "grounds" caused by the bridge 77. The neutral -2l~-~ 4~7 4~,g~
transformer 54 must be fed from an ac supply ~,Jhile the electronic circuit is fed from a dc source. This results in there being no common connection between 54 and the GND
terminal of the chip 75. The current flow through R2 into the NT terminal is, thus, not proportional to the voltage across 54 during the negative half cycle. However, during the positive half cycle the current is proportional, and the grounded neutral system thus trips in the positive half cycle in the same manner as the breaker version.
The present invention provides a 5FCI employing an integrator which approaches the performance of an ideal integrator, performing integration over a period of one half cycle. Thus, 120 Hz false currents produced by stray mag-netic fields are effectively cancelled, reducing the depend-ence of the trip level current upon load current. Means are also provided to detect a grounded neutral condition through the use of a saturable transformer to induc~ a voltage pulse upon the neutral conductor. The saturable transformer method allows a reduction in the size and complexity of circuitry needed to provide grounded neutral protection. In addition, the problems associated with energizing an SCR at the end of a half cycle in the vicinity of current ~ero are alleviated through the use of the memory circuit to provide - a positive firing signal at the beginning of the next succeed-ing half cycle ~ It can be seen therefore that the present inven-- tion provides a ground fault circuit interrupter having improved performance, greater reliability, and decreased cost over the prior art.
Claims (11)
1. Ground fault protective apparatus for use on an AC electrical circuit having a line conductor and a neutral conductor grounded at a power source, comprising:
means for sensing current imbalance on said line and neutral conductors, said sensing means providing an output signal proportional to said imbalance;
means for integrating said output signal and for providing a trip indication whenever the integration of said output exceeds a predetermined reference level;
means for inducing a test voltage on said neutral conductor, whereby a current imbalance is produced between said line and neutral conductors which is proportional to the neutral-to-ground conductance;
means for providing a reference current propor-tional to said test voltage;
means connected to the input of said integrating means for comparing said reference current to the output signal of said sensing means, said comparing means supplying a signal current to the input of said integrating means whenever the output signal of said sensing means rises above said reference current, said signal current being of suf-ficient amplitude to cause aid integrating means to produce a trip indication.
means for sensing current imbalance on said line and neutral conductors, said sensing means providing an output signal proportional to said imbalance;
means for integrating said output signal and for providing a trip indication whenever the integration of said output exceeds a predetermined reference level;
means for inducing a test voltage on said neutral conductor, whereby a current imbalance is produced between said line and neutral conductors which is proportional to the neutral-to-ground conductance;
means for providing a reference current propor-tional to said test voltage;
means connected to the input of said integrating means for comparing said reference current to the output signal of said sensing means, said comparing means supplying a signal current to the input of said integrating means whenever the output signal of said sensing means rises above said reference current, said signal current being of suf-ficient amplitude to cause aid integrating means to produce a trip indication.
2. Apparatus as recited in claim 1 wherein said test voltage inducing means produces voltage pulses upon said neutral conductor.
3. Apparatus as recited in claim 2 wherein the peak value of said reference current is proportional to said test voltage and said comparing means compares the value of said reference current with the value of said sensing means output current.
4. Apparatus as recited in claim 3 wherein said reference current has an instantaneous value proportional to said induced voltage pulses, and a faster rise and decay time than said induced voltage pulses.
5. Apparatus as recited in claim 1 wherein said integrating means is reset every half cycle of frequency upon said line and neutral conductors.
6. Ground fault protective apparatus for use on an AC electrical circuit having a line conductor and a neutral conductor, comprising:
means for sensing current imbalance on said line and neutral conductors, said sensing means providing an output signal proportional to said imbalance;
means for integrating said output signal;
means connected to said integrating means for providing a trip indication whenever the output of said integrating means exceeds a predetermined reference, and means for generating a feedback signal to the input of said integrating means when the output of said integrating means exceeds a predetermined level.
means for sensing current imbalance on said line and neutral conductors, said sensing means providing an output signal proportional to said imbalance;
means for integrating said output signal;
means connected to said integrating means for providing a trip indication whenever the output of said integrating means exceeds a predetermined reference, and means for generating a feedback signal to the input of said integrating means when the output of said integrating means exceeds a predetermined level.
7. Ground fault protective apparatus for use on an AC electrical circuit having a line conductor and a neutral conductor, comprising:
means for sensing current imbalance on said line and neutral conductors, said sensing means providing an output signal proportional to said imbalance;
means for integrating said output signal;
first trip means connected to said integrating means for providing a trip indication whenever the output of said integrating means exceeds a predetermined reference;
means for inducing a test voltage upon said neutral conductor, whereby a current imbalance is produced between said line and neutral conductors which is proportion-al to the neutral-to-ground conductance; and second trip means connected to said sensing means and responsive to the instantaneous value of said sensing means output signal for producing a trip indication when the instantaneous value of said output signal exceeds a second predetermined reference level.
means for sensing current imbalance on said line and neutral conductors, said sensing means providing an output signal proportional to said imbalance;
means for integrating said output signal;
first trip means connected to said integrating means for providing a trip indication whenever the output of said integrating means exceeds a predetermined reference;
means for inducing a test voltage upon said neutral conductor, whereby a current imbalance is produced between said line and neutral conductors which is proportion-al to the neutral-to-ground conductance; and second trip means connected to said sensing means and responsive to the instantaneous value of said sensing means output signal for producing a trip indication when the instantaneous value of said output signal exceeds a second predetermined reference level.
8. Apparatus as recited in claim 7 wherein said induced neutral test voltage comprises a plurality of voltage pulses and said second trip means is responsive to the peak value of output signal pulses produced in response to said voltage pulses upon conditions of high neutral-to-ground conductance.
9. Apparatus as recited in claim 7 wherein said second trip means is connected to the input of said in-tegrating means and produces a large input signal to said integrating means when said output signal exceeds said second predetermined reference level, whereby the output of said integrating means is caused to exceed said first predetermined level and actuate said first trip means to provide a trip indication.
10. Apparatus as recited in claim 7 wherein said integrating means is reset after each half cycle of load current through said apparatus.
11. Apparatus as recited in claim 10 wherein said induced neutral test voltage comprises a plurality of voltage pulses and said second trip means is responsive to the peak value of corresponding current pulses produced by said sensing means upon conditions of high neutral to ground conductance, and said apparatus further comprises means for shaping said output current pulses before applying said output current pulses to said second trip means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000396020A CA1148247A (en) | 1978-10-18 | 1982-02-10 | Ground fault circuit interrupter with grounded neutral protection |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA313,717A CA1125901A (en) | 1977-11-21 | 1978-10-18 | Ground fault circuit interrupter with grounded neutral protection |
| CA000396020A CA1148247A (en) | 1978-10-18 | 1982-02-10 | Ground fault circuit interrupter with grounded neutral protection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1148247A true CA1148247A (en) | 1983-06-14 |
Family
ID=25668795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000396020A Expired CA1148247A (en) | 1978-10-18 | 1982-02-10 | Ground fault circuit interrupter with grounded neutral protection |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1148247A (en) |
-
1982
- 1982-02-10 CA CA000396020A patent/CA1148247A/en not_active Expired
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